; --------------------------------------------------------------------------------
; @Title: AM65xx On-Chip Peripherals
; @Props: Released
; @Author: KOL
; @Changelog: 2019-01-09 KOL
;             2019-12-06 KOL
; @Manufacturer: TI - Texas Instruments
; @Doc: AM65x.xml
; @Core: Cortex-A53, Cortex-R5F
; @Chip: AM6526, AM6526-CR7, AM6527-CR7, AM6528, AM6528-CR7, AM6546, DRA804M-CR7
;        AM6546-CR7, AM6548, AM6548-CR7, DRA802M, DRA802M-CR7, DRA804M, AM6527
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peram65xx_es1.per 11559 2020-02-11 11:32:20Z cmorgenstern $

config 16. 8.
sif (CORENAME()!="PRU")
sif (CORENAME()=="CORTEXA53")
tree "Core Registers (Cortex-A53)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.long 0x0 "MIDR_EL1,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23.  "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field"
newline
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.quad SPR:0x30006++0x0
line.long 0x0 "REVIDR_EL1,Revision ID Register"
rgroup.quad SPR:0x30014++0x00
line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30015++0x00
line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad SPR:0x30016++0x00
line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad SPR:0x30017++0x00
line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
endif
rgroup.quad SPR:0x30020++0x00
line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30022++0x00
line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30024++0x00
line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30025++0x00
line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
endif
rgroup.quad SPR:0x30010++0x00
line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30011++0x00
line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
endif
rgroup.quad SPR:0x30013++0x00
line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad SPR:0x31007++0x00
line.long 0x00 "AIDR_EL1,Auxiliary ID Register"
rgroup.quad SPR:0x33007++0x00
line.long 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad SPR:0x30100++0x0
line.long 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x34100++0x0
line.long 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x36100++0x0
line.long 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad SPR:0x30101++0x0
line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
group.quad SPR:0x34101++0x0
line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x30102++0x00
line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..."
bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped"
group.quad SPR:0x36110++0x0
line.long 0x0 "SCR_EL3,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (CORENAME()=="CORTEXA57")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
elif (CORENAME()=="CORTEXA53")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External,"
newline
hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
endif
tree.end
newline
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address"
rgroup.quad SPR:0x30C10++0x00
line.long 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad SPR:0x36C02++0x00
line.long 0x00 "RMR_EL3,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]"
endif
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad SPR:0x34300++0x00
line.long 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
rgroup.quad SPR:0x30510++0x00
line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
rgroup.quad SPR:0x34510++0x00
line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
rgroup.quad SPR:0x36510++0x00
line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
rgroup.quad SPR:0x30511++0x00
line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
rgroup.quad SPR:0x34511++0x00
line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
rgroup.quad SPR:0x36511++0x00
line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
rgroup.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
rgroup.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
rgroup.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
tree.end
newline
group.quad SPR:0x30D01++0x00
line.long 0x0 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad SPR:0x34000++0x0
line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
endif
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
endif
group.quad SPR:0x34112++0x00
line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x36131++0x00
line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad SPR:0x36112++0x00
line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x34113++0x00
line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
newline
bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
newline
bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
newline
bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
newline
bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
rgroup.quad SPR:0x34117++0x00
line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..."
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
group.quad SPR:0x32000++0x0
line.long 0x0 "CSSELR_EL1,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x30F10++0x00
line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad SPR:0x30F11++0x00
line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad SPR:0x30F12++0x00
line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad SPR:0x30F13++0x00
line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad SPR:0x30F00++0x00
line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad SPR:0x30F01++0x00
line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad SPR:0x30F02++0x00
line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad SPR:0x30F03++0x00
line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
newline
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
newline
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
endif
if (CORENAME()=="CORTEXA57")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
endif
tree.end
tree "Level 2 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..."
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
newline
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
newline
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
newline
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
newline
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3"
bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled"
newline
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad SPR:0x339C0++0x00
line.long 0x0 "PMCR_EL0,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad SPR:0x339C1++0x00
line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad SPR:0x339C2++0x00
line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.quad SPR:0x339C3++0x00
line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00  30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
wgroup.quad SPR:0x339C4++0x00
line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
bitfld.long 0x00  30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00  29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00  28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00  27. "P27,Increment PMN27" "No action,Increment"
newline
bitfld.long 0x00  26. "P26,Increment PMN26" "No action,Increment"
bitfld.long 0x00  25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00  24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00  23. "P23,Increment PMN23" "No action,Increment"
newline
bitfld.long 0x00  22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00  21. "P21,Increment PMN21" "No action,Increment"
bitfld.long 0x00  20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00  19. "P19,Increment PMN19" "No action,Increment"
newline
bitfld.long 0x00  18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00  17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00  16. "P16,Increment PMN16" "No action,Increment"
bitfld.long 0x00  15. "P15,Increment PMN15" "No action,Increment"
newline
bitfld.long 0x00  14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00  13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00  12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00  11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00  10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00  9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00  8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00  7. "P7,Increment PMN7" "No action,Increment"
newline
bitfld.long 0x00  6. "P6,Increment PMN6" "No action,Increment"
bitfld.long 0x00  5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00  4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00  3. "P3,Increment PMN3" "No action,Increment"
newline
bitfld.long 0x00  2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00  1. "P1,Increment PMN1" "No action,Increment"
bitfld.long 0x00  0. "P0,Increment PMN0" "No action,Increment"
group.quad SPR:0x339C5++0x00
line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
newline
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
newline
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
endif
rgroup.quad SPR:0x339C7++0x0
line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad SPR:0x339D1++0x00
line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad SPR:0x339D2++0x00
line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad SPR:0x339E0++0x00
line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad SPR:0x309E1++0x00
line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad SPR:0x309E2++0x00
line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.quad SPR:0x339E3++0x00
line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad SPR:(0x33E80+0x0)++0x00
line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad SPR:(0x33EC0+0x0)++0x00
line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x1)++0x00
line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad SPR:(0x33EC0+0x1)++0x00
line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x2)++0x00
line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad SPR:(0x33EC0+0x2)++0x00
line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x3)++0x00
line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad SPR:(0x33EC0+0x3)++0x00
line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x4)++0x00
line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad SPR:(0x33EC0+0x4)++0x00
line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x5)++0x00
line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad SPR:(0x33EC0+0x5)++0x00
line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:0x33EF7++0x00
line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad SPR:0x33E00++0x00
line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad SPR:0x30E10++0x00
line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x33E20++0x00
line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad SPR:0x33E21++0x00
line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad SPR:0x33E30++0x00
line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad SPR:0x33E31++0x00
line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad SPR:0x34E10++0x00
line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x34E20++0x00
line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad SPR:0x34E21++0x00
line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad SPR:0x37E20++0x00
line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad SPR:0x37E21++0x00
line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
endif
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad SPR:0x30CC6++0x00
line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x30CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x36CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad SPR:0x30460++0x00
line.long 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad SPR:0x30CB3++0x00
line.long 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad SPR:0x30CC5++0x00
line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x34C95++0x00
line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x36CC5++0x00
line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad SPR:0x34C80++0x00
line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34C90++0x00
line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
endif
tree.end
newline
rgroup.quad SPR:0x34CB3++0x00
line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad SPR:0x34CB5++0x00
line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad SPR:0x34CB0++0x00
line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad SPR:0x34CB2++0x00
line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad SPR:0x34CB7++0x00
line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad SPR:0x34C94++0x00
line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad SPR:0x34CB1++0x00
line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad SPR:0x23010++0x00
line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad SPR:0x20020++0x00
line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad SPR:0x24070++0x00
line.long 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
newline
bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
newline
bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
group.quad SPR:0x20002++0x00
line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20022++0x00
line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High"
bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High"
bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High"
bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled"
group.quad SPR:0x20032++0x00
line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20062++0x00
line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad SPR:0x20104++0x00
line.long 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad SPR:0x20114++0x00
line.long 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
group.quad SPR:0x20134++0x00
line.long 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad SPR:0x20144++0x00
line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad SPR:0x20786++0x00
line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad SPR:0x20796++0x00
line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad SPR:0x207E6++0x00
line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
group.quad SPR:0x33450++0x00
line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x0)++0x0
line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x10)++0x0
line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x20)++0x0
line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x30)++0x0
line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x40)++0x0
line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x50)++0x0
line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0"
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1"
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2"
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3"
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0300++0x0
line.long 0x0 "TLBTR,TLB Type Register"
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4"
elif corename()=="CORTEXA53"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..."
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.long c15:0x0600++0x0
line.long 0x0 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
group.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
if corename()=="CORTEXA57"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
elif corename()=="CORTEXA53"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,System Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
newline
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
newline
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
newline
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
newline
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
newline
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
newline
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
endif
if corename()=="CORTEXA57"
group.long c15:0x0201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes"
newline
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
elif corename()=="CORTEXA53"
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
newline
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
endif
group.long c15:0x0011++0x0
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
if corename()=="CORTEXA57"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
elif corename()=="CORTEXA53"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
endif
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
endif
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
if corename()=="CORTEXA57"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]"
elif corename()=="CORTEXA53"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]"
endif
group.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE Process ID register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA57"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
// MPIDR[31]==1 case is missing here for TTBR0 and TTBR1
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
endif
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
else
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
endif
tree.end
newline
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
endif
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x0
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
if corename()=="CORTEXA57"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
elif corename()=="CORTEXA53"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
newline
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
newline
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
newline
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
endif
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..."
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..."
newline
hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13"
bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT"
newline
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
endif
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x0
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
group.long c15:0x2000++0x0
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
if corename()=="CORTEXA57"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
elif corename()=="CORTEXA53"
rgroup.long c15:0x300F++0x00
line.long 0x00 "CDBGDR0,Cache Debug Data Register 0"
rgroup.long c15:0x310F++0x00
line.long 0x00 "CDBGDR1,Cache Debug Data Register 1"
rgroup.long c15:0x320F++0x00
line.long 0x00 "CDBGDR2,Cache Debug Data Register 2"
rgroup.long c15:0x330F++0x00
line.long 0x00 "CDBGDR3,Cache Debug Data Register 3"
wgroup.long c15:0x302F++0x00
line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register"
wgroup.long c15:0x312F++0x00
line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x304F++0x00
line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register"
wgroup.long c15:0x314F++0x00
line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register"
wgroup.long c15:0x324F++0x00
line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register"
endif
tree.end
tree "Level 2 memory system"
if corename()=="CORTEXA57"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
newline
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported"
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present"
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
newline
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
newline
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
newline
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
newline
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif corename()=="CORTEXA53"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
newline
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow"
eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow"
eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow"
eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow"
eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow"
eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow"
eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow"
eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow"
eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow"
eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow"
eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow"
eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow"
eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow"
eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow"
eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow"
eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow"
eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow"
eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow"
eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow"
eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment"
bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment"
newline
bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment"
bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment"
newline
bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment"
bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment"
newline
bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment"
bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment"
bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment"
newline
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
newline
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
if (((per.l(c15:0x4CC))&0x3800)==0x00)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
elif (((per.l(c15:0x4CC))&0x3800)==0x800)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
endif
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
if corename()=="CORTEXA53"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
endif
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA57"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
elif corename()=="CORTEXA53"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
newline
bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x0
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
newline
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
newline
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address"
hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid"
newline
bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
tree.end
tree "Breakpoint Registers"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
group.long c14:0x0141++0x0
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
group.long c14:0x0151++0x0
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
tree.end
tree "Watchpoint Control Registers"
group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0"
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1"
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2"
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3"
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.open "Interrupt Controller (GIC-500)"
base COMP.BASE("GICD",-1.)
width 17.
tree "Distributor Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 6. "       DS            ,Disable Security" "No,Yes"
textline "                          "
bitfld.long 0x00 5. " ARE_NS       ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_S      ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       ENABLEGRP1S   ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_NS        ,Affinity Routing Enable" "Reserved,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1A  ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
rbitfld.long 0x00 6. "       DS            ,Disable Security" "Reserved,Yes"
textline "                          "
bitfld.long 0x00 4. " ARE          ,Affinity Routing Enable" "Reserved,Enabled"
bitfld.long 0x00 1. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0    ,Enable Group 0 interrupts" "Disabled,Enabled"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 25. " NO1N         ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
bitfld.long 0x00 24. "  A3V        ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
bitfld.long 0x00 19.--23. "  IDBITS        ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
textline "                          "
bitfld.long 0x00 17. " LPIS         ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
bitfld.long 0x00 16. "  MBIS       ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
bitfld.long 0x00 10. "  SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER    ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 0.--4. "              ITLN       ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID       ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "        VAR        ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV          ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "             IMP        ,Implementer"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
wgroup.long 0x40++0x03
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
else
hgroup.long 0x40++0x03
hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hgroup.long 0x48++0x03
hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register"
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register"
endif
width 17.
tree "Group Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30  ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29  ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27  ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26  ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24  ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23  ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21  ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20  ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18  ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17  ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15  ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14  ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12  ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11  ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9   ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8   ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6   ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5   ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3   ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2   ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0   ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30  ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29  ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27  ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26  ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24  ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23  ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21  ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20  ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18  ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17  ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15  ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14  ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12  ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11  ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9   ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8   ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6   ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5   ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3   ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2   ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0   ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x0080++0x03
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB62  ,Group Status Bit 62" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB61  ,Group Status Bit 61" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB59  ,Group Status Bit 59" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB58  ,Group Status Bit 58" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB56  ,Group Status Bit 56" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB55  ,Group Status Bit 55" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB53  ,Group Status Bit 53" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB52  ,Group Status Bit 52" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB50  ,Group Status Bit 50" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB49  ,Group Status Bit 49" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB47  ,Group Status Bit 47" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB46  ,Group Status Bit 46" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB44  ,Group Status Bit 44" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB43  ,Group Status Bit 43" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB41  ,Group Status Bit 41" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB40  ,Group Status Bit 40" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB38  ,Group Status Bit 38" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB37  ,Group Status Bit 37" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB35  ,Group Status Bit 35" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB34  ,Group Status Bit 34" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB32  ,Group Status Bit 32" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB62  ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB61  ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB59  ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB58  ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB56  ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB55  ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB53  ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB52  ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB50  ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB49  ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB47  ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB46  ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB44  ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB43  ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB41  ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB40  ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB38  ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB37  ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB35  ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB34  ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB32  ,Group Status Bit 32" "Group 0,Group 1"
else
hgroup.long 0x0084++0x03
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB94  ,Group Status Bit 94" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB93  ,Group Status Bit 93" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB91  ,Group Status Bit 91" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB90  ,Group Status Bit 90" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB88  ,Group Status Bit 88" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB87  ,Group Status Bit 87" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB85  ,Group Status Bit 85" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB84  ,Group Status Bit 84" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB82  ,Group Status Bit 82" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB81  ,Group Status Bit 81" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB79  ,Group Status Bit 79" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB78  ,Group Status Bit 78" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB76  ,Group Status Bit 76" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB75  ,Group Status Bit 75" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB73  ,Group Status Bit 73" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB72  ,Group Status Bit 72" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB70  ,Group Status Bit 70" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB69  ,Group Status Bit 69" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB67  ,Group Status Bit 67" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB66  ,Group Status Bit 66" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB64  ,Group Status Bit 64" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB94  ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB93  ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB91  ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB90  ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB88  ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB87  ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB85  ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB84  ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB82  ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB81  ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB79  ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB78  ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB76  ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB75  ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB73  ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB72  ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB70  ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB69  ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB67  ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB66  ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB64  ,Group Status Bit 64" "Group 0,Group 1"
else
hgroup.long 0x0088++0x03
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB99  ,Group Status Bit 99" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB98  ,Group Status Bit 98" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB96  ,Group Status Bit 96" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB126 ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB125 ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB123 ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB122 ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB120 ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB119 ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB117 ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB116 ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB114 ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB113 ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB111 ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB110 ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB108 ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB107 ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB105 ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB104 ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB102 ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB101 ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB99  ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB98  ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB96  ,Group Status Bit 96" "Group 0,Group 1"
else
hgroup.long 0x008C++0x03
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB158 ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB157 ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB155 ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB154 ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB152 ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB151 ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB149 ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB148 ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB146 ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB145 ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB143 ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB142 ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB140 ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB139 ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB137 ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB136 ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB134 ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB133 ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB131 ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB130 ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB128 ,Group Status Bit 128" "Group 0,Group 1"
else
hgroup.long 0x0090++0x03
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB190 ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB189 ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB187 ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB186 ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB184 ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB183 ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB181 ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB180 ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB178 ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB177 ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB175 ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB174 ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB172 ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB171 ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB169 ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB168 ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB166 ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB165 ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB163 ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB162 ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB160 ,Group Status Bit 160" "Group 0,Group 1"
else
hgroup.long 0x0094++0x03
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB222 ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB221 ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB219 ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB218 ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB216 ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB215 ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB213 ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB212 ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB210 ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB209 ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB207 ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB206 ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB204 ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB203 ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB201 ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB200 ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB198 ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB197 ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB195 ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB194 ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB192 ,Group Status Bit 192" "Group 0,Group 1"
else
hgroup.long 0x0098++0x03
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB254 ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB253 ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB251 ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB250 ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB248 ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB247 ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB245 ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB244 ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB242 ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB241 ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB239 ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB238 ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB236 ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB235 ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB233 ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB232 ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB230 ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB229 ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB227 ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB226 ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB224 ,Group Status Bit 224" "Group 0,Group 1"
else
hgroup.long 0x009C++0x03
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB286 ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB285 ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB283 ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB282 ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB280 ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB279 ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB277 ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB276 ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB274 ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB273 ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB271 ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB270 ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB268 ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB267 ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB265 ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB264 ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB262 ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB261 ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB259 ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB258 ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB256 ,Group Status Bit 256" "Group 0,Group 1"
else
hgroup.long 0x00A0++0x03
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB318 ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB317 ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB315 ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB314 ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB312 ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB311 ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB309 ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB308 ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB306 ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB305 ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB303 ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB302 ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB300 ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB299 ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB297 ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB296 ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB294 ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB293 ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB291 ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB290 ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB288 ,Group Status Bit 288" "Group 0,Group 1"
else
hgroup.long 0x00A4++0x03
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB350 ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB349 ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB347 ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB346 ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB344 ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB343 ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB341 ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB340 ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB338 ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB337 ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB335 ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB334 ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB332 ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB331 ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB329 ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB328 ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB326 ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB325 ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB323 ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB322 ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB320 ,Group Status Bit 320" "Group 0,Group 1"
else
hgroup.long 0x00A8++0x03
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB382 ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB381 ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB379 ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB378 ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB376 ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB375 ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB373 ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB372 ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB370 ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB369 ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB367 ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB366 ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB364 ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB363 ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB361 ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB360 ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB358 ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB357 ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB355 ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB354 ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB352 ,Group Status Bit 352" "Group 0,Group 1"
else
hgroup.long 0x00AC++0x03
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB414 ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB413 ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB411 ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB410 ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB408 ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB407 ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB405 ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB404 ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB402 ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB401 ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB399 ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB398 ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB396 ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB395 ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB393 ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB392 ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB390 ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB389 ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB387 ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB386 ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB384 ,Group Status Bit 384" "Group 0,Group 1"
else
hgroup.long 0x00B0++0x03
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB446 ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB445 ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB443 ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB442 ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB440 ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB439 ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB437 ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB436 ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB434 ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB433 ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB431 ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB430 ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB428 ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB427 ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB425 ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB424 ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB422 ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB421 ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB419 ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB418 ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB416 ,Group Status Bit 416" "Group 0,Group 1"
else
hgroup.long 0x00B4++0x03
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB478 ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB477 ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB475 ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB474 ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB472 ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB471 ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB469 ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB468 ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB466 ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB465 ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB463 ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB462 ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB460 ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB459 ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB457 ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB456 ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB454 ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB453 ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB451 ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB450 ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB448 ,Group Status Bit 448" "Group 0,Group 1"
else
hgroup.long 0x00B8++0x03
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB510 ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB509 ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB507 ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB506 ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB504 ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB503 ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB501 ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB500 ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB498 ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB497 ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB495 ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB494 ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB492 ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB491 ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB489 ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB488 ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB486 ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB485 ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB483 ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB482 ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB480 ,Group Status Bit 480" "Group 0,Group 1"
else
hgroup.long 0x00BC++0x03
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB542 ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB541 ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB539 ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB538 ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB536 ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB535 ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB533 ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB532 ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB530 ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB529 ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB527 ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB526 ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB524 ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB523 ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB521 ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB520 ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB518 ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB517 ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB515 ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB514 ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB512 ,Group Status Bit 512" "Group 0,Group 1"
else
hgroup.long 0x00C0++0x03
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB574 ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB573 ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB571 ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB570 ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB568 ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB567 ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB565 ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB564 ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB562 ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB561 ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB559 ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB558 ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB556 ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB555 ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB553 ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB552 ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB550 ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB549 ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB547 ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB546 ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB544 ,Group Status Bit 544" "Group 0,Group 1"
else
hgroup.long 0x00C4++0x03
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB606 ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB605 ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB603 ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB602 ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB600 ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB599 ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB597 ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB596 ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB594 ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB593 ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB591 ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB590 ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB588 ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB587 ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB585 ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB584 ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB582 ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB581 ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB579 ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB578 ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB576 ,Group Status Bit 576" "Group 0,Group 1"
else
hgroup.long 0x00C8++0x03
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB638 ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB637 ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB635 ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB634 ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB632 ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB631 ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB629 ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB628 ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB626 ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB625 ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB623 ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB622 ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB620 ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB619 ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB617 ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB616 ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB614 ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB613 ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB611 ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB610 ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB608 ,Group Status Bit 608" "Group 0,Group 1"
else
hgroup.long 0x00CC++0x03
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB670 ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB669 ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB667 ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB666 ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB664 ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB663 ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB661 ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB660 ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB658 ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB657 ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB655 ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB654 ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB652 ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB651 ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB649 ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB648 ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB646 ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB645 ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB643 ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB642 ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB640 ,Group Status Bit 640" "Group 0,Group 1"
else
hgroup.long 0x00D0++0x03
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB702 ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB701 ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB699 ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB698 ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB696 ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB695 ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB693 ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB692 ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB690 ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB689 ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB687 ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB686 ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB684 ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB683 ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB681 ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB680 ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB678 ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB677 ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB675 ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB674 ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB672 ,Group Status Bit 672" "Group 0,Group 1"
else
hgroup.long 0x00D4++0x03
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB734 ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB733 ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB731 ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB730 ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB728 ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB727 ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB725 ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB724 ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB722 ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB721 ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB719 ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB718 ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB716 ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB715 ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB713 ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB712 ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB710 ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB709 ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB707 ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB706 ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB704 ,Group Status Bit 704" "Group 0,Group 1"
else
hgroup.long 0x00D8++0x03
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB766 ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB765 ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB763 ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB762 ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB760 ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB759 ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB757 ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB756 ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB754 ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB753 ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB751 ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB750 ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB748 ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB747 ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB745 ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB744 ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB742 ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB741 ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB739 ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB738 ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB736 ,Group Status Bit 736" "Group 0,Group 1"
else
hgroup.long 0x00DC++0x03
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB798 ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB797 ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB795 ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB794 ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB792 ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB791 ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB789 ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB788 ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB786 ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB785 ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB783 ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB782 ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB780 ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB779 ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB777 ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB776 ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB774 ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB773 ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB771 ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB770 ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB768 ,Group Status Bit 768" "Group 0,Group 1"
else
hgroup.long 0x00E0++0x03
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB830 ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB829 ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB827 ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB826 ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB824 ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB823 ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB821 ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB820 ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB818 ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB817 ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB815 ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB814 ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB812 ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB811 ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB809 ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB808 ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB806 ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB805 ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB803 ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB802 ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB800 ,Group Status Bit 800" "Group 0,Group 1"
else
hgroup.long 0x00E4++0x03
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB862 ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB861 ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB859 ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB858 ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB856 ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB855 ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB853 ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB852 ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB850 ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB849 ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB847 ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB846 ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB844 ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB843 ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB841 ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB840 ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB838 ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB837 ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB835 ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB834 ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB832 ,Group Status Bit 832" "Group 0,Group 1"
else
hgroup.long 0x00E8++0x03
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB894 ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB893 ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB891 ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB890 ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB888 ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB887 ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB885 ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB884 ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB882 ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB881 ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB879 ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB878 ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB876 ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB875 ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB873 ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB872 ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB870 ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB869 ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB867 ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB866 ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB864 ,Group Status Bit 864" "Group 0,Group 1"
else
hgroup.long 0x00EC++0x03
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB926 ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB925 ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB923 ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB922 ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB920 ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB919 ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB917 ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB916 ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB914 ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB913 ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB911 ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB910 ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB908 ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB907 ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB905 ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB904 ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB902 ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB901 ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB899 ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB898 ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB896 ,Group Status Bit 896" "Group 0,Group 1"
else
hgroup.long 0x00F0++0x03
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB958 ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB957 ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB955 ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB954 ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB952 ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB951 ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB949 ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB948 ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB946 ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB945 ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB943 ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB942 ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB940 ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB939 ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB937 ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB936 ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB934 ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB933 ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB931 ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB930 ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB928 ,Group Status Bit 928" "Group 0,Group 1"
else
hgroup.long 0x00F4++0x03
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB990 ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB989 ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB987 ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB986 ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB984 ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB983 ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB981 ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB980 ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB978 ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB977 ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB975 ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB974 ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB972 ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB971 ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB969 ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB968 ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB966 ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB965 ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB963 ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB962 ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB960 ,Group Status Bit 960" "Group 0,Group 1"
else
hgroup.long 0x00F8++0x03
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
endif
tree.end
width 24.
tree "Set/Clear Enable Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0100++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
hgroup.long 0x0104++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
hgroup.long 0x0108++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
hgroup.long 0x010C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
hgroup.long 0x0110++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
hgroup.long 0x0114++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
hgroup.long 0x0118++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
hgroup.long 0x011C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
hgroup.long 0x0120++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
hgroup.long 0x0124++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
hgroup.long 0x0128++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
hgroup.long 0x012C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
hgroup.long 0x0130++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
hgroup.long 0x0134++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
hgroup.long 0x0138++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
hgroup.long 0x013C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
hgroup.long 0x0140++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
hgroup.long 0x0144++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
hgroup.long 0x0148++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
hgroup.long 0x014C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
hgroup.long 0x0150++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
hgroup.long 0x0154++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
hgroup.long 0x0158++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
hgroup.long 0x015C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
hgroup.long 0x0160++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
hgroup.long 0x0164++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
hgroup.long 0x0168++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
hgroup.long 0x016C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
hgroup.long 0x0170++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
hgroup.long 0x0174++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
hgroup.long 0x0178++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0200++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
hgroup.long 0x0204++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
hgroup.long 0x0208++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
hgroup.long 0x020C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
hgroup.long 0x0210++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
hgroup.long 0x0214++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
hgroup.long 0x0218++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
hgroup.long 0x021C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
hgroup.long 0x0220++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
hgroup.long 0x0224++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
hgroup.long 0x0228++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
hgroup.long 0x022C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
hgroup.long 0x0230++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
hgroup.long 0x0234++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
hgroup.long 0x0238++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
hgroup.long 0x023C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
hgroup.long 0x0240++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
hgroup.long 0x0244++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
hgroup.long 0x0248++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
hgroup.long 0x024C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
hgroup.long 0x0250++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
hgroup.long 0x0254++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
hgroup.long 0x0258++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
hgroup.long 0x025C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
hgroup.long 0x0260++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
hgroup.long 0x0264++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
hgroup.long 0x0268++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
hgroup.long 0x026C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
hgroup.long 0x0270++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
hgroup.long 0x0274++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
hgroup.long 0x0278++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0300++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
hgroup.long 0x0304++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
hgroup.long 0x0308++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
hgroup.long 0x030C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
hgroup.long 0x0310++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
hgroup.long 0x0314++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
hgroup.long 0x0318++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
hgroup.long 0x031C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
hgroup.long 0x0320++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
hgroup.long 0x0324++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
hgroup.long 0x0328++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
hgroup.long 0x032C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
hgroup.long 0x0330++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
hgroup.long 0x0334++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
hgroup.long 0x0338++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
hgroup.long 0x033C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
else
hgroup.long 0x0340++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
else
hgroup.long 0x0344++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
else
hgroup.long 0x0348++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
else
hgroup.long 0x034C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
else
hgroup.long 0x0350++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
else
hgroup.long 0x0354++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
else
hgroup.long 0x0358++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
else
hgroup.long 0x035C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
else
hgroup.long 0x0360++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
else
hgroup.long 0x0364++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
else
hgroup.long 0x0368++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
else
hgroup.long 0x036C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
else
hgroup.long 0x0370++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
else
hgroup.long 0x0374++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
else
hgroup.long 0x0378++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
endif
tree.end
width 20.
tree "Priority Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x400++0x03
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hgroup.long 0x404++0x03
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hgroup.long 0x408++0x03
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hgroup.long 0x40C++0x03
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hgroup.long 0x410++0x03
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hgroup.long 0x414++0x03
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hgroup.long 0x418++0x03
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hgroup.long 0x41C++0x03
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
else
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
hgroup.long 0x420++0x03
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hgroup.long 0x424++0x03
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hgroup.long 0x428++0x03
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hgroup.long 0x42C++0x03
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hgroup.long 0x430++0x03
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hgroup.long 0x434++0x03
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hgroup.long 0x438++0x03
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hgroup.long 0x43C++0x03
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
hgroup.long 0x440++0x03
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hgroup.long 0x444++0x03
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hgroup.long 0x448++0x03
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hgroup.long 0x44C++0x03
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hgroup.long 0x450++0x03
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hgroup.long 0x454++0x03
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hgroup.long 0x458++0x03
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hgroup.long 0x45C++0x03
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
hgroup.long 0x460++0x03
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hgroup.long 0x464++0x03
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hgroup.long 0x468++0x03
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hgroup.long 0x46C++0x03
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hgroup.long 0x470++0x03
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hgroup.long 0x474++0x03
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hgroup.long 0x478++0x03
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hgroup.long 0x47C++0x03
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
hgroup.long 0x480++0x03
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hgroup.long 0x484++0x03
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hgroup.long 0x488++0x03
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hgroup.long 0x48C++0x03
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hgroup.long 0x490++0x03
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hgroup.long 0x494++0x03
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hgroup.long 0x498++0x03
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hgroup.long 0x49C++0x03
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
hgroup.long 0x4A0++0x03
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hgroup.long 0x4A4++0x03
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hgroup.long 0x4A8++0x03
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hgroup.long 0x4AC++0x03
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hgroup.long 0x4B0++0x03
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hgroup.long 0x4B4++0x03
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hgroup.long 0x4B8++0x03
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hgroup.long 0x4BC++0x03
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
hgroup.long 0x4C0++0x03
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hgroup.long 0x4C4++0x03
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hgroup.long 0x4C8++0x03
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hgroup.long 0x4CC++0x03
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hgroup.long 0x4D0++0x03
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hgroup.long 0x4D4++0x03
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hgroup.long 0x4D8++0x03
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hgroup.long 0x4DC++0x03
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
hgroup.long 0x4E0++0x03
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hgroup.long 0x4E4++0x03
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hgroup.long 0x4E8++0x03
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hgroup.long 0x4EC++0x03
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hgroup.long 0x4F0++0x03
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hgroup.long 0x4F4++0x03
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hgroup.long 0x4F8++0x03
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hgroup.long 0x4FC++0x03
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
hgroup.long 0x500++0x03
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hgroup.long 0x504++0x03
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hgroup.long 0x508++0x03
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hgroup.long 0x50C++0x03
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hgroup.long 0x510++0x03
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hgroup.long 0x514++0x03
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hgroup.long 0x518++0x03
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hgroup.long 0x51C++0x03
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
hgroup.long 0x520++0x03
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hgroup.long 0x524++0x03
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hgroup.long 0x528++0x03
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hgroup.long 0x52C++0x03
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hgroup.long 0x530++0x03
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hgroup.long 0x534++0x03
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hgroup.long 0x538++0x03
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hgroup.long 0x53C++0x03
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
hgroup.long 0x540++0x03
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hgroup.long 0x544++0x03
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hgroup.long 0x548++0x03
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hgroup.long 0x54C++0x03
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hgroup.long 0x550++0x03
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hgroup.long 0x554++0x03
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hgroup.long 0x558++0x03
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hgroup.long 0x55C++0x03
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
hgroup.long 0x560++0x03
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hgroup.long 0x564++0x03
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hgroup.long 0x568++0x03
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hgroup.long 0x56C++0x03
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hgroup.long 0x570++0x03
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hgroup.long 0x574++0x03
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hgroup.long 0x578++0x03
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hgroup.long 0x57C++0x03
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
hgroup.long 0x580++0x03
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hgroup.long 0x584++0x03
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hgroup.long 0x588++0x03
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hgroup.long 0x58C++0x03
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hgroup.long 0x590++0x03
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hgroup.long 0x594++0x03
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hgroup.long 0x598++0x03
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hgroup.long 0x59C++0x03
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
hgroup.long 0x5A0++0x03
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hgroup.long 0x5A4++0x03
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hgroup.long 0x5A8++0x03
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hgroup.long 0x5AC++0x03
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hgroup.long 0x5B0++0x03
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hgroup.long 0x5B4++0x03
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hgroup.long 0x5B8++0x03
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hgroup.long 0x5BC++0x03
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
hgroup.long 0x5C0++0x03
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hgroup.long 0x5C4++0x03
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hgroup.long 0x5C8++0x03
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hgroup.long 0x5CC++0x03
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hgroup.long 0x5D0++0x03
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hgroup.long 0x5D4++0x03
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hgroup.long 0x5D8++0x03
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hgroup.long 0x5DC++0x03
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
hgroup.long 0x5E0++0x03
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hgroup.long 0x5E4++0x03
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hgroup.long 0x5E8++0x03
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hgroup.long 0x5EC++0x03
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hgroup.long 0x5F0++0x03
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hgroup.long 0x5F4++0x03
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hgroup.long 0x5F8++0x03
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hgroup.long 0x5FC++0x03
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
hgroup.long 0x600++0x03
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hgroup.long 0x604++0x03
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hgroup.long 0x608++0x03
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hgroup.long 0x60C++0x03
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hgroup.long 0x610++0x03
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hgroup.long 0x614++0x03
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hgroup.long 0x618++0x03
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hgroup.long 0x61C++0x03
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
hgroup.long 0x620++0x03
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hgroup.long 0x624++0x03
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hgroup.long 0x628++0x03
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hgroup.long 0x62C++0x03
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hgroup.long 0x630++0x03
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hgroup.long 0x634++0x03
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hgroup.long 0x638++0x03
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hgroup.long 0x63C++0x03
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
hgroup.long 0x640++0x03
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hgroup.long 0x644++0x03
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hgroup.long 0x648++0x03
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hgroup.long 0x64C++0x03
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hgroup.long 0x650++0x03
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hgroup.long 0x654++0x03
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hgroup.long 0x658++0x03
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hgroup.long 0x65C++0x03
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
hgroup.long 0x660++0x03
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hgroup.long 0x664++0x03
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hgroup.long 0x668++0x03
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hgroup.long 0x66C++0x03
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hgroup.long 0x670++0x03
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hgroup.long 0x674++0x03
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hgroup.long 0x678++0x03
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hgroup.long 0x67C++0x03
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
hgroup.long 0x680++0x03
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hgroup.long 0x684++0x03
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hgroup.long 0x688++0x03
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hgroup.long 0x68C++0x03
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hgroup.long 0x690++0x03
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hgroup.long 0x694++0x03
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hgroup.long 0x698++0x03
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hgroup.long 0x69C++0x03
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
hgroup.long 0x6A0++0x03
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hgroup.long 0x6A4++0x03
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hgroup.long 0x6A8++0x03
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hgroup.long 0x6AC++0x03
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hgroup.long 0x6B0++0x03
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hgroup.long 0x6B4++0x03
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hgroup.long 0x6B8++0x03
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hgroup.long 0x6BC++0x03
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
hgroup.long 0x6C0++0x03
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hgroup.long 0x6C4++0x03
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hgroup.long 0x6C8++0x03
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hgroup.long 0x6CC++0x03
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hgroup.long 0x6D0++0x03
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hgroup.long 0x6D4++0x03
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hgroup.long 0x6D8++0x03
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hgroup.long 0x6DC++0x03
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
hgroup.long 0x6E0++0x03
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hgroup.long 0x6E4++0x03
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hgroup.long 0x6E8++0x03
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hgroup.long 0x6EC++0x03
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hgroup.long 0x6F0++0x03
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hgroup.long 0x6F4++0x03
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hgroup.long 0x6F8++0x03
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hgroup.long 0x6FC++0x03
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
hgroup.long 0x700++0x03
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hgroup.long 0x704++0x03
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hgroup.long 0x708++0x03
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hgroup.long 0x70C++0x03
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hgroup.long 0x710++0x03
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hgroup.long 0x714++0x03
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hgroup.long 0x718++0x03
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hgroup.long 0x71C++0x03
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
hgroup.long 0x720++0x03
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hgroup.long 0x724++0x03
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hgroup.long 0x728++0x03
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hgroup.long 0x72C++0x03
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hgroup.long 0x730++0x03
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hgroup.long 0x734++0x03
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hgroup.long 0x738++0x03
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hgroup.long 0x73C++0x03
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
hgroup.long 0x740++0x03
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hgroup.long 0x744++0x03
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hgroup.long 0x748++0x03
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hgroup.long 0x74C++0x03
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hgroup.long 0x750++0x03
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hgroup.long 0x754++0x03
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hgroup.long 0x758++0x03
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hgroup.long 0x75C++0x03
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
hgroup.long 0x760++0x03
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hgroup.long 0x764++0x03
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hgroup.long 0x768++0x03
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hgroup.long 0x76C++0x03
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hgroup.long 0x770++0x03
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hgroup.long 0x774++0x03
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hgroup.long 0x778++0x03
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hgroup.long 0x77C++0x03
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
hgroup.long 0x780++0x03
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hgroup.long 0x784++0x03
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hgroup.long 0x788++0x03
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hgroup.long 0x78C++0x03
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hgroup.long 0x790++0x03
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hgroup.long 0x794++0x03
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hgroup.long 0x798++0x03
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hgroup.long 0x79C++0x03
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
hgroup.long 0x7A0++0x03
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hgroup.long 0x7A4++0x03
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hgroup.long 0x7A8++0x03
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hgroup.long 0x7AC++0x03
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hgroup.long 0x7B0++0x03
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hgroup.long 0x7B4++0x03
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hgroup.long 0x7B8++0x03
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hgroup.long 0x7BC++0x03
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
hgroup.long 0x7C0++0x03
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hgroup.long 0x7C4++0x03
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hgroup.long 0x7C8++0x03
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hgroup.long 0x7CC++0x03
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hgroup.long 0x7D0++0x03
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hgroup.long 0x7D4++0x03
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hgroup.long 0x7D8++0x03
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hgroup.long 0x7DC++0x03
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
tree.end
width 19.
tree "Interrupt Targets Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
else
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SGI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SGI)" "Level,Edge"
group.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (PPI)" "Level,Edge"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC08++0x03
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
hgroup.long 0xC0C++0x03
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC10++0x03
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
hgroup.long 0xC14++0x03
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC18++0x03
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
hgroup.long 0xC1C++0x03
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC20++0x03
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
hgroup.long 0xC24++0x03
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC28++0x03
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
hgroup.long 0xC2C++0x03
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC30++0x03
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
hgroup.long 0xC34++0x03
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC38++0x03
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
hgroup.long 0xC3C++0x03
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC40++0x03
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
hgroup.long 0xC44++0x03
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC48++0x03
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
hgroup.long 0xC4C++0x03
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC50++0x03
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
hgroup.long 0xC54++0x03
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC58++0x03
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
hgroup.long 0xC5C++0x03
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC60++0x03
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
hgroup.long 0xC64++0x03
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC68++0x03
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
hgroup.long 0xC6C++0x03
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC70++0x03
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
hgroup.long 0xC74++0x03
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC78++0x03
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
hgroup.long 0xC7C++0x03
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC80++0x03
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
hgroup.long 0xC84++0x03
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC88++0x03
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
hgroup.long 0xC8C++0x03
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC90++0x03
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
hgroup.long 0xC94++0x03
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC98++0x03
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
hgroup.long 0xC9C++0x03
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA0++0x03
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
hgroup.long 0xCA4++0x03
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA8++0x03
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
hgroup.long 0xCAC++0x03
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB0++0x03
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
hgroup.long 0xCB4++0x03
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB8++0x03
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
hgroup.long 0xCBC++0x03
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC0++0x03
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
hgroup.long 0xCC4++0x03
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC8++0x03
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
hgroup.long 0xCCC++0x03
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD0++0x03
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
hgroup.long 0xCD4++0x03
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD8++0x03
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
hgroup.long 0xCDC++0x03
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE0++0x03
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
hgroup.long 0xCE4++0x03
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE8++0x03
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
hgroup.long 0xCEC++0x03
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCF0++0x03
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
hgroup.long 0xCF4++0x03
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
tree.end
width 17.
tree "Interrupt Group Modifier Registers"
hgroup.long 0x0D00++0x03
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
group.long 0x0D04++0x03
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
bitfld.long 0x00 31. " GMB63  ,Group Modifier Bit 63" "0,1"
bitfld.long 0x00 30. "  GMB62  ,Group Modifier Bit 62" "0,1"
bitfld.long 0x00 29. "  GMB61  ,Group Modifier Bit 61" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB60  ,Group Modifier Bit 60" "0,1"
bitfld.long 0x00 27. "  GMB59  ,Group Modifier Bit 59" "0,1"
bitfld.long 0x00 26. "  GMB58  ,Group Modifier Bit 58" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB57  ,Group Modifier Bit 57" "0,1"
bitfld.long 0x00 24. "  GMB56  ,Group Modifier Bit 56" "0,1"
bitfld.long 0x00 23. "  GMB55  ,Group Modifier Bit 55" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB54  ,Group Modifier Bit 54" "0,1"
bitfld.long 0x00 21. "  GMB53  ,Group Modifier Bit 53" "0,1"
bitfld.long 0x00 20. "  GMB52  ,Group Modifier Bit 52" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB51  ,Group Modifier Bit 51" "0,1"
bitfld.long 0x00 18. "  GMB50  ,Group Modifier Bit 50" "0,1"
bitfld.long 0x00 17. "  GMB49  ,Group Modifier Bit 49" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB48  ,Group Modifier Bit 48" "0,1"
bitfld.long 0x00 15. "  GMB47  ,Group Modifier Bit 47" "0,1"
bitfld.long 0x00 14. "  GMB46  ,Group Modifier Bit 46" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB45  ,Group Modifier Bit 45" "0,1"
bitfld.long 0x00 12. "  GMB44  ,Group Modifier Bit 44" "0,1"
bitfld.long 0x00 11. "  GMB43  ,Group Modifier Bit 43" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB42  ,Group Modifier Bit 42" "0,1"
bitfld.long 0x00 9. "  GMB41  ,Group Modifier Bit 41" "0,1"
bitfld.long 0x00 8. "  GMB40  ,Group Modifier Bit 40" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB39  ,Group Modifier Bit 39" "0,1"
bitfld.long 0x00 6. "  GMB38  ,Group Modifier Bit 38" "0,1"
bitfld.long 0x00 5. "  GMB37  ,Group Modifier Bit 37" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB36  ,Group Modifier Bit 36" "0,1"
bitfld.long 0x00 3. "  GMB35  ,Group Modifier Bit 35" "0,1"
bitfld.long 0x00 2. "  GMB34  ,Group Modifier Bit 34" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB33  ,Group Modifier Bit 33" "0,1"
bitfld.long 0x00 0. "  GMB32  ,Group Modifier Bit 32" "0,1"
else
hgroup.long 0x0D04++0x03
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
group.long 0x0D08++0x03
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
bitfld.long 0x00 31. " GMB95  ,Group Modifier Bit 95" "0,1"
bitfld.long 0x00 30. "  GMB94  ,Group Modifier Bit 94" "0,1"
bitfld.long 0x00 29. "  GMB93  ,Group Modifier Bit 93" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB92  ,Group Modifier Bit 92" "0,1"
bitfld.long 0x00 27. "  GMB91  ,Group Modifier Bit 91" "0,1"
bitfld.long 0x00 26. "  GMB90  ,Group Modifier Bit 90" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB89  ,Group Modifier Bit 89" "0,1"
bitfld.long 0x00 24. "  GMB88  ,Group Modifier Bit 88" "0,1"
bitfld.long 0x00 23. "  GMB87  ,Group Modifier Bit 87" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB86  ,Group Modifier Bit 86" "0,1"
bitfld.long 0x00 21. "  GMB85  ,Group Modifier Bit 85" "0,1"
bitfld.long 0x00 20. "  GMB84  ,Group Modifier Bit 84" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB83  ,Group Modifier Bit 83" "0,1"
bitfld.long 0x00 18. "  GMB82  ,Group Modifier Bit 82" "0,1"
bitfld.long 0x00 17. "  GMB81  ,Group Modifier Bit 81" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB80  ,Group Modifier Bit 80" "0,1"
bitfld.long 0x00 15. "  GMB79  ,Group Modifier Bit 79" "0,1"
bitfld.long 0x00 14. "  GMB78  ,Group Modifier Bit 78" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB77  ,Group Modifier Bit 77" "0,1"
bitfld.long 0x00 12. "  GMB76  ,Group Modifier Bit 76" "0,1"
bitfld.long 0x00 11. "  GMB75  ,Group Modifier Bit 75" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB74  ,Group Modifier Bit 74" "0,1"
bitfld.long 0x00 9. "  GMB73  ,Group Modifier Bit 73" "0,1"
bitfld.long 0x00 8. "  GMB72  ,Group Modifier Bit 72" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB71  ,Group Modifier Bit 71" "0,1"
bitfld.long 0x00 6. "  GMB70  ,Group Modifier Bit 70" "0,1"
bitfld.long 0x00 5. "  GMB69  ,Group Modifier Bit 69" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB68  ,Group Modifier Bit 68" "0,1"
bitfld.long 0x00 3. "  GMB67  ,Group Modifier Bit 67" "0,1"
bitfld.long 0x00 2. "  GMB66  ,Group Modifier Bit 66" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB65  ,Group Modifier Bit 65" "0,1"
bitfld.long 0x00 0. "  GMB64  ,Group Modifier Bit 64" "0,1"
else
hgroup.long 0x0D08++0x03
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
group.long 0x0D0C++0x03
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
bitfld.long 0x00 30. "  GMB126 ,Group Modifier Bit 126" "0,1"
bitfld.long 0x00 29. "  GMB125 ,Group Modifier Bit 125" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
bitfld.long 0x00 27. "  GMB123 ,Group Modifier Bit 123" "0,1"
bitfld.long 0x00 26. "  GMB122 ,Group Modifier Bit 122" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
bitfld.long 0x00 24. "  GMB120 ,Group Modifier Bit 120" "0,1"
bitfld.long 0x00 23. "  GMB119 ,Group Modifier Bit 119" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
bitfld.long 0x00 21. "  GMB117 ,Group Modifier Bit 117" "0,1"
bitfld.long 0x00 20. "  GMB116 ,Group Modifier Bit 116" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
bitfld.long 0x00 18. "  GMB114 ,Group Modifier Bit 114" "0,1"
bitfld.long 0x00 17. "  GMB113 ,Group Modifier Bit 113" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
bitfld.long 0x00 15. "  GMB111 ,Group Modifier Bit 111" "0,1"
bitfld.long 0x00 14. "  GMB110 ,Group Modifier Bit 110" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
bitfld.long 0x00 12. "  GMB108 ,Group Modifier Bit 108" "0,1"
bitfld.long 0x00 11. "  GMB107 ,Group Modifier Bit 107" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
bitfld.long 0x00 9. "  GMB105 ,Group Modifier Bit 105" "0,1"
bitfld.long 0x00 8. "  GMB104 ,Group Modifier Bit 104" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
bitfld.long 0x00 6. "  GMB102 ,Group Modifier Bit 102" "0,1"
bitfld.long 0x00 5. "  GMB101 ,Group Modifier Bit 101" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
bitfld.long 0x00 3. "  GMB99  ,Group Modifier Bit 99" "0,1"
bitfld.long 0x00 2. "  GMB98  ,Group Modifier Bit 98" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB97  ,Group Modifier Bit 97" "0,1"
bitfld.long 0x00 0. "  GMB96  ,Group Modifier Bit 96" "0,1"
else
hgroup.long 0x0D0C++0x03
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
group.long 0x0D10++0x03
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
bitfld.long 0x00 30. "  GMB158 ,Group Modifier Bit 158" "0,1"
bitfld.long 0x00 29. "  GMB157 ,Group Modifier Bit 157" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
bitfld.long 0x00 27. "  GMB155 ,Group Modifier Bit 155" "0,1"
bitfld.long 0x00 26. "  GMB154 ,Group Modifier Bit 154" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
bitfld.long 0x00 24. "  GMB152 ,Group Modifier Bit 152" "0,1"
bitfld.long 0x00 23. "  GMB151 ,Group Modifier Bit 151" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
bitfld.long 0x00 21. "  GMB149 ,Group Modifier Bit 149" "0,1"
bitfld.long 0x00 20. "  GMB148 ,Group Modifier Bit 148" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
bitfld.long 0x00 18. "  GMB146 ,Group Modifier Bit 146" "0,1"
bitfld.long 0x00 17. "  GMB145 ,Group Modifier Bit 145" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
bitfld.long 0x00 15. "  GMB143 ,Group Modifier Bit 143" "0,1"
bitfld.long 0x00 14. "  GMB142 ,Group Modifier Bit 142" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
bitfld.long 0x00 12. "  GMB140 ,Group Modifier Bit 140" "0,1"
bitfld.long 0x00 11. "  GMB139 ,Group Modifier Bit 139" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
bitfld.long 0x00 9. "  GMB137 ,Group Modifier Bit 137" "0,1"
bitfld.long 0x00 8. "  GMB136 ,Group Modifier Bit 136" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
bitfld.long 0x00 6. "  GMB134 ,Group Modifier Bit 134" "0,1"
bitfld.long 0x00 5. "  GMB133 ,Group Modifier Bit 133" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
bitfld.long 0x00 3. "  GMB131 ,Group Modifier Bit 131" "0,1"
bitfld.long 0x00 2. "  GMB130 ,Group Modifier Bit 130" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
bitfld.long 0x00 0. "  GMB128 ,Group Modifier Bit 128" "0,1"
else
hgroup.long 0x0D10++0x03
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
group.long 0x0D14++0x03
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
bitfld.long 0x00 30. "  GMB190 ,Group Modifier Bit 190" "0,1"
bitfld.long 0x00 29. "  GMB189 ,Group Modifier Bit 189" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
bitfld.long 0x00 27. "  GMB187 ,Group Modifier Bit 187" "0,1"
bitfld.long 0x00 26. "  GMB186 ,Group Modifier Bit 186" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
bitfld.long 0x00 24. "  GMB184 ,Group Modifier Bit 184" "0,1"
bitfld.long 0x00 23. "  GMB183 ,Group Modifier Bit 183" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
bitfld.long 0x00 21. "  GMB181 ,Group Modifier Bit 181" "0,1"
bitfld.long 0x00 20. "  GMB180 ,Group Modifier Bit 180" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
bitfld.long 0x00 18. "  GMB178 ,Group Modifier Bit 178" "0,1"
bitfld.long 0x00 17. "  GMB177 ,Group Modifier Bit 177" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
bitfld.long 0x00 15. "  GMB175 ,Group Modifier Bit 175" "0,1"
bitfld.long 0x00 14. "  GMB174 ,Group Modifier Bit 174" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
bitfld.long 0x00 12. "  GMB172 ,Group Modifier Bit 172" "0,1"
bitfld.long 0x00 11. "  GMB171 ,Group Modifier Bit 171" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
bitfld.long 0x00 9. "  GMB169 ,Group Modifier Bit 169" "0,1"
bitfld.long 0x00 8. "  GMB168 ,Group Modifier Bit 168" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
bitfld.long 0x00 6. "  GMB166 ,Group Modifier Bit 166" "0,1"
bitfld.long 0x00 5. "  GMB165 ,Group Modifier Bit 165" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
bitfld.long 0x00 3. "  GMB163 ,Group Modifier Bit 163" "0,1"
bitfld.long 0x00 2. "  GMB162 ,Group Modifier Bit 162" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
bitfld.long 0x00 0. "  GMB160 ,Group Modifier Bit 160" "0,1"
else
hgroup.long 0x0D14++0x03
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
group.long 0x0D18++0x03
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
bitfld.long 0x00 30. "  GMB222 ,Group Modifier Bit 222" "0,1"
bitfld.long 0x00 29. "  GMB221 ,Group Modifier Bit 221" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
bitfld.long 0x00 27. "  GMB219 ,Group Modifier Bit 219" "0,1"
bitfld.long 0x00 26. "  GMB218 ,Group Modifier Bit 218" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
bitfld.long 0x00 24. "  GMB216 ,Group Modifier Bit 216" "0,1"
bitfld.long 0x00 23. "  GMB215 ,Group Modifier Bit 215" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
bitfld.long 0x00 21. "  GMB213 ,Group Modifier Bit 213" "0,1"
bitfld.long 0x00 20. "  GMB212 ,Group Modifier Bit 212" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
bitfld.long 0x00 18. "  GMB210 ,Group Modifier Bit 210" "0,1"
bitfld.long 0x00 17. "  GMB209 ,Group Modifier Bit 209" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
bitfld.long 0x00 15. "  GMB207 ,Group Modifier Bit 207" "0,1"
bitfld.long 0x00 14. "  GMB206 ,Group Modifier Bit 206" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
bitfld.long 0x00 12. "  GMB204 ,Group Modifier Bit 204" "0,1"
bitfld.long 0x00 11. "  GMB203 ,Group Modifier Bit 203" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
bitfld.long 0x00 9. "  GMB201 ,Group Modifier Bit 201" "0,1"
bitfld.long 0x00 8. "  GMB200 ,Group Modifier Bit 200" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
bitfld.long 0x00 6. "  GMB198 ,Group Modifier Bit 198" "0,1"
bitfld.long 0x00 5. "  GMB197 ,Group Modifier Bit 197" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
bitfld.long 0x00 3. "  GMB195 ,Group Modifier Bit 195" "0,1"
bitfld.long 0x00 2. "  GMB194 ,Group Modifier Bit 194" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
bitfld.long 0x00 0. "  GMB192 ,Group Modifier Bit 192" "0,1"
else
hgroup.long 0x0D18++0x03
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
group.long 0x0D1C++0x03
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
bitfld.long 0x00 30. "  GMB254 ,Group Modifier Bit 254" "0,1"
bitfld.long 0x00 29. "  GMB253 ,Group Modifier Bit 253" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
bitfld.long 0x00 27. "  GMB251 ,Group Modifier Bit 251" "0,1"
bitfld.long 0x00 26. "  GMB250 ,Group Modifier Bit 250" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
bitfld.long 0x00 24. "  GMB248 ,Group Modifier Bit 248" "0,1"
bitfld.long 0x00 23. "  GMB247 ,Group Modifier Bit 247" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
bitfld.long 0x00 21. "  GMB245 ,Group Modifier Bit 245" "0,1"
bitfld.long 0x00 20. "  GMB244 ,Group Modifier Bit 244" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
bitfld.long 0x00 18. "  GMB242 ,Group Modifier Bit 242" "0,1"
bitfld.long 0x00 17. "  GMB241 ,Group Modifier Bit 241" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
bitfld.long 0x00 15. "  GMB239 ,Group Modifier Bit 239" "0,1"
bitfld.long 0x00 14. "  GMB238 ,Group Modifier Bit 238" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
bitfld.long 0x00 12. "  GMB236 ,Group Modifier Bit 236" "0,1"
bitfld.long 0x00 11. "  GMB235 ,Group Modifier Bit 235" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
bitfld.long 0x00 9. "  GMB233 ,Group Modifier Bit 233" "0,1"
bitfld.long 0x00 8. "  GMB232 ,Group Modifier Bit 232" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
bitfld.long 0x00 6. "  GMB230 ,Group Modifier Bit 230" "0,1"
bitfld.long 0x00 5. "  GMB229 ,Group Modifier Bit 229" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
bitfld.long 0x00 3. "  GMB227 ,Group Modifier Bit 227" "0,1"
bitfld.long 0x00 2. "  GMB226 ,Group Modifier Bit 226" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
bitfld.long 0x00 0. "  GMB224 ,Group Modifier Bit 224" "0,1"
else
hgroup.long 0x0D1C++0x03
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
group.long 0x0D20++0x03
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
bitfld.long 0x00 30. "  GMB286 ,Group Modifier Bit 286" "0,1"
bitfld.long 0x00 29. "  GMB285 ,Group Modifier Bit 285" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
bitfld.long 0x00 27. "  GMB283 ,Group Modifier Bit 283" "0,1"
bitfld.long 0x00 26. "  GMB282 ,Group Modifier Bit 282" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
bitfld.long 0x00 24. "  GMB280 ,Group Modifier Bit 280" "0,1"
bitfld.long 0x00 23. "  GMB279 ,Group Modifier Bit 279" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
bitfld.long 0x00 21. "  GMB277 ,Group Modifier Bit 277" "0,1"
bitfld.long 0x00 20. "  GMB276 ,Group Modifier Bit 276" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
bitfld.long 0x00 18. "  GMB274 ,Group Modifier Bit 274" "0,1"
bitfld.long 0x00 17. "  GMB273 ,Group Modifier Bit 273" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
bitfld.long 0x00 15. "  GMB271 ,Group Modifier Bit 271" "0,1"
bitfld.long 0x00 14. "  GMB270 ,Group Modifier Bit 270" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
bitfld.long 0x00 12. "  GMB268 ,Group Modifier Bit 268" "0,1"
bitfld.long 0x00 11. "  GMB267 ,Group Modifier Bit 267" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
bitfld.long 0x00 9. "  GMB265 ,Group Modifier Bit 265" "0,1"
bitfld.long 0x00 8. "  GMB264 ,Group Modifier Bit 264" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
bitfld.long 0x00 6. "  GMB262 ,Group Modifier Bit 262" "0,1"
bitfld.long 0x00 5. "  GMB261 ,Group Modifier Bit 261" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
bitfld.long 0x00 3. "  GMB259 ,Group Modifier Bit 259" "0,1"
bitfld.long 0x00 2. "  GMB258 ,Group Modifier Bit 258" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
bitfld.long 0x00 0. "  GMB256 ,Group Modifier Bit 256" "0,1"
else
hgroup.long 0x0D20++0x03
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
group.long 0x0D24++0x03
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
bitfld.long 0x00 30. "  GMB318 ,Group Modifier Bit 318" "0,1"
bitfld.long 0x00 29. "  GMB317 ,Group Modifier Bit 317" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
bitfld.long 0x00 27. "  GMB315 ,Group Modifier Bit 315" "0,1"
bitfld.long 0x00 26. "  GMB314 ,Group Modifier Bit 314" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
bitfld.long 0x00 24. "  GMB312 ,Group Modifier Bit 312" "0,1"
bitfld.long 0x00 23. "  GMB311 ,Group Modifier Bit 311" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
bitfld.long 0x00 21. "  GMB309 ,Group Modifier Bit 309" "0,1"
bitfld.long 0x00 20. "  GMB308 ,Group Modifier Bit 308" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
bitfld.long 0x00 18. "  GMB306 ,Group Modifier Bit 306" "0,1"
bitfld.long 0x00 17. "  GMB305 ,Group Modifier Bit 305" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
bitfld.long 0x00 15. "  GMB303 ,Group Modifier Bit 303" "0,1"
bitfld.long 0x00 14. "  GMB302 ,Group Modifier Bit 302" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
bitfld.long 0x00 12. "  GMB300 ,Group Modifier Bit 300" "0,1"
bitfld.long 0x00 11. "  GMB299 ,Group Modifier Bit 299" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
bitfld.long 0x00 9. "  GMB297 ,Group Modifier Bit 297" "0,1"
bitfld.long 0x00 8. "  GMB296 ,Group Modifier Bit 296" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
bitfld.long 0x00 6. "  GMB294 ,Group Modifier Bit 294" "0,1"
bitfld.long 0x00 5. "  GMB293 ,Group Modifier Bit 293" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
bitfld.long 0x00 3. "  GMB291 ,Group Modifier Bit 291" "0,1"
bitfld.long 0x00 2. "  GMB290 ,Group Modifier Bit 290" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
bitfld.long 0x00 0. "  GMB288 ,Group Modifier Bit 288" "0,1"
else
hgroup.long 0x0D24++0x03
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
group.long 0x0D28++0x03
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
bitfld.long 0x00 30. "  GMB350 ,Group Modifier Bit 350" "0,1"
bitfld.long 0x00 29. "  GMB349 ,Group Modifier Bit 349" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
bitfld.long 0x00 27. "  GMB347 ,Group Modifier Bit 347" "0,1"
bitfld.long 0x00 26. "  GMB346 ,Group Modifier Bit 346" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
bitfld.long 0x00 24. "  GMB344 ,Group Modifier Bit 344" "0,1"
bitfld.long 0x00 23. "  GMB343 ,Group Modifier Bit 343" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
bitfld.long 0x00 21. "  GMB341 ,Group Modifier Bit 341" "0,1"
bitfld.long 0x00 20. "  GMB340 ,Group Modifier Bit 340" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
bitfld.long 0x00 18. "  GMB338 ,Group Modifier Bit 338" "0,1"
bitfld.long 0x00 17. "  GMB337 ,Group Modifier Bit 337" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
bitfld.long 0x00 15. "  GMB335 ,Group Modifier Bit 335" "0,1"
bitfld.long 0x00 14. "  GMB334 ,Group Modifier Bit 334" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
bitfld.long 0x00 12. "  GMB332 ,Group Modifier Bit 332" "0,1"
bitfld.long 0x00 11. "  GMB331 ,Group Modifier Bit 331" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
bitfld.long 0x00 9. "  GMB329 ,Group Modifier Bit 329" "0,1"
bitfld.long 0x00 8. "  GMB328 ,Group Modifier Bit 328" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
bitfld.long 0x00 6. "  GMB326 ,Group Modifier Bit 326" "0,1"
bitfld.long 0x00 5. "  GMB325 ,Group Modifier Bit 325" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
bitfld.long 0x00 3. "  GMB323 ,Group Modifier Bit 323" "0,1"
bitfld.long 0x00 2. "  GMB322 ,Group Modifier Bit 322" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
bitfld.long 0x00 0. "  GMB320 ,Group Modifier Bit 320" "0,1"
else
hgroup.long 0x0D28++0x03
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
group.long 0x0D2C++0x03
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
bitfld.long 0x00 30. "  GMB382 ,Group Modifier Bit 382" "0,1"
bitfld.long 0x00 29. "  GMB381 ,Group Modifier Bit 381" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
bitfld.long 0x00 27. "  GMB379 ,Group Modifier Bit 379" "0,1"
bitfld.long 0x00 26. "  GMB378 ,Group Modifier Bit 378" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
bitfld.long 0x00 24. "  GMB376 ,Group Modifier Bit 376" "0,1"
bitfld.long 0x00 23. "  GMB375 ,Group Modifier Bit 375" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
bitfld.long 0x00 21. "  GMB373 ,Group Modifier Bit 373" "0,1"
bitfld.long 0x00 20. "  GMB372 ,Group Modifier Bit 372" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
bitfld.long 0x00 18. "  GMB370 ,Group Modifier Bit 370" "0,1"
bitfld.long 0x00 17. "  GMB369 ,Group Modifier Bit 369" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
bitfld.long 0x00 15. "  GMB367 ,Group Modifier Bit 367" "0,1"
bitfld.long 0x00 14. "  GMB366 ,Group Modifier Bit 366" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
bitfld.long 0x00 12. "  GMB364 ,Group Modifier Bit 364" "0,1"
bitfld.long 0x00 11. "  GMB363 ,Group Modifier Bit 363" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
bitfld.long 0x00 9. "  GMB361 ,Group Modifier Bit 361" "0,1"
bitfld.long 0x00 8. "  GMB360 ,Group Modifier Bit 360" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
bitfld.long 0x00 6. "  GMB358 ,Group Modifier Bit 358" "0,1"
bitfld.long 0x00 5. "  GMB357 ,Group Modifier Bit 357" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
bitfld.long 0x00 3. "  GMB355 ,Group Modifier Bit 355" "0,1"
bitfld.long 0x00 2. "  GMB354 ,Group Modifier Bit 354" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
bitfld.long 0x00 0. "  GMB352 ,Group Modifier Bit 352" "0,1"
else
hgroup.long 0x0D2C++0x03
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
group.long 0x0D30++0x03
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
bitfld.long 0x00 30. "  GMB414 ,Group Modifier Bit 414" "0,1"
bitfld.long 0x00 29. "  GMB413 ,Group Modifier Bit 413" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
bitfld.long 0x00 27. "  GMB411 ,Group Modifier Bit 411" "0,1"
bitfld.long 0x00 26. "  GMB410 ,Group Modifier Bit 410" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
bitfld.long 0x00 24. "  GMB408 ,Group Modifier Bit 408" "0,1"
bitfld.long 0x00 23. "  GMB407 ,Group Modifier Bit 407" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
bitfld.long 0x00 21. "  GMB405 ,Group Modifier Bit 405" "0,1"
bitfld.long 0x00 20. "  GMB404 ,Group Modifier Bit 404" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
bitfld.long 0x00 18. "  GMB402 ,Group Modifier Bit 402" "0,1"
bitfld.long 0x00 17. "  GMB401 ,Group Modifier Bit 401" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
bitfld.long 0x00 15. "  GMB399 ,Group Modifier Bit 399" "0,1"
bitfld.long 0x00 14. "  GMB398 ,Group Modifier Bit 398" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
bitfld.long 0x00 12. "  GMB396 ,Group Modifier Bit 396" "0,1"
bitfld.long 0x00 11. "  GMB395 ,Group Modifier Bit 395" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
bitfld.long 0x00 9. "  GMB393 ,Group Modifier Bit 393" "0,1"
bitfld.long 0x00 8. "  GMB392 ,Group Modifier Bit 392" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
bitfld.long 0x00 6. "  GMB390 ,Group Modifier Bit 390" "0,1"
bitfld.long 0x00 5. "  GMB389 ,Group Modifier Bit 389" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
bitfld.long 0x00 3. "  GMB387 ,Group Modifier Bit 387" "0,1"
bitfld.long 0x00 2. "  GMB386 ,Group Modifier Bit 386" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
bitfld.long 0x00 0. "  GMB384 ,Group Modifier Bit 384" "0,1"
else
hgroup.long 0x0D30++0x03
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
group.long 0x0D34++0x03
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
bitfld.long 0x00 30. "  GMB446 ,Group Modifier Bit 446" "0,1"
bitfld.long 0x00 29. "  GMB445 ,Group Modifier Bit 445" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
bitfld.long 0x00 27. "  GMB443 ,Group Modifier Bit 443" "0,1"
bitfld.long 0x00 26. "  GMB442 ,Group Modifier Bit 442" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
bitfld.long 0x00 24. "  GMB440 ,Group Modifier Bit 440" "0,1"
bitfld.long 0x00 23. "  GMB439 ,Group Modifier Bit 439" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
bitfld.long 0x00 21. "  GMB437 ,Group Modifier Bit 437" "0,1"
bitfld.long 0x00 20. "  GMB436 ,Group Modifier Bit 436" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
bitfld.long 0x00 18. "  GMB434 ,Group Modifier Bit 434" "0,1"
bitfld.long 0x00 17. "  GMB433 ,Group Modifier Bit 433" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
bitfld.long 0x00 15. "  GMB431 ,Group Modifier Bit 431" "0,1"
bitfld.long 0x00 14. "  GMB430 ,Group Modifier Bit 430" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
bitfld.long 0x00 12. "  GMB428 ,Group Modifier Bit 428" "0,1"
bitfld.long 0x00 11. "  GMB427 ,Group Modifier Bit 427" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
bitfld.long 0x00 9. "  GMB425 ,Group Modifier Bit 425" "0,1"
bitfld.long 0x00 8. "  GMB424 ,Group Modifier Bit 424" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
bitfld.long 0x00 6. "  GMB422 ,Group Modifier Bit 422" "0,1"
bitfld.long 0x00 5. "  GMB421 ,Group Modifier Bit 421" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
bitfld.long 0x00 3. "  GMB419 ,Group Modifier Bit 419" "0,1"
bitfld.long 0x00 2. "  GMB418 ,Group Modifier Bit 418" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
bitfld.long 0x00 0. "  GMB416 ,Group Modifier Bit 416" "0,1"
else
hgroup.long 0x0D34++0x03
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
group.long 0x0D38++0x03
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
bitfld.long 0x00 30. "  GMB478 ,Group Modifier Bit 478" "0,1"
bitfld.long 0x00 29. "  GMB477 ,Group Modifier Bit 477" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
bitfld.long 0x00 27. "  GMB475 ,Group Modifier Bit 475" "0,1"
bitfld.long 0x00 26. "  GMB474 ,Group Modifier Bit 474" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
bitfld.long 0x00 24. "  GMB472 ,Group Modifier Bit 472" "0,1"
bitfld.long 0x00 23. "  GMB471 ,Group Modifier Bit 471" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
bitfld.long 0x00 21. "  GMB469 ,Group Modifier Bit 469" "0,1"
bitfld.long 0x00 20. "  GMB468 ,Group Modifier Bit 468" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
bitfld.long 0x00 18. "  GMB466 ,Group Modifier Bit 466" "0,1"
bitfld.long 0x00 17. "  GMB465 ,Group Modifier Bit 465" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
bitfld.long 0x00 15. "  GMB463 ,Group Modifier Bit 463" "0,1"
bitfld.long 0x00 14. "  GMB462 ,Group Modifier Bit 462" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
bitfld.long 0x00 12. "  GMB460 ,Group Modifier Bit 460" "0,1"
bitfld.long 0x00 11. "  GMB459 ,Group Modifier Bit 459" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
bitfld.long 0x00 9. "  GMB457 ,Group Modifier Bit 457" "0,1"
bitfld.long 0x00 8. "  GMB456 ,Group Modifier Bit 456" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
bitfld.long 0x00 6. "  GMB454 ,Group Modifier Bit 454" "0,1"
bitfld.long 0x00 5. "  GMB453 ,Group Modifier Bit 453" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
bitfld.long 0x00 3. "  GMB451 ,Group Modifier Bit 451" "0,1"
bitfld.long 0x00 2. "  GMB450 ,Group Modifier Bit 450" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
bitfld.long 0x00 0. "  GMB448 ,Group Modifier Bit 448" "0,1"
else
hgroup.long 0x0D38++0x03
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
group.long 0x0D3C++0x03
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
bitfld.long 0x00 30. "  GMB510 ,Group Modifier Bit 510" "0,1"
bitfld.long 0x00 29. "  GMB509 ,Group Modifier Bit 509" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
bitfld.long 0x00 27. "  GMB507 ,Group Modifier Bit 507" "0,1"
bitfld.long 0x00 26. "  GMB506 ,Group Modifier Bit 506" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
bitfld.long 0x00 24. "  GMB504 ,Group Modifier Bit 504" "0,1"
bitfld.long 0x00 23. "  GMB503 ,Group Modifier Bit 503" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
bitfld.long 0x00 21. "  GMB501 ,Group Modifier Bit 501" "0,1"
bitfld.long 0x00 20. "  GMB500 ,Group Modifier Bit 500" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
bitfld.long 0x00 18. "  GMB498 ,Group Modifier Bit 498" "0,1"
bitfld.long 0x00 17. "  GMB497 ,Group Modifier Bit 497" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
bitfld.long 0x00 15. "  GMB495 ,Group Modifier Bit 495" "0,1"
bitfld.long 0x00 14. "  GMB494 ,Group Modifier Bit 494" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
bitfld.long 0x00 12. "  GMB492 ,Group Modifier Bit 492" "0,1"
bitfld.long 0x00 11. "  GMB491 ,Group Modifier Bit 491" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
bitfld.long 0x00 9. "  GMB489 ,Group Modifier Bit 489" "0,1"
bitfld.long 0x00 8. "  GMB488 ,Group Modifier Bit 488" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
bitfld.long 0x00 6. "  GMB486 ,Group Modifier Bit 486" "0,1"
bitfld.long 0x00 5. "  GMB485 ,Group Modifier Bit 485" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
bitfld.long 0x00 3. "  GMB483 ,Group Modifier Bit 483" "0,1"
bitfld.long 0x00 2. "  GMB482 ,Group Modifier Bit 482" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
bitfld.long 0x00 0. "  GMB480 ,Group Modifier Bit 480" "0,1"
else
hgroup.long 0x0D3C++0x03
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x0D40++0x03
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
bitfld.long 0x00 30. "  GMB542 ,Group Modifier Bit 542" "0,1"
bitfld.long 0x00 29. "  GMB541 ,Group Modifier Bit 541" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
bitfld.long 0x00 27. "  GMB539 ,Group Modifier Bit 539" "0,1"
bitfld.long 0x00 26. "  GMB538 ,Group Modifier Bit 538" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
bitfld.long 0x00 24. "  GMB536 ,Group Modifier Bit 536" "0,1"
bitfld.long 0x00 23. "  GMB535 ,Group Modifier Bit 535" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
bitfld.long 0x00 21. "  GMB533 ,Group Modifier Bit 533" "0,1"
bitfld.long 0x00 20. "  GMB532 ,Group Modifier Bit 532" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
bitfld.long 0x00 18. "  GMB530 ,Group Modifier Bit 530" "0,1"
bitfld.long 0x00 17. "  GMB529 ,Group Modifier Bit 529" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
bitfld.long 0x00 15. "  GMB527 ,Group Modifier Bit 527" "0,1"
bitfld.long 0x00 14. "  GMB526 ,Group Modifier Bit 526" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
bitfld.long 0x00 12. "  GMB524 ,Group Modifier Bit 524" "0,1"
bitfld.long 0x00 11. "  GMB523 ,Group Modifier Bit 523" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
bitfld.long 0x00 9. "  GMB521 ,Group Modifier Bit 521" "0,1"
bitfld.long 0x00 8. "  GMB520 ,Group Modifier Bit 520" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
bitfld.long 0x00 6. "  GMB518 ,Group Modifier Bit 518" "0,1"
bitfld.long 0x00 5. "  GMB517 ,Group Modifier Bit 517" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
bitfld.long 0x00 3. "  GMB515 ,Group Modifier Bit 515" "0,1"
bitfld.long 0x00 2. "  GMB514 ,Group Modifier Bit 514" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
bitfld.long 0x00 0. "  GMB512 ,Group Modifier Bit 512" "0,1"
else
hgroup.long 0x0D40++0x03
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x0D44++0x03
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
bitfld.long 0x00 30. "  GMB574 ,Group Modifier Bit 574" "0,1"
bitfld.long 0x00 29. "  GMB573 ,Group Modifier Bit 573" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
bitfld.long 0x00 27. "  GMB571 ,Group Modifier Bit 571" "0,1"
bitfld.long 0x00 26. "  GMB570 ,Group Modifier Bit 570" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
bitfld.long 0x00 24. "  GMB568 ,Group Modifier Bit 568" "0,1"
bitfld.long 0x00 23. "  GMB567 ,Group Modifier Bit 567" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
bitfld.long 0x00 21. "  GMB565 ,Group Modifier Bit 565" "0,1"
bitfld.long 0x00 20. "  GMB564 ,Group Modifier Bit 564" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
bitfld.long 0x00 18. "  GMB562 ,Group Modifier Bit 562" "0,1"
bitfld.long 0x00 17. "  GMB561 ,Group Modifier Bit 561" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
bitfld.long 0x00 15. "  GMB559 ,Group Modifier Bit 559" "0,1"
bitfld.long 0x00 14. "  GMB558 ,Group Modifier Bit 558" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
bitfld.long 0x00 12. "  GMB556 ,Group Modifier Bit 556" "0,1"
bitfld.long 0x00 11. "  GMB555 ,Group Modifier Bit 555" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
bitfld.long 0x00 9. "  GMB553 ,Group Modifier Bit 553" "0,1"
bitfld.long 0x00 8. "  GMB552 ,Group Modifier Bit 552" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
bitfld.long 0x00 6. "  GMB550 ,Group Modifier Bit 550" "0,1"
bitfld.long 0x00 5. "  GMB549 ,Group Modifier Bit 549" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
bitfld.long 0x00 3. "  GMB547 ,Group Modifier Bit 547" "0,1"
bitfld.long 0x00 2. "  GMB546 ,Group Modifier Bit 546" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
bitfld.long 0x00 0. "  GMB544 ,Group Modifier Bit 544" "0,1"
else
hgroup.long 0x0D44++0x03
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x0D48++0x03
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
bitfld.long 0x00 30. "  GMB606 ,Group Modifier Bit 606" "0,1"
bitfld.long 0x00 29. "  GMB605 ,Group Modifier Bit 605" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
bitfld.long 0x00 27. "  GMB603 ,Group Modifier Bit 603" "0,1"
bitfld.long 0x00 26. "  GMB602 ,Group Modifier Bit 602" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
bitfld.long 0x00 24. "  GMB600 ,Group Modifier Bit 600" "0,1"
bitfld.long 0x00 23. "  GMB599 ,Group Modifier Bit 599" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
bitfld.long 0x00 21. "  GMB597 ,Group Modifier Bit 597" "0,1"
bitfld.long 0x00 20. "  GMB596 ,Group Modifier Bit 596" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
bitfld.long 0x00 18. "  GMB594 ,Group Modifier Bit 594" "0,1"
bitfld.long 0x00 17. "  GMB593 ,Group Modifier Bit 593" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
bitfld.long 0x00 15. "  GMB591 ,Group Modifier Bit 591" "0,1"
bitfld.long 0x00 14. "  GMB590 ,Group Modifier Bit 590" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
bitfld.long 0x00 12. "  GMB588 ,Group Modifier Bit 588" "0,1"
bitfld.long 0x00 11. "  GMB587 ,Group Modifier Bit 587" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
bitfld.long 0x00 9. "  GMB585 ,Group Modifier Bit 585" "0,1"
bitfld.long 0x00 8. "  GMB584 ,Group Modifier Bit 584" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
bitfld.long 0x00 6. "  GMB582 ,Group Modifier Bit 582" "0,1"
bitfld.long 0x00 5. "  GMB581 ,Group Modifier Bit 581" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
bitfld.long 0x00 3. "  GMB579 ,Group Modifier Bit 579" "0,1"
bitfld.long 0x00 2. "  GMB578 ,Group Modifier Bit 578" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
bitfld.long 0x00 0. "  GMB576 ,Group Modifier Bit 576" "0,1"
else
hgroup.long 0x0D48++0x03
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x0D4C++0x03
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
bitfld.long 0x00 30. "  GMB638 ,Group Modifier Bit 638" "0,1"
bitfld.long 0x00 29. "  GMB637 ,Group Modifier Bit 637" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
bitfld.long 0x00 27. "  GMB635 ,Group Modifier Bit 635" "0,1"
bitfld.long 0x00 26. "  GMB634 ,Group Modifier Bit 634" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
bitfld.long 0x00 24. "  GMB632 ,Group Modifier Bit 632" "0,1"
bitfld.long 0x00 23. "  GMB631 ,Group Modifier Bit 631" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
bitfld.long 0x00 21. "  GMB629 ,Group Modifier Bit 629" "0,1"
bitfld.long 0x00 20. "  GMB628 ,Group Modifier Bit 628" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
bitfld.long 0x00 18. "  GMB626 ,Group Modifier Bit 626" "0,1"
bitfld.long 0x00 17. "  GMB625 ,Group Modifier Bit 625" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
bitfld.long 0x00 15. "  GMB623 ,Group Modifier Bit 623" "0,1"
bitfld.long 0x00 14. "  GMB622 ,Group Modifier Bit 622" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
bitfld.long 0x00 12. "  GMB620 ,Group Modifier Bit 620" "0,1"
bitfld.long 0x00 11. "  GMB619 ,Group Modifier Bit 619" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
bitfld.long 0x00 9. "  GMB617 ,Group Modifier Bit 617" "0,1"
bitfld.long 0x00 8. "  GMB616 ,Group Modifier Bit 616" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
bitfld.long 0x00 6. "  GMB614 ,Group Modifier Bit 614" "0,1"
bitfld.long 0x00 5. "  GMB613 ,Group Modifier Bit 613" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
bitfld.long 0x00 3. "  GMB611 ,Group Modifier Bit 611" "0,1"
bitfld.long 0x00 2. "  GMB610 ,Group Modifier Bit 610" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
bitfld.long 0x00 0. "  GMB608 ,Group Modifier Bit 608" "0,1"
else
hgroup.long 0x0D4C++0x03
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x0D50++0x03
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
bitfld.long 0x00 30. "  GMB670 ,Group Modifier Bit 670" "0,1"
bitfld.long 0x00 29. "  GMB669 ,Group Modifier Bit 669" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
bitfld.long 0x00 27. "  GMB667 ,Group Modifier Bit 667" "0,1"
bitfld.long 0x00 26. "  GMB666 ,Group Modifier Bit 666" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
bitfld.long 0x00 24. "  GMB664 ,Group Modifier Bit 664" "0,1"
bitfld.long 0x00 23. "  GMB663 ,Group Modifier Bit 663" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
bitfld.long 0x00 21. "  GMB661 ,Group Modifier Bit 661" "0,1"
bitfld.long 0x00 20. "  GMB660 ,Group Modifier Bit 660" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
bitfld.long 0x00 18. "  GMB658 ,Group Modifier Bit 658" "0,1"
bitfld.long 0x00 17. "  GMB657 ,Group Modifier Bit 657" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
bitfld.long 0x00 15. "  GMB655 ,Group Modifier Bit 655" "0,1"
bitfld.long 0x00 14. "  GMB654 ,Group Modifier Bit 654" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
bitfld.long 0x00 12. "  GMB652 ,Group Modifier Bit 652" "0,1"
bitfld.long 0x00 11. "  GMB651 ,Group Modifier Bit 651" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
bitfld.long 0x00 9. "  GMB649 ,Group Modifier Bit 649" "0,1"
bitfld.long 0x00 8. "  GMB648 ,Group Modifier Bit 648" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
bitfld.long 0x00 6. "  GMB646 ,Group Modifier Bit 646" "0,1"
bitfld.long 0x00 5. "  GMB645 ,Group Modifier Bit 645" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
bitfld.long 0x00 3. "  GMB643 ,Group Modifier Bit 643" "0,1"
bitfld.long 0x00 2. "  GMB642 ,Group Modifier Bit 642" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
bitfld.long 0x00 0. "  GMB640 ,Group Modifier Bit 640" "0,1"
else
hgroup.long 0x0D50++0x03
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x0D54++0x03
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
bitfld.long 0x00 30. "  GMB702 ,Group Modifier Bit 702" "0,1"
bitfld.long 0x00 29. "  GMB701 ,Group Modifier Bit 701" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
bitfld.long 0x00 27. "  GMB699 ,Group Modifier Bit 699" "0,1"
bitfld.long 0x00 26. "  GMB698 ,Group Modifier Bit 698" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
bitfld.long 0x00 24. "  GMB696 ,Group Modifier Bit 696" "0,1"
bitfld.long 0x00 23. "  GMB695 ,Group Modifier Bit 695" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
bitfld.long 0x00 21. "  GMB693 ,Group Modifier Bit 693" "0,1"
bitfld.long 0x00 20. "  GMB692 ,Group Modifier Bit 692" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
bitfld.long 0x00 18. "  GMB690 ,Group Modifier Bit 690" "0,1"
bitfld.long 0x00 17. "  GMB689 ,Group Modifier Bit 689" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
bitfld.long 0x00 15. "  GMB687 ,Group Modifier Bit 687" "0,1"
bitfld.long 0x00 14. "  GMB686 ,Group Modifier Bit 686" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
bitfld.long 0x00 12. "  GMB684 ,Group Modifier Bit 684" "0,1"
bitfld.long 0x00 11. "  GMB683 ,Group Modifier Bit 683" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
bitfld.long 0x00 9. "  GMB681 ,Group Modifier Bit 681" "0,1"
bitfld.long 0x00 8. "  GMB680 ,Group Modifier Bit 680" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
bitfld.long 0x00 6. "  GMB678 ,Group Modifier Bit 678" "0,1"
bitfld.long 0x00 5. "  GMB677 ,Group Modifier Bit 677" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
bitfld.long 0x00 3. "  GMB675 ,Group Modifier Bit 675" "0,1"
bitfld.long 0x00 2. "  GMB674 ,Group Modifier Bit 674" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
bitfld.long 0x00 0. "  GMB672 ,Group Modifier Bit 672" "0,1"
else
hgroup.long 0x0D54++0x03
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x0D58++0x03
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
bitfld.long 0x00 30. "  GMB734 ,Group Modifier Bit 734" "0,1"
bitfld.long 0x00 29. "  GMB733 ,Group Modifier Bit 733" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
bitfld.long 0x00 27. "  GMB731 ,Group Modifier Bit 731" "0,1"
bitfld.long 0x00 26. "  GMB730 ,Group Modifier Bit 730" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
bitfld.long 0x00 24. "  GMB728 ,Group Modifier Bit 728" "0,1"
bitfld.long 0x00 23. "  GMB727 ,Group Modifier Bit 727" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
bitfld.long 0x00 21. "  GMB725 ,Group Modifier Bit 725" "0,1"
bitfld.long 0x00 20. "  GMB724 ,Group Modifier Bit 724" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
bitfld.long 0x00 18. "  GMB722 ,Group Modifier Bit 722" "0,1"
bitfld.long 0x00 17. "  GMB721 ,Group Modifier Bit 721" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
bitfld.long 0x00 15. "  GMB719 ,Group Modifier Bit 719" "0,1"
bitfld.long 0x00 14. "  GMB718 ,Group Modifier Bit 718" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
bitfld.long 0x00 12. "  GMB716 ,Group Modifier Bit 716" "0,1"
bitfld.long 0x00 11. "  GMB715 ,Group Modifier Bit 715" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
bitfld.long 0x00 9. "  GMB713 ,Group Modifier Bit 713" "0,1"
bitfld.long 0x00 8. "  GMB712 ,Group Modifier Bit 712" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
bitfld.long 0x00 6. "  GMB710 ,Group Modifier Bit 710" "0,1"
bitfld.long 0x00 5. "  GMB709 ,Group Modifier Bit 709" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
bitfld.long 0x00 3. "  GMB707 ,Group Modifier Bit 707" "0,1"
bitfld.long 0x00 2. "  GMB706 ,Group Modifier Bit 706" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
bitfld.long 0x00 0. "  GMB704 ,Group Modifier Bit 704" "0,1"
else
hgroup.long 0x0D58++0x03
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x0D5C++0x03
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
bitfld.long 0x00 30. "  GMB766 ,Group Modifier Bit 766" "0,1"
bitfld.long 0x00 29. "  GMB765 ,Group Modifier Bit 765" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
bitfld.long 0x00 27. "  GMB763 ,Group Modifier Bit 763" "0,1"
bitfld.long 0x00 26. "  GMB762 ,Group Modifier Bit 762" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
bitfld.long 0x00 24. "  GMB760 ,Group Modifier Bit 760" "0,1"
bitfld.long 0x00 23. "  GMB759 ,Group Modifier Bit 759" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
bitfld.long 0x00 21. "  GMB757 ,Group Modifier Bit 757" "0,1"
bitfld.long 0x00 20. "  GMB756 ,Group Modifier Bit 756" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
bitfld.long 0x00 18. "  GMB754 ,Group Modifier Bit 754" "0,1"
bitfld.long 0x00 17. "  GMB753 ,Group Modifier Bit 753" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
bitfld.long 0x00 15. "  GMB751 ,Group Modifier Bit 751" "0,1"
bitfld.long 0x00 14. "  GMB750 ,Group Modifier Bit 750" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
bitfld.long 0x00 12. "  GMB748 ,Group Modifier Bit 748" "0,1"
bitfld.long 0x00 11. "  GMB747 ,Group Modifier Bit 747" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
bitfld.long 0x00 9. "  GMB745 ,Group Modifier Bit 745" "0,1"
bitfld.long 0x00 8. "  GMB744 ,Group Modifier Bit 744" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
bitfld.long 0x00 6. "  GMB742 ,Group Modifier Bit 742" "0,1"
bitfld.long 0x00 5. "  GMB741 ,Group Modifier Bit 741" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
bitfld.long 0x00 3. "  GMB739 ,Group Modifier Bit 739" "0,1"
bitfld.long 0x00 2. "  GMB738 ,Group Modifier Bit 738" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
bitfld.long 0x00 0. "  GMB736 ,Group Modifier Bit 736" "0,1"
else
hgroup.long 0x0D5C++0x03
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x0D60++0x03
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
bitfld.long 0x00 30. "  GMB798 ,Group Modifier Bit 798" "0,1"
bitfld.long 0x00 29. "  GMB797 ,Group Modifier Bit 797" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
bitfld.long 0x00 27. "  GMB795 ,Group Modifier Bit 795" "0,1"
bitfld.long 0x00 26. "  GMB794 ,Group Modifier Bit 794" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
bitfld.long 0x00 24. "  GMB792 ,Group Modifier Bit 792" "0,1"
bitfld.long 0x00 23. "  GMB791 ,Group Modifier Bit 791" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
bitfld.long 0x00 21. "  GMB789 ,Group Modifier Bit 789" "0,1"
bitfld.long 0x00 20. "  GMB788 ,Group Modifier Bit 788" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
bitfld.long 0x00 18. "  GMB786 ,Group Modifier Bit 786" "0,1"
bitfld.long 0x00 17. "  GMB785 ,Group Modifier Bit 785" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
bitfld.long 0x00 15. "  GMB783 ,Group Modifier Bit 783" "0,1"
bitfld.long 0x00 14. "  GMB782 ,Group Modifier Bit 782" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
bitfld.long 0x00 12. "  GMB780 ,Group Modifier Bit 780" "0,1"
bitfld.long 0x00 11. "  GMB779 ,Group Modifier Bit 779" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
bitfld.long 0x00 9. "  GMB777 ,Group Modifier Bit 777" "0,1"
bitfld.long 0x00 8. "  GMB776 ,Group Modifier Bit 776" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
bitfld.long 0x00 6. "  GMB774 ,Group Modifier Bit 774" "0,1"
bitfld.long 0x00 5. "  GMB773 ,Group Modifier Bit 773" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
bitfld.long 0x00 3. "  GMB771 ,Group Modifier Bit 771" "0,1"
bitfld.long 0x00 2. "  GMB770 ,Group Modifier Bit 770" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
bitfld.long 0x00 0. "  GMB768 ,Group Modifier Bit 768" "0,1"
else
hgroup.long 0x0D60++0x03
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x0D64++0x03
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
bitfld.long 0x00 30. "  GMB830 ,Group Modifier Bit 830" "0,1"
bitfld.long 0x00 29. "  GMB829 ,Group Modifier Bit 829" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
bitfld.long 0x00 27. "  GMB827 ,Group Modifier Bit 827" "0,1"
bitfld.long 0x00 26. "  GMB826 ,Group Modifier Bit 826" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
bitfld.long 0x00 24. "  GMB824 ,Group Modifier Bit 824" "0,1"
bitfld.long 0x00 23. "  GMB823 ,Group Modifier Bit 823" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
bitfld.long 0x00 21. "  GMB821 ,Group Modifier Bit 821" "0,1"
bitfld.long 0x00 20. "  GMB820 ,Group Modifier Bit 820" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
bitfld.long 0x00 18. "  GMB818 ,Group Modifier Bit 818" "0,1"
bitfld.long 0x00 17. "  GMB817 ,Group Modifier Bit 817" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
bitfld.long 0x00 15. "  GMB815 ,Group Modifier Bit 815" "0,1"
bitfld.long 0x00 14. "  GMB814 ,Group Modifier Bit 814" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
bitfld.long 0x00 12. "  GMB812 ,Group Modifier Bit 812" "0,1"
bitfld.long 0x00 11. "  GMB811 ,Group Modifier Bit 811" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
bitfld.long 0x00 9. "  GMB809 ,Group Modifier Bit 809" "0,1"
bitfld.long 0x00 8. "  GMB808 ,Group Modifier Bit 808" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
bitfld.long 0x00 6. "  GMB806 ,Group Modifier Bit 806" "0,1"
bitfld.long 0x00 5. "  GMB805 ,Group Modifier Bit 805" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
bitfld.long 0x00 3. "  GMB803 ,Group Modifier Bit 803" "0,1"
bitfld.long 0x00 2. "  GMB802 ,Group Modifier Bit 802" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
bitfld.long 0x00 0. "  GMB800 ,Group Modifier Bit 800" "0,1"
else
hgroup.long 0x0D64++0x03
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
group.long 0x0D68++0x03
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
bitfld.long 0x00 30. "  GMB862 ,Group Modifier Bit 862" "0,1"
bitfld.long 0x00 29. "  GMB861 ,Group Modifier Bit 861" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
bitfld.long 0x00 27. "  GMB859 ,Group Modifier Bit 859" "0,1"
bitfld.long 0x00 26. "  GMB858 ,Group Modifier Bit 858" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
bitfld.long 0x00 24. "  GMB856 ,Group Modifier Bit 856" "0,1"
bitfld.long 0x00 23. "  GMB855 ,Group Modifier Bit 855" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
bitfld.long 0x00 21. "  GMB853 ,Group Modifier Bit 853" "0,1"
bitfld.long 0x00 20. "  GMB852 ,Group Modifier Bit 852" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
bitfld.long 0x00 18. "  GMB850 ,Group Modifier Bit 850" "0,1"
bitfld.long 0x00 17. "  GMB849 ,Group Modifier Bit 849" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
bitfld.long 0x00 15. "  GMB847 ,Group Modifier Bit 847" "0,1"
bitfld.long 0x00 14. "  GMB846 ,Group Modifier Bit 846" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
bitfld.long 0x00 12. "  GMB844 ,Group Modifier Bit 844" "0,1"
bitfld.long 0x00 11. "  GMB843 ,Group Modifier Bit 843" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
bitfld.long 0x00 9. "  GMB841 ,Group Modifier Bit 841" "0,1"
bitfld.long 0x00 8. "  GMB840 ,Group Modifier Bit 840" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
bitfld.long 0x00 6. "  GMB838 ,Group Modifier Bit 838" "0,1"
bitfld.long 0x00 5. "  GMB837 ,Group Modifier Bit 837" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
bitfld.long 0x00 3. "  GMB835 ,Group Modifier Bit 835" "0,1"
bitfld.long 0x00 2. "  GMB834 ,Group Modifier Bit 834" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
bitfld.long 0x00 0. "  GMB832 ,Group Modifier Bit 832" "0,1"
else
hgroup.long 0x0D68++0x03
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x0D6C++0x03
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
bitfld.long 0x00 30. "  GMB894 ,Group Modifier Bit 894" "0,1"
bitfld.long 0x00 29. "  GMB893 ,Group Modifier Bit 893" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
bitfld.long 0x00 27. "  GMB891 ,Group Modifier Bit 891" "0,1"
bitfld.long 0x00 26. "  GMB890 ,Group Modifier Bit 890" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
bitfld.long 0x00 24. "  GMB888 ,Group Modifier Bit 888" "0,1"
bitfld.long 0x00 23. "  GMB887 ,Group Modifier Bit 887" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
bitfld.long 0x00 21. "  GMB885 ,Group Modifier Bit 885" "0,1"
bitfld.long 0x00 20. "  GMB884 ,Group Modifier Bit 884" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
bitfld.long 0x00 18. "  GMB882 ,Group Modifier Bit 882" "0,1"
bitfld.long 0x00 17. "  GMB881 ,Group Modifier Bit 881" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
bitfld.long 0x00 15. "  GMB879 ,Group Modifier Bit 879" "0,1"
bitfld.long 0x00 14. "  GMB878 ,Group Modifier Bit 878" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
bitfld.long 0x00 12. "  GMB876 ,Group Modifier Bit 876" "0,1"
bitfld.long 0x00 11. "  GMB875 ,Group Modifier Bit 875" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
bitfld.long 0x00 9. "  GMB873 ,Group Modifier Bit 873" "0,1"
bitfld.long 0x00 8. "  GMB872 ,Group Modifier Bit 872" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
bitfld.long 0x00 6. "  GMB870 ,Group Modifier Bit 870" "0,1"
bitfld.long 0x00 5. "  GMB869 ,Group Modifier Bit 869" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
bitfld.long 0x00 3. "  GMB867 ,Group Modifier Bit 867" "0,1"
bitfld.long 0x00 2. "  GMB866 ,Group Modifier Bit 866" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
bitfld.long 0x00 0. "  GMB864 ,Group Modifier Bit 864" "0,1"
else
hgroup.long 0x0D6C++0x03
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x0D70++0x03
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
bitfld.long 0x00 30. "  GMB926 ,Group Modifier Bit 926" "0,1"
bitfld.long 0x00 29. "  GMB925 ,Group Modifier Bit 925" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
bitfld.long 0x00 27. "  GMB923 ,Group Modifier Bit 923" "0,1"
bitfld.long 0x00 26. "  GMB922 ,Group Modifier Bit 922" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
bitfld.long 0x00 24. "  GMB920 ,Group Modifier Bit 920" "0,1"
bitfld.long 0x00 23. "  GMB919 ,Group Modifier Bit 919" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
bitfld.long 0x00 21. "  GMB917 ,Group Modifier Bit 917" "0,1"
bitfld.long 0x00 20. "  GMB916 ,Group Modifier Bit 916" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
bitfld.long 0x00 18. "  GMB914 ,Group Modifier Bit 914" "0,1"
bitfld.long 0x00 17. "  GMB913 ,Group Modifier Bit 913" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
bitfld.long 0x00 15. "  GMB911 ,Group Modifier Bit 911" "0,1"
bitfld.long 0x00 14. "  GMB910 ,Group Modifier Bit 910" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
bitfld.long 0x00 12. "  GMB908 ,Group Modifier Bit 908" "0,1"
bitfld.long 0x00 11. "  GMB907 ,Group Modifier Bit 907" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
bitfld.long 0x00 9. "  GMB905 ,Group Modifier Bit 905" "0,1"
bitfld.long 0x00 8. "  GMB904 ,Group Modifier Bit 904" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
bitfld.long 0x00 6. "  GMB902 ,Group Modifier Bit 902" "0,1"
bitfld.long 0x00 5. "  GMB901 ,Group Modifier Bit 901" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
bitfld.long 0x00 3. "  GMB899 ,Group Modifier Bit 899" "0,1"
bitfld.long 0x00 2. "  GMB898 ,Group Modifier Bit 898" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
bitfld.long 0x00 0. "  GMB896 ,Group Modifier Bit 896" "0,1"
else
hgroup.long 0x0D70++0x03
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x0D74++0x03
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
bitfld.long 0x00 30. "  GMB958 ,Group Modifier Bit 958" "0,1"
bitfld.long 0x00 29. "  GMB957 ,Group Modifier Bit 957" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
bitfld.long 0x00 27. "  GMB955 ,Group Modifier Bit 955" "0,1"
bitfld.long 0x00 26. "  GMB954 ,Group Modifier Bit 954" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
bitfld.long 0x00 24. "  GMB952 ,Group Modifier Bit 952" "0,1"
bitfld.long 0x00 23. "  GMB951 ,Group Modifier Bit 951" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
bitfld.long 0x00 21. "  GMB949 ,Group Modifier Bit 949" "0,1"
bitfld.long 0x00 20. "  GMB948 ,Group Modifier Bit 948" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
bitfld.long 0x00 18. "  GMB946 ,Group Modifier Bit 946" "0,1"
bitfld.long 0x00 17. "  GMB945 ,Group Modifier Bit 945" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
bitfld.long 0x00 15. "  GMB943 ,Group Modifier Bit 943" "0,1"
bitfld.long 0x00 14. "  GMB942 ,Group Modifier Bit 942" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
bitfld.long 0x00 12. "  GMB940 ,Group Modifier Bit 940" "0,1"
bitfld.long 0x00 11. "  GMB939 ,Group Modifier Bit 939" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
bitfld.long 0x00 9. "  GMB937 ,Group Modifier Bit 937" "0,1"
bitfld.long 0x00 8. "  GMB936 ,Group Modifier Bit 936" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
bitfld.long 0x00 6. "  GMB934 ,Group Modifier Bit 934" "0,1"
bitfld.long 0x00 5. "  GMB933 ,Group Modifier Bit 933" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
bitfld.long 0x00 3. "  GMB931 ,Group Modifier Bit 931" "0,1"
bitfld.long 0x00 2. "  GMB930 ,Group Modifier Bit 930" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
bitfld.long 0x00 0. "  GMB928 ,Group Modifier Bit 928" "0,1"
else
hgroup.long 0x0D74++0x03
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x0D78++0x03
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
bitfld.long 0x00 30. "  GMB990 ,Group Modifier Bit 990" "0,1"
bitfld.long 0x00 29. "  GMB989 ,Group Modifier Bit 989" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
bitfld.long 0x00 27. "  GMB987 ,Group Modifier Bit 987" "0,1"
bitfld.long 0x00 26. "  GMB986 ,Group Modifier Bit 986" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
bitfld.long 0x00 24. "  GMB984 ,Group Modifier Bit 984" "0,1"
bitfld.long 0x00 23. "  GMB983 ,Group Modifier Bit 983" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
bitfld.long 0x00 21. "  GMB981 ,Group Modifier Bit 981" "0,1"
bitfld.long 0x00 20. "  GMB980 ,Group Modifier Bit 980" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
bitfld.long 0x00 18. "  GMB978 ,Group Modifier Bit 978" "0,1"
bitfld.long 0x00 17. "  GMB977 ,Group Modifier Bit 977" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
bitfld.long 0x00 15. "  GMB975 ,Group Modifier Bit 975" "0,1"
bitfld.long 0x00 14. "  GMB974 ,Group Modifier Bit 974" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
bitfld.long 0x00 12. "  GMB972 ,Group Modifier Bit 972" "0,1"
bitfld.long 0x00 11. "  GMB971 ,Group Modifier Bit 971" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
bitfld.long 0x00 9. "  GMB969 ,Group Modifier Bit 969" "0,1"
bitfld.long 0x00 8. "  GMB968 ,Group Modifier Bit 968" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
bitfld.long 0x00 6. "  GMB966 ,Group Modifier Bit 966" "0,1"
bitfld.long 0x00 5. "  GMB965 ,Group Modifier Bit 965" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
bitfld.long 0x00 3. "  GMB963 ,Group Modifier Bit 963" "0,1"
bitfld.long 0x00 2. "  GMB962 ,Group Modifier Bit 962" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
bitfld.long 0x00 0. "  GMB960 ,Group Modifier Bit 960" "0,1"
else
hgroup.long 0x0D78++0x03
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
endif
tree.end
width 14.
tree "Non-secure Access Control Registers"
hgroup.long 0x0E00++0x03
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
hgroup.long 0xE04++0x03
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
group.long 0xE08++0x03
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
bitfld.long 0x00 30.--31. " NS_ACCESS47  ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS46  ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS45  ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS44  ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS43  ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS42  ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS41  ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS40  ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS39  ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS38  ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS37  ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS36  ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS35  ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS34  ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS33  ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS32  ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
group.long 0xE0C++0x03
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
bitfld.long 0x00 30.--31. " NS_ACCESS63  ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS62  ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS61  ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS60  ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS59  ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS58  ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS57  ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS56  ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS55  ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS54  ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS53  ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS52  ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS51  ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS50  ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS49  ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS48  ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE0C++0x03
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
group.long 0xE10++0x03
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
bitfld.long 0x00 30.--31. " NS_ACCESS79  ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS78  ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS77  ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS76  ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS75  ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS74  ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS73  ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS72  ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS71  ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS70  ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS69  ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS68  ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS67  ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS66  ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS65  ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS64  ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE10++0x03
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
group.long 0xE14++0x03
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
bitfld.long 0x00 30.--31. " NS_ACCESS95  ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS94  ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS93  ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS92  ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS91  ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS90  ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS89  ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS88  ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS87  ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS86  ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS85  ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS84  ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS83  ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS82  ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS81  ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS80  ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE14++0x03
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
group.long 0xE18++0x03
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS99  ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS98  ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS97  ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS96  ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE18++0x03
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
group.long 0xE1C++0x03
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE1C++0x03
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
group.long 0xE20++0x03
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE20++0x03
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
group.long 0xE24++0x03
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE24++0x03
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
group.long 0xE28++0x03
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE28++0x03
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
group.long 0xE2C++0x03
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE2C++0x03
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
group.long 0xE30++0x03
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE30++0x03
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
group.long 0xE34++0x03
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE34++0x03
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
group.long 0xE38++0x03
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE38++0x03
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
group.long 0xE3C++0x03
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE3C++0x03
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
group.long 0xE40++0x03
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE40++0x03
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
group.long 0xE44++0x03
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE44++0x03
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
group.long 0xE48++0x03
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE48++0x03
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
group.long 0xE4C++0x03
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE4C++0x03
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
group.long 0xE50++0x03
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE50++0x03
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
group.long 0xE54++0x03
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE54++0x03
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
group.long 0xE58++0x03
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE58++0x03
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
group.long 0xE5C++0x03
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE5C++0x03
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
group.long 0xE60++0x03
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE60++0x03
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
group.long 0xE64++0x03
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE64++0x03
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
group.long 0xE68++0x03
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE68++0x03
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
group.long 0xE6C++0x03
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE6C++0x03
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
group.long 0xE70++0x03
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE70++0x03
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
group.long 0xE74++0x03
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE74++0x03
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
group.long 0xE78++0x03
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE78++0x03
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
group.long 0xE7C++0x03
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE7C++0x03
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
group.long 0xE80++0x03
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE80++0x03
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
group.long 0xE84++0x03
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE84++0x03
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
group.long 0xE88++0x03
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE88++0x03
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
group.long 0xE8C++0x03
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE8C++0x03
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
group.long 0xE90++0x03
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE90++0x03
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
group.long 0xE94++0x03
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE94++0x03
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
group.long 0xE98++0x03
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE98++0x03
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
group.long 0xE9C++0x03
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE9C++0x03
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
group.long 0xEA0++0x03
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA0++0x03
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
group.long 0xEA4++0x03
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA4++0x03
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
group.long 0xEA8++0x03
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA8++0x03
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
group.long 0xEAC++0x03
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEAC++0x03
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
group.long 0xEB0++0x03
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB0++0x03
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
group.long 0xEB4++0x03
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB4++0x03
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
group.long 0xEB8++0x03
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB8++0x03
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
group.long 0xEBC++0x03
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEBC++0x03
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
group.long 0xEC0++0x03
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC0++0x03
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
group.long 0xEC4++0x03
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC4++0x03
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
group.long 0xEC8++0x03
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC8++0x03
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
group.long 0xECC++0x03
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xECC++0x03
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
group.long 0xED0++0x03
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED0++0x03
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
group.long 0xED4++0x03
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED4++0x03
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
group.long 0xED8++0x03
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED8++0x03
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
group.long 0xEDC++0x03
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEDC++0x03
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
group.long 0xEE0++0x03
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE0++0x03
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
group.long 0xEE4++0x03
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE4++0x03
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
group.long 0xEE8++0x03
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE8++0x03
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
group.long 0xEEC++0x03
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEEC++0x03
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
group.long 0xEF0++0x03
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF0++0x03
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
group.long 0xEF4++0x03
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF4++0x03
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0F00++0x03
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
hgroup.long 0xF10++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
hgroup.long 0xF14++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
hgroup.long 0xF18++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
hgroup.long 0xF1C++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
hgroup.long 0xF20++0x03
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
hgroup.long 0xF24++0x03
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
hgroup.long 0xF28++0x03
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
hgroup.long 0xF2C++0x03
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x03
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
group.long 0xF14++0x03
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
group.long 0xF18++0x03
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
group.long 0xF1C++0x03
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
group.long 0xF20++0x03
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
group.long 0xF24++0x03
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
group.long 0xF28++0x03
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
group.long 0xF2C++0x03
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
endif
tree.end
width 24.
tree "Interrupt Routing Registers"
group.quad 0x6100++0x07
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6108++0x07
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6110++0x07
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6118++0x07
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6120++0x07
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6128++0x07
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6130++0x07
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6138++0x07
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6140++0x07
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6148++0x07
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6150++0x07
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6158++0x07
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6160++0x07
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6168++0x07
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6170++0x07
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6178++0x07
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6180++0x07
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6188++0x07
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6190++0x07
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6198++0x07
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A0++0x07
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A8++0x07
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B0++0x07
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B8++0x07
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C0++0x07
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C8++0x07
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D0++0x07
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D8++0x07
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E0++0x07
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E8++0x07
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F0++0x07
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F8++0x07
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6200++0x07
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6208++0x07
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6210++0x07
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6218++0x07
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6220++0x07
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6228++0x07
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6230++0x07
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6238++0x07
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6240++0x07
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6248++0x07
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6250++0x07
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6258++0x07
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6260++0x07
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6268++0x07
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6270++0x07
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6278++0x07
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6280++0x07
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6288++0x07
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6290++0x07
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6298++0x07
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A0++0x07
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A8++0x07
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B0++0x07
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B8++0x07
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C0++0x07
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C8++0x07
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D0++0x07
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D8++0x07
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E0++0x07
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E8++0x07
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F0++0x07
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F8++0x07
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6300++0x07
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6308++0x07
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6310++0x07
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6318++0x07
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6320++0x07
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6328++0x07
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6330++0x07
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6338++0x07
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6340++0x07
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6348++0x07
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6350++0x07
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6358++0x07
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6360++0x07
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6368++0x07
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6370++0x07
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6378++0x07
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6380++0x07
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6388++0x07
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6390++0x07
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6398++0x07
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A0++0x07
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A8++0x07
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B0++0x07
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B8++0x07
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C0++0x07
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C8++0x07
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D0++0x07
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D8++0x07
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E0++0x07
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E8++0x07
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F0++0x07
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F8++0x07
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6400++0x07
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6408++0x07
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6410++0x07
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6418++0x07
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6420++0x07
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6428++0x07
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6430++0x07
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6438++0x07
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6440++0x07
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6448++0x07
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6450++0x07
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6458++0x07
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6460++0x07
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6468++0x07
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6470++0x07
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6478++0x07
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6480++0x07
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6488++0x07
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6490++0x07
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6498++0x07
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A0++0x07
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A8++0x07
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B0++0x07
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B8++0x07
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C0++0x07
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C8++0x07
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D0++0x07
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D8++0x07
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E0++0x07
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E8++0x07
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F0++0x07
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F8++0x07
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6500++0x07
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6508++0x07
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6510++0x07
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6518++0x07
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6520++0x07
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6528++0x07
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6530++0x07
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6538++0x07
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6540++0x07
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6548++0x07
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6550++0x07
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6558++0x07
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6560++0x07
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6568++0x07
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6570++0x07
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6578++0x07
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6580++0x07
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6588++0x07
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6590++0x07
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6598++0x07
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A0++0x07
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A8++0x07
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B0++0x07
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B8++0x07
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C0++0x07
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C8++0x07
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D0++0x07
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D8++0x07
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E0++0x07
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E8++0x07
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F0++0x07
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F8++0x07
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6600++0x07
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6608++0x07
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6610++0x07
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6618++0x07
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6620++0x07
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6628++0x07
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6630++0x07
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6638++0x07
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6640++0x07
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6648++0x07
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6650++0x07
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6658++0x07
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6660++0x07
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6668++0x07
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6670++0x07
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6678++0x07
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6680++0x07
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6688++0x07
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6690++0x07
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6698++0x07
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A0++0x07
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A8++0x07
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B0++0x07
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B8++0x07
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C0++0x07
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C8++0x07
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D0++0x07
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D8++0x07
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E0++0x07
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E8++0x07
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F0++0x07
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F8++0x07
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6700++0x07
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6708++0x07
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6710++0x07
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6718++0x07
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6720++0x07
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6728++0x07
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6730++0x07
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6738++0x07
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6740++0x07
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6748++0x07
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6750++0x07
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6758++0x07
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6760++0x07
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6768++0x07
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6770++0x07
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6778++0x07
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6780++0x07
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6788++0x07
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6790++0x07
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6798++0x07
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A0++0x07
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A8++0x07
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B0++0x07
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B8++0x07
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C0++0x07
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C8++0x07
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D0++0x07
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D8++0x07
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E0++0x07
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E8++0x07
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F0++0x07
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F8++0x07
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6800++0x07
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6808++0x07
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6810++0x07
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6818++0x07
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6820++0x07
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6828++0x07
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6830++0x07
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6838++0x07
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6840++0x07
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6848++0x07
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6850++0x07
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6858++0x07
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6860++0x07
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6868++0x07
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6870++0x07
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6878++0x07
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6880++0x07
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6888++0x07
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6890++0x07
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6898++0x07
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A0++0x07
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A8++0x07
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B0++0x07
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B8++0x07
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C0++0x07
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C8++0x07
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D0++0x07
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D8++0x07
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E0++0x07
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E8++0x07
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F0++0x07
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F8++0x07
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6900++0x07
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6908++0x07
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6910++0x07
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6918++0x07
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6920++0x07
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6928++0x07
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6930++0x07
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6938++0x07
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6940++0x07
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6948++0x07
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6950++0x07
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6958++0x07
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6960++0x07
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6968++0x07
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6970++0x07
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6978++0x07
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6980++0x07
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6988++0x07
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6990++0x07
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6998++0x07
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A0++0x07
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A8++0x07
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B0++0x07
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B8++0x07
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C0++0x07
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C8++0x07
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D0++0x07
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D8++0x07
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E0++0x07
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E8++0x07
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F0++0x07
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F8++0x07
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A00++0x07
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A08++0x07
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A10++0x07
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A18++0x07
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A20++0x07
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A28++0x07
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A30++0x07
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A38++0x07
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A40++0x07
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A48++0x07
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A50++0x07
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A58++0x07
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A60++0x07
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A68++0x07
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A70++0x07
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A78++0x07
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A80++0x07
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A88++0x07
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A90++0x07
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A98++0x07
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA0++0x07
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA8++0x07
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB0++0x07
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB8++0x07
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC0++0x07
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC8++0x07
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD0++0x07
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD8++0x07
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE0++0x07
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE8++0x07
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF0++0x07
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF8++0x07
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B00++0x07
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B08++0x07
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B10++0x07
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B18++0x07
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B20++0x07
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B28++0x07
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B30++0x07
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B38++0x07
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B40++0x07
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B48++0x07
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B50++0x07
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B58++0x07
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B60++0x07
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B68++0x07
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B70++0x07
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B78++0x07
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B80++0x07
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B88++0x07
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B90++0x07
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B98++0x07
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA0++0x07
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA8++0x07
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB0++0x07
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB8++0x07
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC0++0x07
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC8++0x07
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD0++0x07
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD8++0x07
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE0++0x07
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE8++0x07
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF0++0x07
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF8++0x07
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C00++0x07
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C08++0x07
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C10++0x07
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C18++0x07
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C20++0x07
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C28++0x07
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C30++0x07
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C38++0x07
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C40++0x07
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C48++0x07
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C50++0x07
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C58++0x07
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C60++0x07
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C68++0x07
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C70++0x07
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C78++0x07
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C80++0x07
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C88++0x07
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C90++0x07
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C98++0x07
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA0++0x07
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA8++0x07
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB0++0x07
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB8++0x07
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC0++0x07
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC8++0x07
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD0++0x07
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD8++0x07
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE0++0x07
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE8++0x07
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF0++0x07
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF8++0x07
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D00++0x07
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D08++0x07
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D10++0x07
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D18++0x07
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D20++0x07
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D28++0x07
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D30++0x07
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D38++0x07
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D40++0x07
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D48++0x07
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D50++0x07
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D58++0x07
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D60++0x07
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D68++0x07
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D70++0x07
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D78++0x07
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D80++0x07
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D88++0x07
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D90++0x07
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D98++0x07
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA0++0x07
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA8++0x07
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB0++0x07
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB8++0x07
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC0++0x07
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC8++0x07
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD0++0x07
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD8++0x07
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE0++0x07
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE8++0x07
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF0++0x07
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF8++0x07
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E00++0x07
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E08++0x07
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E10++0x07
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E18++0x07
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E20++0x07
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E28++0x07
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E30++0x07
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E38++0x07
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E40++0x07
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E48++0x07
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E50++0x07
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E58++0x07
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E60++0x07
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E68++0x07
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E70++0x07
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E78++0x07
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E80++0x07
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E88++0x07
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E90++0x07
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E98++0x07
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA0++0x07
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA8++0x07
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB0++0x07
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB8++0x07
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC0++0x07
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC8++0x07
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED0++0x07
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED8++0x07
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE0++0x07
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE8++0x07
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF0++0x07
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF8++0x07
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F00++0x07
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F08++0x07
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F10++0x07
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F18++0x07
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F20++0x07
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F28++0x07
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F30++0x07
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F38++0x07
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F40++0x07
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F48++0x07
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F50++0x07
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F58++0x07
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F60++0x07
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F68++0x07
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F70++0x07
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F78++0x07
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F80++0x07
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F88++0x07
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F90++0x07
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F98++0x07
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA0++0x07
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA8++0x07
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB0++0x07
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB8++0x07
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC0++0x07
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC8++0x07
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD0++0x07
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD8++0x07
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE0++0x07
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE8++0x07
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF0++0x07
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF8++0x07
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7000++0x07
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7008++0x07
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7010++0x07
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7018++0x07
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7020++0x07
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7028++0x07
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7030++0x07
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7038++0x07
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7040++0x07
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7048++0x07
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7050++0x07
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7058++0x07
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7060++0x07
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7068++0x07
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7070++0x07
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7078++0x07
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7080++0x07
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7088++0x07
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7090++0x07
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7098++0x07
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A0++0x07
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A8++0x07
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B0++0x07
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B8++0x07
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C0++0x07
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C8++0x07
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D0++0x07
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D8++0x07
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E0++0x07
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E8++0x07
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F0++0x07
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F8++0x07
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7100++0x07
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7108++0x07
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7110++0x07
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7118++0x07
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7120++0x07
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7128++0x07
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7130++0x07
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7138++0x07
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7140++0x07
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7148++0x07
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7150++0x07
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7158++0x07
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7160++0x07
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7168++0x07
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7170++0x07
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7178++0x07
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7180++0x07
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7188++0x07
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7190++0x07
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7198++0x07
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A0++0x07
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A8++0x07
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B0++0x07
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B8++0x07
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C0++0x07
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C8++0x07
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D0++0x07
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D8++0x07
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E0++0x07
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E8++0x07
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F0++0x07
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F8++0x07
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7200++0x07
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7208++0x07
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7210++0x07
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7218++0x07
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7220++0x07
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7228++0x07
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7230++0x07
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7238++0x07
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7240++0x07
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7248++0x07
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7250++0x07
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7258++0x07
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7260++0x07
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7268++0x07
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7270++0x07
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7278++0x07
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7280++0x07
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7288++0x07
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7290++0x07
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7298++0x07
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A0++0x07
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A8++0x07
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B0++0x07
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B8++0x07
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C0++0x07
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C8++0x07
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D0++0x07
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D8++0x07
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E0++0x07
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E8++0x07
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F0++0x07
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F8++0x07
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7300++0x07
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7308++0x07
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7310++0x07
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7318++0x07
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7320++0x07
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7328++0x07
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7330++0x07
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7338++0x07
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7340++0x07
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7348++0x07
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7350++0x07
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7358++0x07
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7360++0x07
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7368++0x07
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7370++0x07
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7378++0x07
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7380++0x07
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7388++0x07
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7390++0x07
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7398++0x07
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A0++0x07
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A8++0x07
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B0++0x07
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B8++0x07
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C0++0x07
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C8++0x07
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D0++0x07
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D8++0x07
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E0++0x07
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E8++0x07
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F0++0x07
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F8++0x07
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7400++0x07
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7408++0x07
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7410++0x07
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7418++0x07
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7420++0x07
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7428++0x07
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7430++0x07
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7438++0x07
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7440++0x07
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7448++0x07
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7450++0x07
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7458++0x07
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7460++0x07
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7468++0x07
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7470++0x07
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7478++0x07
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7480++0x07
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7488++0x07
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7490++0x07
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7498++0x07
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A0++0x07
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A8++0x07
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B0++0x07
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B8++0x07
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C0++0x07
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C8++0x07
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D0++0x07
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D8++0x07
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E0++0x07
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E8++0x07
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F0++0x07
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F8++0x07
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7500++0x07
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7508++0x07
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7510++0x07
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7518++0x07
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7520++0x07
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7528++0x07
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7530++0x07
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7538++0x07
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7540++0x07
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7548++0x07
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7550++0x07
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7558++0x07
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7560++0x07
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7568++0x07
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7570++0x07
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7578++0x07
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7580++0x07
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7588++0x07
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7590++0x07
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7598++0x07
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A0++0x07
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A8++0x07
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B0++0x07
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B8++0x07
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C0++0x07
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C8++0x07
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D0++0x07
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D8++0x07
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E0++0x07
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E8++0x07
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F0++0x07
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F8++0x07
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7600++0x07
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7608++0x07
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7610++0x07
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7618++0x07
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7620++0x07
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7628++0x07
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7630++0x07
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7638++0x07
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7640++0x07
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7648++0x07
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7650++0x07
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7658++0x07
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7660++0x07
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7668++0x07
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7670++0x07
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7678++0x07
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7680++0x07
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7688++0x07
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7690++0x07
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7698++0x07
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A0++0x07
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A8++0x07
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B0++0x07
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B8++0x07
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C0++0x07
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C8++0x07
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D0++0x07
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D8++0x07
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E0++0x07
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E8++0x07
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F0++0x07
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F8++0x07
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7700++0x07
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7708++0x07
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7710++0x07
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7718++0x07
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7720++0x07
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7728++0x07
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7730++0x07
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7738++0x07
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7740++0x07
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7748++0x07
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7750++0x07
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7758++0x07
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7760++0x07
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7768++0x07
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7770++0x07
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7778++0x07
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7780++0x07
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7788++0x07
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7790++0x07
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7798++0x07
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A0++0x07
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A8++0x07
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B0++0x07
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B8++0x07
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C0++0x07
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C8++0x07
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D0++0x07
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D8++0x07
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E0++0x07
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E8++0x07
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F0++0x07
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F8++0x07
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7800++0x07
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7808++0x07
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7810++0x07
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7818++0x07
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7820++0x07
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7828++0x07
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7830++0x07
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7838++0x07
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7840++0x07
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7848++0x07
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7850++0x07
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7858++0x07
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7860++0x07
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7868++0x07
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7870++0x07
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7878++0x07
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7880++0x07
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7888++0x07
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7890++0x07
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7898++0x07
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A0++0x07
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A8++0x07
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B0++0x07
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B8++0x07
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C0++0x07
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C8++0x07
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D0++0x07
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D8++0x07
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E0++0x07
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E8++0x07
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F0++0x07
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F8++0x07
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7900++0x07
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7908++0x07
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7910++0x07
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7918++0x07
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7920++0x07
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7928++0x07
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7930++0x07
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7938++0x07
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7940++0x07
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7948++0x07
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7950++0x07
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7958++0x07
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7960++0x07
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7968++0x07
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7970++0x07
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7978++0x07
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7980++0x07
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7988++0x07
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7990++0x07
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7998++0x07
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A0++0x07
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A8++0x07
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B0++0x07
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B8++0x07
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C0++0x07
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C8++0x07
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D0++0x07
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D8++0x07
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E0++0x07
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E8++0x07
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F0++0x07
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F8++0x07
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A00++0x07
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A08++0x07
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A10++0x07
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A18++0x07
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A20++0x07
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A28++0x07
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A30++0x07
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A38++0x07
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A40++0x07
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A48++0x07
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A50++0x07
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A58++0x07
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A60++0x07
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A68++0x07
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A70++0x07
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A78++0x07
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A80++0x07
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A88++0x07
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A90++0x07
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A98++0x07
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA0++0x07
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA8++0x07
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB0++0x07
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB8++0x07
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC0++0x07
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC8++0x07
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD0++0x07
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD8++0x07
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE0++0x07
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE8++0x07
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF0++0x07
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF8++0x07
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B00++0x07
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B08++0x07
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B10++0x07
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B18++0x07
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B20++0x07
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B28++0x07
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B30++0x07
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B38++0x07
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B40++0x07
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B48++0x07
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B50++0x07
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B58++0x07
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B60++0x07
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B68++0x07
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B70++0x07
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B78++0x07
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B80++0x07
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B88++0x07
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B90++0x07
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B98++0x07
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA0++0x07
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA8++0x07
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB0++0x07
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB8++0x07
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC0++0x07
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC8++0x07
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD0++0x07
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD8++0x07
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE0++0x07
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE8++0x07
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF0++0x07
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF8++0x07
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C00++0x07
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C08++0x07
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C10++0x07
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C18++0x07
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C20++0x07
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C28++0x07
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C30++0x07
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C38++0x07
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C40++0x07
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C48++0x07
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C50++0x07
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C58++0x07
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C60++0x07
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C68++0x07
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C70++0x07
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C78++0x07
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C80++0x07
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C88++0x07
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C90++0x07
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C98++0x07
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA0++0x07
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA8++0x07
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB0++0x07
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB8++0x07
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC0++0x07
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC8++0x07
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD0++0x07
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD8++0x07
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE0++0x07
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE8++0x07
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF0++0x07
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF8++0x07
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D00++0x07
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D08++0x07
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D10++0x07
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D18++0x07
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D20++0x07
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D28++0x07
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D30++0x07
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D38++0x07
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D40++0x07
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D48++0x07
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D50++0x07
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D58++0x07
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D60++0x07
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D68++0x07
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D70++0x07
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D78++0x07
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D80++0x07
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D88++0x07
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D90++0x07
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D98++0x07
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA0++0x07
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA8++0x07
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB0++0x07
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB8++0x07
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC0++0x07
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC8++0x07
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD0++0x07
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD8++0x07
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE0++0x07
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE8++0x07
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF0++0x07
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF8++0x07
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E00++0x07
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E08++0x07
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E10++0x07
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E18++0x07
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E20++0x07
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E28++0x07
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E30++0x07
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E38++0x07
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E40++0x07
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E48++0x07
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E50++0x07
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E58++0x07
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E60++0x07
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E68++0x07
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E70++0x07
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E78++0x07
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E80++0x07
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E88++0x07
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E90++0x07
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E98++0x07
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA0++0x07
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA8++0x07
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB0++0x07
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB8++0x07
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC0++0x07
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC8++0x07
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED0++0x07
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED8++0x07
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE0++0x07
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE8++0x07
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF0++0x07
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF8++0x07
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
tree.end
width 22.
tree "Implementation Defined Test Registers"
rgroup.long 0xC000++0x03
line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR"
bitfld.long 0x00 31. " SRWP     ,Super Register Write Pending" "Not pending,Pending"
wgroup.long 0xC004++0x03
line.long 0x00 "GICD_ERRTESTR,Error Test Register"
bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High"
bitfld.long 0x00 0. "         ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High"
textline "                               "
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
rgroup.long 0xC084++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " SPIS63  ,SPI Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  SPIS62  ,SPI Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  SPIS61  ,SPI Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS60  ,SPI Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  SPIS59  ,SPI Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  SPIS58  ,SPI Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS57  ,SPI Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  SPIS56  ,SPI Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  SPIS55  ,SPI Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS54  ,SPI Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  SPIS53  ,SPI Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  SPIS52  ,SPI Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS51  ,SPI Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  SPIS50  ,SPI Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  SPIS49  ,SPI Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS48  ,SPI Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  SPIS47  ,SPI Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  SPIS46  ,SPI Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS45  ,SPI Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  SPIS44  ,SPI Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  SPIS43  ,SPI Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS42  ,SPI Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  SPIS41  ,SPI Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  SPIS40  ,SPI Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS39  ,SPI Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  SPIS38  ,SPI Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  SPIS37  ,SPI Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS36  ,SPI Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  SPIS35  ,SPI Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  SPIS34  ,SPI Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS33  ,SPI Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  SPIS32  ,SPI Status Bit 32" "Low,High"
else
hgroup.long 0xC084++0x03
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
rgroup.long 0xC088++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " SPIS95  ,SPI Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  SPIS94  ,SPI Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  SPIS93  ,SPI Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS92  ,SPI Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  SPIS91  ,SPI Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  SPIS90  ,SPI Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS89  ,SPI Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  SPIS88  ,SPI Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  SPIS87  ,SPI Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS86  ,SPI Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  SPIS85  ,SPI Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  SPIS84  ,SPI Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS83  ,SPI Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  SPIS82  ,SPI Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  SPIS81  ,SPI Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS80  ,SPI Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  SPIS79  ,SPI Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  SPIS78  ,SPI Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS77  ,SPI Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  SPIS76  ,SPI Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  SPIS75  ,SPI Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS74  ,SPI Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  SPIS73  ,SPI Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  SPIS72  ,SPI Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS71  ,SPI Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  SPIS70  ,SPI Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  SPIS69  ,SPI Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS68  ,SPI Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  SPIS67  ,SPI Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  SPIS66  ,SPI Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS65  ,SPI Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  SPIS64  ,SPI Status Bit 64" "Low,High"
else
hgroup.long 0xC088++0x03
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
rgroup.long 0xC08C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  SPIS126 ,SPI Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  SPIS125 ,SPI Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  SPIS123 ,SPI Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  SPIS122 ,SPI Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  SPIS120 ,SPI Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  SPIS119 ,SPI Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  SPIS117 ,SPI Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  SPIS116 ,SPI Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  SPIS114 ,SPI Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  SPIS113 ,SPI Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  SPIS111 ,SPI Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  SPIS110 ,SPI Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  SPIS108 ,SPI Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  SPIS107 ,SPI Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  SPIS105 ,SPI Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  SPIS104 ,SPI Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  SPIS102 ,SPI Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  SPIS101 ,SPI Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  SPIS99  ,SPI Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  SPIS98  ,SPI Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS97  ,SPI Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  SPIS96  ,SPI Status Bit 96" "Low,High"
else
hgroup.long 0xC08C++0x03
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
rgroup.long 0xC090++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  SPIS158 ,SPI Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  SPIS157 ,SPI Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  SPIS155 ,SPI Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  SPIS154 ,SPI Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  SPIS152 ,SPI Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  SPIS151 ,SPI Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  SPIS149 ,SPI Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  SPIS148 ,SPI Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  SPIS146 ,SPI Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  SPIS145 ,SPI Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  SPIS143 ,SPI Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  SPIS142 ,SPI Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  SPIS140 ,SPI Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  SPIS139 ,SPI Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  SPIS137 ,SPI Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  SPIS136 ,SPI Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  SPIS134 ,SPI Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  SPIS133 ,SPI Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  SPIS131 ,SPI Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  SPIS130 ,SPI Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  SPIS128 ,SPI Status Bit 128" "Low,High"
else
hgroup.long 0xC090++0x03
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
rgroup.long 0xC094++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  SPIS190 ,SPI Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  SPIS189 ,SPI Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  SPIS187 ,SPI Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  SPIS186 ,SPI Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  SPIS184 ,SPI Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  SPIS183 ,SPI Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  SPIS181 ,SPI Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  SPIS180 ,SPI Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  SPIS178 ,SPI Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  SPIS177 ,SPI Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  SPIS175 ,SPI Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  SPIS174 ,SPI Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  SPIS172 ,SPI Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  SPIS171 ,SPI Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  SPIS169 ,SPI Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  SPIS168 ,SPI Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  SPIS166 ,SPI Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  SPIS165 ,SPI Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  SPIS163 ,SPI Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  SPIS162 ,SPI Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  SPIS160 ,SPI Status Bit 160" "Low,High"
else
hgroup.long 0xC094++0x03
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
rgroup.long 0xC098++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  SPIS222 ,SPI Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  SPIS221 ,SPI Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  SPIS219 ,SPI Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  SPIS218 ,SPI Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  SPIS216 ,SPI Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  SPIS215 ,SPI Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  SPIS213 ,SPI Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  SPIS212 ,SPI Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  SPIS210 ,SPI Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  SPIS209 ,SPI Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  SPIS207 ,SPI Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  SPIS206 ,SPI Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  SPIS204 ,SPI Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  SPIS203 ,SPI Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  SPIS201 ,SPI Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  SPIS200 ,SPI Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  SPIS198 ,SPI Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  SPIS197 ,SPI Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  SPIS195 ,SPI Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  SPIS194 ,SPI Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  SPIS192 ,SPI Status Bit 192" "Low,High"
else
hgroup.long 0xC098++0x03
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
rgroup.long 0xC09C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  SPIS254 ,SPI Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  SPIS253 ,SPI Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  SPIS251 ,SPI Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  SPIS250 ,SPI Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  SPIS248 ,SPI Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  SPIS247 ,SPI Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  SPIS245 ,SPI Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  SPIS244 ,SPI Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  SPIS242 ,SPI Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  SPIS241 ,SPI Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  SPIS239 ,SPI Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  SPIS238 ,SPI Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  SPIS236 ,SPI Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  SPIS235 ,SPI Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  SPIS233 ,SPI Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  SPIS232 ,SPI Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  SPIS230 ,SPI Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  SPIS229 ,SPI Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  SPIS227 ,SPI Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  SPIS226 ,SPI Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  SPIS224 ,SPI Status Bit 224" "Low,High"
else
hgroup.long 0xC09C++0x03
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
rgroup.long 0xC0A0++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  SPIS286 ,SPI Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  SPIS285 ,SPI Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  SPIS283 ,SPI Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  SPIS282 ,SPI Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  SPIS280 ,SPI Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  SPIS279 ,SPI Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  SPIS277 ,SPI Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  SPIS276 ,SPI Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  SPIS274 ,SPI Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  SPIS273 ,SPI Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  SPIS271 ,SPI Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  SPIS270 ,SPI Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  SPIS268 ,SPI Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  SPIS267 ,SPI Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  SPIS265 ,SPI Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  SPIS264 ,SPI Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  SPIS262 ,SPI Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  SPIS261 ,SPI Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  SPIS259 ,SPI Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  SPIS258 ,SPI Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  SPIS256 ,SPI Status Bit 256" "Low,High"
else
hgroup.long 0xC0A0++0x03
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
rgroup.long 0xC0A4++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  SPIS318 ,SPI Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  SPIS317 ,SPI Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  SPIS315 ,SPI Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  SPIS314 ,SPI Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  SPIS312 ,SPI Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  SPIS311 ,SPI Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  SPIS309 ,SPI Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  SPIS308 ,SPI Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  SPIS306 ,SPI Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  SPIS305 ,SPI Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  SPIS303 ,SPI Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  SPIS302 ,SPI Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  SPIS300 ,SPI Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  SPIS299 ,SPI Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  SPIS297 ,SPI Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  SPIS296 ,SPI Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  SPIS294 ,SPI Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  SPIS293 ,SPI Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  SPIS291 ,SPI Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  SPIS290 ,SPI Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  SPIS288 ,SPI Status Bit 288" "Low,High"
else
hgroup.long 0xC0A4++0x03
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0xC0A8++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  SPIS350 ,SPI Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  SPIS349 ,SPI Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  SPIS347 ,SPI Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  SPIS346 ,SPI Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  SPIS344 ,SPI Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  SPIS343 ,SPI Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  SPIS341 ,SPI Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  SPIS340 ,SPI Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  SPIS338 ,SPI Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  SPIS337 ,SPI Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  SPIS335 ,SPI Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  SPIS334 ,SPI Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  SPIS332 ,SPI Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  SPIS331 ,SPI Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  SPIS329 ,SPI Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  SPIS328 ,SPI Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  SPIS326 ,SPI Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  SPIS325 ,SPI Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  SPIS323 ,SPI Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  SPIS322 ,SPI Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  SPIS320 ,SPI Status Bit 320" "Low,High"
else
hgroup.long 0xC0A8++0x03
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0xC0AC++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  SPIS382 ,SPI Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  SPIS381 ,SPI Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  SPIS379 ,SPI Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  SPIS378 ,SPI Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  SPIS376 ,SPI Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  SPIS375 ,SPI Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  SPIS373 ,SPI Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  SPIS372 ,SPI Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  SPIS370 ,SPI Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  SPIS369 ,SPI Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  SPIS367 ,SPI Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  SPIS366 ,SPI Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  SPIS364 ,SPI Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  SPIS363 ,SPI Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  SPIS361 ,SPI Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  SPIS360 ,SPI Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  SPIS358 ,SPI Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  SPIS357 ,SPI Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  SPIS355 ,SPI Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  SPIS354 ,SPI Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  SPIS352 ,SPI Status Bit 352" "Low,High"
else
hgroup.long 0xC0AC++0x03
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0xC0B0++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  SPIS414 ,SPI Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  SPIS413 ,SPI Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  SPIS411 ,SPI Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  SPIS410 ,SPI Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  SPIS408 ,SPI Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  SPIS407 ,SPI Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  SPIS405 ,SPI Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  SPIS404 ,SPI Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  SPIS402 ,SPI Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  SPIS401 ,SPI Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  SPIS399 ,SPI Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  SPIS398 ,SPI Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  SPIS396 ,SPI Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  SPIS395 ,SPI Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  SPIS393 ,SPI Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  SPIS392 ,SPI Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  SPIS390 ,SPI Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  SPIS389 ,SPI Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  SPIS387 ,SPI Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  SPIS386 ,SPI Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  SPIS384 ,SPI Status Bit 384" "Low,High"
else
hgroup.long 0xC0B0++0x03
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0xC0B4++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  SPIS446 ,SPI Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  SPIS445 ,SPI Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  SPIS443 ,SPI Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  SPIS442 ,SPI Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  SPIS440 ,SPI Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  SPIS439 ,SPI Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  SPIS437 ,SPI Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  SPIS436 ,SPI Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  SPIS434 ,SPI Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  SPIS433 ,SPI Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  SPIS431 ,SPI Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  SPIS430 ,SPI Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  SPIS428 ,SPI Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  SPIS427 ,SPI Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  SPIS425 ,SPI Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  SPIS424 ,SPI Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  SPIS422 ,SPI Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  SPIS421 ,SPI Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  SPIS419 ,SPI Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  SPIS418 ,SPI Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  SPIS416 ,SPI Status Bit 416" "Low,High"
else
hgroup.long 0xC0B4++0x03
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0xC0B8++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  SPIS478 ,SPI Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  SPIS477 ,SPI Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  SPIS475 ,SPI Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  SPIS474 ,SPI Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  SPIS472 ,SPI Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  SPIS471 ,SPI Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  SPIS469 ,SPI Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  SPIS468 ,SPI Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  SPIS466 ,SPI Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  SPIS465 ,SPI Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  SPIS463 ,SPI Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  SPIS462 ,SPI Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  SPIS460 ,SPI Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  SPIS459 ,SPI Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  SPIS457 ,SPI Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  SPIS456 ,SPI Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  SPIS454 ,SPI Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  SPIS453 ,SPI Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  SPIS451 ,SPI Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  SPIS450 ,SPI Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  SPIS448 ,SPI Status Bit 448" "Low,High"
else
hgroup.long 0xC0B8++0x03
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0xC0BC++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  SPIS510 ,SPI Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  SPIS509 ,SPI Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  SPIS507 ,SPI Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  SPIS506 ,SPI Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  SPIS504 ,SPI Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  SPIS503 ,SPI Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  SPIS501 ,SPI Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  SPIS500 ,SPI Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  SPIS498 ,SPI Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  SPIS497 ,SPI Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  SPIS495 ,SPI Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  SPIS494 ,SPI Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  SPIS492 ,SPI Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  SPIS491 ,SPI Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  SPIS489 ,SPI Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  SPIS488 ,SPI Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  SPIS486 ,SPI Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  SPIS485 ,SPI Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  SPIS483 ,SPI Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  SPIS482 ,SPI Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  SPIS480 ,SPI Status Bit 480" "Low,High"
else
hgroup.long 0xC0BC++0x03
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
rgroup.long 0xC0C0++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  SPIS542 ,SPI Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  SPIS541 ,SPI Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  SPIS539 ,SPI Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  SPIS538 ,SPI Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  SPIS536 ,SPI Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  SPIS535 ,SPI Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  SPIS533 ,SPI Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  SPIS532 ,SPI Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  SPIS530 ,SPI Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  SPIS529 ,SPI Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  SPIS527 ,SPI Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  SPIS526 ,SPI Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  SPIS524 ,SPI Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  SPIS523 ,SPI Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  SPIS521 ,SPI Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  SPIS520 ,SPI Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  SPIS518 ,SPI Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  SPIS517 ,SPI Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  SPIS515 ,SPI Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  SPIS514 ,SPI Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  SPIS512 ,SPI Status Bit 512" "Low,High"
else
hgroup.long 0xC0C0++0x03
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
rgroup.long 0xC0C4++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  SPIS574 ,SPI Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  SPIS573 ,SPI Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  SPIS571 ,SPI Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  SPIS570 ,SPI Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  SPIS568 ,SPI Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  SPIS567 ,SPI Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  SPIS565 ,SPI Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  SPIS564 ,SPI Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  SPIS562 ,SPI Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  SPIS561 ,SPI Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  SPIS559 ,SPI Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  SPIS558 ,SPI Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  SPIS556 ,SPI Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  SPIS555 ,SPI Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  SPIS553 ,SPI Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  SPIS552 ,SPI Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  SPIS550 ,SPI Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  SPIS549 ,SPI Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  SPIS547 ,SPI Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  SPIS546 ,SPI Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  SPIS544 ,SPI Status Bit 544" "Low,High"
else
hgroup.long 0xC0C4++0x03
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
rgroup.long 0xC0C8++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  SPIS606 ,SPI Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  SPIS605 ,SPI Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  SPIS603 ,SPI Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  SPIS602 ,SPI Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  SPIS600 ,SPI Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  SPIS599 ,SPI Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  SPIS597 ,SPI Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  SPIS596 ,SPI Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  SPIS594 ,SPI Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  SPIS593 ,SPI Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  SPIS591 ,SPI Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  SPIS590 ,SPI Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  SPIS588 ,SPI Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  SPIS587 ,SPI Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  SPIS585 ,SPI Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  SPIS584 ,SPI Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  SPIS582 ,SPI Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  SPIS581 ,SPI Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  SPIS579 ,SPI Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  SPIS578 ,SPI Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  SPIS576 ,SPI Status Bit 576" "Low,High"
else
hgroup.long 0xC0C8++0x03
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
rgroup.long 0xC0CC++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  SPIS638 ,SPI Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  SPIS637 ,SPI Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  SPIS635 ,SPI Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  SPIS634 ,SPI Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  SPIS632 ,SPI Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  SPIS631 ,SPI Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  SPIS629 ,SPI Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  SPIS628 ,SPI Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  SPIS626 ,SPI Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  SPIS625 ,SPI Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  SPIS623 ,SPI Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  SPIS622 ,SPI Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  SPIS620 ,SPI Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  SPIS619 ,SPI Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  SPIS617 ,SPI Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  SPIS616 ,SPI Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  SPIS614 ,SPI Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  SPIS613 ,SPI Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  SPIS611 ,SPI Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  SPIS610 ,SPI Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  SPIS608 ,SPI Status Bit 608" "Low,High"
else
hgroup.long 0xC0CC++0x03
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
rgroup.long 0xC0D0++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  SPIS670 ,SPI Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  SPIS669 ,SPI Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  SPIS667 ,SPI Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  SPIS666 ,SPI Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  SPIS664 ,SPI Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  SPIS663 ,SPI Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  SPIS661 ,SPI Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  SPIS660 ,SPI Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  SPIS658 ,SPI Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  SPIS657 ,SPI Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  SPIS655 ,SPI Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  SPIS654 ,SPI Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  SPIS652 ,SPI Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  SPIS651 ,SPI Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  SPIS649 ,SPI Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  SPIS648 ,SPI Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  SPIS646 ,SPI Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  SPIS645 ,SPI Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  SPIS643 ,SPI Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  SPIS642 ,SPI Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  SPIS640 ,SPI Status Bit 640" "Low,High"
else
hgroup.long 0xC0D0++0x03
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
rgroup.long 0xC0D4++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  SPIS702 ,SPI Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  SPIS701 ,SPI Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  SPIS699 ,SPI Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  SPIS698 ,SPI Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  SPIS696 ,SPI Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  SPIS695 ,SPI Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  SPIS693 ,SPI Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  SPIS692 ,SPI Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  SPIS690 ,SPI Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  SPIS689 ,SPI Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  SPIS687 ,SPI Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  SPIS686 ,SPI Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  SPIS684 ,SPI Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  SPIS683 ,SPI Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  SPIS681 ,SPI Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  SPIS680 ,SPI Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  SPIS678 ,SPI Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  SPIS677 ,SPI Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  SPIS675 ,SPI Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  SPIS674 ,SPI Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  SPIS672 ,SPI Status Bit 672" "Low,High"
else
hgroup.long 0xC0D4++0x03
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
rgroup.long 0xC0D8++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  SPIS734 ,SPI Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  SPIS733 ,SPI Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  SPIS731 ,SPI Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  SPIS730 ,SPI Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  SPIS728 ,SPI Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  SPIS727 ,SPI Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  SPIS725 ,SPI Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  SPIS724 ,SPI Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  SPIS722 ,SPI Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  SPIS721 ,SPI Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  SPIS719 ,SPI Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  SPIS718 ,SPI Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  SPIS716 ,SPI Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  SPIS715 ,SPI Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  SPIS713 ,SPI Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  SPIS712 ,SPI Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  SPIS710 ,SPI Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  SPIS709 ,SPI Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  SPIS707 ,SPI Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  SPIS706 ,SPI Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  SPIS704 ,SPI Status Bit 704" "Low,High"
else
hgroup.long 0xC0D8++0x03
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
rgroup.long 0xC0DC++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  SPIS766 ,SPI Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  SPIS765 ,SPI Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  SPIS763 ,SPI Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  SPIS762 ,SPI Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  SPIS760 ,SPI Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  SPIS759 ,SPI Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  SPIS757 ,SPI Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  SPIS756 ,SPI Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  SPIS754 ,SPI Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  SPIS753 ,SPI Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  SPIS751 ,SPI Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  SPIS750 ,SPI Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  SPIS748 ,SPI Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  SPIS747 ,SPI Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  SPIS745 ,SPI Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  SPIS744 ,SPI Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  SPIS742 ,SPI Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  SPIS741 ,SPI Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  SPIS739 ,SPI Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  SPIS738 ,SPI Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  SPIS736 ,SPI Status Bit 736" "Low,High"
else
hgroup.long 0xC0DC++0x03
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
rgroup.long 0xC0E0++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  SPIS798 ,SPI Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  SPIS797 ,SPI Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  SPIS795 ,SPI Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  SPIS794 ,SPI Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  SPIS792 ,SPI Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  SPIS791 ,SPI Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  SPIS789 ,SPI Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  SPIS788 ,SPI Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  SPIS786 ,SPI Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  SPIS785 ,SPI Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  SPIS783 ,SPI Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  SPIS782 ,SPI Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  SPIS780 ,SPI Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  SPIS779 ,SPI Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  SPIS777 ,SPI Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  SPIS776 ,SPI Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  SPIS774 ,SPI Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  SPIS773 ,SPI Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  SPIS771 ,SPI Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  SPIS770 ,SPI Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  SPIS768 ,SPI Status Bit 768" "Low,High"
else
hgroup.long 0xC0E0++0x03
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
rgroup.long 0xC0E4++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  SPIS830 ,SPI Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  SPIS829 ,SPI Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  SPIS827 ,SPI Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  SPIS826 ,SPI Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  SPIS824 ,SPI Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  SPIS823 ,SPI Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  SPIS821 ,SPI Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  SPIS820 ,SPI Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  SPIS818 ,SPI Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  SPIS817 ,SPI Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  SPIS815 ,SPI Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  SPIS814 ,SPI Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  SPIS812 ,SPI Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  SPIS811 ,SPI Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  SPIS809 ,SPI Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  SPIS808 ,SPI Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  SPIS806 ,SPI Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  SPIS805 ,SPI Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  SPIS803 ,SPI Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  SPIS802 ,SPI Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  SPIS800 ,SPI Status Bit 800" "Low,High"
else
hgroup.long 0xC0E4++0x03
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0xC0E8++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  SPIS862 ,SPI Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  SPIS861 ,SPI Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  SPIS859 ,SPI Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  SPIS858 ,SPI Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  SPIS856 ,SPI Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  SPIS855 ,SPI Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  SPIS853 ,SPI Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  SPIS852 ,SPI Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  SPIS850 ,SPI Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  SPIS849 ,SPI Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  SPIS847 ,SPI Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  SPIS846 ,SPI Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  SPIS844 ,SPI Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  SPIS843 ,SPI Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  SPIS841 ,SPI Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  SPIS840 ,SPI Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  SPIS838 ,SPI Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  SPIS837 ,SPI Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  SPIS835 ,SPI Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  SPIS834 ,SPI Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  SPIS832 ,SPI Status Bit 832" "Low,High"
else
hgroup.long 0xC0E8++0x03
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0xC0EC++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  SPIS894 ,SPI Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  SPIS893 ,SPI Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  SPIS891 ,SPI Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  SPIS890 ,SPI Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  SPIS888 ,SPI Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  SPIS887 ,SPI Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  SPIS885 ,SPI Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  SPIS884 ,SPI Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  SPIS882 ,SPI Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  SPIS881 ,SPI Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  SPIS879 ,SPI Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  SPIS878 ,SPI Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  SPIS876 ,SPI Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  SPIS875 ,SPI Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  SPIS873 ,SPI Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  SPIS872 ,SPI Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  SPIS870 ,SPI Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  SPIS869 ,SPI Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  SPIS867 ,SPI Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  SPIS866 ,SPI Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  SPIS864 ,SPI Status Bit 864" "Low,High"
else
hgroup.long 0xC0EC++0x03
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0xC0F0++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  SPIS926 ,SPI Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  SPIS925 ,SPI Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  SPIS923 ,SPI Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  SPIS922 ,SPI Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  SPIS920 ,SPI Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  SPIS919 ,SPI Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  SPIS917 ,SPI Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  SPIS916 ,SPI Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  SPIS914 ,SPI Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  SPIS913 ,SPI Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  SPIS911 ,SPI Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  SPIS910 ,SPI Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  SPIS908 ,SPI Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  SPIS907 ,SPI Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  SPIS905 ,SPI Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  SPIS904 ,SPI Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  SPIS902 ,SPI Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  SPIS901 ,SPI Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  SPIS899 ,SPI Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  SPIS898 ,SPI Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  SPIS896 ,SPI Status Bit 896" "Low,High"
else
hgroup.long 0xC0F0++0x03
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0xC0F4++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  SPIS958 ,SPI Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  SPIS957 ,SPI Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  SPIS955 ,SPI Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  SPIS954 ,SPI Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  SPIS952 ,SPI Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  SPIS951 ,SPI Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  SPIS949 ,SPI Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  SPIS948 ,SPI Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  SPIS946 ,SPI Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  SPIS945 ,SPI Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  SPIS943 ,SPI Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  SPIS942 ,SPI Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  SPIS940 ,SPI Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  SPIS939 ,SPI Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  SPIS937 ,SPI Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  SPIS936 ,SPI Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  SPIS934 ,SPI Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  SPIS933 ,SPI Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  SPIS931 ,SPI Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  SPIS930 ,SPI Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  SPIS928 ,SPI Status Bit 928" "Low,High"
else
hgroup.long 0xC0F4++0x03
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0xC0F8++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High"
bitfld.long 0x00 30. "  SPIS990 ,SPI Status Bit 990" "Low,High"
bitfld.long 0x00 29. "  SPIS989 ,SPI Status Bit 989" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High"
bitfld.long 0x00 27. "  SPIS987 ,SPI Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  SPIS986 ,SPI Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  SPIS984 ,SPI Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  SPIS983 ,SPI Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  SPIS981 ,SPI Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  SPIS980 ,SPI Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  SPIS978 ,SPI Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  SPIS977 ,SPI Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  SPIS975 ,SPI Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  SPIS974 ,SPI Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  SPIS972 ,SPI Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  SPIS971 ,SPI Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  SPIS969 ,SPI Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  SPIS968 ,SPI Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  SPIS966 ,SPI Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  SPIS965 ,SPI Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  SPIS963 ,SPI Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  SPIS962 ,SPI Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  SPIS960 ,SPI Status Bit 960" "Low,High"
else
hgroup.long 0xC0F8++0x03
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
endif
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
base (COMP.BASE("GICD",-1.)+0x20000)
width 24.
tree "Interrupt Translation Service"
group.long 0x00++0x03
line.long 0x00 "GITS_CTLR,ITS Control Register"
rbitfld.long 0x00 31. "         QUIESCENT              ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
bitfld.long 0x00 0. "                      ENABLED                ,Controls whether the ITS is enabled" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID                 ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "                            VAR                    ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " REV                    ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                                 IMP                    ,Implementer"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 2. "                                 CCT                    ,Cumulative Collection Tables" "0,1"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.quad 0x00 2. " CCT                    ,Cumulative Collection Tables" "0,1"
else
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.quad 0x80++0x07
line.quad 0x00 "GITS_CBASER,The command queue control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
bitfld.quad 0x00 59.--61. "                      INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "    PHYSICAL_ADDRESS       ,Bits [51:12] of the base physical address of the command queue"
textline "                                         "
bitfld.quad 0x00 10.--11. " SHAREABILITY           ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                    SIZE                   ,The number of 4KB pages of physical memory allocated to the command queue minus one"
group.quad 0x88++0x7
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               RETRY                  ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
group.quad 0x90++0x07
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               STALLED                ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00)
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                               SIZE                   ,The number of pages of physical memory allocated to the table minus one"
endif
textline "                                         "
wgroup.long 0xC000++0x03
line.long 0x00 "GITS_TRKCTLR,Tracking Control Register"
bitfld.long 0x00 1. "         LPI_TRACK              ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture"
bitfld.long 0x00 0. "  CACHE_COUNT_RESET      ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset"
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 6. "         PID_OUT_OF_RANGE       ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1"
bitfld.long 0x00 5. "          TARGET_OUT_OF_RANGE    ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1"
textline "                                 "
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 3. "         INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
bitfld.long 0x00 2. "          DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
textline "                                 "
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
else
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC008++0x03
line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
hexmask.long.tbyte 0x00 0.--19. 1. "         LPI_DID                ,The Device ID for the interrupt that was tracked"
else
hgroup.long 0xC008++0x03
hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC00C++0x03
line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_PID                ,The ID after translation for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC00C++0x03
hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC010++0x03
line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_ID                 ,The ID before translation of the interrupt that was tracked"
else
hgroup.long 0xC010++0x03
hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC014++0x03
line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
hexmask.long.byte 0x00 0.--6. 1. "         LPI_TARGET_CORE        ,The target core for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC014++0x03
hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
endif
rgroup.long 0xC018++0x03
line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         ITE_CACHE_HITS         ,Number of hits in the ITE cache"
hexmask.long.word 0x00 0.--15. 1. "       ITE_CACHE_MISSES       ,Number of misses in the ITE cache"
rgroup.long 0xC01C++0x03
line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         LPI_CACHE_HITS         ,Number of hits in the LPI cache"
hexmask.long.word 0x00 0.--15. 1. "       LPI_CACHE_MISSES       ,Number of misses in the LPI cache"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         PART_0                 ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "         DES_1                  ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         PART_1                 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "         ARCHREV                ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "   JEDEC                  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
textline "                                 "
bitfld.long 0x00 0.--2. "         DES_1                  ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "         REVAND                 ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         CMOD                   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "         SIZE                   ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         DES_2                  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
textline "                                 "
base (COMP.BASE("GICD",-1.)+0x20000)+0x10000
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01)
wgroup.long 0x40++0x03
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
else
hgroup.long 0x40++0x03
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
endif
tree.end
width 0x0B
base COMP.BASE("GICR",-1.)
width 17.
tree "Redistributor Interface"
tree "Control Registers"
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID    ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "           VAR            ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 12.--15. " REV       ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                IMP            ,Implementer"
rgroup.quad 0x0008++0x07
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
hexmask.quad.byte 0x00 56.--63. 1. " AFF3      ,Affinity level 3 value for the Redistributor"
hexmask.quad.byte 0x00 48.--55. 1. "                AFF2           ,Affinity level 2 value for the Redistributor"
hexmask.quad.byte 0x00 40.--47. 1. "              AFF1             ,Affinity level 1 value for the Redistributor"
textline "                                  "
hexmask.quad.byte 0x00 32.--39. 1. " AFF0      ,Affinity level 0 value for the Redistributor"
bitfld.quad 0x00 24.--25. "                COMMONLPIAFF   ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1"
hexmask.quad.word 0x00 8.--23. 1. "  PROCESSOR_NUMBER ,A unique identifier for the PE"
textline "                                  "
bitfld.quad 0x00 5. " DPGS      ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
bitfld.quad 0x00 4. "     LAST           ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
bitfld.quad 0x00 3. "     DIRECTLPI        ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
textline "                                  "
bitfld.quad 0x00 0. " PLPIS     ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
group.long 0x0014++0x03
line.long 0x00 "GICR_WAKER,Power Management Control Register"
bitfld.long 0x00 31. "         QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent"
bitfld.long 0x00 2. "     CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
bitfld.long 0x00 1. "   PROCESSORASLEEP  ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
textline "                                  "
bitfld.long 0x00 0. " SLEEP     ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
textline "                                  "
else
hgroup.long 0x0014++0x03
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
endif
group.quad 0x070++0x07
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
bitfld.quad 0x00 56.--58. " OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
textline "                                  "
bitfld.quad 0x00 10.--11. " SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
bitfld.quad 0x00 7.--9. "                  INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                  "
bitfld.quad 0x00 0.--4. " IDBITS           ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
group.quad 0x78++0x07
line.quad 0x00 "GICR_PENDBASER,LPI pending table base register"
bitfld.quad 0x00 62. "         PTZ              ,Pending Table Zero" "Not zero,Zero" 
bitfld.quad 0x00 56.--58. "                         OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
textline "                                  "
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
bitfld.quad 0x00 10.--11. "                 SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                  "
bitfld.quad 0x00 7.--9. " INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                 "
tree.end
tree "SGI and PPI Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9  ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8  ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6  ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5  ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3  ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2  ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0  ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30 ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29 ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27 ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26 ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24 ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23 ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21 ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20 ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18 ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17 ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15 ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14 ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12 ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11 ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9  ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8  ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6  ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5  ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3  ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2  ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0  ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x10080++0x03
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
textline "                          "
width 24.
group.long 0x10100++0x03
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRENB31    ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRENB30    ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRENB29    ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRENB28    ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRENB27    ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRENB26    ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRENB25    ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRENB24    ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRENB23    ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRENB22    ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRENB21    ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRENB20    ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRENB19    ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRENB18    ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRENB17    ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRENB16    ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRENB15    ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRENB14    ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRENB13    ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRENB12    ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRENB11    ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRENB10    ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRENB9     ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRENB8     ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRENB7     ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRENB6     ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRENB5     ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRENB4     ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRENB3     ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRENB2     ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRENB1     ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRENB0     ,Set/Clear Enable Bit 0" "Disabled,Enabled"
group.long 0x10200++0x03
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
group.long 0x10300++0x03
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9  ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8  ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRACTIVE7  ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6  ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5  ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRACTIVE4  ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3  ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2  ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRACTIVE1  ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0  ,Set/Clear Active Bit 0" "Not active,Active"
textline "                                 "
width 18.
group.long 0x10400++0x03
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID2    ,Interrupt ID2    Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID0    ,Interrupt ID0    Priority/Priority Byte Offset 0   "
group.long 0x10404++0x03
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID6    ,Interrupt ID6    Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID4    ,Interrupt ID4    Priority/Priority Byte Offset 4   "
group.long 0x10408++0x03
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID10   ,Interrupt ID10   Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID8    ,Interrupt ID8    Priority/Priority Byte Offset 8   "
group.long 0x1040C++0x03
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID14   ,Interrupt ID14   Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID12   ,Interrupt ID12   Priority/Priority Byte Offset 12  "
group.long 0x10410++0x03
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID18   ,Interrupt ID18   Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID16   ,Interrupt ID16   Priority/Priority Byte Offset 16  "
group.long 0x10414++0x03
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID22   ,Interrupt ID22   Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID20   ,Interrupt ID20   Priority/Priority Byte Offset 20  "
group.long 0x10418++0x03
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID26   ,Interrupt ID26   Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID24   ,Interrupt ID24   Priority/Priority Byte Offset 24  "
group.long 0x1041C++0x03
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID30   ,Interrupt ID30   Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID28   ,Interrupt ID28   Priority/Priority Byte Offset 28  "
textline "                                 "
rgroup.long 0x10C00++0x03
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (SGI)" "Level,Edge"
group.long 0x10C04++0x03
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1    ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                           "
width 18.
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
group.long 0x10D00++0x03
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
bitfld.long 0x00 30. "  GMB30 ,Group Modifier Bit 30" "0,1"
bitfld.long 0x00 29. "  GMB29 ,Group Modifier Bit 29" "0,1"
textline "                           "
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
bitfld.long 0x00 27. "  GMB27 ,Group Modifier Bit 27" "0,1"
bitfld.long 0x00 26. "  GMB26 ,Group Modifier Bit 26" "0,1"
textline "                           "
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
bitfld.long 0x00 24. "  GMB24 ,Group Modifier Bit 24" "0,1"
bitfld.long 0x00 23. "  GMB23 ,Group Modifier Bit 23" "0,1"
textline "                           "
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
bitfld.long 0x00 21. "  GMB21 ,Group Modifier Bit 21" "0,1"
bitfld.long 0x00 20. "  GMB20 ,Group Modifier Bit 20" "0,1"
textline "                           "
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
bitfld.long 0x00 18. "  GMB18 ,Group Modifier Bit 18" "0,1"
bitfld.long 0x00 17. "  GMB17 ,Group Modifier Bit 17" "0,1"
textline "                           "
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
bitfld.long 0x00 15. "  GMB15 ,Group Modifier Bit 15" "0,1"
bitfld.long 0x00 14. "  GMB14 ,Group Modifier Bit 14" "0,1"
textline "                           "
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
bitfld.long 0x00 12. "  GMB12 ,Group Modifier Bit 12" "0,1"
bitfld.long 0x00 11. "  GMB11 ,Group Modifier Bit 11" "0,1"
textline "                           "
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
bitfld.long 0x00 9. "  GMB9  ,Group Modifier Bit 9" "0,1"
bitfld.long 0x00 8. "  GMB8  ,Group Modifier Bit 8" "0,1"
textline "                           "
bitfld.long 0x00 7. " GMB7  ,Group Modifier Bit 7" "0,1"
bitfld.long 0x00 6. "  GMB6  ,Group Modifier Bit 6" "0,1"
bitfld.long 0x00 5. "  GMB5  ,Group Modifier Bit 5" "0,1"
textline "                           "
bitfld.long 0x00 4. " GMB4  ,Group Modifier Bit 4" "0,1"
bitfld.long 0x00 3. "  GMB3  ,Group Modifier Bit 3" "0,1"
bitfld.long 0x00 2. "  GMB2  ,Group Modifier Bit 2" "0,1"
textline "                           "
bitfld.long 0x00 1. " GMB1  ,Group Modifier Bit 1" "0,1"
bitfld.long 0x00 0. "  GMB0  ,Group Modifier Bit 0" "0,1"
textline "                           "
else
hgroup.long 0x10D00++0x03
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
group.long 0x10E00++0x03
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 28.--29. "  NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 26.--27. "  NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 22.--23. "  NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 20.--21. "  NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 18.--19. " NS_ACCESS9  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 16.--17. "  NS_ACCESS8  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 14.--15. "  NS_ACCESS7  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 12.--13. " NS_ACCESS6  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 10.--11. "  NS_ACCESS5  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 8.--9. "  NS_ACCESS4  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 6.--7. " NS_ACCESS3  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 4.--5. "  NS_ACCESS2  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 2.--3. "  NS_ACCESS1  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 0.--1. " NS_ACCESS0  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
textline "                           "
else
hgroup.long 0x10E00++0x03
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
rgroup.long 0x1C000++0x03
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
bitfld.long 0x00 31. " CPU_AS     ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
bitfld.long 0x00 2. "  ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
bitfld.long 0x00 1. "     ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
textline "                           "
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
rgroup.long 0x1C080++0x03
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 31. " PPI31S     ,Actual status of the PPI31 input signal" "Low,High"
bitfld.long 0x00 30. "  PPI30S       ,Actual status of the PPI30 input signal" "Low,High"
bitfld.long 0x00 29. "  PPI29S        ,Actual status of the PPI29 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 28. " PPI28S     ,Actual status of the PPI28 input signal" "Low,High"
bitfld.long 0x00 27. "  PPI27S       ,Actual status of the PPI27 input signal" "Low,High"
bitfld.long 0x00 26. "  PPI26S        ,Actual status of the PPI26 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 25. " PPI25S     ,Actual status of the PPI25 input signal" "Low,High"
bitfld.long 0x00 24. "  PPI24S       ,Actual status of the PPI24 input signal" "Low,High"
bitfld.long 0x00 23. "  PPI23S        ,Actual status of the PPI23 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 22. " PPI22S     ,Actual status of the PPI22 input signal" "Low,High"
bitfld.long 0x00 21. "  PPI21S       ,Actual status of the PPI21 input signal" "Low,High"
bitfld.long 0x00 20. "  PPI20S        ,Actual status of the PPI20 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 19. " PPI19S     ,Actual status of the PPI19 input signal" "Low,High"
bitfld.long 0x00 18. "  PPI18S       ,Actual status of the PPI18 input signal" "Low,High"
bitfld.long 0x00 17. "  PPI17S        ,Actual status of the PPI17 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 16. " PPI16S     ,Actual status of the PPI16 input signal" "Low,High"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
sif COMP.AVAILABLE("GICC")
base COMP.BASE("GICC",-1.)
width 14.
tree "CPU Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 6. "          IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 4. " CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "               FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODE       ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 7. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 4. "          CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
textline "                       "
bitfld.long 0x00 3. " FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
endif
textline "                       "
group.long 0x04++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x0C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x10++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x20++0x03
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x24++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x2C++0x03
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
bitfld.long 0x00 4. " ASV      ,Attempted security violation" "Not detected,Detected"
bitfld.long 0x00 3. "  WROD    ,Write to an RO location" "Not detected,Detected"
bitfld.long 0x00 2. "  RWOD ,Read of a WO location" "Not detected,Detected"
textline "                       "
bitfld.long 0x00 1. " WRD      ,Write to a reserved location" "Not detected,Detected"
bitfld.long 0x00 0. "  RRD     ,Read of a reserved location" "Not detected,Detected"
group.long 0xD0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
group.long 0xD4++0x03
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
group.long 0xD8++0x03
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
group.long 0xDC++0x03
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
group.long 0xE0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
group.long 0xE4++0x03
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
group.long 0xE8++0x03
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
group.long 0xEC++0x03
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
rgroup.long 0xFC++0x03
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID   ,Product ID"
bitfld.long 0x00 16.--19. "          ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
bitfld.long 0x00 12.--15. "         REV  ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "            IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICH")
base COMP.BASE("GICH",-1.)
width 13.
tree "Virtual CPU Control Interface"
group.long 0x00++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "             VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "             VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "       NPIE     ,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      LRENPIE  ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "             UIE      ,Underflow Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " EN       ,Virtual CPU interface Enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GICH_VTR,Virtual Type Register"
bitfld.long 0x00 29.--31. " PRIBITS  ,Number of priority bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 26.--28. "              PREBITS  ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 23.--25. "             IDBITS   ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
textline "                      "
bitfld.long 0x00 22. " SEIS     ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "  A3V      ,Affinity 3 valid" "Invalid,Valid"
bitfld.long 0x00 0.--4. "       LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x08++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VPMR     ,Virtual priority mask"
bitfld.long 0x00 21.--23. "             VBPR0    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VBPR1    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "                    VEOIM    ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
textline "                      "
bitfld.long 0x00 4. " VCBPR    ,Virtual Common Binary Point Register" "ABPR,BPR"
bitfld.long 0x00 3. "           VFIQEN   ,Virtual FIQ enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      VACKCTL  ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
bitfld.long 0x00 1. "  VENG1    ,Virtual interrupt enable for group 1" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " VENG0    ,Virtual interrupt enable for group 0" "Disabled,Enabled"
rgroup.long 0x10++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D   ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 6. "   VGRP1E   ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. "  VGRP0D   ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 4. "         VGRP0E   ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
textline "                      "
bitfld.long 0x00 3. " NP       ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "   LRENP    ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. "  U        ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "         EOI      ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
rgroup.long 0x20++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,Status bit for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,Status bit for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,Status bit for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,Status bit for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,Status bit for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,Status bit for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,Status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,Status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,Status bit for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,Status bit for List register 0" "No interrupt,Interrupt"
textline "                      "
group.long 0xF0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF4++0x03
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
textline "                       "
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x110++0x03
line.long 0x00 "GICH_LR4,List Register 4"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x114++0x03
line.long 0x00 "GICH_LR5,List Register 5"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x118++0x03
line.long 0x00 "GICH_LR6,List Register 6"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x11C++0x03
line.long 0x00 "GICH_LR7,List Register 7"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x120++0x03
line.long 0x00 "GICH_LR8,List Register 8"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x124++0x03
line.long 0x00 "GICH_LR9,List Register 9"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x128++0x03
line.long 0x00 "GICH_LR10,List Register 10"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x12C++0x03
line.long 0x00 "GICH_LR11,List Register 11"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x130++0x03
line.long 0x00 "GICH_LR12,List Register 12"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x134++0x03
line.long 0x00 "GICH_LR13,List Register 13"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x138++0x03
line.long 0x00 "GICH_LR14,List Register 14"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICV")
base COMP.BASE("GICV",-1.)
width 14.
tree "Virtual CPU Interface"
group.long 0x00++0x03
line.long 0x00 "GICV_CTLR,VM Control Register"
bitfld.long 0x00 9. " EOIMODE    ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 4. "  CBPR       ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "       FIQEN ,FIQ Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
textline "                      "
bitfld.long 0x00 1. "  ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x04++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority mask level for the virtual CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x0C++0x03
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x10++0x03
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0x03
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x24++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
textline ""
group.long 0xD0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xDC++0x03
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
textline "                      "
rgroup.long 0xFC++0x03
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID     ,Product ID"
bitfld.long 0x00 16.--19. "    ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "  REV ,Revision number for the CPU interface" ",,,GICv3,?..."
hexmask.long.word 0x00 0.--11. 1. "  IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
tree.end
width 0x0b
endif
width 0x0B
tree.end
tree.end
else
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
;    Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL     ,Implementer code"
bitfld.long 0x0 20.--23.  "           VAR      ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "           ARCH     ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline "                 "
hexmask.long.word 0x0 4.--15. 0x1 " PART     ,Primary Part Number"
bitfld.long 0x0 0.--3. "         REV      ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
bitfld.long 0x00 20.--23. " ERG      ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "           DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. "  L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline "                 "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM   ,Number of regions"
bitfld.long 0x00 0. "           TYPE     ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline "                 "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2    ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. "           AFFL1    ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. "           AFFL0    ,Affitnity Level 0"
textline "                 "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SL         ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. "              OS         ,Outermost Shareability domain support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "   L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "  L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "  WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS         ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. "      CW         ,Coherent walk" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MB         ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "  DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "  CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " SI         ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      SVCI       ,SVC Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC   ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. "      PSR_M_I    ,PSR_M Instructions Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "  STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "  STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM    ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "  SE     ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      PM     ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline "                 "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "      TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR    ,Default high address for the TCM"
bitfld.long 0x00 1. "                  FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline "                 "
bitfld.long 0x00 0. " PP_BUS_ECC          ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU             ,Number of CPUs" "1,2"
bitfld.long 0x00 30. "                       LOCK_STEP       ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline "                 "
bitfld.long 0x00 29. " NO_ICACHE           ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. "                     NO_DCACHE       ,Indicate whether the CPU contains data cache" "Yes,No"
textline "                 "
bitfld.long 0x00 26.--27. " ATCM_ES             ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. "  BTCM_ES         ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline "                 "
bitfld.long 0x00 23. " NO_IE               ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. "                     NO_FPU          ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline "                 "
bitfld.long 0x00 20.--21. " MPU_REGIONS         ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. "              BREAK_POINTS    ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline "                 "
bitfld.long 0x00 14.--16. " WATCH_POINTS        ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "                       NO_A_TCM_INF    ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 12. " NO_B0_TCM_INF       ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. "                     NO_B1_TCM_INF   ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 10. " TCMBUSPARITY        ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. "                     NO_SLAVE        ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline "                 "
bitfld.long 0x00 7.--8. " ICACHE_ES           ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. "         DCACHE_ES       ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline "                 "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. "                     AXI_BUS_ECC     ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline "                 "
bitfld.long 0x00 2. " SL                  ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. "                     AHB_PP          ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline "                 "
bitfld.long 0x00 0. " MICRO_SCU           ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP        ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. "                    INTSYNCEN       ,Value of the INTSYNCEN pin" "Low,High"
textline "                 "
bitfld.long 0x00 2. " IRQADDRVSYNCEN      ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. "                    SLBTCMSB        ,Value of the SLBTCMSBm pin" "Low,High"
textline "                 "
bitfld.long 0x00 0. " PARITYLEVEL         ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI     ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. "    DIB2DI    ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. "    DIB1DI    ,Disable Case B1 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 28. " DIADI     ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. "    B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. "    B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 25. " ATCMPCEN  ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. "    AXISCEN   ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. "    AXISCUEN  ,AXI slave cache User mode access enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 22. " DILSM     ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. "    DEOLP     ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. "    DBHE      ,Disable BH extension" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " FRCDIS    ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. "    RSDIS     ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. "    BP        ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline "                 "
bitfld.long 0x00 14. " DBWR      ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. "    DLFO      ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. "    ERPEG     ,Enable random parity error generation" "Disable,Enable"
textline "                 "
bitfld.long 0x00 11. " DNCH      ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. "    FORA      ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT       ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline "                 "
bitfld.long 0x00 8. " FDSnS     ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV      ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. "   DILS      ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline "                 "
bitfld.long 0x00 3.--5. " CEC       ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline "                 "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. "    B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMECEN  ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE      ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. "    DR2B      ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. "    DF6DI     ,F6 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " DF2DI     ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. "    DDI       ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. "    DOODPFP   ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 16. " DOOFMACS  ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. "    IXC       ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. "  OFC       ,Floating-point overflow exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 11. " UFC       ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. "  IOC       ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. "  DZC       ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 8. " IDC       ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. "  BTCMECC   ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. "    ATCMECC   ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline "                 "
bitfld.long 0x00 1. " BTCMRMW   ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMRMW   ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS    ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. "        D32DIS    ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline "                 "
bitfld.long 0x0 26.--27. " CP13      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 22.--23. " CP11      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 18.--19. " CP9       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 14.--15. " CP7       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 10.--11. " CP5       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 6.--7. " CP3       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 2.--3. " CP1       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                      "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV    ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. "  AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. "            RW       ,Access Caused an Abort Type" "Read,Write"
textline "                 "
bitfld.long 0x00 4.--7. " DOMAIN   ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10.  "               STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. "            STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION  ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU      ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "  LOC       ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline "                     "
bitfld.long 0x00 21.--23. " CL8      ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "  CL7       ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 15.--17. " CL6      ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "  CL5       ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9.--11. " CL4      ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "  CL3       ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 3.--5. " CL2      ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "  CL1       ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "  WB     ,Write-Back" "Not supported,Supported"
textline "                     "
bitfld.long 0x00 29. " RA       ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "  WA     ,Write-Allocate" "Not supported,Supported"
textline "                     "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS  ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Associativity"
textline "                     "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "              IND    ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY      ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "             SIDE   ,Source of the error" "0,1,2,3"
textline "                     "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. "           TYPE   ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY      ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. "              SET    ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache   ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. "       Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "           IDCODE ,Identification code"
bitfld.long 0x00 11.--15. "           N  ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "           DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline "                     "
bitfld.long 0x00 4. " X   ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "     D      ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "  C  ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. "    P  ,Event counter reset" "No action,Reset"
textline "                     "
bitfld.long 0x00 0. " E   ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C   ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00  2. "  P2     ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00  1. "  P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00  0. "  P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00  2. " P2  ,Increment  PMN2" "No action,Increment"
eventfld.long 0x00  1. "    P1     ,Increment  PMN1" "No action,Increment"
eventfld.long 0x00  0. "    P0 ,Increment  PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00  0. " EN  ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL       ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 "               SPECREV    ,Variant number"
textline "                           "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH       ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 "               PARTNUM    ,Part Number"
textline "                           "
hexmask.long.byte 0x0 0.--3. 0x1 " REV        ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE   ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. "  L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " IMINLINE   ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3     ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        STATE2     ,Java Extension Interface Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " STATE1     ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        STATE0     ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM        ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "        SE         ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " PM         ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM     ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    TDM_MM     ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " TDM_CB     ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CDM_MM     ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SDM_CB     ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    CDM_CB     ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " CC_PLEA    ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CC_CPUA    ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "     L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "    WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "    DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "    CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "        BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " AI         ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        SWII       ,SWI Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE      ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS          ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC          ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA         ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline "                        "
bitfld.long 0x00 1. " LB           ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. "              LIB          ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI        ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "         SNDFE        ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " SIDFI        ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "         SIDFE        ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE      ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. "                      MAIN_CLASS   ,Main class"
tree.end
textline "                     "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP          ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. "                       BRP          ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline "                     "
bitfld.long 0x0 20.--23. " CTX_CMP      ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. "                      VERSION      ,Debug Architecture Version"
textline "                     "
bitfld.long 0x0 15. " DEVID        ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "                    NSUHD        ,Secure User halting debug-mode" "Low,High"
textline "                     "
bitfld.long 0x0 13. " PCSR         ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. "                    SE           ,Security Extensions implemented" "Low,High"
textline "                     "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT      ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. "                      REVISION     ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL       ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "                   TXFULL       ,DBGDTRTX Register full" "Empty,Full"
textline "                     "
bitfld.long 0x00 25. " PIPEADV      ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. "                INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline "                     "
bitfld.long 0x00 20.--21. " EXTDCCMODE   ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. "            ADADISCARD   ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. "         NS      ,Non-secure status bit" "Secure,Non-secure"
textline "                     "
bitfld.long 0x00 17. " SPNIDDIS     ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "                     SPIDDIS      ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "            MDBGEN  ,Monitor debug-mode enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 14. " HDBGEN       ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. "                ITREN        ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. "       UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " INTDIS       ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. "                     DBGACK       ,Force debug acknowledge" "Normal,Forced"
textline "                     "
bitfld.long 0x00 8. " UND_L        ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. "            ADABORT      ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "    SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline "                     "
bitfld.long 0x00 2.--5. " MOE          ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. "  RESTARTED    ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. "        HALTED  ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S     ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " IRQVCE_S     ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "                DAVCE_S      ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " PAVCE_S      ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "                SVCVCE_S     ,SVC vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 1. " UIVCE_S      ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "                RVCE         ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD          ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT          ,Write through disable" "No,Yes"
bitfld.long 0x00 1. "                     NIL          ,L1 instruction cache line-fills disable" "No,Yes"
textline "                     "
bitfld.long 0x00 0. " NDL          ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR          ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. "              CSPA         ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline "                     "
bitfld.long 0x00 2. " CSE          ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. "               RR           ,Restart request" "No effect,Restart"
textline "                     "
bitfld.long 0x00 0. " HR           ,Halt request" "No effect,Halt"
textline "                     "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR         ,Hold core warm reset" "Not held,Held"
textline "                     "
bitfld.long 0x00 1. " CWRR         ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. "    CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR           ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. "        R         ,Reset Status" "No reset,Reset"
textline "                     "
bitfld.long 0x00 1. " SPD          ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. "        PU        ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
endif
tree "ADC"
tree "MCU_ADC_ECC"
tree "MCU_ADC0_ECC"
base ad:0x40707000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "ADC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU               ,bu" "0,1,2,3"
textline "                                  "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM           ,Custom version" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "ADC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. " RD_SVBUS_DONE   ,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         RD_SVBUS_ADDRESS ,Read address"
textline "                                  "
bitfld.long 0x00 15. " RD_SVBUS        ,Write 1h = Trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "         ECC_VECTOR       ,Value written to select the corresponding ECC RAM for"
rgroup.long 0xC++0x3
line.long 0x00 "ADC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS        ,Indicates the number of RAMS serviced by the ECC aggregator"
rgroup.long 0x10++0x3
line.long 0x00 "ADC_WRAP_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU               ,bu" "0,1,2,3"
textline "                                  "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM           ,Custom version" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "ADC_CTRL,ECC Control Register"
bitfld.long 0x00 6. " ERROR_ONCE      ,Force Error only once" "0,1"
bitfld.long 0x00 5. "         FORCE_N_ROW      ,Force Error on any RAM read" "0,1"
textline "                                  "
bitfld.long 0x00 4. " FORCE_DED       ,Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "         FORCE_SEC        ,Force Single Bit Error" "0,1"
textline "                                  "
bitfld.long 0x00 2. " ENABLE_RMW      ,Enable rmw" "0,1"
bitfld.long 0x00 1. "         ECC_CHECK        ,Enable ECC check" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ECC_ENABLE      ,Enable ECC" "0,1"
group.long 0x18++0x3
line.long 0x00 "ADC_ERR_CTRL1,ECC Error Control1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW         ,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
group.long 0x1C++0x3
line.long 0x00 "ADC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT2        ,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x00 0.--15. 1. "      ECC_BIT1         ,Data bit that needs to be flipped when force_sec is set"
group.long 0x20++0x3
line.long 0x00 "ADC_ERR_STAT1,ECC Error Status1 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT1        ,Data bit that corresponds to the single-bit error"
bitfld.long 0x00 10. "      CLR_ECC_OTHER    ,Clear other Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 9. " CLR_ECC_DED     ,Clear Double Bit Error Status" "0,1"
bitfld.long 0x00 8. "         CLR_ECC_SEC      ,Clear Single Bit Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 2. " ECC_OTHER       ,Successive single-bit errors have occurred while a writeback is still pending, Level interrupt" "0,1"
bitfld.long 0x00 1. "         ECC_DED          ,Level Double Bit Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ECC_SEC         ,Level Single Bit Error Status" "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "ADC_ERR_STAT2,ECC Error Status1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW         ,Row address where the single or double-bit error has occurred"
group.long 0x3C++0x3
line.long 0x00 "ADC_SEC_EOI_REG,Register"
bitfld.long 0x00 0. " EOI_WR          ," "0,1"
group.long 0x40++0x3
line.long 0x00 "ADC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RAM1_PEND       ,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_PEND        ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "ADC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_SET ,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_SET  ,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x00 "ADC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_CLR ,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_CLR  ,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x13C++0x3
line.long 0x00 "ADC_DED_EOI_REG,Register"
bitfld.long 0x00 0. " EOI_WR          ," "0,1"
group.long 0x140++0x3
line.long 0x00 "ADC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RAM1_PEND       ,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_PEND        ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "ADC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_SET ,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_SET  ,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x00 "ADC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_CLR ,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_CLR  ,Interrupt Enable Clear Register for ram0_pend" "0,1"
width 0x0B
tree.end
tree "MCU_ADC1_ECC"
base ad:0x40708000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "ADC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU               ,bu" "0,1,2,3"
textline "                                  "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM           ,Custom version" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "ADC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. " RD_SVBUS_DONE   ,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         RD_SVBUS_ADDRESS ,Read address"
textline "                                  "
bitfld.long 0x00 15. " RD_SVBUS        ,Write 1h = Trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "         ECC_VECTOR       ,Value written to select the corresponding ECC RAM for"
rgroup.long 0xC++0x3
line.long 0x00 "ADC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS        ,Indicates the number of RAMS serviced by the ECC aggregator"
rgroup.long 0x10++0x3
line.long 0x00 "ADC_WRAP_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU               ,bu" "0,1,2,3"
textline "                                  "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM           ,Custom version" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "ADC_CTRL,ECC Control Register"
bitfld.long 0x00 6. " ERROR_ONCE      ,Force Error only once" "0,1"
bitfld.long 0x00 5. "         FORCE_N_ROW      ,Force Error on any RAM read" "0,1"
textline "                                  "
bitfld.long 0x00 4. " FORCE_DED       ,Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "         FORCE_SEC        ,Force Single Bit Error" "0,1"
textline "                                  "
bitfld.long 0x00 2. " ENABLE_RMW      ,Enable rmw" "0,1"
bitfld.long 0x00 1. "         ECC_CHECK        ,Enable ECC check" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ECC_ENABLE      ,Enable ECC" "0,1"
group.long 0x18++0x3
line.long 0x00 "ADC_ERR_CTRL1,ECC Error Control1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW         ,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
group.long 0x1C++0x3
line.long 0x00 "ADC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT2        ,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x00 0.--15. 1. "      ECC_BIT1         ,Data bit that needs to be flipped when force_sec is set"
group.long 0x20++0x3
line.long 0x00 "ADC_ERR_STAT1,ECC Error Status1 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT1        ,Data bit that corresponds to the single-bit error"
bitfld.long 0x00 10. "      CLR_ECC_OTHER    ,Clear other Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 9. " CLR_ECC_DED     ,Clear Double Bit Error Status" "0,1"
bitfld.long 0x00 8. "         CLR_ECC_SEC      ,Clear Single Bit Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 2. " ECC_OTHER       ,Successive single-bit errors have occurred while a writeback is still pending, Level interrupt" "0,1"
bitfld.long 0x00 1. "         ECC_DED          ,Level Double Bit Error Status" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ECC_SEC         ,Level Single Bit Error Status" "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "ADC_ERR_STAT2,ECC Error Status1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW         ,Row address where the single or double-bit error has occurred"
group.long 0x3C++0x3
line.long 0x00 "ADC_SEC_EOI_REG,Register"
bitfld.long 0x00 0. " EOI_WR          ," "0,1"
group.long 0x40++0x3
line.long 0x00 "ADC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RAM1_PEND       ,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_PEND        ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "ADC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_SET ,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_SET  ,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0xC0++0x3
line.long 0x00 "ADC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_CLR ,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_CLR  ,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x13C++0x3
line.long 0x00 "ADC_DED_EOI_REG,Register"
bitfld.long 0x00 0. " EOI_WR          ," "0,1"
group.long 0x140++0x3
line.long 0x00 "ADC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RAM1_PEND       ,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_PEND        ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "ADC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_SET ,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_SET  ,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0x1C0++0x3
line.long 0x00 "ADC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. " RAM1_ENABLE_CLR ,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "         RAM0_ENABLE_CLR  ,Interrupt Enable Clear Register for ram0_pend" "0,1"
width 0x0B
tree.end
tree.end
tree "MCU_ADC_FIFO"
tree "MCU_ADC0_FIFO"
base ad:0x40208000
width 11.
rgroup.long 0x100++0x3
line.long 0x00 "ADC_DATA0,DMA sample FIFO"
bitfld.long 0x00 16.--19. " ADCCHANLID ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "  ADCDATA ,Sampled ADC converted data value stored in FIFO0."
rgroup.long 0x200++0x3
line.long 0x00 "ADC_DATA1,DMA sample FIFO"
bitfld.long 0x00 16.--19. " ADCCHANLID ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "  ADCDATA ,Sampled ADC converted data value stored in FIFO1."
width 0x0B
tree.end
tree "MCU_ADC1_FIFO"
base ad:0x40218000
width 11.
rgroup.long 0x100++0x3
line.long 0x00 "ADC_DATA0,DMA sample FIFO"
bitfld.long 0x00 16.--19. " ADCCHANLID ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "  ADCDATA ,Sampled ADC converted data value stored in FIFO0."
rgroup.long 0x200++0x3
line.long 0x00 "ADC_DATA1,DMA sample FIFO"
bitfld.long 0x00 16.--19. " ADCCHANLID ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "  ADCDATA ,Sampled ADC converted data value stored in FIFO1."
width 0x0B
tree.end
tree.end
tree "MCU_ADC"
tree "MCU_ADC0"
base ad:0x40200000
width 20.
group.long 0x0++0x3
line.long 0x00 "ADC_CONFIG_j,The user should write to this register the values of the input pins send to the AFE during step 1. the StepConfig WriteEnable bit should be set to 1 before a write can occur. Offset = 64h + (j * 8h); where j = 0h to Fh"
bitfld.long 0x00 27. " RANGECHECK      ,0h = Disable ADC_RANGE check 1h = compare ADC data with ADC_RANGE" "0,1"
bitfld.long 0x00 26. "     FIFOSEL       ,Sampled data will be stored in FIFO. 0h = FIFO0 1h = FIFO1" "0,1"
textline "                             "
bitfld.long 0x00 25. " DIFF_CNTRL      ,DifferentialADC_CONTROL. 0h = Single ended 1h = Differential input" "0,1"
bitfld.long 0x00 19.--22. "     SEL_INP_SWC   ,SEL_INP pins SW configuration. 0h = Channel 1 1h = Channel 2 2h = Channel 3 3h = Channel 4 4h = Channel 5 5h = Channel 6 6h = Channel 7 7h = Channel 8 8h = VREFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 15.--18. " SEL_INM_SWM     ,SEL_INM pins negative differential. 0h = Channel 1 1h = Channel 2 2h = Channel 3 3h = Channel 4 4h = Channel 5 5h = Channel 6 6h = Channel 7 7h = Channel 8 8h = VREFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--4. "    AVERAGING     ,Number of samplings to average. 0h = no average 1h = 2 samples average 2h = 4 samples average 3h = 8 samples average 4h = 16 samples average" "0,1,2,3,4,5,6,7"
textline "                             "
bitfld.long 0x00 0.--1. " MODE            ,0h = SW enabled, one-shot 1h = SW enabled, continuous 2h = HW synchronized, one-shot 3h = HW synchronized, continuous" "0,1,2,3"
group.long 0x0++0x3
line.long 0x00 "ADC_DELAY_j,Controls number of clock periods to sample and delay. Offset = 68h + (j ? 8h); where j = 0h to Fh"
hexmask.long.byte 0x00 24.--31. 1. " SAMPLEDELAY     ,This register will control the number of ADC clock cycles to hold SOC high. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x00 0.--17. 1. "    OPENDELAY     ,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion."
rgroup.long 0x0++0x3
line.long 0x00 "ADC_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility."
hexmask.long.word 0x00 16.--31. 1. " MODID           ,Module ID field"
bitfld.long 0x00 11.--15. "  REVRTL        ,RTLADC_REVISION. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM        ,Custom" "0,1,2,3"
textline "                             "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
wgroup.long 0x20++0x3
line.long 0x00 "ADC_EOI,The End of Interrupt () Register allows the CPU to acknowledge completion of an interrupt by writing to the for interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to."
bitfld.long 0x00 0. " LINENUMEOI      ,Software End Of Interrupt (EOI) control." "0,1"
group.long 0x24++0x3
line.long 0x00 "ADC_STATUS_RAW,The register allows the MCU_ADC0/1 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 8. " OUTOFRANGE      ,Status raw for interrupt." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC." "0,1"
group.long 0x28++0x3
line.long 0x00 "ADC_STATUS,The register allows the MCU_ADC0/1 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 8. " OUTOFRANGE      ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC." "0,1"
group.long 0x2C++0x3
line.long 0x00 "ADC_ENABLE_SET,The register allows the MCU_ADC0/1 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 8. " OUTOFRANGE      ,Interrupt enable." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Interrupt enable." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Interrupt enable." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Interrupt enable." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC" "0,1"
group.long 0x30++0x3
line.long 0x00 "ADC_ENABLE_CLR,The register allows the MCU_ADC0/1 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 8. " OUTOFRANGE      ,Interrupt disable." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Interrupt disable." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Interrupt disable." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Interrupt disable." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC" "0,1"
group.long 0x38++0x3
line.long 0x00 "ADC_DMAENABLE_SET,The register allows the enabling of DMA requests."
bitfld.long 0x00 1. " ENABLE1         ,Enable DMA request FIFO1" "0,1"
bitfld.long 0x00 0. "     ENABLE0       ,Enable DMA request FIFO0" "0,1"
group.long 0x3C++0x3
line.long 0x00 "ADC_DMAENABLE_CLR,The register allows the disabling of DMA requests."
bitfld.long 0x00 1. " ENABLE1         ,Clears the enable of the DMA reguest FIFO1. Disable DMA request FIFO1 Write 0h = No action Write 1h = Disable DMA line Read 0h = DMA line disabled Read 1h = DMA line enabled" "0,1"
bitfld.long 0x00 0. "     ENABLE0       ,Clears the enable of the DMA reguest FIFO0. Disable DMA request FIFO0 Write 0h = No action Write 1h = Disable DMA line Read 0h = DMA line disabled Read 1h = DMA line enabled" "0,1"
group.long 0x40++0x3
line.long 0x00 "ADC_CONTROL,Controls various parameters of the cotroller state."
bitfld.long 0x00 11. " HI_MID_SEL      ,Functional safety debug mode. 0h = Choose ADCREFP 1h = VMID reference input to ADC" "0,1"
bitfld.long 0x00 10. "     HI_MID_EN     ,Functional safety debug mode. Enable fixed reference to ADC for testing." "0,1"
textline "                             "
bitfld.long 0x00 9. " HW_PREEMPT      ,0h = SW steps are not preempted by HW events 1h = SW steps are preempted by HW events" "0,1"
bitfld.long 0x00 8. "     HW_MAP        ,0h = HW events are disabled 1h = HW events are enabled" "0,1"
textline "                             "
bitfld.long 0x00 4. " PD              ,ADC Power Down control. 0h = AFE is powered up 1h = AFE is powered down (default) At default, AFE is powered down; Software must write 0 to turn on the power and wait 4 us before starting a conversion" "0,1"
bitfld.long 0x00 3. "     BIAS_SEL      ,AFE select bias" "0,1"
textline "                             "
bitfld.long 0x00 1. " STEP_ID_EN      ,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO. 0h = Write zeros 1h = Store the channel id tag" "0,1"
bitfld.long 0x00 0. "     MODULE_ENABLE ,ADC module enable bit. After programming all the configuration and step enable registers, write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again, the ADC_SEQUENCER_STAT register show read back STEP_IDLE = 0h and FSM_BUSY = 0h. Enabling the controller will be held off until MEM_INIT_DONE = 1h." "0,1"
rgroup.long 0x44++0x3
line.long 0x00 "ADC_SEQUENCER_STAT,SW can read this register to find out the currently scheduled step id being converted on the ADC port. If you want to turn the controller off and then back on, the step_id bit should be checked and compared to IDLE before enabling the ADC module again. Also, before enabling the controller again, the user should wait for the FSM bit 5 to read idl."
bitfld.long 0x00 8. " GPADC_BUSY      ,Monitor the AFE internal calibration (busy bit)" "0,1"
bitfld.long 0x00 6. "     MEM_INIT_DONE ,ADC_STATUS of RAM initialization. 1h = RAM initialization to 0 after reset is done." "0,1"
textline "                             "
bitfld.long 0x00 5. " FSM_BUSY        ,ADC_STATUS of FSM. 0h = Idle 1h = Conversion in progress" "0,1"
bitfld.long 0x00 0.--4. "     STEP_IDLE     ,10h = Idle 0h - Fh = Corresponds to Step 1 - Step 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48++0x3
line.long 0x00 "ADC_RANGE,This feature requires the check interrupt bit to be enabled first. The user can decide which channel input is compared by programming the RangeCheck bit of the StepConfig Registers. It is up to software to sort through FIFO data to determine which channel data was out of . Software should only use LSB 10 bits for comparison and make sure bits 11,12 are 0."
hexmask.long.word 0x00 16.--27. 1. " HIRANGE         ,Sampled ADC data is compared to this value. If the sampled data is > HIRANGE, then interrupt is generated."
hexmask.long.word 0x00 0.--11. 1. "  LOWRANGE      ,Sampled ADC data is compared to this value. If the sampled data is < LOWRANGE, then interrupt is generated."
group.long 0x50++0x3
line.long 0x00 "ADC_MISC,Spare inputs of the AFE are driven by this register, spare outputs from the AFE are read."
bitfld.long 0x00 8.--11. " AFE_SPARE_OUT   ,Connected to AFE Spare Output pins." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    AFE_SPARE_IN  ,Connected to AFE Spare Input pins." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "ADC_STEPENABLE,Contains the enable bit for each step in the sequencer. When all steps are disabled, the FSM will stay in IDLE state. These bits can be enabled or disabled dynamically during operation. When a write to this register occurs during operational mode, the HW will make sure the new settings are updated after the END_OF_SEQUENCE event"
bitfld.long 0x00 16. " STEP16          ,Enable step 16" "0,1"
bitfld.long 0x00 15. "     STEP15        ,Enable step 15" "0,1"
textline "                             "
bitfld.long 0x00 14. " STEP14          ,Enable step 14" "0,1"
bitfld.long 0x00 13. "     STEP13        ,Enable step 13" "0,1"
textline "                             "
bitfld.long 0x00 12. " STEP12          ,Enable step 12" "0,1"
bitfld.long 0x00 11. "     STEP11        ,Enable step 11" "0,1"
textline "                             "
bitfld.long 0x00 10. " STEP10          ,Enable step 10" "0,1"
bitfld.long 0x00 9. "     STEP9         ,Enable step 9" "0,1"
textline "                             "
bitfld.long 0x00 8. " STEP8           ,Enable step 8" "0,1"
bitfld.long 0x00 7. "     STEP7         ,Enable step 7" "0,1"
textline "                             "
bitfld.long 0x00 6. " STEP6           ,Enable step 6" "0,1"
bitfld.long 0x00 5. "     STEP5         ,Enable step 5" "0,1"
textline "                             "
bitfld.long 0x00 4. " STEP4           ,Enable step 4" "0,1"
bitfld.long 0x00 3. "     STEP3         ,Enable step 3" "0,1"
textline "                             "
bitfld.long 0x00 2. " STEP2           ,Enable step 2" "0,1"
bitfld.long 0x00 1. "     STEP1         ,Enable step 1" "0,1"
rgroup.long 0xE4++0x3
line.long 0x00 "ADC_FIFO0WC,FIFO word count"
hexmask.long.word 0x00 0.--8. 1. " NUMWDS          ,Number of words currently in the FIFO0."
group.long 0xE8++0x3
line.long 0x00 "ADC_FIFO0THRESHOLD,FIFO threshold"
hexmask.long.byte 0x00 0.--7. 1. " THRESHOLD       ,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU."
group.long 0xEC++0x3
line.long 0x00 "ADC_FIFO0DMAREQ,dma request."
hexmask.long.byte 0x00 0.--7. 1. " DMAREQLEVEL     ,Number of words in FIFO0 before generating a DMA request."
rgroup.long 0xF0++0x3
line.long 0x00 "ADC_FIFO1WC,FIFO word count"
hexmask.long.word 0x00 0.--8. 1. " NUMWDS          ,Number of words currently in the FIFO1."
group.long 0xF4++0x3
line.long 0x00 "ADC_FIFO1THRESHOLD,FIFO threshold"
hexmask.long.byte 0x00 0.--7. 1. " THRESHOLD       ,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU."
group.long 0xF8++0x3
line.long 0x00 "ADC_FIFO1DMAREQ,dma request."
hexmask.long.byte 0x00 0.--7. 1. " DMAREQLEVEL     ,Number of words in FIFO1 before generating a DMA request."
rgroup.long 0x100++0x3
line.long 0x00 "ADC_FIFO0DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt."
bitfld.long 0x00 16.--19. " ADCCHANLID      ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "    ADCDATA       ,Sampled ADC converted data value stored in FIFO0."
rgroup.long 0x200++0x3
line.long 0x00 "ADC_FIFO1DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt."
bitfld.long 0x00 16.--19. " ADCCHANLID      ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "    ADCDATA       ,Sampled ADC converted data value stored in FIFO1."
width 0x0B
tree.end
tree "MCU_ADC1"
base ad:0x40210000
width 20.
group.long 0x0++0x3
line.long 0x00 "ADC_CONFIG_j,The user should write to this register the values of the input pins send to the AFE during step 1. the StepConfig WriteEnable bit should be set to 1 before a write can occur. Offset = 64h + (j * 8h); where j = 0h to Fh"
bitfld.long 0x00 27. " RANGECHECK      ,0h = Disable ADC_RANGE check 1h = compare ADC data with ADC_RANGE" "0,1"
bitfld.long 0x00 26. "     FIFOSEL       ,Sampled data will be stored in FIFO. 0h = FIFO0 1h = FIFO1" "0,1"
textline "                             "
bitfld.long 0x00 25. " DIFF_CNTRL      ,DifferentialADC_CONTROL. 0h = Single ended 1h = Differential input" "0,1"
bitfld.long 0x00 19.--22. "     SEL_INP_SWC   ,SEL_INP pins SW configuration. 0h = Channel 1 1h = Channel 2 2h = Channel 3 3h = Channel 4 4h = Channel 5 5h = Channel 6 6h = Channel 7 7h = Channel 8 8h = VREFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 15.--18. " SEL_INM_SWM     ,SEL_INM pins negative differential. 0h = Channel 1 1h = Channel 2 2h = Channel 3 3h = Channel 4 4h = Channel 5 5h = Channel 6 6h = Channel 7 7h = Channel 8 8h = VREFN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--4. "    AVERAGING     ,Number of samplings to average. 0h = no average 1h = 2 samples average 2h = 4 samples average 3h = 8 samples average 4h = 16 samples average" "0,1,2,3,4,5,6,7"
textline "                             "
bitfld.long 0x00 0.--1. " MODE            ,0h = SW enabled, one-shot 1h = SW enabled, continuous 2h = HW synchronized, one-shot 3h = HW synchronized, continuous" "0,1,2,3"
group.long 0x0++0x3
line.long 0x00 "ADC_DELAY_j,Controls number of clock periods to sample and delay. Offset = 68h + (j ? 8h); where j = 0h to Fh"
hexmask.long.byte 0x00 24.--31. 1. " SAMPLEDELAY     ,This register will control the number of ADC clock cycles to hold SOC high. Any value programmed here will be added to the minimum requirement of 1 clock cycle."
hexmask.long.tbyte 0x00 0.--17. 1. "    OPENDELAY     ,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion."
rgroup.long 0x0++0x3
line.long 0x00 "ADC_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility."
hexmask.long.word 0x00 16.--31. 1. " MODID           ,Module ID field"
bitfld.long 0x00 11.--15. "  REVRTL        ,RTLADC_REVISION. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM        ,Custom" "0,1,2,3"
textline "                             "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
wgroup.long 0x20++0x3
line.long 0x00 "ADC_EOI,The End of Interrupt () Register allows the CPU to acknowledge completion of an interrupt by writing to the for interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to."
bitfld.long 0x00 0. " LINENUMEOI      ,Software End Of Interrupt (EOI) control." "0,1"
group.long 0x24++0x3
line.long 0x00 "ADC_STATUS_RAW,The register allows the MCU_ADC0/1 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 8. " OUTOFRANGE      ,Status raw for interrupt." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Status raw for interrupt." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Status raw for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC." "0,1"
group.long 0x28++0x3
line.long 0x00 "ADC_STATUS,The register allows the MCU_ADC0/1 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 8. " OUTOFRANGE      ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Enabled status for interrupt." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Enabled status for interrupt." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC." "0,1"
group.long 0x2C++0x3
line.long 0x00 "ADC_ENABLE_SET,The register allows the MCU_ADC0/1 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 8. " OUTOFRANGE      ,Interrupt enable." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Interrupt enable." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Interrupt enable." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Interrupt enable." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Interrupt enable." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC" "0,1"
group.long 0x30++0x3
line.long 0x00 "ADC_ENABLE_CLR,The register allows the MCU_ADC0/1 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 8. " OUTOFRANGE      ,Interrupt disable." "0,1"
bitfld.long 0x00 7. "     FIFO1UNFL     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 6. " FIFO1OVFL       ,Interrupt disable." "0,1"
bitfld.long 0x00 5. "     FIFO1THRS     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 4. " FIFO0UNFL       ,Interrupt disable." "0,1"
bitfld.long 0x00 3. "     FIFO0OVFL     ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 2. " FIFO0THRS       ,Interrupt disable." "0,1"
bitfld.long 0x00 1. "     ENDOFEQUENCE  ,Interrupt disable." "0,1"
textline "                             "
bitfld.long 0x00 0. " AFE_EOC_MISSING ,EOC from the analog front end missing at expected time after SOC" "0,1"
group.long 0x38++0x3
line.long 0x00 "ADC_DMAENABLE_SET,The register allows the enabling of DMA requests."
bitfld.long 0x00 1. " ENABLE1         ,Enable DMA request FIFO1" "0,1"
bitfld.long 0x00 0. "     ENABLE0       ,Enable DMA request FIFO0" "0,1"
group.long 0x3C++0x3
line.long 0x00 "ADC_DMAENABLE_CLR,The register allows the disabling of DMA requests."
bitfld.long 0x00 1. " ENABLE1         ,Clears the enable of the DMA reguest FIFO1. Disable DMA request FIFO1 Write 0h = No action Write 1h = Disable DMA line Read 0h = DMA line disabled Read 1h = DMA line enabled" "0,1"
bitfld.long 0x00 0. "     ENABLE0       ,Clears the enable of the DMA reguest FIFO0. Disable DMA request FIFO0 Write 0h = No action Write 1h = Disable DMA line Read 0h = DMA line disabled Read 1h = DMA line enabled" "0,1"
group.long 0x40++0x3
line.long 0x00 "ADC_CONTROL,Controls various parameters of the cotroller state."
bitfld.long 0x00 11. " HI_MID_SEL      ,Functional safety debug mode. 0h = Choose ADCREFP 1h = VMID reference input to ADC" "0,1"
bitfld.long 0x00 10. "     HI_MID_EN     ,Functional safety debug mode. Enable fixed reference to ADC for testing." "0,1"
textline "                             "
bitfld.long 0x00 9. " HW_PREEMPT      ,0h = SW steps are not preempted by HW events 1h = SW steps are preempted by HW events" "0,1"
bitfld.long 0x00 8. "     HW_MAP        ,0h = HW events are disabled 1h = HW events are enabled" "0,1"
textline "                             "
bitfld.long 0x00 4. " PD              ,ADC Power Down control. 0h = AFE is powered up 1h = AFE is powered down (default) At default, AFE is powered down; Software must write 0 to turn on the power and wait 4 us before starting a conversion" "0,1"
bitfld.long 0x00 3. "     BIAS_SEL      ,AFE select bias" "0,1"
textline "                             "
bitfld.long 0x00 1. " STEP_ID_EN      ,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO. 0h = Write zeros 1h = Store the channel id tag" "0,1"
bitfld.long 0x00 0. "     MODULE_ENABLE ,ADC module enable bit. After programming all the configuration and step enable registers, write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again, the ADC_SEQUENCER_STAT register show read back STEP_IDLE = 0h and FSM_BUSY = 0h. Enabling the controller will be held off until MEM_INIT_DONE = 1h." "0,1"
rgroup.long 0x44++0x3
line.long 0x00 "ADC_SEQUENCER_STAT,SW can read this register to find out the currently scheduled step id being converted on the ADC port. If you want to turn the controller off and then back on, the step_id bit should be checked and compared to IDLE before enabling the ADC module again. Also, before enabling the controller again, the user should wait for the FSM bit 5 to read idl."
bitfld.long 0x00 8. " GPADC_BUSY      ,Monitor the AFE internal calibration (busy bit)" "0,1"
bitfld.long 0x00 6. "     MEM_INIT_DONE ,ADC_STATUS of RAM initialization. 1h = RAM initialization to 0 after reset is done." "0,1"
textline "                             "
bitfld.long 0x00 5. " FSM_BUSY        ,ADC_STATUS of FSM. 0h = Idle 1h = Conversion in progress" "0,1"
bitfld.long 0x00 0.--4. "     STEP_IDLE     ,10h = Idle 0h - Fh = Corresponds to Step 1 - Step 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48++0x3
line.long 0x00 "ADC_RANGE,This feature requires the check interrupt bit to be enabled first. The user can decide which channel input is compared by programming the RangeCheck bit of the StepConfig Registers. It is up to software to sort through FIFO data to determine which channel data was out of . Software should only use LSB 10 bits for comparison and make sure bits 11,12 are 0."
hexmask.long.word 0x00 16.--27. 1. " HIRANGE         ,Sampled ADC data is compared to this value. If the sampled data is > HIRANGE, then interrupt is generated."
hexmask.long.word 0x00 0.--11. 1. "  LOWRANGE      ,Sampled ADC data is compared to this value. If the sampled data is < LOWRANGE, then interrupt is generated."
group.long 0x50++0x3
line.long 0x00 "ADC_MISC,Spare inputs of the AFE are driven by this register, spare outputs from the AFE are read."
bitfld.long 0x00 8.--11. " AFE_SPARE_OUT   ,Connected to AFE Spare Output pins." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    AFE_SPARE_IN  ,Connected to AFE Spare Input pins." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "ADC_STEPENABLE,Contains the enable bit for each step in the sequencer. When all steps are disabled, the FSM will stay in IDLE state. These bits can be enabled or disabled dynamically during operation. When a write to this register occurs during operational mode, the HW will make sure the new settings are updated after the END_OF_SEQUENCE event"
bitfld.long 0x00 16. " STEP16          ,Enable step 16" "0,1"
bitfld.long 0x00 15. "     STEP15        ,Enable step 15" "0,1"
textline "                             "
bitfld.long 0x00 14. " STEP14          ,Enable step 14" "0,1"
bitfld.long 0x00 13. "     STEP13        ,Enable step 13" "0,1"
textline "                             "
bitfld.long 0x00 12. " STEP12          ,Enable step 12" "0,1"
bitfld.long 0x00 11. "     STEP11        ,Enable step 11" "0,1"
textline "                             "
bitfld.long 0x00 10. " STEP10          ,Enable step 10" "0,1"
bitfld.long 0x00 9. "     STEP9         ,Enable step 9" "0,1"
textline "                             "
bitfld.long 0x00 8. " STEP8           ,Enable step 8" "0,1"
bitfld.long 0x00 7. "     STEP7         ,Enable step 7" "0,1"
textline "                             "
bitfld.long 0x00 6. " STEP6           ,Enable step 6" "0,1"
bitfld.long 0x00 5. "     STEP5         ,Enable step 5" "0,1"
textline "                             "
bitfld.long 0x00 4. " STEP4           ,Enable step 4" "0,1"
bitfld.long 0x00 3. "     STEP3         ,Enable step 3" "0,1"
textline "                             "
bitfld.long 0x00 2. " STEP2           ,Enable step 2" "0,1"
bitfld.long 0x00 1. "     STEP1         ,Enable step 1" "0,1"
rgroup.long 0xE4++0x3
line.long 0x00 "ADC_FIFO0WC,FIFO word count"
hexmask.long.word 0x00 0.--8. 1. " NUMWDS          ,Number of words currently in the FIFO0."
group.long 0xE8++0x3
line.long 0x00 "ADC_FIFO0THRESHOLD,FIFO threshold"
hexmask.long.byte 0x00 0.--7. 1. " THRESHOLD       ,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU."
group.long 0xEC++0x3
line.long 0x00 "ADC_FIFO0DMAREQ,dma request."
hexmask.long.byte 0x00 0.--7. 1. " DMAREQLEVEL     ,Number of words in FIFO0 before generating a DMA request."
rgroup.long 0xF0++0x3
line.long 0x00 "ADC_FIFO1WC,FIFO word count"
hexmask.long.word 0x00 0.--8. 1. " NUMWDS          ,Number of words currently in the FIFO1."
group.long 0xF4++0x3
line.long 0x00 "ADC_FIFO1THRESHOLD,FIFO threshold"
hexmask.long.byte 0x00 0.--7. 1. " THRESHOLD       ,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU."
group.long 0xF8++0x3
line.long 0x00 "ADC_FIFO1DMAREQ,dma request."
hexmask.long.byte 0x00 0.--7. 1. " DMAREQLEVEL     ,Number of words in FIFO1 before generating a DMA request."
rgroup.long 0x100++0x3
line.long 0x00 "ADC_FIFO0DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt."
bitfld.long 0x00 16.--19. " ADCCHANLID      ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "    ADCDATA       ,Sampled ADC converted data value stored in FIFO0."
rgroup.long 0x200++0x3
line.long 0x00 "ADC_FIFO1DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt."
bitfld.long 0x00 16.--19. " ADCCHANLID      ,Optional ID tag of channel that captured the data. If tag option is disabled, these bits will be 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "    ADCDATA       ,Sampled ADC converted data value stored in FIFO1."
width 0x0B
tree.end
tree.end
tree.end
tree "CALSS"
tree "CAL"
base ad:0x6F00000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "CALSS_MOD_VER,The Module and Version Register identifies the module identifier and CAL_REVISION of the CAL module."
bitfld.long 0x00 30.--31. " MODULE_SCHEME                          ,CAL module Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         MODULE_BU                           ,CAL module Bussiness Unit" "0,1,2,3"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " MODULE_FUNCTION_ID                     ,CAL module ID."
bitfld.long 0x00 11.--15. "      RTL_VERSION                         ,RTL Version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " MAJOR_REVISION                         ,Major Revision." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM_REVISION                     ,Custom Revision." "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--5. " MINOR_REVISION                         ,Minor Revision." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "CALSS_COS,The Class of Service register is used to set the priority of master transactions based on the state of ~imflag."
bitfld.long 0x00 4.--6. " MFLAG_PRIORITY_HI                      ,CAL Master hi priority value when mflag is set." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         MFLAG_PRIORITY_LO                   ,CAL Master low priority value when mflag is not set." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CALSS_VID_MUX_CTRL,Updated CALSS_VID_MUX_CTRL Register The Video Mux Control manages the video mux"
bitfld.long 0x00 0.--2. " BYS_MUX_SEL                            ,CAL BYS in video mux control 4 - Selects LVDSRX output 1 7 - Selects LVDSRX output 4 Others - Reserved" "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CALSS_MODE,The CAL Mode register controls CAL operational mode."
bitfld.long 0x00 0. " BASELINE_MODE                          ,The BASELINE_MODE bit selects CAL operational mode. 0: Selects CAL full operational mode (YUV422 to YUV422BP conversion option enabled) 1: Selects CAL baseline mode (YUV422 to YUV422BP conversion option disabled)" "0,1"
group.long 0x80++0x3
line.long 0x00 "CALSS_TE_GRP_03_00,The Trace Event Group registers contains the Trace Event selection for a particular Trace Event group."
hexmask.long.byte 0x00 24.--31. 1. " EVENT_SEL_3                            ,This field describes which Trace Event will be sent to trace_events[3]. See trace events for more info."
hexmask.long.byte 0x00 16.--23. 1. "        EVENT_SEL_2                         ,This field describes which Trace Event will be sent to trace_events[2]. See trace events for more info."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " EVENT_SEL_1                            ,This field describes which Trace Event will be sent to trace_events[1]. See trace events for more info."
hexmask.long.byte 0x00 0.--7. 1. "        EVENT_SEL_0                         ,This field describes which Trace Event will be sent to trace_events[0]. See trace events for more info."
group.long 0x84++0x3
line.long 0x00 "CALSS_TE_GRP_07_04,The Trace Event Group registers contains the Trace Event selection for a particular Trace Event group."
hexmask.long.byte 0x00 24.--31. 1. " EVENT_SEL_7                            ,This field describes which Trace Event will be sent to trace_events[7]. See trace events for more info."
hexmask.long.byte 0x00 16.--23. 1. "        EVENT_SEL_6                         ,This field describes which Trace Event will be sent to trace_events[6]. See trace events for more info."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " EVENT_SEL_5                            ,This field describes which Trace Event will be sent to trace_events[5]. See trace events for more info."
hexmask.long.byte 0x00 0.--7. 1. "        EVENT_SEL_4                         ,This field describes which Trace Event will be sent to trace_events[4]. See trace events for more info."
rgroup.long 0x1000++0x3
line.long 0x00 "RAT_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " PID_SCHEME                             ,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         PID_BU                              ,Business Unit: 10 = Processors" "0,1,2,3"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PID_FUNC                               ,Module ID"
bitfld.long 0x00 11.--15. "      PID_RTL                             ,RTL REVISION. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " PID_MAJOR                              ,Major REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         PID_CUSTOM                          ,Custom" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--5. " PID_MINOR                              ,Minor REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x1004++0x3
line.long 0x00 "RAT_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " CONFIG_ADDR_WIDTH                      ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        CONFIG_ADDRS                        ,Number of addresses"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " CONFIG_REGIONS                         ,Number of regions"
group.long 0x1020++0x3
line.long 0x00 "RAT_CTRL_k,The Control for Region a Offset = 1020h + (k * 10h); where k = 0h to Fh"
bitfld.long 0x00 31. " CTRL_EN                                ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         CTRL_SIZE                           ,Size of the Region in Address Bits. 0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1024++0x3
line.long 0x00 "RAT_BASE_k,The Base Address for Region a. This is the source address for matching to a region. Offset = 1024h + (k * 10h); where k = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " BASE_BASE                              ,Base Address for the Region. It must be aligned to the programmed size."
group.long 0x1028++0x3
line.long 0x00 "RAT_TRANS_L_k,The Translated Lower Address Bits for Region a Offset = 1028h + (k * 10h); where k = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " TRANS_L_LOWER                          ,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
group.long 0x102C++0x3
line.long 0x00 "RAT_TRANS_U_k,The Translated Upper Address Bits for Region a Offset = 102Ch + (k * 10h); where k = 0h to Fh"
hexmask.long.word 0x00 0.--15. 1. " TRANS_U_UPPER                          ,Translated Upper Address Bits for the Region"
group.long 0x1804++0x3
line.long 0x00 "RAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DESTINATION_ID_DEST_ID                 ,The destination ID."
group.long 0x1820++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " EXCEPTION_LOGGING_CONTROL_DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         EXCEPTION_LOGGING_CONTROL_DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x1824++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " EXCEPTION_LOGGING_HEADER0_TYPE_F       ,Type. 4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        EXCEPTION_LOGGING_HEADER0_SRC_ID    ,Source ID."
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " EXCEPTION_LOGGING_HEADER0_DEST_ID      ,Destination ID."
rgroup.long 0x1828++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " EXCEPTION_LOGGING_HEADER1_GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        EXCEPTION_LOGGING_HEADER1_CODE      ,Code. 1 = Boundary crossing error."
rgroup.long 0x182C++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " EXCEPTION_LOGGING_DATA0_ADDR_L         ,Address lower 32 bits."
rgroup.long 0x1830++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " EXCEPTION_LOGGING_DATA1_ADDR_H         ,Address upper 12 bits."
rgroup.long 0x1834++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " EXCEPTION_LOGGING_DATA2_ROUTEID        ,Route ID."
bitfld.long 0x00 13. "      EXCEPTION_LOGGING_DATA2_WRITE       ,Write." "0,1"
textline "                                         "
bitfld.long 0x00 12. " EXCEPTION_LOGGING_DATA2_READ           ,Read." "0,1"
bitfld.long 0x00 11. "         EXCEPTION_LOGGING_DATA2_DEBUG       ,Debug." "0,1"
textline "                                         "
bitfld.long 0x00 10. " EXCEPTION_LOGGING_DATA2_CACHEABLE      ,Cacheable." "0,1"
bitfld.long 0x00 9. "         EXCEPTION_LOGGING_DATA2_PRIV        ,Priv." "0,1"
textline "                                         "
bitfld.long 0x00 8. " EXCEPTION_LOGGING_DATA2_SECURE         ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         EXCEPTION_LOGGING_DATA2_PRIV_ID     ,Priv ID."
rgroup.long 0x1838++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " EXCEPTION_LOGGING_DATA3_BYTECNT        ,Byte count."
group.long 0x1840++0x3
line.long 0x00 "RAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " EXCEPTION_PEND_SET_PEND_SET            ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x1844++0x3
hide.long 0x00 "RAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                         "
group.long 0x1848++0x3
line.long 0x00 "RAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " EXCEPTION_ENABLE_SET_ENABLE_SET        ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x184C++0x3
hide.long 0x00 "RAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                         "
group.long 0x1850++0x3
line.long 0x00 "RAT_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_REG_EOI_WR                         ,EOI Register"
rgroup.long 0x2000++0x3
line.long 0x00 "LVDSRX_REVISION,"
bitfld.long 0x00 30.--31. " SCHEME                                 ,Used to distinguish between old scheme and current. RD: 0 - LEGACY : Legacy ASP or WTBU scheme RD: 1 - H08 : Highlander 0.8 scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "         FUNC                                ,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number (and hence REVISION) should be assigned."
textline "                                         "
bitfld.long 0x00 11.--15. " R_RTL                                  ,RTL Version (R), maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: (1) PDS uploads occur which may have been due to spec changes (2) Bug fixes occur (3) Resets to '0' when X or Y changes. Design team has an internal 'Z' (customer invisible) number which increments on every drop that happens due to DV and RTL updates. Z resets to 0 when R increments." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        X_MAJOR                             ,Major Revision (X), maintained by IP specification owner. X changes ONLY when: (1) There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field (or Class/Type in old PID format) will remain the same. X does NOT change due to: (1) Bug fixes (2) Change in feature parameters." "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 6.--7. " CUSTOM                                 ,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. STANDARD Non custom (standard) REVISION RD: 0 - STANDARD : Non custom (standard) REVISION" "0,1,2,3"
bitfld.long 0x00 0.--5. "         Y_MINOR                             ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2010++0x3
line.long 0x00 "LVDSRX_SYSCONFIG,"
group.long 0x2014++0x3
line.long 0x00 "LVDSRX_CAMCFG,"
bitfld.long 0x00 19. " CAM4TEST                               ,Camera port #4 monitor" "0,1"
bitfld.long 0x00 18. "         CAM3TEST                            ,Camera port #3 monitor" "0,1"
textline "                                         "
bitfld.long 0x00 17. " CAM2TEST                               ,Camera port #2 monitor" "0,1"
bitfld.long 0x00 16. "         CAM1TEST                            ,Camera port #1 monitor" "0,1"
textline "                                         "
bitfld.long 0x00 3. " CAM4ENA                                ,Camera port #4 control" "0,1"
bitfld.long 0x00 2. "         CAM3ENA                             ,Camera port #3 control" "0,1"
textline "                                         "
bitfld.long 0x00 1. " CAM2ENA                                ,Camera port #2 control" "0,1"
bitfld.long 0x00 0. "         CAM1ENA                             ,Camera port #1 control" "0,1"
wgroup.long 0x201C++0x3
line.long 0x00 "LVDSRX_IRQ_EOI,"
bitfld.long 0x00 0.--2. " LINE_NUMBER                            ,Software End Of Interrupt (EOI) control. Write number of interrupt output to force re-evaluation of associated pending interrupts. Write n: EOI for interrupt output associated with EOI #n. WR:1 - EOI1 : EOI for interrupt output line #1 RD:0 - READ0 : Reads always 0 (no EOI memory) WR:2 - EOI2 : EOI for interrupt output line #2 WR:3 - EOI3 : EOI for interrupt output line #3 WR:4 - EOI4 : EOI for interrupt output line #4" "0,1,2,3,4,5,6,7"
group.long 0x2020++0x3
line.long 0x00 "LVDSRX_IRQSTATUS_RAW_0,"
bitfld.long 0x00 9. " CAM1_ERR7                              ,sync detected timeout reached RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 8. "         CAM1_ERR6                           ,CRC error RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 7. " CAM1_ERR5                              ,unexpected SOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 6. "         CAM1_ERR4                           ,unexpected SOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 5. " CAM1_ERR3                              ,unexpected EOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 4. "         CAM1_ERR2                           ,unexpected EOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 3. " CAM1_ERR1                              ,unexpected SOV RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 2. "         CAM1_ERR0                           ,EOX not received RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 1. " CAM1_EOF                               ,End of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 0. "         CAM1_SOF                            ,Start of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
hgroup.long 0x2024++0x3
hide.long 0x00 "LVDSRX_IRQSTATUS_0,"
in
textline "                                         "
group.long 0x2028++0x3
line.long 0x00 "LVDSRX_IRQENABLE_SET_0,"
bitfld.long 0x00 9. " EN_CAM1_ERR7                           ,sync detected timeout reached WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 8. "         EN_CAM1_ERR6                        ,CRC error WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 7. " EN_CAM1_ERR5                           ,unexpected SOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 6. "         EN_CAM1_ERR4                        ,unexpected SOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 5. " EN_CAM1_ERR3                           ,unexpected EOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 4. "         EN_CAM1_ERR2                        ,unexpected EOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 3. " EN_CAM1_ERR1                           ,unexpected SOV WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 2. "         EN_CAM1_ERR0                        ,EOX not received WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 1. " EN_CAM1_EOF                            ,End of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 0. "         EN_CAM1_SOF                         ,Start of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
hgroup.long 0x202C++0x3
hide.long 0x00 "LVDSRX_IRQENABLE_CLR_0,"
in
textline "                                         "
group.long 0x2030++0x3
line.long 0x00 "LVDSRX_IRQSTATUS_RAW_1,"
bitfld.long 0x00 9. " CAM2_ERR7                              ,sync detected timeout reached RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 8. "         CAM2_ERR6                           ,CRC error RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 7. " CAM2_ERR5                              ,unexpected SOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 6. "         CAM2_ERR4                           ,unexpected SOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 5. " CAM2_ERR3                              ,unexpected EOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 4. "         CAM2_ERR2                           ,unexpected EOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 3. " CAM2_ERR1                              ,unexpected SOV RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 2. "         CAM2_ERR0                           ,EOX not received RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 1. " CAM2_EOF                               ,End of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 0. "         CAM2_SOF                            ,Start of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
hgroup.long 0x2034++0x3
hide.long 0x00 "LVDSRX_IRQSTATUS_1,"
in
textline "                                         "
group.long 0x2038++0x3
line.long 0x00 "LVDSRX_IRQENABLE_SET_1,"
bitfld.long 0x00 9. " EN_CAM2_ERR7                           ,sync detected timeout reached WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 8. "         EN_CAM2_ERR6                        ,CRC error WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 7. " EN_CAM2_ERR5                           ,unexpected SOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 6. "         EN_CAM2_ERR4                        ,unexpected SOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 5. " EN_CAM2_ERR3                           ,unexpected EOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 4. "         EN_CAM2_ERR2                        ,unexpected EOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 3. " EN_CAM2_ERR1                           ,unexpected SOV WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 2. "         EN_CAM2_ERR0                        ,EOX not received WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 1. " EN_CAM2_EOF                            ,End of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 0. "         EN_CAM2_SOF                         ,Start of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
hgroup.long 0x203C++0x3
hide.long 0x00 "LVDSRX_IRQENABLE_CLR_1,"
in
textline "                                         "
group.long 0x2040++0x3
line.long 0x00 "LVDSRX_IRQSTATUS_RAW2_2,"
bitfld.long 0x00 9. " CAM3_ERR7                              ,sync detected timeout reached RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 8. "         CAM3_ERR6                           ,CRC error RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 7. " CAM3_ERR5                              ,unexpected SOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 6. "         CAM3_ERR4                           ,unexpected SOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 5. " CAM3_ERR3                              ,unexpected EOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 4. "         CAM3_ERR2                           ,unexpected EOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 3. " CAM3_ERR1                              ,unexpected SOV RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 2. "         CAM3_ERR0                           ,EOX not received RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 1. " CAM3_EOF                               ,End of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 0. "         CAM3_SOF                            ,Start of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
hgroup.long 0x2044++0x3
hide.long 0x00 "LVDSRX_IRQSTATUS_2,"
in
textline "                                         "
group.long 0x2048++0x3
line.long 0x00 "LVDSRX_IRQENABLE_SET_2,"
bitfld.long 0x00 9. " EN_CAM3_ERR7                           ,sync detected timeout reached WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 8. "         EN_CAM3_ERR6                        ,CRC error WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 7. " EN_CAM3_ERR5                           ,unexpected SOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 6. "         EN_CAM3_ERR4                        ,unexpected SOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 5. " EN_CAM3_ERR3                           ,unexpected EOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 4. "         EN_CAM3_ERR2                        ,unexpected EOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 3. " EN_CAM3_ERR1                           ,unexpected SOV WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 2. "         EN_CAM3_ERR0                        ,EOX not received WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 1. " EN_CAM3_EOF                            ,End of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 0. "         EN_CAM3_SOF                         ,Start of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
hgroup.long 0x204C++0x3
hide.long 0x00 "LVDSRX_IRQENABLE_CLR_2,"
in
textline "                                         "
group.long 0x2050++0x3
line.long 0x00 "LVDSRX_IRQSTATUS_RAW_3,"
bitfld.long 0x00 9. " CAM4_ERR7                              ,sync detected timeout reached RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 8. "         CAM4_ERR6                           ,CRC error RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 7. " CAM4_ERR5                              ,unexpected SOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 6. "         CAM4_ERR4                           ,unexpected SOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 5. " CAM4_ERR3                              ,unexpected EOF RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 4. "         CAM4_ERR2                           ,unexpected EOL RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 3. " CAM5_ERR1                              ,unexpected SOV RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 2. "         CAM4_ERR0                           ,EOX not received RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
textline "                                         "
bitfld.long 0x00 1. " CAM4_EOF                               ,End of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
bitfld.long 0x00 0. "         CAM4_SOF                            ,Start of frame timing RD: 0 - NOEVENT : No event pending RD: 1 - PENDING : Event pending" "0,1"
hgroup.long 0x2054++0x3
hide.long 0x00 "LVDSRX_IRQSTATUS_3,"
in
textline "                                         "
group.long 0x2058++0x3
line.long 0x00 "LVDSRX_IRQENABLE_SET_3,"
bitfld.long 0x00 9. " EN_CAM4_ERR7                           ,sync detected timeout reached WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 8. "         EN_CAM4_ERR6                        ,CRC error WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 7. " EN_CAM4_ERR5                           ,unexpected SOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 6. "         EN_CAM4_ERR4                        ,unexpected SOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 5. " EN_CAM4_ERR3                           ,unexpected EOF WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 4. "         EN_CAM4_ERR2                        ,unexpected EOL WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 3. " EN_CAM4_ERR1                           ,unexpected SOV WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 2. "         EN_CAM4_ERR0                        ,EOX not received WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
textline "                                         "
bitfld.long 0x00 1. " EN_CAM4_EOF                            ,End of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
bitfld.long 0x00 0. "         EN_CAM4_SOF                         ,Start of frame timing WR: 0 - NOACTION : No action RD: 0 - DISABLED : Interrupt disabled (masked) RD: 1 - ENABLED : Interrupt enabled WR: 1 - ENABLE : Enable interrupt" "0,1"
hgroup.long 0x205C++0x3
hide.long 0x00 "LVDSRX_IRQENABLE_CLR_3,"
in
textline "                                         "
group.long 0x2060++0x3
line.long 0x00 "LVDSRX_CAM1_CFG,"
bitfld.long 0x00 28.--30. " CC1_NUM_LANE4                          ,Number of lanes of PHY4 when NUM_PHY>3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         CC1_NUM_LANE3                       ,Number of lanes of PHY3 when NUM_PHY>2" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 20.--22. " CC1_NUM_LANE2                          ,Number of lanes of PHY2 when NUM_PHY>1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         CC1_NUM_LANE1                       ,Number of lanes of PHY1" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 15. " CC1_ALIGN                              ,MSB, LSB alignment for output pixel data 0: LSB align 1: MSB align" "0,1"
bitfld.long 0x00 14. "         CC1_DENDIAN                         ,Transmit format of none SYNC area 0: Little endian 1: big endian" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CC1_FILEN                              ,1: Transmitted data includes filier codes" "0,1"
bitfld.long 0x00 12. "         CC1_CRCEN                           ,1: enables checking of the checksum transmitted in the APTINA HiSPi data stream" "0,1"
textline "                                         "
bitfld.long 0x00 11. " CC1_SENDIAN                            ,Transmit format of SYNC area 0: Little endian 1: big endian" "0,1"
bitfld.long 0x00 8.--10. "         CC1_PIX_WIDTH                       ,Word width of recovered parallel data. 0: 8-BITS 1: 10-BITS 2: 12-BITS 3: 14-BITS 4: 16-BITS 5-7: RESERVED" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 7. " CC1_FRSTAT_INIT                        ,Specifies Initial frame state in mode2,mode4,mod5 and mode8.If the first comming sync code is knows as start of frame(SOF) when enable decoding, it is able to write 0. If sync code is unknown, should write 1.In other mode, should be coded 0." "0,1"
bitfld.long 0x00 4.--6. "         CC1_NUMPHY                          ,Number of PHYs 0 ~ 4 is available" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 0.--3. " CC1_OP_MODE                            ,Protocol selection 0: Serial LVDS mode 1 1: Serial LVDS mode 2 2: Serial LVDS mode 3 3: Serial LVDS mode 4 4: Serial LVDS mode 5 5: Serial LVDS mode 6 6: Serial LVDS mode 7 7: Serial LVDS mode 8 8: Serial LVDS mode 9-15: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2064++0x3
line.long 0x00 "LVDSRX_CAM1_FRMSIZE,"
hexmask.long.word 0x00 16.--31. 1. " C1FS_FRWIDTH                           ,Frame size in number of image lines"
hexmask.long.word 0x00 0.--15. 1. "      C1FS_LNWIDTH                        ,Image line width in number of data words"
group.long 0x2068++0x3
line.long 0x00 "LVDSRX_CAM1_MAXWIDTH,"
hexmask.long.word 0x00 0.--15. 1. " C1MW_MAXWIDTH                          ,The maximum line width expected in number of pixels."
group.long 0x206C++0x3
line.long 0x00 "LVDSRX_CAM1_SYNCSOF,"
hexmask.long.word 0x00 16.--31. 1. " C1SF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C1SF_SOFPTN                         ,Specifies SOF(Start Of Frame) sync pattern"
group.long 0x2070++0x3
line.long 0x00 "LVDSRX_CAM1_SYNCEOF,"
hexmask.long.word 0x00 16.--31. 1. " C1EF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C1EF_SOFPTN                         ,Specifies SOF(End Of Frame) sync pattern"
group.long 0x2074++0x3
line.long 0x00 "LVDSRX_CAM1_SYNCSOL,"
hexmask.long.word 0x00 16.--31. 1. " C1SL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C1SL_SOFPTN                         ,Specifies SOF(Start Of Line) sync pattern"
group.long 0x2078++0x3
line.long 0x00 "LVDSRX_CAM1_SYNCEOL,"
hexmask.long.word 0x00 16.--31. 1. " C1EL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C1EL_SOFPTN                         ,Specifies SOF(End Of Line) sync pattern"
group.long 0x207C++0x3
line.long 0x00 "LVDSRX_CAM1_SYNCSOV,"
hexmask.long.word 0x00 16.--31. 1. " C1SV_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C1SV_SOFPTN                         ,Specifies SOF(Start Of V-blanking) sync pattern"
group.long 0x2080++0x3
line.long 0x00 "LVDSRX_CAM2_CFG,"
bitfld.long 0x00 16.--18. " CC2_NUM_LANE                           ,Number of lanes of PHY2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "         CC2_ALIGN                           ,MSB, LSB alignment for output pixel data 0: LSB align 1: MSB align" "0,1"
textline "                                         "
bitfld.long 0x00 14. " CC2_DENDIAN                            ,Transmit format of none SYNC area 0: Little endian 1: big endian" "0,1"
bitfld.long 0x00 13. "         CC2_FILEN                           ,1: Transmitted data includes filier codes" "0,1"
textline "                                         "
bitfld.long 0x00 12. " CC2_CRCEN                              ,1: enables checking of the checksum transmitted in the APTINA HiSPi data stream" "0,1"
bitfld.long 0x00 11. "         CC2_SENDIAN                         ,Transmit format of SYNC area 0: Little endian 1: big endian" "0,1"
textline "                                         "
bitfld.long 0x00 8.--10. " CC2_PIX_WIDTH                          ,Word width of recovered parallel data. 0: 8-BITS 1: 10-BITS 2: 12-BITS 3: 14-BITS 4: 16-BITS 5-7: RESERVED" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         CC2_FRSTAT_INIT                     ,Specifies Initial frame state in mode2, mode4, mod5 and mode8. If the first comming sync code is knows as start of frame(SOF) when enable decoding, it is able to write 0. If sync code is unknown, should write 1. In other mode, should be coded 0." "0,1"
textline "                                         "
bitfld.long 0x00 4.--5. " CC2_NUMPHY                             ,Number of PHYs 0 ~ 1 is available" "0,1,2,3"
bitfld.long 0x00 0.--3. "         CC2_OP_MODE                         ,Protocol selection 0: Serial LVDS mode 1 1: Serial LVDS mode 2 2: Serial LVDS mode 3 3: Serial LVDS mode 4 4: Serial LVDS mode 5 5: Serial LVDS mode 6 6: Serial LVDS mode 7 7: Serial LVDS mode 8: Serial LVDS mode 9 9-15: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2084++0x3
line.long 0x00 "LVDSRX_CAM2_FRMSIZE,"
hexmask.long.word 0x00 16.--31. 1. " C2FS_FRWIDTH                           ,Frame size in number of image lines"
hexmask.long.word 0x00 0.--15. 1. "      C2FS_LNWIDTH                        ,Image line width in number of data words"
group.long 0x2088++0x3
line.long 0x00 "LVDSRX_CAM2_MAXWIDTH,"
hexmask.long.word 0x00 0.--15. 1. " C2MW_MAXWIDTH                          ,The maximum line width expected in number of pixels."
group.long 0x208C++0x3
line.long 0x00 "LVDSRX_CAM2_SYNCSOF,"
hexmask.long.word 0x00 16.--31. 1. " C2SF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C2SF_SOFPTN                         ,Specifies SOF(Start Of Frame) sync pattern"
group.long 0x2090++0x3
line.long 0x00 "LVDSRX_CAM2_SYNCEOF,"
hexmask.long.word 0x00 16.--31. 1. " C2EF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C2EF_SOFPTN                         ,Specifies SOF(End Of Frame) sync pattern"
group.long 0x2094++0x3
line.long 0x00 "LVDSRX_CAM2_SYNCSOL,"
hexmask.long.word 0x00 16.--31. 1. " C2SL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C2SL_SOFPTN                         ,Specifies SOF(Start Of Line) sync pattern"
group.long 0x2098++0x3
line.long 0x00 "LVDSRX_CAM2_SYNCEOL,"
hexmask.long.word 0x00 16.--31. 1. " C2EL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C2EL_SOFPTN                         ,Specifies SOF(End Of Line) sync pattern"
group.long 0x209C++0x3
line.long 0x00 "LVDSRX_CAM2_SYNCSOV,"
hexmask.long.word 0x00 16.--31. 1. " C2SV_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C2SV_SOFPTN                         ,Specifies SOF(Start Of V-blanking) sync pattern"
group.long 0x20A0++0x3
line.long 0x00 "LVDSRX_CAM3_CFG,"
bitfld.long 0x00 20.--22. " CC3_NUM_LANE2                          ,Number of lanes of PHY4 when NUM_PHY>1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         CC3_NUM_LANE1                       ,Number of lanes of PHY3" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 15. " CC3_ALIGN                              ,MSB, LSB alignment for output pixel data 0: LSB align 1: MSB align" "0,1"
bitfld.long 0x00 14. "         CC3_DENDIAN                         ,Transmit format of none SYNC area 0: Little endian 1: big endian" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CC3_FILEN                              ,1: Transmitted data includes filier codes" "0,1"
bitfld.long 0x00 12. "         CC3_CRCEN                           ,1: enables checking of the checksum transmitted in the APTINA HiSPi data stream" "0,1"
textline "                                         "
bitfld.long 0x00 11. " CC3_SENDIAN                            ,Transmit format of SYNC area 0: Little endian 1: big endian" "0,1"
bitfld.long 0x00 8.--10. "         CC3_PIX_WIDTH                       ,Word width of recovered parallel data. 0: 8-BITS 1: 10-BITS 2: 12-BITS 3: 14-BITS 4: 16-BITS 5-7: RESERVED" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 7. " CC3_FRSTAT_INIT                        ,Specifies Initial frame state in mode2, mode4, mod5 and mode8. If the first comming sync code is knows as start of frame(SOF) when enable decoding, it is able to write 0. If sync code is unknown, should write 1. In other mode, should be coded 0." "0,1"
bitfld.long 0x00 4.--5. "         CC3_NUMPHY                          ,Number of PHYs 0,1, 2 is available" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--3. " CC3_OP_MODE                            ,Protocol selection 0: Serial LVDS mode 1 1: Serial LVDS mode 2 2: Serial LVDS mode 3 3: Serial LVDS mode 4 4: Serial LVDS mode 5 5: Serial LVDS mode 6 6: Serial LVDS mode 7 7: Serial LVDS mode 8: Serial LVDS mode 9 9-15: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20A4++0x3
line.long 0x00 "LVDSRX_CAM3_FRMSIZE,"
hexmask.long.word 0x00 16.--31. 1. " C3FS_FRWIDTH                           ,Frame size in number of image lines"
hexmask.long.word 0x00 0.--15. 1. "      C3FS_LNWIDTH                        ,Image line width in number of data words"
group.long 0x20A8++0x3
line.long 0x00 "LVDSRX_CAM3_MAXWIDTH,"
hexmask.long.word 0x00 0.--15. 1. " C3MW_MAXWIDTH                          ,The maximum line width expected in number of pixels."
group.long 0x20AC++0x3
line.long 0x00 "LVDSRX_CAM3_SYNCSOF,"
hexmask.long.word 0x00 16.--31. 1. " C3SF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C3SF_SOFPTN                         ,Specifies SOF(Start Of Frame) sync pattern"
group.long 0x20B0++0x3
line.long 0x00 "LVDSRX_CAM3_SYNCEOF,"
hexmask.long.word 0x00 16.--31. 1. " C3EF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C3EF_SOFPTN                         ,Specifies SOF(End Of Frame) sync pattern"
group.long 0x20B4++0x3
line.long 0x00 "LVDSRX_CAM3_SYNCSOL,"
hexmask.long.word 0x00 16.--31. 1. " C3SL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C3SL_SOFPTN                         ,Specifies SOF(Start Of Line) sync pattern"
group.long 0x20B8++0x3
line.long 0x00 "LVDSRX_CAM3_SYNCEOL,"
hexmask.long.word 0x00 16.--31. 1. " C3EL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C3EL_SOFPTN                         ,Specifies SOF(End Of Line) sync pattern"
group.long 0x20BC++0x3
line.long 0x00 "LVDSRX_CAM3_SYNCSOV,"
hexmask.long.word 0x00 16.--31. 1. " C3SV_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C3SV_SOFPTN                         ,Specifies SOF(Start Of V-blanking) sync pattern"
group.long 0x20C0++0x3
line.long 0x00 "LVDSRX_CAM4_CFG,"
bitfld.long 0x00 16.--18. " CC4_NUM_LANE                           ,Number of lanes of PHY4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "         CC4_ALIGN                           ,MSB, LSB alignment for output pixel data 0: LSB align 1: MSB align" "0,1"
textline "                                         "
bitfld.long 0x00 14. " CC4_DENDIAN                            ,Transmit format of none SYNC area 0: Little endian 1: big endian" "0,1"
bitfld.long 0x00 13. "         CC4_FILEN                           ,1: Transmitted data includes filier codes" "0,1"
textline "                                         "
bitfld.long 0x00 12. " CC4_CRCEN                              ,1: enables checking of the checksum transmitted in the APTINA HiSPi data stream" "0,1"
bitfld.long 0x00 11. "         CC4_SENDIAN                         ,Transmit format of SYNC area 0: Little endian 1: big endian" "0,1"
textline "                                         "
bitfld.long 0x00 8.--10. " CC4_PIX_WIDTH                          ,Word width of recovered parallel data. 0: 8-BITS 1: 10-BITS 2: 12-BITS 3: 14-BITS 4: 16-BITS 5-7: RESERVED" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         CC4_FRSTAT_INIT                     ,Specifies Initial frame state in mode2, mode4, mod5 and mode8. If the first comming sync code is knows as start of frame(SOF) when enable decoding, it is able to write 0. If sync code is unknown, should write 1. In other mode, should be coded 0." "0,1"
textline "                                         "
bitfld.long 0x00 4. " CC4_NUMPHY                             ,Number of PHYs 0,1 is available" "0,1"
bitfld.long 0x00 0.--3. "         CC4_OP_MODE                         ,Protocol selection 0: Serial LVDS mode 1 1: Serial LVDS mode 2 2: Serial LVDS mode 3 3: Serial LVDS mode 4 4: Serial LVDS mode 5 5: Serial LVDS mode 6 6: Serial LVDS mode 7: Serial LVDS mode 8: Serial LVDS mode 9 9-13: Reserved 14: CMOS parallel IF (CCIR656 embeded sync) 15: CMOS parallel IF (extenal HSYNC/VSYNC). When in mode 14,15, the input parallel i/f signals go to CAM #4 output port." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20C4++0x3
line.long 0x00 "LVDSRX_CAM4_FRMSIZE,"
hexmask.long.word 0x00 16.--31. 1. " C4FS_FRWIDTH                           ,Frame size in number of image lines"
hexmask.long.word 0x00 0.--15. 1. "      C4FS_LNWIDTH                        ,Image line width in number of data words"
group.long 0x20C8++0x3
line.long 0x00 "LVDSRX_CAM4_MAXWIDTH,"
hexmask.long.word 0x00 0.--15. 1. " C4MW_MAXWIDTH                          ,The maximum line width expected in number of pixels."
group.long 0x20CC++0x3
line.long 0x00 "LVDSRX_CAM4_SYNCSOF,"
hexmask.long.word 0x00 16.--31. 1. " C4SF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C4SF_SOFPTN                         ,Specifies SOF(Start Of Frame) sync pattern"
group.long 0x20D0++0x3
line.long 0x00 "LVDSRX_CAM4_SYNCEOF,"
hexmask.long.word 0x00 16.--31. 1. " C4EF_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C4EF_SOFPTN                         ,Specifies SOF(End Of Frame) sync pattern"
group.long 0x20D4++0x3
line.long 0x00 "LVDSRX_CAM4_SYNCSOL,"
hexmask.long.word 0x00 16.--31. 1. " C4SL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C4SL_SOFPTN                         ,Specifies SOF(Start Of Line) sync pattern"
group.long 0x20D8++0x3
line.long 0x00 "LVDSRX_CAM4_SYNCEOL,"
hexmask.long.word 0x00 16.--31. 1. " C4EL_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C4EL_SOFPTN                         ,Specifies SOF(End Of Line) sync pattern"
group.long 0x20DC++0x3
line.long 0x00 "LVDSRX_CAM4_SYNCSOV,"
hexmask.long.word 0x00 16.--31. 1. " C4SV_BITMASK                           ,Specifies the mask bit to be compared. Example: set 0x3ff when doing pattern matching for low 10bit."
hexmask.long.word 0x00 0.--15. 1. "      C4SV_SOFPTN                         ,Specifies SOF(Start Of V-blanking) sync pattern"
group.long 0x20E0++0x3
line.long 0x00 "LVDSRX_WDRCFG,"
bitfld.long 0x00 8.--11. " PIX_WIDTH                              ,Word width after de-companded. 0: 12-BITS 1: 13-BITS 2: 14-BITS 3: 15-BITS 4: 16-BITS 5: 17-BITS 6: 18-BITS 7: 19-BITS 8: 20-BITS 9-15: RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4. "        WDRMODE                             ,WDR mode select 0: de-companding 1: bit interlaced format. Not allowed to code 1 to WDRENA3 and WDRENA4 at the same time." "0,1"
textline "                                         "
bitfld.long 0x00 3. " WDRENA4                                ,WDR mode enable for CAM port #4. 0: disable 1: enable WDR function. Not allowed to code 1 to WDRENA3 and WDRENA4 at the same time." "0,1"
bitfld.long 0x00 2. "         WDRENA3                             ,WDR mode enable for CAM port #3. 0: disable 1: enable WDR function. Not allowed to code 1 to WDRENA3 and WDRENA4 at the same time." "0,1"
textline "                                         "
bitfld.long 0x00 1. " WDRENA2                                ,WDR mode enable for CAM port #2. 0: disable 1: enable WDR function. Not allowed to code 1 to WDRENA1 and WDRENA2 at the same time." "0,1"
bitfld.long 0x00 0. "         WDRENA1                             ,WDR mode enable for CAM port #1. 0: disable 1: enable WDR function. Not allowed to code 1 to WDRENA1 and WDRENA2 at the same time." "0,1"
group.long 0x20E4++0x3
line.long 0x00 "LVDSRX_WDRGN,"
bitfld.long 0x00 16.--21. " WDRNPXY1                               ,Specifies the pixel level for area #1 knee point in X/Y axis. Level = WDRNPXY1 * 256." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "        WDRGN4                              ,Specifies the gain for area #4. Gain = 1/2WDRGN4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " WDRGN3                                 ,Specifies the gain for area #3. Gain = 1/2WDRGN3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        WDRGN2                              ,Specifies the gain for area #2. Gain = 1/2WDRGN2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20E8++0x3
line.long 0x00 "LVDSRX_WDRKP1,"
hexmask.long.word 0x00 16.--25. 1. " WDRNPY3                                ,Specifies the pixel level for area #3 knee point in Y axis. Level = WDRNPY3 * 256."
hexmask.long.word 0x00 0.--9. 1. "      WDRNPY2                             ,Specifies the pixel level for area #2 knee point in Y axis. Level = WDRNPY2 * 256."
group.long 0x20EC++0x3
line.long 0x00 "LVDSRX_WDRKP2,"
hexmask.long.word 0x00 16.--29. 1. " WDRNPX3                                ,Specifies the pixel level for area #3 knee point in X axis. Level = WDRNPX3."
hexmask.long.word 0x00 0.--13. 1. "      WDRNPX2                             ,Specifies the pixel level for area #2 knee point in X axis. Level = WDRNPX2."
rgroup.long 0x2100++0x3
line.long 0x00 "LVDSRX_TEST1,"
hexmask.long.byte 0x00 24.--31. 1. " T1_LANE4                               ,lane #4 byte data"
hexmask.long.byte 0x00 16.--23. 1. "        T1_LANE3                            ,lane #3 byte data"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " T1_LANE2                               ,lane #2 byte data"
hexmask.long.byte 0x00 0.--7. 1. "        T1_LANE1                            ,lane #1 byte data"
rgroup.long 0x2104++0x3
line.long 0x00 "LVDSRX_TEST2,"
hexmask.long.byte 0x00 24.--31. 1. " T2_LANE4                               ,lane #4 byte data"
hexmask.long.byte 0x00 16.--23. 1. "        T2_LANE3                            ,lane #3 byte data"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " T2_LANE2                               ,lane #2 byte data"
hexmask.long.byte 0x00 0.--7. 1. "        T2_LANE1                            ,lane #1 byte data"
rgroup.long 0x2108++0x3
line.long 0x00 "LVDSRX_TEST3,"
hexmask.long.byte 0x00 24.--31. 1. " T3_LANE4                               ,lane #4 byte data"
hexmask.long.byte 0x00 16.--23. 1. "        T3_LANE3                            ,lane #3 byte data"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " T3_LANE2                               ,lane #2 byte data"
hexmask.long.byte 0x00 0.--7. 1. "        T3_LANE1                            ,lane #1 byte data"
rgroup.long 0x210C++0x3
line.long 0x00 "LVDSRX_TEST4,"
hexmask.long.byte 0x00 24.--31. 1. " T4_LANE4                               ,lane #4 byte data"
hexmask.long.byte 0x00 16.--23. 1. "        T4_LANE3                            ,lane #3 byte data"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " T4_LANE2                               ,lane #2 byte data"
hexmask.long.byte 0x00 0.--7. 1. "        T4_LANE1                            ,lane #1 byte data"
rgroup.long 0x3000++0x3
line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 30.--31. " SCHEME                                 ,Used to distinguish between old scheme and current." "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "         FUNC                                ,Function indicates a software compatible module family. If there is no level of software compatibility a new Func number (and hence CAL_REVISION) should be assigned."
textline "                                         "
bitfld.long 0x00 11.--15. " R_RTL                                  ,RTL Version (R), maintained by IP design owner. RTL follows a numbering such as X.Y.R.Z which are explained in this table. R changes ONLY when: (1) PDS uploads occur which may have been due to spec changes (2) Bug fixes occur (3) Resets to '0' when X or Y changes. Design team has an internal 'Z' (customer invisible) number which increments on every drop that happens due to DV and RTL updates. Z resets to 0 when R increments." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        X_MAJOR                             ,Major Revision (X), maintained by IP specification owner. X changes ONLY when: (1) There is a major feature addition. An example would be adding Master Mode to Utopia Level2. The Func field (or Class/Type in old CAL_PID format) will remain the same. X does NOT change due to: (1) Bug fixes (2) Change in feature parameters." "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 6.--7. " CUSTOM                                 ,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers." "0,1,2,3"
bitfld.long 0x00 0.--5. "         Y_MINOR                             ,Minor Revision (Y), maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available. (2) When feature creeps from Is-Not list to Is list. But this may not be the case once it sees silicon in which case X will change. Y does NOT change due to: (1) Bug fixes (2) Typos or clarifications (3) major functional/feature change/addition/deletion. Instead these changes may be reflected via R, S, X as applicable. Spec owner maintains a customer-invisible number 'S' which changes due to: (1) Typos/clarifications (2) Bug documentation. Note that this bug is not due to a spec change but due to implementation. Nevertheless, the spec tracks the IP bugs. An RTL release (say for silicon PG1.1) that occurs due to bug fix should" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x3004++0x3
line.long 0x00 "CAL_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide."
bitfld.long 0x00 30.--31. " NPPI_CONTEXTS1                         ,Number of contexts for PPI interface #1" "0,1,2,3"
bitfld.long 0x00 28.--29. "         NPPI_CONTEXTS0                      ,Number of contexts for PPI interface #0" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 23.--27. " NCPORT                                 ,Number of supported CPORTs (including CPORT #0) minus 1. That number typically corresponds to the number of CPORTs that can provide data from OCPI. Example: NCPORT = 7 means that CAL implements 8 CPorts but one of them (CPORT0) is typically used for data read from memory and typically 7 CPorts (CPORT1 ~ CPORT7) can be used for data received on OCPI. Note: Equals NCPORT generic parameter minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19.--22. "        VFIFO                               ,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 13.--18. " WCTX                                   ,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--12. "        PCTX                                ,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--7. " RFIFO                                  ,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        WFIFO                               ,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3010++0x3
line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. " IDLEMODE                               ,IDLE protocol configuration" "0,1,2,3"
bitfld.long 0x00 0. "         SOFTRESET                           ,Software reset" "0,1"
group.long 0x301C++0x3
line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. " LINE_NUMBER                            ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x3020++0x3
line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j,Per-event raw interrupt status vector, line #0. Raw status is set even if event is not enabled. Offset = 3020h + (j * 10h); where j = 0h to 7h"
bitfld.long 0x00 31. " IRQ31                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 30. "         IRQ30                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 29. " IRQ29                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 28. "         IRQ28                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 27. " IRQ27                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 26. "         IRQ26                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 25. " IRQ25                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 24. "         IRQ24                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 23. " IRQ23                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 22. "         IRQ22                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 21. " IRQ21                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 20. "         IRQ20                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 19. " IRQ19                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 18. "         IRQ18                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 17. " IRQ17                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 16. "         IRQ16                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 15. " IRQ15                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 14. "         IRQ14                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 13. " IRQ13                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 12. "         IRQ12                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 11. " IRQ11                                  ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 10. "         IRQ10                               ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 9. " IRQ9                                   ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 8. "         IRQ8                                ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 7. " IRQ7                                   ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 6. "         IRQ6                                ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 5. " IRQ5                                   ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 4. "         IRQ4                                ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 3. " IRQ3                                   ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 2. "         IRQ2                                ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 1. " IRQ1                                   ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 0. "         IRQ0                                ,For details, check section CAL Interrupt Events." "0,1"
hgroup.long 0x3024++0x3
hide.long 0x00 "CAL_HL_IRQSTATUS_j,Per-event enabled interrupt status vector, line #0. Enabled status isn't set unless event is enabled. Offset = 3024h + (j * 10h); where j = 0h to 7h"
in
textline "                                         "
group.long 0x3028++0x3
line.long 0x00 "CAL_HL_IRQENABLE_SET_j,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Offset = 3028h + (j * 10h); where j = 0h to 7h"
bitfld.long 0x00 31. " IRQ31_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 30. "         IRQ30_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 29. " IRQ29_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 28. "         IRQ28_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 27. " IRQ27_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 26. "         IRQ26_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 25. " IRQ25_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 24. "         IRQ24_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 23. " IRQ23_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 22. "         IRQ22_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 21. " IRQ21_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 20. "         IRQ20_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 19. " IRQ19_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 18. "         IRQ18_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 17. " IRQ17_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 16. "         IRQ16_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 15. " IRQ15_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 14. "         IRQ14_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 13. " IRQ13_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 12. "         IRQ12_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 11. " IRQ11_EN                               ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 10. "         IRQ10_EN                            ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 9. " IRQ9_EN                                ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 8. "         IRQ8_EN                             ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 7. " IRQ7_EN                                ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 6. "         IRQ6_EN                             ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 5. " IRQ5_EN                                ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 4. "         IRQ4_EN                             ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 3. " IRQ3_EN                                ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 2. "         IRQ2_EN                             ,For details, check section CAL Interrupt Events." "0,1"
textline "                                         "
bitfld.long 0x00 1. " IRQ1_EN                                ,For details, check section CAL Interrupt Events." "0,1"
bitfld.long 0x00 0. "         IRQ0_EN                             ,For details, check section CAL Interrupt Events." "0,1"
hgroup.long 0x302C++0x3
hide.long 0x00 "CAL_HL_IRQENABLE_CLR_j,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Offset = 302Ch + (j * 10h); where j = 0h to 7h"
in
textline "                                         "
group.long 0x30C0++0x3
line.long 0x00 "CAL_PIX_PROC_j,Pixel processing control Offset = 30C0h + (j * 4h); where j = 0h to 3h"
bitfld.long 0x00 19.--23. " CPORT                                  ,CPort ID to process." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--18. "        PACK                                ,Control pixel packing" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 11.--15. " DPCME                                  ,DPCM encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "        DPCMD                               ,DPCM Decoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 1.--4. " EXTRACT                                ,Control pixel extraction from the byte stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        EN                                  ,Enable the pixel processing context" "0,1"
group.long 0x3100++0x3
line.long 0x00 "CAL_CTRL,Global control register"
hexmask.long.byte 0x00 24.--31. 1. " MFLAGH                                 ,Refer to section CAL Write DMA Real Time Traffic."
bitfld.long 0x00 22. "        RD_DMA_STALL                        ,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0. Shall be enabled to protect real time traffic against non real time, memory to memory dataflows through CAL." "0,1"
textline "                                         "
bitfld.long 0x00 21. " PWRSCPCLK                              ,Controls autogating of the PWRSCP clock" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "         MFLAGL                              ,Refer to section CAL Write DMA Real Time Traffic."
textline "                                         "
bitfld.long 0x00 7.--12. " LL_FORCE_STATE                         ,Forces the state of the CSI-3 low level protocol state machine. Intended to recover synchronization. Writing 0 into this register has no effect. Reads always return 0s bit 0: 0: the next OCPI transaction for this CPORT will only contain data 1: the next OCPI transaction for this CPORT will contain the CSI-3 packet header bit 1~5: CPort ID (1..31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5.--6. "        BURSTSIZE                           ,Maximum allowed burst size for the write DMA." "0,1,2,3"
textline "                                         "
bitfld.long 0x00 1.--4. " TAGCNT                                 ,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        POSTED_WRITES                       ," "0,1"
group.long 0x3104++0x3
line.long 0x00 "CAL_CTRL1,CAL global control register"
bitfld.long 0x00 4.--5. " INTERLEAVE23                           ,Controls stream interleaving Context #2 and #3" "0,1,2,3"
bitfld.long 0x00 2.--3. "         INTERLEAVE01                        ,Controls stream interleaving Context #0 and #1" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--1. " PPI_GROUPING                           ,Controls PPI grouping" "0,1,2,3"
group.long 0x3108++0x3
line.long 0x00 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event"
hexmask.long.word 0x00 16.--29. 1. " LINE                                   ,0: Event triggered when PIX_DAT_FS TAG is received by the line number event generator 1 ~ 2^14-1: Event triggered when the LINEth occurece of the PIX_DAT_LS TAG is received by the line number event generator."
bitfld.long 0x00 0.--4. "      CPORT                               ,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3130++0x3
line.long 0x00 "CAL_BYS_CTRL1,BYS port control register"
bitfld.long 0x00 31. " BC1_BYSINEN                            ,Enable/disable the BYS input port." "0,1"
bitfld.long 0x00 25.--30. "         BC1_YBLK                            ,Vertical blanking = YBLK lines. Valid range: 0 ... 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                         "
hexmask.long.byte 0x00 17.--24. 1. " BC1_XBLK                               ,Horizontal blanking = 8*XBLK cycles. Valid range = 0..2040 cycles."
hexmask.long.tbyte 0x00 0.--16. 1. "        BC1_PCLK                            ,BYSout port pixel clock = FCLK * PCLK / 2^16. Valid range: 0 .. 2^16. 0 disables the BYS output port."
group.long 0x3134++0x3
line.long 0x00 "CAL_BYS_CTRL2,BYS port control register"
bitfld.long 0x00 11. " BC2_FREERUNNING                        ,Controls PCLK generation when the BYSout state machine is in the IDLE state" "0,1"
bitfld.long 0x00 10. "         BC2_DUPLICATEDDATA                  ,Control if data sent to the BYS output port should also be send to the DPCM encoder" "0,1"
textline "                                         "
bitfld.long 0x00 5.--9. " BC2_CPORTOUT                           ,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        BC2_CPORTIN                         ,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3200++0x3
line.long 0x00 "CAL_WR_DMA_CTRL_j,Write DMA control register Offset = 3200h + (j * 10h); where j = 0h to 7h"
hexmask.long.word 0x00 18.--31. 1. " YSIZE                                  ,Maximum number of lines the WR DMA can write to memory. That feature is typically used to prevent writes outside of an allocated memory buffer (may, for example, happen when sync information is lost). 0: No limitation. All received lines are written to memory. 1 ~ 2^14-1: maximum number of lines to write to memory"
bitfld.long 0x00 15. "      YUV422BP                            ,Activates YUV422BP conversation (from YUV422). Requires two consecutive WrDMA channels where first channel is even and second is odd. Both channels shall be programmed identically except for DMA destination address. 0 - DISABLED - normal, no conversion. 1 - ENABLED - conversion enabled. Only supported, if CALSS_MODE[0] BASELINE_MODE register bit is '0'." "0,1"
textline "                                         "
bitfld.long 0x00 14. " STALL_RD_DMA                           ,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse. 0 - DISABLED, Don't stall the read DMA 1 - ENABLE, Stall the read DMA if the write DMA context is stalled." "0,1"
bitfld.long 0x00 9.--13. "         CPORT                               ,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--8. " DTAG                                   ,Store data tagged as DTAG 0x0 - ATT_HDR, Attribute packet headers. TAG=ATT_HDR_S, ATT_HDR_E 0x1 - ATT_DAT, Attribute data. TAG=ATT_DAT_S, ATT_DAT, ATT_DAT_E 0x2 - CAL_CTRL, Control packets. TAG=CTRL_HDR_S, CTRL_HDR_E 0x3 - PIX_HDR, Pixel packet headers. TAG=PIX_HDR_S, PIX_HDR_E 0x4 - PIX_DAT, Pixel data. TAG=PIX_DAT_FS, PIX_DAT_LS, PIX_DAT, PIX_DAT_LE, PIX_DAT_FE, FE_CODE 0x5 - D5, reserved 0x6 - D6, reserved 0x7 - D7, reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5. "         ICM_PSTART                          ,Enables monitoring of the ICM_PSTART[x] signal. 0 - Disabled. Ignore PSTART input. 1 - Enabled. Write the number of lines defined by CAL_WR_DMA_OFST_j.CIRC_MODE for each received PSTART pulse." "0,1"
textline "                                         "
bitfld.long 0x00 3.--4. " WR_PATTERN                             ,Data write pattern" "0,1,2,3"
bitfld.long 0x00 0.--2. "         MODE                                ,Mode 0x0 - DIS - Disable 0x1 - SHD - Ping/pong destination address on every frame 0x2 - CNT - Continously write data to memory 0x3 - CNT_INIT - Initialize start address for continous mode. The 1st frame will be written at this address and consecutive frames will be appended. 0x4 - CONST - Use CAL_WR_DMA_ADDR_j as base address. 0x5 - 0x7 - Reserved" "0,1,2,3,4,5,6,7"
group.long 0x3204++0x3
line.long 0x00 "CAL_WR_DMA_ADDR_j,Byte address of the top left corner of the buffer to write in system memory Offset = 3204h + (j * 10h); where j = 0h to 7h"
hexmask.long 0x00 4.--31. 1. " ADDR                                   ,Destination address, in words of 16 bytes. This value should be a multiple of 128 bytes for best performance."
group.long 0x3208++0x3
line.long 0x00 "CAL_WR_DMA_OFST_j,Offset between two consecutive line starts. Signed value. SW can directly write a signed 32-bit offset into that register. Valid range = -262144 .. 262143 Offset = 3208h + (j * 10h); where j = 0h to 7h"
hexmask.long.byte 0x00 24.--31. 1. " CIRC_SIZE                              ,Circular buffer size minus one. Unit defined by the CIRC_MODE register. Example: Circular buffer size = 16k lines when CIRC_SIZE=255 and CIRC_MODE=3"
bitfld.long 0x00 22.--23. "        CIRC_MODE                           ,Defines the granularity for circular buffer mode. Circular adressing mode shall be disabled (CIRC_MODE=0) when CAL_WR_DMA_CTRL_j.MODE bit isn't CONST. 0x0 - DISABLED, Circular addressing mode disabled 0x1 - ONE, 1 Line 0x2 - FOUR, 4 lines 0x3 - SIXTYFOUR, 64 lines" "0,1,2,3"
textline "                                         "
hexmask.long.word 0x00 4.--18. 1. " OFST                                   ,Offset in words of 16 bytes."
group.long 0x320C++0x3
line.long 0x00 "CAL_WR_DMA_XSIZE_j,Defines the size of a line written to memory. The minimum size to be written must be >= 16 bytes. Offset = 320Ch + (j * 10h); where j = 0h to 7h"
hexmask.long.word 0x00 19.--31. 1. " XSIZE                                  ,Words of 64-bits to write per line. Valid range = 0 or 1..n 0 : write the complete stream until the end is detected. n = stream size in words of 64 bits"
hexmask.long.word 0x00 3.--15. 1. "      XSKIP                               ,Words of 64 bits to skip from the line start. Valid range: 0...n-1 n = number or 64-bit words in the stream"
group.long 0x3300++0x3
line.long 0x00 "CAL_CSI2_PPI_CTRL_j,Controls the low level CSI-2 protocol interface (PPI) Offset = 3300h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 3. " FRAME                                  ,Set the modality in which IF_EN works." "0,1"
bitfld.long 0x00 2. "         ECC_EN                              ,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel IDs)." "0,1"
textline "                                         "
bitfld.long 0x00 0. " IF_EN                                  ,Enables the physical interface to the module." "0,1"
group.long 0x3304++0x3
line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_j,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the control bit for the power FSM. Offset = 3304h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 30. " RESET_CTRL                             ,Controls the reset of the complex IO" "0,1"
bitfld.long 0x00 29. "         RESET_DONE                          ,Internal reset monitoring of the power domain using the PPI byte clock from the complex IO" "0,1"
textline "                                         "
bitfld.long 0x00 27.--28. " PWR_CMD                                ,Command for power control of the complex IO" "0,1,2,3"
bitfld.long 0x00 25.--26. "         PWR_STATUS                          ,Status of the power control of the complex IO" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 24. " PWR_AUTO                               ,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "0,1"
bitfld.long 0x00 19. "         DATA4_POL                           ,+/- differential pin order of DATA lane 4." "0,1"
textline "                                         "
bitfld.long 0x00 16.--18. " DATA4_POSITION                         ,Position and order of the DATA lane 4. The values 6 and 7 are reserved." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "         DATA3_POL                           ,+/- differential pin order of DATA lane 3." "0,1"
textline "                                         "
bitfld.long 0x00 12.--14. " DATA3_POSITION                         ,Position and order of the DATA lane 3. The values 6 and 7 are reserved." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "         DATA2_POL                           ,+/- differential pin order of DATA lane 2." "0,1"
textline "                                         "
bitfld.long 0x00 8.--10. " DATA2_POSITION                         ,Position and order of the DATA lane 2. The values 6 and 7 are reserved." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         DATA1_POL                           ,+/- differential pin order of DATA lane 1." "0,1"
textline "                                         "
bitfld.long 0x00 4.--6. " DATA1_POSITION                         ,Position and order of the DATA lane 1. 0, 6 and 7 are reserved. The data lane 1 is always present." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         CLOCK_POL                           ,+/- differential pin order of CLOCK lane." "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " CLOCK_POSITION                         ,Position and order of the CLOCK lane. 0, 6 and 7 are reserved. The clock lane is always present." "0,1,2,3,4,5,6,7"
group.long 0x3308++0x3
line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_j,INTERRUPT STATUS REGISTER - All errors from complex IO #1 Offset = 3308h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 30. " IRQ_STS_ECC_NO_CORRECTION              ,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)." "0,1"
bitfld.long 0x00 28. "         IRQ_STS_SHORT_PACKET                ,Short packet (other than FS, FE, LS, LE) received." "0,1"
textline "                                         "
bitfld.long 0x00 27. " IRQ_STS_FIFO_OVR                       ,CSI-2 low level protocol interface FIFO overflow" "0,1"
bitfld.long 0x00 26. "         IRQ_STS_STATEALLULPMEXIT            ,At least one of the active lanes has exit the ULPM" "0,1"
textline "                                         "
bitfld.long 0x00 25. " IRQ_STS_STATEALLULPMENTER              ,All active lanes are entering in ULPM." "0,1"
bitfld.long 0x00 24. "         IRQ_STS_STATEULPM5                  ,Lane #5 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 23. " IRQ_STS_STATEULPM4                     ,Lane #4 in Ultra Low Power Mode" "0,1"
bitfld.long 0x00 22. "         IRQ_STS_STATEULPM3                  ,Lane #3 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 21. " IRQ_STS_STATEULPM2                     ,Lane #2 in Ultra Low Power Mode" "0,1"
bitfld.long 0x00 20. "         IRQ_STS_STATEULPM1                  ,Lane #1 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 19. " IRQ_STS_ERRCONTROL5                    ,Control error for lane #5" "0,1"
bitfld.long 0x00 18. "         IRQ_STS_ERRCONTROL4                 ,Control error for lane #4" "0,1"
textline "                                         "
bitfld.long 0x00 17. " IRQ_STS_ERRCONTROL3                    ,Control error for lane #3" "0,1"
bitfld.long 0x00 16. "         IRQ_STS_ERRCONTROL2                 ,Control error for lane #2" "0,1"
textline "                                         "
bitfld.long 0x00 15. " IRQ_STS_ERRCONTROL1                    ,Control error for lane #1" "0,1"
bitfld.long 0x00 14. "         IRQ_STS_ERRESC5                     ,Escape entry error for lane #5" "0,1"
textline "                                         "
bitfld.long 0x00 13. " IRQ_STS_ERRESC4                        ,Escape entry error for lane #4" "0,1"
bitfld.long 0x00 12. "         IRQ_STS_ERRESC3                     ,Escape entry error for lane #3" "0,1"
textline "                                         "
bitfld.long 0x00 11. " IRQ_STS_ERRESC2                        ,Escape entry error for lane #2" "0,1"
bitfld.long 0x00 10. "         IRQ_STS_ERRESC1                     ,Escape entry error for lane #1" "0,1"
textline "                                         "
bitfld.long 0x00 9. " IRQ_STS_ERRSOTSYNCHS5                  ,Start of transmission sync error for lane #5" "0,1"
bitfld.long 0x00 8. "         IRQ_STS_ERRSOTSYNCHS4               ,Start of transmission sync error for lane #4" "0,1"
textline "                                         "
bitfld.long 0x00 7. " IRQ_STS_ERRSOTSYNCHS3                  ,Start of transmission sync error for lane #3" "0,1"
bitfld.long 0x00 6. "         IRQ_STS_ERRSOTSYNCHS2               ,Start of transmission sync error for lane #2" "0,1"
textline "                                         "
bitfld.long 0x00 5. " IRQ_STS_ERRSOTSYNCHS1                  ,Start of transmission sync error for lane #1" "0,1"
bitfld.long 0x00 4. "         IRQ_STS_ERRSOTHS5                   ,Start of transmission error for lane #5" "0,1"
textline "                                         "
bitfld.long 0x00 3. " IRQ_STS_ERRSOTHS4                      ,Start of transmission error for lane #4" "0,1"
bitfld.long 0x00 2. "         IRQ_STS_ERRSOTHS3                   ,Start of transmission error for lane #3" "0,1"
textline "                                         "
bitfld.long 0x00 1. " IRQ_STS_ERRSOTHS2                      ,Start of transmission error for lane #2" "0,1"
bitfld.long 0x00 0. "         IRQ_STS_ERRSOTHS1                   ,Start of transmission error for lane #1" "0,1"
rgroup.long 0x330C++0x3
line.long 0x00 "CAL_CSI2_SHORT_PACKET_j,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F Offset = 330Ch + (j * 80h); where j = 0h to 1h"
hexmask.long.tbyte 0x00 0.--23. 1. " INFO_SHORT_PACKET                      ,Short Packet information: DATA ID + DATA FIELD"
group.long 0x3310++0x3
line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_j,INTERRUPT ENABLE REGISTER - All errors from complex IO #1 Offset = 3310h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 30. " IRQ_EN_ECC_NO_CORRECTION               ,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)." "0,1"
bitfld.long 0x00 28. "         IRQ_EN_SHORT_PACKET                 ,Short packet (other than FS, FE, LS, LE) received." "0,1"
textline "                                         "
bitfld.long 0x00 27. " IRQ_EN_FIFO_OVR                        ,CSI-2 low level protocol interface FIFO overflow" "0,1"
bitfld.long 0x00 26. "         IRQ_EN_STATEALLULPMEXIT             ,At least one of the active lanes has exit the ULPM" "0,1"
textline "                                         "
bitfld.long 0x00 25. " IRQ_EN_STATEALLULPMENTER               ,All active lanes are entering in ULPM." "0,1"
bitfld.long 0x00 24. "         IRQ_EN_STATEULPM5                   ,Lane #5 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 23. " IRQ_EN_STATEULPM4                      ,Lane #4 in Ultra Low Power Mode" "0,1"
bitfld.long 0x00 22. "         IRQ_EN_STATEULPM3                   ,Lane #3 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 21. " IRQ_EN_STATEULPM2                      ,Lane #2 in Ultra Low Power Mode" "0,1"
bitfld.long 0x00 20. "         IRQ_EN_STATEULPM1                   ,Lane #1 in Ultra Low Power Mode" "0,1"
textline "                                         "
bitfld.long 0x00 19. " IRQ_EN_ERRCONTROL5                     ,Control error for lane #5" "0,1"
bitfld.long 0x00 18. "         IRQ_EN_ERRCONTROL4                  ,Control error for lane #4" "0,1"
textline "                                         "
bitfld.long 0x00 17. " IRQ_EN_ERRCONTROL3                     ,Control error for lane #3" "0,1"
bitfld.long 0x00 16. "         IRQ_EN_ERRCONTROL2                  ,Control error for lane #2" "0,1"
textline "                                         "
bitfld.long 0x00 15. " IRQ_EN_ERRCONTROL1                     ,Control error for lane #1" "0,1"
bitfld.long 0x00 14. "         IRQ_EN_ERRESC5                      ,Escape entry error for lane #5" "0,1"
textline "                                         "
bitfld.long 0x00 13. " IRQ_EN_ERRESC4                         ,Escape entry error for lane #4" "0,1"
bitfld.long 0x00 12. "         IRQ_EN_ERRESC3                      ,Escape entry error for lane #3" "0,1"
textline "                                         "
bitfld.long 0x00 11. " IRQ_EN_ERRESC2                         ,Escape entry error for lane #2" "0,1"
bitfld.long 0x00 10. "         IRQ_EN_ERRESC1                      ,Escape entry error for lane #1" "0,1"
textline "                                         "
bitfld.long 0x00 9. " IRQ_EN_ERRSOTSYNCHS5                   ,Start of transmission sync error for lane #5" "0,1"
bitfld.long 0x00 8. "         IRQ_EN_ERRSOTSYNCHS4                ,Start of transmission sync error for lane #4" "0,1"
textline "                                         "
bitfld.long 0x00 7. " IRQ_EN_ERRSOTSYNCHS3                   ,Start of transmission sync error for lane #3" "0,1"
bitfld.long 0x00 6. "         IRQ_EN_ERRSOTSYNCHS2                ,Start of transmission sync error for lane #2" "0,1"
textline "                                         "
bitfld.long 0x00 5. " IRQ_EN_ERRSOTSYNCHS1                   ,Start of transmission sync error for lane #1" "0,1"
bitfld.long 0x00 4. "         IRQ_EN_ERRSOTHS5                    ,Start of transmission error for lane #5" "0,1"
textline "                                         "
bitfld.long 0x00 3. " IRQ_EN_ERRSOTHS4                       ,Start of transmission error for lane #4" "0,1"
bitfld.long 0x00 2. "         IRQ_EN_ERRSOTHS3                    ,Start of transmission error for lane #3" "0,1"
textline "                                         "
bitfld.long 0x00 1. " IRQ_EN_ERRSOTHS2                       ,Start of transmission error for lane #2" "0,1"
bitfld.long 0x00 0. "         IRQ_EN_ERRSOTHS1                    ,Start of transmission error for lane #1" "0,1"
group.long 0x3314++0x3
line.long 0x00 "CAL_CSI2_TIMING_j,TIMING REGISTER This register shall not be =modified when CAL_CSI2_PPI_CTRL.IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring. Offset = 3314h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 15. " FORCE_RX_MODE_IO1                      ,Control of ForceRxMode signal" "0,1"
bitfld.long 0x00 14. "         STOP_STATE_X16_IO1                  ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "0,1"
textline "                                         "
bitfld.long 0x00 13. " STOP_STATE_X4_IO1                      ,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "0,1"
hexmask.long.word 0x00 0.--12. 1. "         STOP_STATE_COUNTER_IO1              ,Stop State counter for monitoring. It indicates the number of L3 to monitor for Stop State before de-asserting ForceRxMode (Complex IO #1). The value is from 0 to 8191."
group.long 0x3318++0x3
line.long 0x00 "CAL_CSI2_VC_IRQENABLE_j,INTERRUPT ENABLE REGISTER - Virtual channels Offset = 3318h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 29. " VC_IE_ECC_CORRECTION0_IRQ_3            ,ECC has been used to correct the only 1-bit error" "0,1"
bitfld.long 0x00 28. "         VC_IE_CS_IRQ_3                      ,Check-Sum of the payload mismatch detection" "0,1"
textline "                                         "
bitfld.long 0x00 27. " VC_IE_LE_IRQ_3                         ,Line end sync code detection." "0,1"
bitfld.long 0x00 26. "         VC_IE_LS_IRQ_3                      ,Line start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 25. " VC_IE_FE_IRQ_3                         ,Frame end sync code detection." "0,1"
bitfld.long 0x00 24. "         VC_IE_FS_IRQ_3                      ,Frame start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 21. " VC_IE_ECC_CORRECTION0_IRQ_2            ,ECC has been used to correct the only 1-bit error" "0,1"
bitfld.long 0x00 20. "         VC_IE_CS_IRQ_2                      ,Check-Sum of the payload mismatch detection" "0,1"
textline "                                         "
bitfld.long 0x00 19. " VC_IE_LE_IRQ_2                         ,Line end sync code detection." "0,1"
bitfld.long 0x00 18. "         VC_IE_LS_IRQ_2                      ,Line start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 17. " VC_IE_FE_IRQ_2                         ,Frame end sync code detection." "0,1"
bitfld.long 0x00 16. "         VC_IE_FS_IRQ_2                      ,Frame start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 13. " VC_IE_ECC_CORRECTION0_IRQ_1            ,ECC has been used to correct the only 1-bit error" "0,1"
bitfld.long 0x00 12. "         VC_IE_CS_IRQ_1                      ,Check-Sum of the payload mismatch detection" "0,1"
textline "                                         "
bitfld.long 0x00 11. " VC_IE_LE_IRQ_1                         ,Line end sync code detection." "0,1"
bitfld.long 0x00 10. "         VC_IE_LS_IRQ_1                      ,Line start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 9. " VC_IE_FE_IRQ_1                         ,Frame end sync code detection." "0,1"
bitfld.long 0x00 8. "         VC_IE_FS_IRQ_1                      ,Frame start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 5. " VC_IE_ECC_CORRECTION0_IRQ_0            ,ECC has been used to correct the only 1-bit error" "0,1"
bitfld.long 0x00 4. "         VC_IE_CS_IRQ_0                      ,Check-Sum of the payload mismatch detection" "0,1"
textline "                                         "
bitfld.long 0x00 3. " VC_IE_LE_IRQ_0                         ,Line end sync code detection." "0,1"
bitfld.long 0x00 2. "         VC_IE_LS_IRQ_0                      ,Line start sync code detection." "0,1"
textline "                                         "
bitfld.long 0x00 1. " VC_IE_FE_IRQ_0                         ,Frame end sync code detection." "0,1"
bitfld.long 0x00 0. "         VC_IE_FS_IRQ_0                      ,Frame start sync code detection." "0,1"
group.long 0x3328++0x3
line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_j,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context. Offset = 3328h + (j * 80h); where j = 0h to 1h"
bitfld.long 0x00 29. " VC_IS_ECC_CORRECTION_IRQ_3             ,ECC has been used to do the correction of the only 1-bit error status" "0,1"
bitfld.long 0x00 28. "         VC_IS_CS_IRQ_3                      ,Check-Sum mismatch status." "0,1"
textline "                                         "
bitfld.long 0x00 27. " VC_IS_LE_IRQ_3                         ,Line end sync code detection status." "0,1"
bitfld.long 0x00 26. "         VC_IS_LS_IRQ_3                      ,Line start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 25. " VC_IS_FE_IRQ_3                         ,Frame end sync code detection status." "0,1"
bitfld.long 0x00 24. "         VC_IS_FS_IRQ_3                      ,Frame start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 21. " VC_IS_ECC_CORRECTION_IRQ_2             ,ECC has been used to do the correction of the only 1-bit error status" "0,1"
bitfld.long 0x00 20. "         VC_IS_CS_IRQ_2                      ,Check-Sum mismatch status." "0,1"
textline "                                         "
bitfld.long 0x00 19. " VC_IS_LE_IRQ_2                         ,Line end sync code detection status." "0,1"
bitfld.long 0x00 18. "         VC_IS_LS_IRQ_2                      ,Line start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 17. " VC_IS_FE_IRQ_2                         ,Frame end sync code detection status." "0,1"
bitfld.long 0x00 16. "         VC_IS_FS_IRQ_2                      ,Frame start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 13. " VC_IS_ECC_CORRECTION_IRQ_1             ,ECC has been used to do the correction of the only 1-bit error status" "0,1"
bitfld.long 0x00 12. "         VC_IS_CS_IRQ_1                      ,Check-Sum mismatch status." "0,1"
textline "                                         "
bitfld.long 0x00 11. " VC_IS_LE_IRQ_1                         ,Line end sync code detection status." "0,1"
bitfld.long 0x00 10. "         VC_IS_LS_IRQ_1                      ,Line start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 9. " VC_IS_FE_IRQ_1                         ,Frame end sync code detection status." "0,1"
bitfld.long 0x00 8. "         VC_IS_FS_IRQ_1                      ,Frame start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 5. " VC_IS_ECC_CORRECTION_IRQ_0             ,ECC has been used to do the correction of the only 1-bit error status" "0,1"
bitfld.long 0x00 4. "         VC_IS_CS_IRQ_0                      ,Check-Sum mismatch status." "0,1"
textline "                                         "
bitfld.long 0x00 3. " VC_IS_LE_IRQ_0                         ,Line end sync code detection status." "0,1"
bitfld.long 0x00 2. "         VC_IS_LS_IRQ_0                      ,Line start sync code detection status." "0,1"
textline "                                         "
bitfld.long 0x00 1. " VC_IS_FE_IRQ_0                         ,Frame end sync code detection status." "0,1"
bitfld.long 0x00 0. "         VC_IS_FS_IRQ_0                      ,Frame start sync code detection status." "0,1"
group.long 0x3330++0x3
line.long 0x00 "CAL_CSI2_CTX0_j,Context control Offset = 3330h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX0_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX0_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX0_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX0_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX0_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX0_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3334++0x3
line.long 0x00 "CAL_CSI2_CTX1_j,Context control Offset = 3334h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX1_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX1_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX1_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX1_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX1_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX1_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3338++0x3
line.long 0x00 "CAL_CSI2_CTX2_j,Context control Offset = 3338h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX2_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX2_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX2_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX2_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX2_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX2_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x333C++0x3
line.long 0x00 "CAL_CSI2_CTX3_j,Context control Offset = 333Ch + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX3_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX3_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX3_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX3_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX3_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX3_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3340++0x3
line.long 0x00 "CAL_CSI2_CTX4_j,Context control Offset = 3340h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX4_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX4_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX4_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX4_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX4_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX4_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3344++0x3
line.long 0x00 "CAL_CSI2_CTX5_j,Context control Offset = 3344h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX5_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX5_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX5_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX5_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX5_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX5_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3348++0x3
line.long 0x00 "CAL_CSI2_CTX6_j,Context control Offset = 3348h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX6_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX6_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX6_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX6_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX6_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX6_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x334C++0x3
line.long 0x00 "CAL_CSI2_CTX7_j,Context control Offset = 334Ch + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--29. 1. " CTX7_LINES                             ,Number of expected lines 0: Number of lines unknown. TAG generation FSM will insert a dummy line upon reception of a FE short packet. >0: Number of lines"
bitfld.long 0x00 14. "      CTX7_PACK_MODE                      ,Controls the data packing behavior" "0,1"
textline "                                         "
bitfld.long 0x00 13. " CTX7_ATT                               ,Selects which tags to use for the CAL internal pipeline" "0,1"
bitfld.long 0x00 8.--12. "         CTX7_CPORT                          ,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 6.--7. " CTX7_VC                                ,Virtual channel" "0,1,2,3"
bitfld.long 0x00 0.--5. "         CTX7_DT                             ,DT value received over CSI-2 to use for data. 0x00 : context is disabled (don't receive data) 0x01 : filter is disabled (accept any DT) 0x02 ~ 0x0F: reserved 0x10 ~ 0x3F: receive data with Data Type field = DT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x3350++0x3
line.long 0x00 "CAL_CSI2_STATUS0_j,Context status register Offset = 3350h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS0_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x3354++0x3
line.long 0x00 "CAL_CSI2_STATUS1_j,Context status register Offset = 3354h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS1_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x3358++0x3
line.long 0x00 "CAL_CSI2_STATUS2_j,Context status register Offset = 3358h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS2_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x335C++0x3
line.long 0x00 "CAL_CSI2_STATUS3_j,Context status register Offset = 335Ch + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS3_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x3360++0x3
line.long 0x00 "CAL_CSI2_STATUS4_j,Context status register Offset = 3360h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS4_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x3364++0x3
line.long 0x00 "CAL_CSI2_STATUS5_j,Context status register Offset = 3364h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS5_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x3368++0x3
line.long 0x00 "CAL_CSI2_STATUS6_j,Context status register Offset = 3368h + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS6_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
rgroup.long 0x336C++0x3
line.long 0x00 "CAL_CSI2_STATUS7_j,Context status register Offset = 336Ch + (j * 80h); where j = 0h to 1h"
hexmask.long.word 0x00 0.--15. 1. " STS7_FRAME                             ,Frame number. Matches the frame number sent by the camera when the camera transmits it. Otherwise, incremented by one on every FS short packet for this context. Reset when the context is enabled."
width 0x0B
tree.end
tree.end
tree "CAMERARX"
tree "CAMERARX0"
base ad:0x6F03800
width 16.
group.long 0x0++0x3
line.long 0x00 "CAMERARX_REG0,First Register"
bitfld.long 0x00 24. " HSCLOCKCONFIG              ,Disable clock missing detector" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "       THS_TERM                   ,Ths-Term timing parameter in multiples of DDR clock. Requirement from D-PHY spec = (Dn Voltage < 450 mV) - 35 ns+ 4UI. Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay. ~ (1-2) * DDRCLK + THS-TERM + ~ (1-15)ns Programmed Value = ceil (12.5 / DDR Clock period) - 1 Default value : 4 (for 400 MHz) Note: +/- 20% clock frequency tolerance"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " THS_SETTLE                 ,THS-Settle timing parameter in multiples of DDR clock frequency. Derived requirement from D-PHY spec = (90ns + 6UI) - (145ns + 10UI). Effective Ths-settle seen on line (starting to look for sync pattern) = synchronizer delay + timer delay + LPRX delay + combinational routing delay - pipeline delay in HS data path. ~ (1-2)* DDRCLK + THS-SETTLE + ~ (1-15)ns - 1*DDRCLK Programmed Value = ceil (90ns / DDR Clock Period) + 3 Default value : 39 (for 400 MHz) Note: (i) Minimum supported THS-SETTLE programmed value = 3 (ii) One clock delay in datapath from HSRX also needs to be compensated. Hence +3"
group.long 0x4++0x3
line.long 0x00 "CAMERARX_REG1,Second Register"
bitfld.long 0x00 30.--31. " RESET_DONE_STATUS1         ,Reset done read bits" "0,1,2,3"
bitfld.long 0x00 28.--29. "       RESET_DONE_STATUS          ,Reset done read bits. 28: RESETDONERXBYTECLK 29: RESETDONECTRLCLK" "0,1,2,3"
textline "                         "
bitfld.long 0x00 25. " CLOCK_MISS_DETECTOR_STATUS ,Clock missing detector status. Internal debug bit. 1: Error in clock missing detector. 0: Clock missing detector successful Note: CLKMISS detector is likely to malfunction, if tclk-trail spec (60ns) is not honoured." "0,1"
hexmask.long.byte 0x00 18.--24. 1. "       TCLK_TERM                  ,TCLK_TERM timing parameter in multiples of CTRLCLK. Requirement from D-PHY spec = (Dn Voltage < 450 mV) - 38 ns. Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay. ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15)ns Programmed Value = ceil (9.5 / CTRLCLK Period) - 1 Default value : 0 (for 96 MHz) Note: +/- 5% clock frequency tolerance"
textline "                         "
hexmask.long.byte 0x00 10.--17. 1. " DPHY_HS_SYNC_PATTERN       ,DPHY mode HS sync pattern in byte order (reverse of received order). D-PHY mode sync pattern. Default : '10111000'"
bitfld.long 0x00 8.--9. "      TCLK_DIV                   ,CTRLCLK_DIV_FACTOR. Divide factor for CTRLCLK for CLKMISS detector. Programmed value = ceil (15ns / CTRLCLK Period) - 1 Default value: 1 (for 96 MHz) CLKMISS detection time = (5*DIV+1)*(CTRLCLK period) < 60ns Note: Only the CTRLCLK frequencies that satisfies above relationship are allowed. Typically 96MHz should always be used at CTRLCLK." "0,1,2,3"
textline "                         "
hexmask.long.byte 0x00 0.--7. 1. " TCLK_SETTLE                ,TClk_Settle timing parameter in multiples of DDR Clock. Derived requirement from D-PHY spec = 100ns-300ns. Effective Ths-settle = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + Tclk-settle + ~ (1-15)ns Programmed Value = max (3, ceil (155ns/CTRLCLK Period)) Default value: 14 (for 96 MHz) Note: +/- 5% clock frequency tolerance"
group.long 0x8++0x3
line.long 0x00 "CAMERARX_REG2,Third register"
bitfld.long 0x00 30.--31. " TRIGGER_CMD_RXTRIGESC0     ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0 00: '01100010' 01: '01011101' 10: '00100001' 11: '10100000'" "0,1,2,3"
bitfld.long 0x00 28.--29. "       TRIGGER_CMD_RXTRIGESC1     ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1 00: '01011101' 01: '00100001' 10: '10100000' 11: '01100010'" "0,1,2,3"
textline "                         "
bitfld.long 0x00 26.--27. " TRIGGER_CMD_RXTRIGESC2     ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2 00: '00100001' 01: '01100010' 10: '01100010' 11: '01011101'" "0,1,2,3"
bitfld.long 0x00 24.--25. "       TRIGGER_CMD_RXTRIGESC3     ,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3 00: '10100000' 01: '01100010' 10: '01011101' 11: '00100001'" "0,1,2,3"
textline "                         "
hexmask.long.tbyte 0x00 0.--23. 1. " CCP2_SYNC_PATTERN          ,CCP2 mode sync pattern in byte order (reverse of received order)"
group.long 0xC++0x3
line.long 0x00 "CAMERARX_REG3,Fourth Register"
bitfld.long 0x00 31. " OVRD_HSRXEN                ,1: Override. 0: Default" "0,1"
bitfld.long 0x00 26.--30. "       ENHSRX                     ,HSRX Enable on LANE 5-0. 1: Enable. 0: Disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 25. " OVRD_HSRXTERM              ,Override with register bit. 1: Override. 0: Default" "0,1"
bitfld.long 0x00 20.--24. "       ENRXTERM                   ,HS-RX Termination enable on LANE 5-0. 1: Enable. 0: Default" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 19. " OVRD_LPRXEN_ULPRXEN        ,Override LP-RX and ULP-RX Enable. 1: Override. 0: Default" "0,1"
bitfld.long 0x00 14.--18. "       ENLPRX                     ,Enable for LP-RX on LANE 5-0 1: Enable 0: Disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 9.--13. " ENULPRX                    ,Enable for ULP-RX on LANE 5-0 1: Enable 0: Disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "      LDO_EN_OVRD                ,LDO Enable Override. 1: Override. 0: Default" "0,1"
textline "                         "
bitfld.long 0x00 7. " EN_LDO                     ,Enable LDO. 1: Enable. 0: Default" "0,1"
bitfld.long 0x00 6. "       BIAS_EN_OVRD               ,BIAS Enable Override. 1: Override with register bit. 0: Default" "0,1"
textline "                         "
bitfld.long 0x00 5. " ENABLE_BIAS                ,Enable BIAS. 1: Enable 0: Disable" "0,1"
bitfld.long 0x00 4. "       OVERRIDE_ENCCP             ,Override ENCCP to anatop. 1: Override with register bit 0: Default" "0,1"
textline "                         "
bitfld.long 0x00 3. " ENCCP_OVRRD_HSRX           ,ENCCP override to HSRX. 1: Enable 0: Disable" "0,1"
bitfld.long 0x00 1. "       RECALIB_HSRX_COMP_OFFSET   ,Recalibrate HS-RX comparator offset. Make this bit 0'1 to restart offset calibration. Usually offset calibration happens after PWRCMDON is received." "0,1"
textline "                         "
bitfld.long 0x00 0. " RECALIB_BIAS_CURRENT       ,Recalibrate biasgen. Make this bit 0'1 to restart bias calibration. Biasgen trim code in efuse is overridden with new calibrated value till this bit is '1'." "0,1"
group.long 0x10++0x3
line.long 0x00 "CAMERARX_REG4,Fifth Register"
bitfld.long 0x00 27.--31. " TRIM_BIASGEN_CURRENT       ,Trim biasgen current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22.--26. "      TRIM_TERM_LANE4            ,Trim termination resistor of lane 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 17.--21. " TRIM_TERM_LANE3            ,Trim termination resistor of lane 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--16. "      TRIM_TERM_LANE2            ,Trim termination resistor of lane 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 7.--11. " TRIM_TERM_LANE1            ,Trim termination resistor of lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2.--6. "      TRIM_TERM_LANE0            ,Trim termination resistor of lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 1. " BYPASS_EFUSE_TERM_RES      ,Bypass efuse bits for termination resistor. 1: Bypass EFUSE bits 0: Use EFUSE bits" "0,1"
bitfld.long 0x00 0. "       BYPASS_EFUSE_TERM_RESA_ALL ,Trim Termination resistor of all Lanes 1: overrides all restrim codes to same code from SCP register 4 bits [6:2], instead of individual control for individual bits. 0: Default" "0,1"
group.long 0x14++0x3
line.long 0x00 "CAMERARX_REG5,Sixth Register"
bitfld.long 0x00 26.--31. " TRIMOFFSET_LANE4HS_RX      ,Trim Offset of Lane4 HS-RX. Sign Magnitude Trim code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20.--25. "      TRIMOFFSET_LANE3HS_RX      ,Trim Offset of Lane3 HS-RX. Sign Magnitude Trim code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                         "
bitfld.long 0x00 14.--19. " TRIMOFFSET_LANE2_HS_RX     ,Trim Offset of Lane2 HS-RX. Sign Magnitude Trim code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "      TRIMOFFSET_LANE1_HS_RX     ,Trim Offset of Lane1 HS-RX. Sign Magnitude Trim code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                         "
bitfld.long 0x00 2.--7. " TRIMOFFSET_LANE0_HS_RX     ,Trim Offset of Lane0 HS-RX. Sign Magnitude Trim code." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "      BYPASS_CALIBRATED_OFFSET   ,1: Bypass the calibrated offset 0: Donot bypass" "0,1"
group.long 0x18++0x3
line.long 0x00 "CAMERARX_REG6,Seventh Register"
bitfld.long 0x00 30. " BGAP_EN_OVRD               ,BGAP enable override 0: Default 1: Override bandgap enable with following register bit" "0,1"
bitfld.long 0x00 29. "       BGAP_EN                    ,BANDGAP enable 0: Disable 1: enable" "0,1"
textline "                         "
bitfld.long 0x00 28. " BYP_HS_SYNC                ,To bypass HS Sync sequence 0: Normal 1: Bypass the HS Sync sequence" "0,1"
bitfld.long 0x00 27. "       BYP_LPSOT                  ,To bypass the LP SoT sequence in loopback mode 0: Normal 1: Bypass the LP SoT sequence" "0,1"
textline "                         "
bitfld.long 0x00 26. " LDO_RDY_EN_OVRD            ,LDO_RDY override 0: Default 1: Override LDO_RDY with the following register bit" "0,1"
bitfld.long 0x00 25. "       LDO_RDY_EN                 ,LDO_RDY makes internal LDO_RDY=1" "0,1"
textline "                         "
bitfld.long 0x00 24. " ENCALIB_EN                 ,ENCALIBA and ENCALIBB" "0,1"
bitfld.long 0x00 23. "       ENCALIB_EN_OVRD            ,ENCALIB override 0: Default 1: Override ENCALIBA and ENCALIBB with following register bit" "0,1"
textline "                         "
bitfld.long 0x00 22. " ENBIASCALIB_EN             ,ENBIASCALIB" "0,1"
bitfld.long 0x00 21. "       ENBIASCALIB_EN_OVRD        ,ENBIASCALIB override 0: Default 1: Override ENBIASCALIB with following register bit" "0,1"
textline "                         "
bitfld.long 0x00 20. " OVRD_AFE_INPUTS            ,Override LANEENABLE and POLARITY AFE inputs. 0:Normal. 1:Override" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "       AFE_LANE_SELECT            ,Selects clock lane and data lane mapping for AFE. 8 bit LANESEL for AFE"
textline "                         "
bitfld.long 0x00 11. " SEL_AFE_LANE_POLARITY      ,Select AFE lane polarity. Polarity for clock lane in AFE" "0,1"
bitfld.long 0x00 10. "       HSCOMPOUT_FAR              ,Select FAR lane HSCOMP output to HSCOMOOUT in AFE." "0,1"
textline "                         "
bitfld.long 0x00 9. " BYPASS_LDO_REF             ,0:Normal. 1:Bypass reference with VDD" "0,1"
bitfld.long 0x00 8. "       LDO_VLTG_DYA               ,Observe LDO voltage on DYA pad. 0:Normal. 1:Observe LDO voltage" "0,1"
textline "                         "
bitfld.long 0x00 7. " BIAS_CRNT_DXA              ,Observe bias current on DXA pad. 0:Normal. 1:Observe bias current" "0,1"
bitfld.long 0x00 5. "       OVRD_BIASGEN_CALIB         ,1:Override the EFUSE bits with register value. 0:Default" "0,1"
textline "                         "
bitfld.long 0x00 0.--4. " BIAS_CALIB_OVRD_VAL        ,Biasgen calibration code override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x3
line.long 0x00 "CAMERARX_REG7,Eigth register"
bitfld.long 0x00 31. " BG_TRIM_BITS_OVRD          ,Bandgap trim bits override 0: Normal (default mode) 1: Override Bandgap trim bits with SCP register bits" "0,1"
hexmask.long.byte 0x00 23.--30. 1. "       BG_TRIM_BITS               ,Bandgap trim bitsBandgap trim bits 00000000: Minimum bandgap voltage 11111111: Maximum bandgap voltage"
textline "                         "
bitfld.long 0x00 22. " BG_MAG_TRIM_BITS_OVRD      ,Bandgap magnitude trim bits override Bandgap magnitude trim bits override 0: Normal (default mode) 1: Override Bandgap trim bits with SCP register bits" "0,1"
hexmask.long.byte 0x00 14.--21. 1. "       BG_MAG_TRIM_BITS           ,Bandgap magnitude trim bits 00000000: Minimum bandgap voltage 11111111: Maximum bandgap voltage"
textline "                         "
bitfld.long 0x00 12.--13. " DUTY_CYC_HSRX              ,Duty cycle measurement in HSRX mode 00: Default 11: TBD" "0,1,2,3"
bitfld.long 0x00 9.--10. "       DOUBLER_DIV                ,2 bit for doubler programmable div: 00 - No division 01 - Div2 10 - Div3 11 - Div4 Default: 01 - Div2 selected since CTRLCLK is 96Mhz and doubler clk req is 48Mhz" "0,1,2,3"
textline "                         "
bitfld.long 0x00 8. " DOUBLER_EN_OVRD            ,Doubler enable override from bit 7" "0,1"
bitfld.long 0x00 7. "       DOUBLER_EN                 ,Doubler enable from this bit" "0,1"
textline "                         "
bitfld.long 0x00 6. " BIAS_COMP_OP_OVRD          ,BIASCALIB override 0: Default 1: Override BIASCALIB with the register bit[5]" "0,1"
bitfld.long 0x00 5. "       BIAS_COMP_OP               ,BIASCALIB bit from SCP reg" "0,1"
textline "                         "
bitfld.long 0x00 0.--4. " DIS_HS_TERM                ,Disable HS Termination 00000: Normal 11111: Disable Lane4,3,2,1,0 resp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x3
line.long 0x00 "CAMERARX_REG8,Ninth register"
bitfld.long 0x00 31. " CCP_OVRD                   ,CCP override 0: Normal 1: Override CCP outputs with the register bits" "0,1"
bitfld.long 0x00 30. "       CCP_LANEB                  ,CCPF Override CCPF from analog with this register bit" "0,1"
textline "                         "
bitfld.long 0x00 29. " CCP_LANEA                  ,CCPR Override CCPR from analog with this register bit" "0,1"
bitfld.long 0x00 28. "       HSRX_OVRD                  ,HSRX override 0: Normal 1: Override HSRX signals with the following register bits" "0,1"
textline "                         "
bitfld.long 0x00 24.--27. " HSRXDR                     ,CSI2R[3:0] Override CSI2R [3:0] for 4 lanes from analog with these register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "      HSRXDF                     ,CSI2F[3:0] Override CSI2F [3:0] for 4 lanes from analog with these register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                         "
bitfld.long 0x00 19. " HSCLK_COMPOUT              ,HSCOMPOUT" "0,1"
bitfld.long 0x00 18. "       BYP_DX_DY_OVRD             ,SELDX*/Y* override 0: Overrides the control to bypass of LPRX delay on DX/DY pads depending on testmode_sel_reg[6] and WPI_PMT[0] for DX pads and WPI_PMT[1] for DY pads. 1: Override the control to bypass the LPRX delay on DY/DX pads with the following register bits for all lanes" "0,1"
textline "                         "
bitfld.long 0x00 13.--17. " BYP_DY                     ,SELDY* controls bypass of LPRX delay on DY pads (5 lanes) Bit Mapping: 17 -> ADDON3 16 -> ADDON2 15 -> LaneB 14 -> LaneA 13 -> ADDON1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "      BYP_DX                     ,SELDX* controls bypass of LPRX delay on DX pads (5 lanes) Bit Mapping: 12 -> ADDON3 11 -> ADDON2 10 -> LaneB 9 -> LaneA 8 -> ADDON1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                         "
bitfld.long 0x00 7. " EN_LPBK_OVRD               ,ENLOOPBACK Override 0: Normal 1: Override ENLOOPBACK transmitter enable (in self or internal loopback mode) with register bit[6]" "0,1"
bitfld.long 0x00 6. "       EN_LPBK                    ,ENLOOPBACK transmitter enable (in self or internal loopback mode) from SCP register bit" "0,1"
textline "                         "
bitfld.long 0x00 5. " IE_OVRD                    ,IE override 0: Normal 1: Override IE (4 lanes) with the following register bit" "0,1"
bitfld.long 0x00 4. "       IE                         ,IE [3:0] Override IE [3:0] (4 lanes) with this single bit." "0,1"
textline "                         "
bitfld.long 0x00 3. " PIPU_OVRD                  ,PIPU override 0: Normal 1: Override PIPU (4 lanes) with the following register bit" "0,1"
bitfld.long 0x00 2. "       PIPU                       ,PIPU [3:0] Override PIPU [3:0] (4 lanes) with this single bit." "0,1"
textline "                         "
bitfld.long 0x00 1. " PIPD_OVRD                  ,PIPD override 0: Normal 1: Override PIPD (4 lanes) with the following register bit" "0,1"
bitfld.long 0x00 0. "       PIPD                       ,PIPD [3:0] Override PIPD [3:0] (4 lanes) with this single bit." "0,1"
group.long 0x24++0x3
line.long 0x00 "CAMERARX_REG9,Tenth register"
bitfld.long 0x00 31. " LPRX_OVRD                  ,LPRX override 0: Normal (defautlt mode) 1: Override the LPRXD* signals with SCP register bits" "0,1"
bitfld.long 0x00 30. "       LPRXDXA                    ,Bypass LPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 29. " LPRXDYA                    ,Bypass LPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 28. "       LPRXDXB                    ,Bypass LPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 27. " LPRXDYB                    ,Bypass LPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 26. "       LPRXDX_TOP                 ,Bypass LPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 25. " LPRXDY_TOP                 ,Bypass LPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 24. "       LPRXDX_BOT                 ,Bypass LPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 23. " LPRXDY_BOT                 ,Bypass LPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 22. "       LPRXDX_FAR                 ,Bypass LPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 21. " LPRXDY_FAR                 ,Bypass LPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 20. "       ULPRX_OVRD                 ,ULPRX Override 0: Normal (default mode) 1: Override the ULPRXD* signals with SCP register bits" "0,1"
textline "                         "
bitfld.long 0x00 19. " ULPRXDXA                   ,Bypass ULPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 18. "       ULPRXDYA                   ,Bypass ULPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 17. " ULPRXDXB                   ,Bypass ULPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 16. "       ULPRXDYB                   ,Bypass ULPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 15. " ULPRXDX_TOP                ,Bypass ULPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 14. "       ULPRXDY_TOP                ,Bypass ULPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 13. " ULPRXDX_BOT                ,Bypass ULPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 12. "       ULPRXDY_BOT                ,Bypass ULPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 11. " ULPRXDX_FAR                ,Bypass ULPRXD* comparator output with this bit" "0,1"
bitfld.long 0x00 10. "       ULPRXDY_FAR                ,Bypass ULPRXD* comparator output with this bit" "0,1"
textline "                         "
bitfld.long 0x00 7. " HISPI_MODE_EN              ,This bit enables the PHY in HiSPi mode. 0: HiSPi mode disabled (Default) 1: HiSPI mode enabled" "0,1"
bitfld.long 0x00 6. "       ENCCP_HSRX_ADDON1          ,ENCCP override to HSRX of ADDON1. 1: Enable 0: Disable" "0,1"
textline "                         "
bitfld.long 0x00 5. " ENCCP_HSRX_ADDON2          ,ENCCP override to HSRX of ADDON2. 1: Enable 0: Disable" "0,1"
bitfld.long 0x00 4. "       ENCCP_HSRX_ADDON_FAR       ,ENCCP override to HSRX of ADDON_FAR. 1: Enable 0: Disable" "0,1"
group.long 0x28++0x3
line.long 0x00 "CAMERARX_REG10,Eleventh register"
hexmask.long.word 0x00 0.--15. 1. " SPAREIN_ANATOP             ,Sparein Anatop. These bits are directly mapped to SPAREIN* pins of Analog (both LDO and Core voltage domains) and ADDONs for future use."
width 0x0B
tree.end
tree.end
tree "PSILSS_CFG_MMRS"
tree "PSILSS0_CFG_MMRS2"
base ad:0x285E0000
width 17.
rgroup.long 0x0++0x3
line.long 0x00 "PSIL_CFG_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV       ,TI internal data."
rgroup.long 0x4++0x3
line.long 0x00 "PSIL_CFG_CONFIG,The Config Register shows configured params."
hexmask.long.word 0x00 0.--15. 1. " ENDPOINTS ,Number of endpoints supported."
group.long 0x10++0x3
line.long 0x00 "PSIL_CFG_EVENT,The Event Register defines the event to produce for a link down event."
hexmask.long.word 0x00 0.--15. 1. " EVT       ,The event to produce."
rgroup.long 0x20++0x3
line.long 0x00 "PSIL_CFG_LINK,The Link Register shows the current status of the endpoint links."
hexmask.long 0x00 0.--31. 1. " STATUS    ,The status of the endpoint links."
hgroup.long 0x40++0x3
hide.long 0x00 "PSIL_CFG_DOWN,The Link Down Register shows which links are down for the endpoints."
in
textline "                          "
width 0x0B
tree.end
tree "PSILSS0_CFG_MMRS1"
base ad:0x31170000
width 17.
rgroup.long 0x0++0x3
line.long 0x00 "PSIL_CFG_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV       ,TI internal data."
rgroup.long 0x4++0x3
line.long 0x00 "PSIL_CFG_CONFIG,The Config Register shows configured params."
hexmask.long.word 0x00 0.--15. 1. " ENDPOINTS ,Number of endpoints supported."
group.long 0x10++0x3
line.long 0x00 "PSIL_CFG_EVENT,The Event Register defines the event to produce for a link down event."
hexmask.long.word 0x00 0.--15. 1. " EVT       ,The event to produce."
rgroup.long 0x20++0x3
line.long 0x00 "PSIL_CFG_LINK,The Link Register shows the current status of the endpoint links."
hexmask.long 0x00 0.--31. 1. " STATUS    ,The status of the endpoint links."
hgroup.long 0x40++0x3
hide.long 0x00 "PSIL_CFG_DOWN,The Link Down Register shows which links are down for the endpoints."
in
textline "                          "
width 0x0B
tree.end
tree.end
tree "PSI_L_CFG_PROXY"
tree "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY"
base ad:0x2A268000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV   ,TI internal data."
group.long 0x10++0x3
line.long 0x00 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy."
bitfld.long 0x00 31. " TOUT  ,Timeout occurred. When set indicates that a timeout has occurred on a configuration access. Once set, this bit is persistent until manually cleared." "0,1"
hexmask.long.word 0x00 0.--15. 1. "         TOUT_CNT  ,Timeout period. Specifies how many cycles to wait before closing up a configuration read or write transaction and asserting the TOUT bit"
group.long 0x100++0x3
line.long 0x00 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator, direction, and thread number for the configuration transaction."
bitfld.long 0x00 31. " BUSY  ,Indication that a configuration read or write is in progress 0h = No transaction is in progress 1h = Transaction is in progress" "0,1"
bitfld.long 0x00 30. "         DIR       ,Direction of configuration transaction 0h = Write transaction 1h = Read transaction" "0,1"
textline "                                  "
bitfld.long 0x00 29. " TO    ,Indication that a timeout occurred. This bit should be written to 0h on each new transaction. 0h = Transaction completed normally 1h = Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         THREAD_ID ,Thread ID to which configuration read or write is being sent. The thread ID mapping is shown in"
group.long 0x104++0x3
line.long 0x00 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction."
bitfld.long 0x00 28.--31. " BYTEN ,Byte enables to use for configuration read or write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "        ADDRESS   ,Word (32-bit) address within thread configuration space for transaction 0h = Peer thread ID register ( 1h = Peer credit register ( 2h = Enable register ( 40h = Capabilities register ( 400h = Static TR register"
group.long 0x108++0x3
line.long 0x00 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction."
hexmask.long 0x00 0.--31. 1. " WDATA ,Configuration data word to be written"
group.long 0x140++0x3
line.long 0x00 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction."
hexmask.long 0x00 0.--31. 1. " RDATA ,Configuration data word that was read"
width 0x0B
tree.end
tree "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY"
base ad:0x31F78000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV   ,TI internal data."
group.long 0x10++0x3
line.long 0x00 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy."
bitfld.long 0x00 31. " TOUT  ,Timeout occurred. When set indicates that a timeout has occurred on a configuration access. Once set, this bit is persistent until manually cleared." "0,1"
hexmask.long.word 0x00 0.--15. 1. "         TOUT_CNT  ,Timeout period. Specifies how many cycles to wait before closing up a configuration read or write transaction and asserting the TOUT bit"
group.long 0x100++0x3
line.long 0x00 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator, direction, and thread number for the configuration transaction."
bitfld.long 0x00 31. " BUSY  ,Indication that a configuration read or write is in progress 0h = No transaction is in progress 1h = Transaction is in progress" "0,1"
bitfld.long 0x00 30. "         DIR       ,Direction of configuration transaction 0h = Write transaction 1h = Read transaction" "0,1"
textline "                                  "
bitfld.long 0x00 29. " TO    ,Indication that a timeout occurred. This bit should be written to 0h on each new transaction. 0h = Transaction completed normally 1h = Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         THREAD_ID ,Thread ID to which configuration read or write is being sent. The thread ID mapping is shown in"
group.long 0x104++0x3
line.long 0x00 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction."
bitfld.long 0x00 28.--31. " BYTEN ,Byte enables to use for configuration read or write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "        ADDRESS   ,Word (32-bit) address within thread configuration space for transaction 0h = Peer thread ID register ( 1h = Peer credit register ( 2h = Enable register ( 40h = Capabilities register ( 400h = Static TR register"
group.long 0x108++0x3
line.long 0x00 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction."
hexmask.long 0x00 0.--31. 1. " WDATA ,Configuration data word to be written"
group.long 0x140++0x3
line.long 0x00 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction."
hexmask.long 0x00 0.--31. 1. " RDATA ,Configuration data word that was read"
width 0x0B
tree.end
tree.end
tree "Firewall_Region"
tree "PSRAM0"
base ad:0x45000400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PSRAM0_ECC_AGGR"
base ad:0x45000800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PSC0"
base ad:0x45001400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PLLCTRL0_SLV"
base ad:0x45001800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GTC0"
base ad:0x45001C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PLL_MMR0"
base ad:0x45002000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CTRL_MMR0"
base ad:0x45002400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EFUSE0_SLV"
base ad:0x45002C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PBIST0_CFG"
base ad:0x45003000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PBIST1_CFG"
base ad:0x45003400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPIO0"
base ad:0x45004000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPIO1"
base ad:0x45004400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ESM0_CFG"
base ad:0x45006000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC0"
base ad:0x45008000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC1"
base ad:0x45008400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC2"
base ad:0x45008800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC3"
base ad:0x45008C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC4"
base ad:0x45009000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC5"
base ad:0x45009400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC6"
base ad:0x45009800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DCC7"
base ad:0x45009C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "SERDES0_SLV"
base ad:0x4500C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "SERDES1_SLV"
base ad:0x4500C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPIOMUX_INTRTR0_CFG"
base ad:0x4500E000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MAIN2MCU_LVL_INTRTR0_CFG"
base ad:0x4500E400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MAIN2MCU_PLS_INTRTR0_CFG"
base ad:0x4500E800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CMPEVT_INTRTR0_CFG"
base ad:0x4500EC00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMESYNC_INTRTR0_CFG"
base ad:0x4500F000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CBASS_FW0"
base ad:0x45012400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "INFRA_CBASS0"
base ad:0x45012800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ECC_AGGR3"
base ad:0x45012C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ECC_AGGR0"
base ad:0x45013000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_PSC0"
base ad:0x45020400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_PLLCTRL0_SLV"
base ad:0x45020800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_CTRL_MMR0"
base ad:0x45020C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_GPIO0"
base ad:0x45021000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_ESM0_CFG"
base ad:0x45021400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_VTM0"
base ad:0x45021C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_I2C0"
base ad:0x45024000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_USART0"
base ad:0x45028000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_GPIOMUX_INTRTR0_CFG"
base ad:0x4502A000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_CBASS0"
base ad:0x4502C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_CBASS_FW0"
base ad:0x4502C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "WKUP_ECC_AGGR0"
base ad:0x4502C800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ARMSS0_CORE0_SLV"
base ad:0x45100000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ARMSS0_CORE0_CFG_SLV"
base ad:0x45100400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_RTI0_SLV"
base ad:0x45100800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ARMSS0_CORE1_SLV"
base ad:0x45101000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ARMSS0_CORE1_CFG_SLV"
base ad:0x45101400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_RTI1_SLV"
base ad:0x45101800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_FSS0_CFG"
base ad:0x45102000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_FSS0_S1"
base ad:0x45102400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_FSS0_S0"
base ad:0x45103000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ROM0_SLV"
base ad:0x45106000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MSRAM_SLV"
base ad:0x45106800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MSRAM_CFG"
base ad:0x45106C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_PSRAM0"
base ad:0x45107000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_TIMER0"
base ad:0x45108000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_TIMER1"
base ad:0x45108400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_TIMER2"
base ad:0x45108800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_TIMER3"
base ad:0x45108C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MCSPI0_SLV"
base ad:0x4510C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MCSPI1_SLV"
base ad:0x4510C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MCSPI2_SLV"
base ad:0x4510C800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_DCC0"
base ad:0x45110000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_DCC1"
base ad:0x45110400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_DCC2"
base ad:0x45110800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ADC0_DMA"
base ad:0x45114000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ADC0_CFG"
base ad:0x45114400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ADC1_DMA"
base ad:0x45114800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ADC1_CFG"
base ad:0x45114C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_USART0"
base ad:0x45118000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_I2C0"
base ad:0x45120000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ESM0_CFG"
base ad:0x45124000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MCAN0"
base ad:0x45128000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_MCAN1"
base ad:0x45128400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_CTRL_MMR0"
base ad:0x4512C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_PLL_MMR0"
base ad:0x4512C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_EFUSE0_SLV"
base ad:0x4512E000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_PBIST0_CFG"
base ad:0x4512F000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_CPSW0"
base ad:0x45131000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_PDMA0_ECC_AGGR"
base ad:0x45136000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_PDMA1_ECC_AGGR"
base ad:0x45136400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_CBASS0"
base ad:0x45137000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_CBASS_FW0"
base ad:0x45137800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ECC_AGGR0"
base ad:0x45139000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_ECC_AGGR1"
base ad:0x45139400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "NAVSS0_NBSS_CFG"
base ad:0x45200400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "COMPUTE_CLUSTER0_CFG"
base ad:0x45201000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MMCSD1_CFG"
base ad:0x45202400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MMCSD0_CFG"
base ad:0x45202800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PRU_ICSSG0_SLV"
base ad:0x45204000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PRU_ICSSG1_SLV"
base ad:0x45204400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PRU_ICSSG2_SLV"
base ad:0x45204800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CAL0_CFG"
base ad:0x4520C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ELM0"
base ad:0x45214000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPMC0_SLV"
base ad:0x45218000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GIC0_CFG"
base ad:0x4521C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GIC0_ECC_AGGR_CFG"
base ad:0x4521C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USB3SS0_SLV0"
base ad:0x45220000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USB3SS0_SLV1"
base ad:0x45220400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USB3SS1_SLV0"
base ad:0x45220800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USB3SS1_SLV1"
base ad:0x45220C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EQEP0"
base ad:0x45224000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EQEP1"
base ad:0x45224400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EQEP2"
base ad:0x45224800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ECAP0"
base ad:0x45228000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM0"
base ad:0x4522C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM0"
base ad:0x4522C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM5"
base ad:0x4522C800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM5"
base ad:0x4522CC00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM4"
base ad:0x4522D000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM4"
base ad:0x4522D400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM3"
base ad:0x4522D800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM3"
base ad:0x4522DC00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM2"
base ad:0x4522E000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM2"
base ad:0x4522E400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "EPWM1"
base ad:0x4522E800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "HRPWM1"
base ad:0x4522EC00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER0"
base ad:0x45230000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER1"
base ad:0x45230400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER2"
base ad:0x45230800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER3"
base ad:0x45230C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER4"
base ad:0x45231000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER5"
base ad:0x45231400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER6"
base ad:0x45231800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER7"
base ad:0x45231C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER8"
base ad:0x45232000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER9"
base ad:0x45232400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER10"
base ad:0x45232800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "TIMER11"
base ad:0x45232C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DDRSS0_CFG"
base ad:0x45242000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "I2C0"
base ad:0x45244000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "I2C1"
base ad:0x45244400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "I2C2"
base ad:0x45244800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "I2C3"
base ad:0x45244C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PCIE0_SLV"
base ad:0x45248000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PCIE1_SLV"
base ad:0x45248400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "STM0"
base ad:0x4524C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DEBUGSS0_CFG"
base ad:0x45254000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCSPI0_SLV"
base ad:0x4525C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCSPI1_SLV"
base ad:0x4525C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCSPI2_SLV"
base ad:0x4525C800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCSPI3_SLV"
base ad:0x4525CC00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCSPI4_SLV"
base ad:0x4525D000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USART0"
base ad:0x45260000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USART1"
base ad:0x45260400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "USART2"
base ad:0x45260800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP0_CFG"
base ad:0x45268000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP0_DMA"
base ad:0x45268400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP1_CFG"
base ad:0x45268800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP1_DMA"
base ad:0x45268C00
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP2_CFG"
base ad:0x45269000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCASP2_DMA"
base ad:0x45269400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CC_DEBUG_CELL0"
base ad:0x4526C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MAIN_DEBUG_CELL0"
base ad:0x4526C400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "MCU_DEBUG_CELL0"
base ad:0x4526C800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "DSS0_CFG"
base ad:0x4528C000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PCIE0_CFG"
base ad:0x452A0000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PCIE1_CFG"
base ad:0x452A0400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPU0_KLIO_CFG"
base ad:0x452A4000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "GPU0_RAT_CFG"
base ad:0x452A4400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PDMA_DEBUG0_ECC_AGGR"
base ad:0x452A8000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PDMA0_ECC_AGGR"
base ad:0x452A8400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "PDMA1_ECC_AGGR"
base ad:0x452A8800
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "NAVSS0_NB0_BP"
base ad:0x452BE000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ECC_AGGR1"
base ad:0x452C0000
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "ECC_AGGR2"
base ad:0x452C0400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree "CBASS0"
base ad:0x452C2400
width 22.
group.long 0x0++0x3
line.long 0x00 "CBA_CONTROL_i_j,The Firewall i Region j Control Register defines the control fields for the firewall. Offset = 0h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                               "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "CBA_PERMISSION_i_j_0,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "CBA_PERMISSION_i_j_1,The Firewall i Region j Permission 0 to Permission 2 Registers define the permissions for the firewall. Offset = 4h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                               "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                               "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                               "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "CBA_START_ADDR_l_i_j,The Firewall i Region j Start Address Low Register defines the start address bits 31 to 0 for the firewall. Offset = 10h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_L                ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  ADDR_LSB          ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "CBA_START_ADDR_H_i_j,The Firewall i Region j Start Address High Register defines the start address bits 47 to 32 for the firewall. Offset = 14h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " ADDR_H                ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "CBA_END_ADDR_l_i_j,The Firewall i Region j End Address Low Register defines the end address bits 31 to 0 to include for the firewall. Offset = 18h + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDR_L            ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDR_LSB      ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "CBA_END_ADDR_H_i_j,The Firewall i Region j End Address High Register defines the end address bits 47 to 32 to include for the firewall. Offset = 1Ch + (i * 400h) + (j * 20h), where: i = 0h to 7Fh, j = 0h to 1Fh"
hexmask.long.word 0x00 0.--15. 1. " END_ADDR_H            ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree.end
tree "Firewall_Exception"
tree "WKUP_CBASS0_GLB"
base ad:0x45B02000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "CBA_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV          ,TI internal data."
group.long 0x4++0x3
line.long 0x00 "CBA_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
group.long 0x44++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x00 0. " PEND_CLR     ,Write a 1 to clear the exception pend signal." "0,1"
width 0x0B
tree.end
tree "MCU_CBASS0_GLB"
base ad:0x45B06000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "CBA_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV          ,TI internal data."
group.long 0x4++0x3
line.long 0x00 "CBA_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
group.long 0x44++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x00 0. " PEND_CLR     ,Write a 1 to clear the exception pend signal." "0,1"
width 0x0B
tree.end
tree "CBASS0_GLB"
base ad:0x45B08000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "CBA_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV          ,TI internal data."
group.long 0x4++0x3
line.long 0x00 "CBA_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
group.long 0x44++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x00 0. " PEND_CLR     ,Write a 1 to clear the exception pend signal." "0,1"
width 0x0B
tree.end
tree "CBASS_INFRA0_GLB"
base ad:0x45B0C000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "CBA_PID,The Revision Register contains the major and minor revisions for the module."
hexmask.long 0x00 0.--31. 1. " REV          ,TI internal data."
group.long 0x4++0x3
line.long 0x00 "CBA_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "CBA_EXCEPTION_lOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
group.long 0x44++0x3
line.long 0x00 "CBA_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
bitfld.long 0x00 0. " PEND_CLR     ,Write a 1 to clear the exception pend signal." "0,1"
width 0x0B
tree.end
tree.end
tree "QoS"
tree "MCU_ARMSS0_DBG_RD0"
base ad:0x45D10000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_ARMSS0_DBG_WR0"
base ad:0x45D10400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_ARMSS0_P0"
base ad:0x45D10800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_ARMSS0_DBG_RD1"
base ad:0x45D11000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_ARMSS0_DBG_WR1"
base ad:0x45D11400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_ARMSS0_P1"
base ad:0x45D11800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MMCSD1_WR"
base ad:0x45D80000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MMCSD1_RD"
base ad:0x45D80400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MMCSD0_RD"
base ad:0x45D80800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MMCSD0_WR"
base ad:0x45D80C00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PRU_ICSSG0"
base ad:0x45D84000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PRU_ICSSG1"
base ad:0x45D84400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PRU_ICSSG2"
base ad:0x45D84800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "CAL0"
base ad:0x45D8A000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "GIC0_RD"
base ad:0x45D8B800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "GIC0_WR"
base ad:0x45D8BC00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "USB3SS0_WR"
base ad:0x45D8C000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "USB3SS0_RD"
base ad:0x45D8C400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "USB3SS1_WR"
base ad:0x45D8C800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "USB3SS1_RD"
base ad:0x45D8CC00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DSS0"
base ad:0x45D92800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DEBUGSS0_RD"
base ad:0x45D97800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DEBUGSS0_WR"
base ad:0x45D97C00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE0_RD_HP"
base ad:0x45D98000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE0_WR_HP"
base ad:0x45D98400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE0_RD_LP"
base ad:0x45D98800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE0_WR_LP"
base ad:0x45D98C00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE1_RD_HP"
base ad:0x45D99000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE1_WR_HP"
base ad:0x45D99400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE1_RD_LP"
base ad:0x45D99800
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PCIE1_WR_LP"
base ad:0x45D99C00
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "GPU0_P0"
base ad:0x45D9C000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "GPU0_P1"
base ad:0x45D9C400
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "PDMA_DEBUG0_RD"
base ad:0x45DA0000
width 15.
group.long 0x0++0x3
line.long 0x00 "CBA_MAP_i_0,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4++0x3
line.long 0x00 "CBA_MAP_i_1,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8++0x3
line.long 0x00 "CBA_MAP_i_2,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC++0x3
line.long 0x00 "CBA_MAP_i_3,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "CBA_MAP_i_4,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14++0x3
line.long 0x00 "CBA_MAP_i_5,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18++0x3
line.long 0x00 "CBA_MAP_i_6,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C++0x3
line.long 0x00 "CBA_MAP_i_7,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20++0x3
line.long 0x00 "CBA_MAP_i_8,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24++0x3
line.long 0x00 "CBA_MAP_i_9,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28++0x3
line.long 0x00 "CBA_MAP_i_10,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C++0x3
line.long 0x00 "CBA_MAP_i_11,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x00 "CBA_MAP_i_12,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x34++0x3
line.long 0x00 "CBA_MAP_i_13,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x38++0x3
line.long 0x00 "CBA_MAP_i_14,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x3C++0x3
line.long 0x00 "CBA_MAP_i_15,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x40++0x3
line.long 0x00 "CBA_MAP_i_16,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x44++0x3
line.long 0x00 "CBA_MAP_i_17,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "CBA_MAP_i_18,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x4C++0x3
line.long 0x00 "CBA_MAP_i_19,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "CBA_MAP_i_20,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x54++0x3
line.long 0x00 "CBA_MAP_i_21,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x58++0x3
line.long 0x00 "CBA_MAP_i_22,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x5C++0x3
line.long 0x00 "CBA_MAP_i_23,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x60++0x3
line.long 0x00 "CBA_MAP_i_24,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CBA_MAP_i_25,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x68++0x3
line.long 0x00 "CBA_MAP_i_26,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x6C++0x3
line.long 0x00 "CBA_MAP_i_27,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CBA_MAP_i_28,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "CBA_MAP_i_29,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x78++0x3
line.long 0x00 "CBA_MAP_i_30,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x7C++0x3
line.long 0x00 "CBA_MAP_i_31,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x80++0x3
line.long 0x00 "CBA_MAP_i_32,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x84++0x3
line.long 0x00 "CBA_MAP_i_33,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x88++0x3
line.long 0x00 "CBA_MAP_i_34,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "CBA_MAP_i_35,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x90++0x3
line.long 0x00 "CBA_MAP_i_36,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x94++0x3
line.long 0x00 "CBA_MAP_i_37,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x98++0x3
line.long 0x00 "CBA_MAP_i_38,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "CBA_MAP_i_39,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "CBA_MAP_i_40,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA4++0x3
line.long 0x00 "CBA_MAP_i_41,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xA8++0x3
line.long 0x00 "CBA_MAP_i_42,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xAC++0x3
line.long 0x00 "CBA_MAP_i_43,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB0++0x3
line.long 0x00 "CBA_MAP_i_44,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB4++0x3
line.long 0x00 "CBA_MAP_i_45,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xB8++0x3
line.long 0x00 "CBA_MAP_i_46,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xBC++0x3
line.long 0x00 "CBA_MAP_i_47,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "CBA_MAP_i_48,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC4++0x3
line.long 0x00 "CBA_MAP_i_49,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xC8++0x3
line.long 0x00 "CBA_MAP_i_50,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xCC++0x3
line.long 0x00 "CBA_MAP_i_51,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD0++0x3
line.long 0x00 "CBA_MAP_i_52,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD4++0x3
line.long 0x00 "CBA_MAP_i_53,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xD8++0x3
line.long 0x00 "CBA_MAP_i_54,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xDC++0x3
line.long 0x00 "CBA_MAP_i_55,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE0++0x3
line.long 0x00 "CBA_MAP_i_56,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "CBA_MAP_i_57,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xE8++0x3
line.long 0x00 "CBA_MAP_i_58,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xEC++0x3
line.long 0x00 "CBA_MAP_i_59,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF0++0x3
line.long 0x00 "CBA_MAP_i_60,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF4++0x3
line.long 0x00 "CBA_MAP_i_61,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xF8++0x3
line.long 0x00 "CBA_MAP_i_62,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0xFC++0x3
line.long 0x00 "CBA_MAP_i_63,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x100++0x3
line.long 0x00 "CBA_MAP_i_64,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "CBA_MAP_i_65,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x108++0x3
line.long 0x00 "CBA_MAP_i_66,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x10C++0x3
line.long 0x00 "CBA_MAP_i_67,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "CBA_MAP_i_68,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "CBA_MAP_i_69,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x118++0x3
line.long 0x00 "CBA_MAP_i_70,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x11C++0x3
line.long 0x00 "CBA_MAP_i_71,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "CBA_MAP_i_72,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x124++0x3
line.long 0x00 "CBA_MAP_i_73,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x128++0x3
line.long 0x00 "CBA_MAP_i_74,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x12C++0x3
line.long 0x00 "CBA_MAP_i_75,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x130++0x3
line.long 0x00 "CBA_MAP_i_76,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x134++0x3
line.long 0x00 "CBA_MAP_i_77,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "CBA_MAP_i_78,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x13C++0x3
line.long 0x00 "CBA_MAP_i_79,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x140++0x3
line.long 0x00 "CBA_MAP_i_80,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x144++0x3
line.long 0x00 "CBA_MAP_i_81,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x148++0x3
line.long 0x00 "CBA_MAP_i_82,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x14C++0x3
line.long 0x00 "CBA_MAP_i_83,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x00 "CBA_MAP_i_84,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x00 "CBA_MAP_i_85,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x158++0x3
line.long 0x00 "CBA_MAP_i_86,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x15C++0x3
line.long 0x00 "CBA_MAP_i_87,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x160++0x3
line.long 0x00 "CBA_MAP_i_88,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x164++0x3
line.long 0x00 "CBA_MAP_i_89,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x168++0x3
line.long 0x00 "CBA_MAP_i_90,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x16C++0x3
line.long 0x00 "CBA_MAP_i_91,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x170++0x3
line.long 0x00 "CBA_MAP_i_92,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x174++0x3
line.long 0x00 "CBA_MAP_i_93,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x178++0x3
line.long 0x00 "CBA_MAP_i_94,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x17C++0x3
line.long 0x00 "CBA_MAP_i_95,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "CBA_MAP_i_96,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x184++0x3
line.long 0x00 "CBA_MAP_i_97,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "CBA_MAP_i_98,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x18C++0x3
line.long 0x00 "CBA_MAP_i_99,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x190++0x3
line.long 0x00 "CBA_MAP_i_100,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x194++0x3
line.long 0x00 "CBA_MAP_i_101,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "CBA_MAP_i_102,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x19C++0x3
line.long 0x00 "CBA_MAP_i_103,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A0++0x3
line.long 0x00 "CBA_MAP_i_104,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A4++0x3
line.long 0x00 "CBA_MAP_i_105,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1A8++0x3
line.long 0x00 "CBA_MAP_i_106,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "CBA_MAP_i_107,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B0++0x3
line.long 0x00 "CBA_MAP_i_108,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B4++0x3
line.long 0x00 "CBA_MAP_i_109,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1B8++0x3
line.long 0x00 "CBA_MAP_i_110,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1BC++0x3
line.long 0x00 "CBA_MAP_i_111,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C0++0x3
line.long 0x00 "CBA_MAP_i_112,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C4++0x3
line.long 0x00 "CBA_MAP_i_113,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1C8++0x3
line.long 0x00 "CBA_MAP_i_114,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1CC++0x3
line.long 0x00 "CBA_MAP_i_115,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D0++0x3
line.long 0x00 "CBA_MAP_i_116,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D4++0x3
line.long 0x00 "CBA_MAP_i_117,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "CBA_MAP_i_118,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1DC++0x3
line.long 0x00 "CBA_MAP_i_119,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E0++0x3
line.long 0x00 "CBA_MAP_i_120,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E4++0x3
line.long 0x00 "CBA_MAP_i_121,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1E8++0x3
line.long 0x00 "CBA_MAP_i_122,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1EC++0x3
line.long 0x00 "CBA_MAP_i_123,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F0++0x3
line.long 0x00 "CBA_MAP_i_124,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F4++0x3
line.long 0x00 "CBA_MAP_i_125,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1F8++0x3
line.long 0x00 "CBA_MAP_i_126,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x1FC++0x3
line.long 0x00 "CBA_MAP_i_127,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "CBA_MAP_i_128,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "CBA_MAP_i_129,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x208++0x3
line.long 0x00 "CBA_MAP_i_130,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x20C++0x3
line.long 0x00 "CBA_MAP_i_131,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x210++0x3
line.long 0x00 "CBA_MAP_i_132,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x214++0x3
line.long 0x00 "CBA_MAP_i_133,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x218++0x3
line.long 0x00 "CBA_MAP_i_134,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x21C++0x3
line.long 0x00 "CBA_MAP_i_135,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x220++0x3
line.long 0x00 "CBA_MAP_i_136,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x224++0x3
line.long 0x00 "CBA_MAP_i_137,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x228++0x3
line.long 0x00 "CBA_MAP_i_138,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x22C++0x3
line.long 0x00 "CBA_MAP_i_139,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x230++0x3
line.long 0x00 "CBA_MAP_i_140,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x234++0x3
line.long 0x00 "CBA_MAP_i_141,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x238++0x3
line.long 0x00 "CBA_MAP_i_142,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x3
line.long 0x00 "CBA_MAP_i_143,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x240++0x3
line.long 0x00 "CBA_MAP_i_144,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x244++0x3
line.long 0x00 "CBA_MAP_i_145,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x248++0x3
line.long 0x00 "CBA_MAP_i_146,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x24C++0x3
line.long 0x00 "CBA_MAP_i_147,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x250++0x3
line.long 0x00 "CBA_MAP_i_148,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x254++0x3
line.long 0x00 "CBA_MAP_i_149,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x258++0x3
line.long 0x00 "CBA_MAP_i_150,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "CBA_MAP_i_151,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x00 "CBA_MAP_i_152,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "CBA_MAP_i_153,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x268++0x3
line.long 0x00 "CBA_MAP_i_154,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "CBA_MAP_i_155,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "CBA_MAP_i_156,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x274++0x3
line.long 0x00 "CBA_MAP_i_157,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x278++0x3
line.long 0x00 "CBA_MAP_i_158,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x27C++0x3
line.long 0x00 "CBA_MAP_i_159,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x280++0x3
line.long 0x00 "CBA_MAP_i_160,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x284++0x3
line.long 0x00 "CBA_MAP_i_161,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x288++0x3
line.long 0x00 "CBA_MAP_i_162,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x28C++0x3
line.long 0x00 "CBA_MAP_i_163,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x290++0x3
line.long 0x00 "CBA_MAP_i_164,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x294++0x3
line.long 0x00 "CBA_MAP_i_165,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x298++0x3
line.long 0x00 "CBA_MAP_i_166,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x29C++0x3
line.long 0x00 "CBA_MAP_i_167,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A0++0x3
line.long 0x00 "CBA_MAP_i_168,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x3
line.long 0x00 "CBA_MAP_i_169,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x3
line.long 0x00 "CBA_MAP_i_170,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2AC++0x3
line.long 0x00 "CBA_MAP_i_171,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B0++0x3
line.long 0x00 "CBA_MAP_i_172,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B4++0x3
line.long 0x00 "CBA_MAP_i_173,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2B8++0x3
line.long 0x00 "CBA_MAP_i_174,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2BC++0x3
line.long 0x00 "CBA_MAP_i_175,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x3
line.long 0x00 "CBA_MAP_i_176,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C4++0x3
line.long 0x00 "CBA_MAP_i_177,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2C8++0x3
line.long 0x00 "CBA_MAP_i_178,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2CC++0x3
line.long 0x00 "CBA_MAP_i_179,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D0++0x3
line.long 0x00 "CBA_MAP_i_180,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D4++0x3
line.long 0x00 "CBA_MAP_i_181,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2D8++0x3
line.long 0x00 "CBA_MAP_i_182,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2DC++0x3
line.long 0x00 "CBA_MAP_i_183,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x3
line.long 0x00 "CBA_MAP_i_184,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E4++0x3
line.long 0x00 "CBA_MAP_i_185,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2E8++0x3
line.long 0x00 "CBA_MAP_i_186,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2EC++0x3
line.long 0x00 "CBA_MAP_i_187,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F0++0x3
line.long 0x00 "CBA_MAP_i_188,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F4++0x3
line.long 0x00 "CBA_MAP_i_189,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x2F8++0x3
line.long 0x00 "CBA_MAP_i_190,The Map Register defines the fields for the master per channel. Channel N is calculated as b*2 and N+1 is b*2+1, where: b = 0h to BFh. Offset = 0h + (i * 400h), where: i = 0h to 7h"
bitfld.long 0x00 28.--30. " EPRIORITY1 ,epriority signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "   ORDERID1  ,Initial order ID value for channel N+1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 16.--18. " QOS1       ,qos signal for channel N+1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "   EPRIORITY ,epriority signal for channel N." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID    ,Initial order ID value for channel N." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "  QOS       ,qos signal for channel N." "0,1,2,3,4,5,6,7"
group.long 0x300++0x3
line.long 0x00 "CBA_MAP1_i_j,The Group Map Register 1 defines the final order ID for the master group j from input order ID values of 0 to 7. Offset = 300h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID7   ,Final order ID value for initial order ID value of 7." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID6  ,Final order ID value for initial order ID value of 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID5   ,Final order ID value for initial order ID value of 5." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID4  ,Final order ID value for initial order ID value of 4." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID3   ,Final order ID value for initial order ID value of 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID2  ,Final order ID value for initial order ID value of 2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID1   ,Final order ID value for initial order ID value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID0  ,Final order ID value for initial order ID value of 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x3
line.long 0x00 "CBA_MAP2_i_j,The Group Map Register 2 defines the final order ID for the master group j from input order ID values of 8 to 15. Offset = 304h + (i * 400h) + (j * 8h), where: i = 0h to 7h, j = 0h to 1Fh"
bitfld.long 0x00 28.--31. " ORDERID15  ,Final order ID value for initial order ID value of 15." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  ORDERID14 ,Final order ID value for initial order ID value of 14." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 20.--23. " ORDERID13  ,Final order ID value for initial order ID value of 13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  ORDERID12 ,Final order ID value for initial order ID value of 12." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 12.--15. " ORDERID11  ,Final order ID value for initial order ID value of 11." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  ORDERID10 ,Final order ID value for initial order ID value of 10." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ORDERID9   ,Final order ID value for initial order ID value of 9." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  ORDERID8  ,Final order ID value for initial order ID value of 8." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree.end
tree "MSMC"
base ad:0x6E000000
width 21.
rgroup.quad 0x0++0x7
line.quad 0x00 "MSMC_PID,Peripheral ID Register."
hexmask.quad.long 0x00 0.--31. 1. " REVISION           ,PID Revision"
group.quad 0x1000++0x7
line.quad 0x00 "MSMC_CACHE_CTRL,Cache Control Register."
bitfld.quad 0x00 8. " REPLACEMENT_POLICY ,Replacement Policy" "0,1"
bitfld.quad 0x00 4. "                 SZ_TRANSITION ,Cache Size Change in Progress" "0,1"
textline "                                      "
bitfld.quad 0x00 0.--3. " CACHE_SIZE         ,Cache Size Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad 0x1010++0x7
line.quad 0x00 "MSMC_RT_WAY_SELECT,Real Time Way Select."
bitfld.quad 0x00 5.--6. " OR_MASK            ,OR mask for way-select" "0,1,2,3"
bitfld.quad 0x00 0.--1. "                 AND_MASK      ,AND mask for way-select" "0,1,2,3"
group.quad 0x1018++0x7
line.quad 0x00 "MSMC_NRT_WAY_SELECT,Non Real Time Way Select."
bitfld.quad 0x00 5.--6. " OR_MASK            ,OR mask for way-select" "0,1,2,3"
bitfld.quad 0x00 0.--1. "                 AND_MASK      ,AND mask for way-select" "0,1,2,3"
group.quad 0x2048++0x7
line.quad 0x00 "MSMC_COHCTRL,Coherence Control Register."
bitfld.quad 0x00 0. " BCM                ,Broadcast Mode" "0,1"
group.quad 0x3080++0x7
line.quad 0x00 "MSMC_SMEDCC,Scrub Rate Register."
bitfld.quad 0x00 31. " SEN                ,Scrub Engine Enable" "0,1"
hexmask.quad.byte 0x00 0.--7. 1. "                 REFDEL        ,Number of Clock Cycles Between Scrubs"
rgroup.quad 0x5000++0x7
line.quad 0x00 "MSMC_SMESTAT,Interrupt Enabled Status register. ANDed value of and ."
bitfld.quad 0x00 0. " NULL_SLV           ,Null slave error is enabled and pending" "0,1"
rgroup.quad 0x5008++0x7
line.quad 0x00 "MSMC_SMIRSTAT,Interrupt raw status register."
bitfld.quad 0x00 0. " NULL_SLV           ,Null slave error flagged" "0,1"
wgroup.quad 0x5008++0x7
line.quad 0x00 "MSMC_SMIRWS,set interrupt raw status register."
bitfld.quad 0x00 0. " NULL_SLV           ,Set software null slave error" "0,1"
wgroup.quad 0x5010++0x7
line.quad 0x00 "MSMC_SMIRC,Interrupt clear register."
bitfld.quad 0x00 0. " NULL_SLV           ,Clear null slave error flag" "0,1"
rgroup.quad 0x5018++0x7
line.quad 0x00 "MSMC_SMIESTAT,Interrupt raw status register."
bitfld.quad 0x00 0. " NULL_SLV           ,Null slave error interrupt is enabled" "0,1"
wgroup.quad 0x5018++0x7
line.quad 0x00 "MSMC_SMIEWS,set interrupt raw status register."
bitfld.quad 0x00 0. " NULL_SLV           ,Enable null slave error" "0,1"
wgroup.quad 0x5020++0x7
line.quad 0x00 "MSMC_SMIEC,Interrupt clear register."
bitfld.quad 0x00 0. " NULL_SLV           ,clear null slave error interrupt enable" "0,1"
group.quad 0x6000++0x7
line.quad 0x00 "MSMC_SBNDCOH0,Starvation Bound for Coherent Port 0."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6008++0x7
line.quad 0x00 "MSMC_SBNDCOH1,Starvation Bound for Coherent Port 1."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6010++0x7
line.quad 0x00 "MSMC_SBNDCOH2,Starvation Bound for Coherent Port 2."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6018++0x7
line.quad 0x00 "MSMC_SBNDCOH3,Starvation Bound for Coherent Port 3."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6100++0x7
line.quad 0x00 "MSMC_SBNDDRU,Starvation Bound for Data Routing Unit."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6200++0x7
line.quad 0x00 "MSMC_SBNDRESP,Starvation Bound for Read Response."
hexmask.quad.byte 0x00 48.--55. 1. " SBNDE_RT           ,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "                SBNDM_RT      ,Starvation Bound for Real-Time On-Chip Memory"
textline "                                      "
hexmask.quad.byte 0x00 16.--23. 1. " SBNDE_NRT          ,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "                SBNDM_NRT     ,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x7000++0x7
line.quad 0x00 "MSMC_DBGTAGCTL,Debug Tag View Control."
bitfld.quad 0x00 40. " L3CACHE            ,Level 3 Cache Tag Select" "0,1"
bitfld.quad 0x00 32.--33. "                 BANK          ,Physical Bank Select" "0,1,2,3"
textline "                                      "
hexmask.quad.word 0x00 16.--29. 1. " INDEX              ,Index Select"
bitfld.quad 0x00 0.--4. "              WAY           ,Way Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.quad 0x7080++0x7
line.quad 0x00 "MSMC_DBGTAGVIEW,Debug Tag View Read."
bitfld.quad 0x00 54.--58. " SF                 ,Snoop Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 52. "                DIRTY         ,Dirty" "0,1"
textline "                                      "
bitfld.quad 0x00 50. " DATA_VALID         ,Data Valid" "0,1"
bitfld.quad 0x00 48. "                 ADDR_VALID    ,Address Valid" "0,1"
textline "                                      "
hexmask.quad.quad 0x00 0.--47. 1. " ADDRESS            ,Tag Address"
rgroup.quad 0xA000++0x7
line.quad 0x00 "MSMC_NULL_SLV_STAT0,Null Slave Status 0."
hexmask.quad 0x00 0.--63. 1. " ADDR               ,Address"
rgroup.quad 0xA008++0x7
line.quad 0x00 "MSMC_NULL_SLV_STAT1,Null Slave Status 1."
bitfld.quad 0x00 52.--53. " PRIV               ,Privilege" "0,1,2,3"
bitfld.quad 0x00 48. "                 SECURE        ,Secure" "0,1"
textline "                                      "
bitfld.quad 0x00 44. " EMU                ,Emulation" "0,1"
bitfld.quad 0x00 40.--41. "                 MEMTYPE       ,Memory Type" "0,1,2,3"
textline "                                      "
bitfld.quad 0x00 32.--37. " OPCODE             ,Opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.quad.byte 0x00 24.--31. 1. "                PRIVID        ,Priv ID"
textline "                                      "
hexmask.quad.word 0x00 12.--23. 1. " ROUTEID            ,Route ID"
hexmask.quad.word 0x00 0.--9. 1. "              BYTECNT       ,Byte Count"
group.quad 0xA018++0x7
line.quad 0x00 "MSMC_NULL_SLV_CNT,Null Slave Error Count."
hexmask.quad.byte 0x00 0.--7. 1. " COUNT              ,Count"
width 0x0B
tree.end
tree "CTRL_MMR"
tree "CTRL_MMR0_CFG0"
base ad:0x100000
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "CTRLMMR_PID,Peripheral release details."
hexmask.long 0x00 0.--31. 1. " REV               ,TI internal data."
rgroup.long 0x8++0x3
line.long 0x00 "CTRLMMR_MMR_CFG1,Indicates the MMR configuration."
hexmask.long.byte 0x00 0.--7. 1. " PARTITIONS        ,Indicates present partitions"
group.long 0x30++0x3
line.long 0x00 "CTRLMMR_MAIN_DEVSTAT,Indicates SoC bootstrap selection. The default value of this register is determined by the SoC bootstrap pins when the por_boot_cfg_srst_n input is de-asserted. Note that this register will not be valid when returning from Deepsleep powerdown modes as the bootstrap pins are not relatched in this scenario."
hexmask.long.tbyte 0x00 0.--18. 1. " BOOTMODE          ,Specifies the device Primary and Backup boot media."
rgroup.long 0x34++0x3
line.long 0x00 "CTRLMMR_MAIN_BOOTCFG,Indicates SoC bootstrap selection latched at power-on reset by PORz. The default value of this register is determined by the SoC bootstrap pins when the MMR por_boot_cfg_srst_n input is de-asserted and will remain until the SOC bootstrap pins are re-latched on a subsequent MMR por_boot_cfg_srst_n rising edge. Note that this register will not be valid when returning from Deepsleep powerdown modes as the bootstrap pins are not relatched in this scenario."
hexmask.long.tbyte 0x00 0.--18. 1. " BOOTMODE          ,Specifies the device Primary and Backup boot media as latched at PORz"
rgroup.long 0x50++0x3
line.long 0x00 "CTRLMMR_ICSSG0_DISABLE_STAT,Indicates disabled ICSSG0 features."
hexmask.long.byte 0x00 0.--7. 1. " DISABLE_STAT      ,ICSSG0 feature disable status"
rgroup.long 0x54++0x3
line.long 0x00 "CTRLMMR_ICSSG1_DISABLE_STAT,Indicates disabled ICSSG1 features."
hexmask.long.byte 0x00 0.--7. 1. " DISABLE_STAT      ,ICSSG1 feature disable status"
rgroup.long 0x58++0x3
line.long 0x00 "CTRLMMR_ICSSG2_DISABLE_STAT,Indicates disabled ICSSG2 features."
hexmask.long.byte 0x00 0.--7. 1. " DISABLE_STAT      ,ICSSG2 feature disable status"
group.long 0x120++0x3
line.long 0x00 "CTRLMMR_IPC_SET8,Generate interprocessor communication interrupt to A5x core0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x124++0x3
line.long 0x00 "CTRLMMR_IPC_SET9,Generate interprocessor communication interrupt to A5x core1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x128++0x3
line.long 0x00 "CTRLMMR_IPC_SET10,Generate interprocessor communication interrupt to A5x core2."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x12C++0x3
line.long 0x00 "CTRLMMR_IPC_SET11,Generate interprocessor communication interrupt to A5x core3."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x150++0x3
line.long 0x00 "CTRLMMR_IPC_SET20,Generate interprocessor communication interrupt to ICSSG0 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x154++0x3
line.long 0x00 "CTRLMMR_IPC_SET21,Generate interprocessor communication interrupt to ICSSG0 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x158++0x3
line.long 0x00 "CTRLMMR_IPC_SET22,Generate interprocessor communication interrupt to ICSSG1 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x15C++0x3
line.long 0x00 "CTRLMMR_IPC_SET23,Generate interprocessor communication interrupt to ICSSG1 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x160++0x3
line.long 0x00 "CTRLMMR_IPC_SET24,Generate interprocessor communication interrupt to ICSSG2 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x164++0x3
line.long 0x00 "CTRLMMR_IPC_SET25,Generate interprocessor communication interrupt to ICSSG2 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET           ,Read returns 0" "0,1"
group.long 0x1A0++0x3
line.long 0x00 "CTRLMMR_IPC_CLR8,Acknowledge interprocessor communication interrupt to A5x core0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1A4++0x3
line.long 0x00 "CTRLMMR_IPC_CLR9,Acknowledge interprocessor communication interrupt to A5x core1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1A8++0x3
line.long 0x00 "CTRLMMR_IPC_CLR10,Acknowledge interprocessor communication interrupt to A5x core2."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1AC++0x3
line.long 0x00 "CTRLMMR_IPC_CLR11,Acknowledge interprocessor communication interrupt to A5x core3."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1D0++0x3
line.long 0x00 "CTRLMMR_IPC_CLR20,Acknowledge interprocessor communication interrupt to ICSSG0 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1D4++0x3
line.long 0x00 "CTRLMMR_IPC_CLR21,Acknowledge interprocessor communication interrupt to ICSSG0 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1D8++0x3
line.long 0x00 "CTRLMMR_IPC_CLR22,Acknowledge interprocessor communication interrupt to ICSSG1 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1DC++0x3
line.long 0x00 "CTRLMMR_IPC_CLR23,Acknowledge interprocessor communication interrupt to ICSSG1 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1E0++0x3
line.long 0x00 "CTRLMMR_IPC_CLR24,Acknowledge interprocessor communication interrupt to ICSSG2 PRU0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
group.long 0x1E4++0x3
line.long 0x00 "CTRLMMR_IPC_CLR25,Acknowledge interprocessor communication interrupt to ICSSG2 PRU1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR       ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR           ,Read returns current value" "0,1"
rgroup.long 0x210++0x3
line.long 0x00 "CTRLMMR_PCI_DEVICE_ID,PCIe device ID and vendor ID register."
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID         ,Device ID"
hexmask.long.word 0x00 0.--15. 1. "      VENDOR_ID         ,TI Vendor ID"
group.long 0x1008++0x3
line.long 0x00 "CTRLMMR_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x100C++0x3
line.long 0x00 "CTRLMMR_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x1010++0x3
line.long 0x00 "CTRLMMR_INTR_RAW_STAT,Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test)."
bitfld.long 0x00 2. " LOCK_ERR          ,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR          ,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR          ,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1"
group.long 0x1014++0x3
line.long 0x00 "CTRLMMR_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared."
bitfld.long 0x00 2. " EN_LOCK_ERR       ,Enabled lock interrupt event status" "0,1"
bitfld.long 0x00 1. "         EN_ADDR_ERR       ,Enabled address interrupt event status" "0,1"
textline "                                      "
bitfld.long 0x00 0. " EN_PROT_ERR       ,Enabled protection interrupt event status" "0,1"
group.long 0x1018++0x3
line.long 0x00 "CTRLMMR_INTR_EN_SET,Allows interrupt enables to be set."
bitfld.long 0x00 2. " LOCK_ERR_EN_SET   ,Lock interrupt enable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_SET   ,Address interrupt enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR_EN_SET   ,Protection interrupt enable" "0,1"
group.long 0x101C++0x3
line.long 0x00 "CTRLMMR_INTR_EN_CLR,Allows interrupt enables to be cleared."
bitfld.long 0x00 2. " LOCK_ERR_EN_CLR   ,Lock interrupt disable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_CLR   ,Address interrupt disable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR_EN_CLR   ,Protection interrupt disable" "0,1"
rgroup.long 0x1024++0x3
line.long 0x00 "CTRLMMR_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur."
hexmask.long 0x00 0.--31. 1. " ADDRESS           ,Address of the faulted access"
rgroup.long 0x1028++0x3
line.long 0x00 "CTRLMMR_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur."
bitfld.long 0x00 0.--5. " TYPE              ,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x102C++0x3
line.long 0x00 "CTRLMMR_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur."
hexmask.long.word 0x00 20.--31. 1. " XID               ,Transaction ID"
hexmask.long.word 0x00 8.--19. 1. "      ROUTEID           ,Route ID"
textline "                                      "
hexmask.long.byte 0x00 0.--7. 1. " PRIVID            ,Privilege ID"
group.long 0x1030++0x3
line.long 0x00 "CTRLMMR_FAULT_CLR,Allows software to clear the current fault Clearing the current fault allows the , , and registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits."
bitfld.long 0x00 0. " CLEAR             ,Fault clear" "0,1"
group.long 0x4000++0x3
line.long 0x00 "CTRLMMR_USB0_CTRL,Controls USB0 operation."
bitfld.long 0x00 8. " OTG_PWRDN         ,Power down VBUS/ID detection macro" "0,1"
bitfld.long 0x00 5. "         VBUS_DET_EN       ,Enable ID detection and VBUS AVALID, BVALID, and SESSEND detection for USB0" "0,1"
textline "                                      "
bitfld.long 0x00 4. " VBUSVALID_DET_EN  ,Enable VBUSVALID detection for USB0" "0,1"
group.long 0x4004++0x3
line.long 0x00 "CTRLMMR_USB0_EBC_CFG,Configures the operation of the USB0 external buffer controls."
bitfld.long 0x00 8.--9. " EP15_SEL          ,Endpoint 15 EBC control select 0h - Driven high 1h - Driven by MCU TBR DMA event 2h - Driven by MAIN TBR DMA event 3h - Driven by ComputeCluster TBR DMA event" "0,1,2,3"
bitfld.long 0x00 0.--1. "         EP14_SEL          ,Endpoint 14 EBC control select 0h - Driven high 1h - Driven by MCU TBR DMA event 2h - Driven by MAIN TBR DMA event 3h - Driven by ComputeCluster TBR DMA event" "0,1,2,3"
group.long 0x4020++0x3
line.long 0x00 "CTRLMMR_USB1_CTRL,Controls USB1 operation."
bitfld.long 0x00 8. " OTG_PWRDN         ,Power down VBUS/ID detection macro" "0,1"
bitfld.long 0x00 5. "         VBUS_DET_EN       ,Enable ID detection and VBUS AVALID, BVALID, and SESSEND detection for USB1" "0,1"
textline "                                      "
bitfld.long 0x00 4. " VBUSVALID_DET_EN  ,Enable VBUSVALID detection for USB1" "0,1"
group.long 0x4024++0x3
line.long 0x00 "CTRLMMR_USB1_EBC_CFG,Configures the operation of the USB1 external buffer controls."
bitfld.long 0x00 8.--9. " EP15_SEL          ,Endpoint 15 EBC control select 0h - Driven high 1h - Driven by MCU TBR DMA event 2h - Driven by MAIN TBR DMA event 3h - Driven by ComputeCluster TBR DMA event" "0,1,2,3"
bitfld.long 0x00 0.--1. "         EP14_SEL          ,Endpoint 14 EBC control select 0h - Driven high 1h - Driven by MCU TBR DMA event 2h - Driven by MAIN TBR DMA event 3h - Driven by ComputeCluster TBR DMA event" "0,1,2,3"
group.long 0x4060++0x3
line.long 0x00 "CTRLMMR_PCIE0_CTRL,Controls PCIe0 operation."
bitfld.long 0x00 0.--1. " DEVICE_TYPE       ,Configures the PCIe interface operating mode 0h - Endpoint 1h - Legacy Endpoint 2h - Root Complex" "0,1,2,3"
group.long 0x4070++0x3
line.long 0x00 "CTRLMMR_PCIE1_CTRL,Controls PCIe1 operation."
bitfld.long 0x00 0.--1. " DEVICE_TYPE       ,Configures the PCIe interface operating mode 0h - Endpoint 1h - Legacy Endpoint 2h - Root Complex" "0,1,2,3"
group.long 0x4080++0x3
line.long 0x00 "CTRLMMR_SERDES0_CTRL,Controls SERDES0 lane and clock assignment."
bitfld.long 0x00 8. " RET_EN            ,Retention enable" "0,1"
bitfld.long 0x00 4.--7. "         CLK_SEL           ,Selects the SERDES0 clock source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0.--1. " LANE_FUNC_SEL     ,Selects the SERDES0 lane function 0h - USB3 1h - PCIe0 Lane0 2h - ICSS2 SGMII Lane0" "0,1,2,3"
group.long 0x4090++0x3
line.long 0x00 "CTRLMMR_SERDES1_CTRL,Controls SERDES1 lane and clock assignment."
bitfld.long 0x00 8. " RET_EN            ,Retention enable" "0,1"
bitfld.long 0x00 4.--7. "         CLK_SEL           ,Selects the SERDES1 clock source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0.--1. " LANE_FUNC_SEL     ,Selects the SERDES1 lane function 0h - PCIe1 Lane0 1h - PCIe0 Lane1 2h - ICSS2 SGMII Lane1" "0,1,2,3"
group.long 0x40C0++0x3
line.long 0x00 "CTRLMMR_CAL0_CTRL,Controls Camera Adaptation Layer0 operation."
bitfld.long 0x00 24.--25. " CAMRX0_MODE       ,Selects camera mode of operation 0h - DPHY mode 1h - CCP2 Data/Strobe mode 2h - CCP2 Data/Clock mode 3h - GP mode" "0,1,2,3"
bitfld.long 0x00 16. "         CAMRX0_OFFMODE    ,When set, powers down the PHY analog circuits" "0,1"
textline "                                      "
bitfld.long 0x00 15. " CAMRX0_CTRLCLK_EN ,CSI0 CTRLCLK enable" "0,1"
bitfld.long 0x00 0.--4. "         CAMRX0_LANE_EN    ,Lane enable bit for each CSI0 lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x40D0++0x3
line.long 0x00 "CTRLMMR_DDR_STATUS,Indicates DDR status."
bitfld.long 0x00 0. " PLL_BYPASS        ,When set, indicates DDR PLL is bypassed." "0,1"
group.long 0x4100++0x3
line.long 0x00 "CTRLMMR_ICSSG0_CTRL0,Controls ICSS_G0 operation."
bitfld.long 0x00 24. " RGMII0_ID_MODE    ,Controls the PRU_ICSSG0 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the ICSS_G0 GPO0 pins. Each bit n controls the corresponding PRG0_PRU0GPOn I/O"
group.long 0x4104++0x3
line.long 0x00 "CTRLMMR_ICSSG0_CTRL1,Controls ICSS_G0 operation."
bitfld.long 0x00 24. " RGMII1_ID_MODE    ,Controls the PRU_ICSSG0 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the ICSS_G0 GPO0 pins. Each bit n controls the corresponding PRG0_PRU1GPOn I/O"
group.long 0x4108++0x3
line.long 0x00 "CTRLMMR_ICSSG0_CTRL2,Controls ICSS_G0 operation."
bitfld.long 0x00 8.--10. " EPRIOR            ,ICSSG0 QoS epriority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--7. "         PRIOR             ,ICSSG0 QoS priority" "0,1,2,3,4,5,6,7"
textline "                                      "
bitfld.long 0x00 0.--3. " ORDER_ID          ,ICSSG0 QoS orderid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4110++0x3
line.long 0x00 "CTRLMMR_ICSSG1_CTRL0,Controls ICSS_G1 operation."
bitfld.long 0x00 24. " RGMII0_ID_MODE    ,Controls the PRU_ICSSG1 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the ICSS_G1 GPO0 pins. Each bit n controls the corresponding PRG1_PRU0GPOn I/O"
group.long 0x4114++0x3
line.long 0x00 "CTRLMMR_ICSSG1_CTRL1,Controls ICSS_G1 operation."
bitfld.long 0x00 24. " RGMII1_ID_MODE    ,Controls the PRU_ICSSG1 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the ICSS_G1 GPO0 pins. Each bit n controls the corresponding PRG1_PRU1GPOn I/O"
group.long 0x4118++0x3
line.long 0x00 "CTRLMMR_ICSSG1_CTRL2,Controls ICSS_G1 operation."
bitfld.long 0x00 8.--10. " EPRIOR            ,ICSSG1 QoS epriority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--7. "         PRIOR             ,ICSSG1 QoS priority" "0,1,2,3,4,5,6,7"
textline "                                      "
bitfld.long 0x00 0.--3. " ORDER_ID          ,ICSSG1 QoS orderid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4120++0x3
line.long 0x00 "CTRLMMR_ICSSG2_CTRL0,Controls ICSS_G2 operation."
bitfld.long 0x00 24. " RGMII0_ID_MODE    ,Controls the PRU_ICSSG2 RGMII0 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the PRU_ICSSG2 GPO0 pins. Each bit n controls the corresponding PRG2_PRU0GPOn I/O"
group.long 0x4124++0x3
line.long 0x00 "CTRLMMR_ICSSG2_CTRL1,Controls ICSS_G2 operation."
bitfld.long 0x00 24. " RGMII1_ID_MODE    ,Controls the PRU_ICSSG2 RGMII1 port internal transmit delay" "0,1"
hexmask.long.tbyte 0x00 0.--19. 1. "         GPM_BIDI          ,Controls operation of the ICSS_G2 GPO0 pins. Each bit n controls the corresponding PRG2_PRU1GPOn I/O"
group.long 0x4128++0x3
line.long 0x00 "CTRLMMR_ICSSG2_CTRL2,Controls ICSS_G2 operation."
bitfld.long 0x00 8.--10. " EPRIOR            ,ICSSG2 QoS epriority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5.--7. "         PRIOR             ,ICSSG2 QoS priority" "0,1,2,3,4,5,6,7"
textline "                                      "
bitfld.long 0x00 0.--3. " ORDER_ID          ,ICSSG2 QoS orderid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4140++0x3
line.long 0x00 "CTRLMMR_EPWM0_CTRL,Controls eHRPWM0 Operation."
bitfld.long 0x00 8.--10. " SYNCIN_SEL        ,Selects the source of the PWM0 synchronization input 0h - PWM0_SYNCIN Pin 1h - None 2h - None 3h - None 4h - ICSSG0 Host Interrupt 6 5h - ICSSG1 Host Interrupt 6 6h - ICSSG2 Host Interrupt 6 7h - None" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "         EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
textline "                                      "
bitfld.long 0x00 0. " TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x4144++0x3
line.long 0x00 "CTRLMMR_EPWM1_CTRL,Controls eHRPWM1 Operation."
bitfld.long 0x00 4. " EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
bitfld.long 0x00 0. "         TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x4148++0x3
line.long 0x00 "CTRLMMR_EPWM2_CTRL,Controls eHRPWM2 Operation."
bitfld.long 0x00 4. " EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
bitfld.long 0x00 0. "         TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x414C++0x3
line.long 0x00 "CTRLMMR_EPWM3_CTRL,Controls eHRPWM3 Operation."
bitfld.long 0x00 8.--10. " SYNCIN_SEL        ,Selects the source of the PWM3 synchronization input 0h - PWM3_SYNCIN Pin 1h - PWM2 syncout signal, daisy chained 2h - None 3h - None 4h - ICSSG0 Host Interrupt 7 5h - ICSSG1 Host Interrupt 7 6h - ICSSG2 Host Interrupt 7 7h - None" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "         EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
textline "                                      "
bitfld.long 0x00 0. " TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x4150++0x3
line.long 0x00 "CTRLMMR_EPWM4_CTRL,Controls eHRPWM4 Operation."
bitfld.long 0x00 4. " EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
bitfld.long 0x00 0. "         TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x4154++0x3
line.long 0x00 "CTRLMMR_EPWM5_CTRL,Controls eHRPWM5 Operation."
bitfld.long 0x00 4. " EALLOW            ,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
bitfld.long 0x00 0. "         TB_CLKEN          ,Enable eHRPWM timebase clock" "0,1"
group.long 0x4160++0x3
line.long 0x00 "CTRLMMR_SOCA_SEL,Selects Start of Conversion A output signal source. Each eHRPWM provides a SOCA event that can be used to trigger external ADCs. All eHRPWM SOCA events are ORed together allowing any of the 6 eHRPWMs to generate the event (if enabled within the eHRPWM). This event is then muxed with an ICSSx host interrupt allowing either an ICSSx or eHRPWMs to source the SOCA event pin."
bitfld.long 0x00 0.--1. " SOCA_SEL          ,Selects the SOC A output source 0h - OR of all eHRPWM SOCA outputs 1h - ICSSG0 Host Interrupt 1 2h - ICSSG1 Host Interrupt 1 3h - ICSSG2 Host Interrupt 1" "0,1,2,3"
group.long 0x4164++0x3
line.long 0x00 "CTRLMMR_SOCB_SEL,Selects Start of Conversion B output signal source.. Each eHRPWM provides a SOCB event that can be used to trigger external ADCs. All eHRPWM SOCB events are ORed together allowing any of the 6 eHRPWMs to generate the event (if enabled within the eHRPWM). This event is then muxed with an ICSSx host interrupt allowing either an ICSSx or eHRPWMs to source the SOCB event pin."
bitfld.long 0x00 0.--1. " SOCB_SEL          ,Selects the SOC B output source 0h - OR of all eHRPWM SOCB ouputs 1h - ICSSG0 Host Interrupt 2 2h - ICSSG1 Host Interrupt 2 3h - ICSSG2 Host Interrupt 2" "0,1,2,3"
rgroup.long 0x41A0++0x3
line.long 0x00 "CTRLMMR_EQEP_STAT,Displays status of EQEP modules."
bitfld.long 0x00 2. " PHASE_ERR2        ,eQEP2 Phase error status" "0,1"
bitfld.long 0x00 1. "         PHASE_ERR1        ,eQEP1 Phase error status" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PHASE_ERR0        ,eQEP0 Phase error status" "0,1"
group.long 0x41E0++0x3
line.long 0x00 "CTRLMMR_OLDI_DAT0_IO_CTRL,Controls the characteristics of the OLDI DATA IO."
bitfld.long 0x00 24.--27. " SPAREOUT          ,Buffer spare status outputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "        SPAREIN           ,Buffer spare control inputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 16. " RX_EN             ,Enable differential receiver (active high)" "0,1"
bitfld.long 0x00 8. "         PWRDN_TX          ,Powerdown transmitter (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 6. " HIZ_DIS           ,Disable Hi-Z on power down (pwrdn_tx = 1)" "0,1"
bitfld.long 0x00 5. "         IN_TERM_EN        ,Enable internal termination (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 4. " I_INT_EN          ,Both internal and external termination used" "0,1"
bitfld.long 0x00 2. "         BOOSTA_EN         ,Enable fast rise/fall (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SUB_LVDS_EN       ,Common mode Voltage selection" "0,1"
bitfld.long 0x00 0. "         VODLOW_EN         ,Reduced differential output enable (active high)" "0,1"
group.long 0x41E4++0x3
line.long 0x00 "CTRLMMR_OLDI_DAT1_IO_CTRL,Controls the characteristics of the OLDI DATA IO."
bitfld.long 0x00 24.--27. " SPAREOUT          ,Buffer spare status outputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "        SPAREIN           ,Buffer spare control inputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 16. " RX_EN             ,Enable differential receiver (active high)" "0,1"
bitfld.long 0x00 8. "         PWRDN_TX          ,Powerdown transmitter (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 6. " HIZ_DIS           ,Disable Hi-Z on power down (pwrdn_tx = 1)" "0,1"
bitfld.long 0x00 5. "         IN_TERM_EN        ,Enable internal termination (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 4. " I_INT_EN          ,Both internal and external termination used" "0,1"
bitfld.long 0x00 2. "         BOOSTA_EN         ,Enable fast rise/fall (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SUB_LVDS_EN       ,Common mode Voltage selection" "0,1"
bitfld.long 0x00 0. "         VODLOW_EN         ,Reduced differential output enable (active high)" "0,1"
group.long 0x41E8++0x3
line.long 0x00 "CTRLMMR_OLDI_DAT2_IO_CTRL,Controls the characteristics of the OLDI DATA IO."
bitfld.long 0x00 24.--27. " SPAREOUT          ,Buffer spare status outputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "        SPAREIN           ,Buffer spare control inputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 16. " RX_EN             ,Enable differential receiver (active high)" "0,1"
bitfld.long 0x00 8. "         PWRDN_TX          ,Powerdown transmitter (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 6. " HIZ_DIS           ,Disable Hi-Z on power down (pwrdn_tx = 1)" "0,1"
bitfld.long 0x00 5. "         IN_TERM_EN        ,Enable internal termination (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 4. " I_INT_EN          ,Both internal and external termination used" "0,1"
bitfld.long 0x00 2. "         BOOSTA_EN         ,Enable fast rise/fall (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SUB_LVDS_EN       ,Common mode Voltage selection" "0,1"
bitfld.long 0x00 0. "         VODLOW_EN         ,Reduced differential output enable (active high)" "0,1"
group.long 0x41EC++0x3
line.long 0x00 "CTRLMMR_OLDI_DAT3_IO_CTRL,Controls the characteristics of the OLDI DATA IO."
bitfld.long 0x00 24.--27. " SPAREOUT          ,Buffer spare status outputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "        SPAREIN           ,Buffer spare control inputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 16. " RX_EN             ,Enable differential receiver (active high)" "0,1"
bitfld.long 0x00 8. "         PWRDN_TX          ,Powerdown transmitter (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 6. " HIZ_DIS           ,Disable Hi-Z on power down (pwrdn_tx = 1)" "0,1"
bitfld.long 0x00 5. "         IN_TERM_EN        ,Enable internal termination (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 4. " I_INT_EN          ,Both internal and external termination used" "0,1"
bitfld.long 0x00 2. "         BOOSTA_EN         ,Enable fast rise/fall (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SUB_LVDS_EN       ,Common mode Voltage selection" "0,1"
bitfld.long 0x00 0. "         VODLOW_EN         ,Reduced differential output enable (active high)" "0,1"
group.long 0x41F0++0x3
line.long 0x00 "CTRLMMR_OLDI_CLK_IO_CTRL,Controls the characteristics of the OLDI CLK IO."
bitfld.long 0x00 24.--27. " SPAREOUT          ,Buffer spare status outputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "        SPAREIN           ,Buffer spare control inputs (not used)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 16. " RX_EN             ,Enable differential receiver (active high)" "0,1"
bitfld.long 0x00 8. "         PWRDN_TX          ,Powerdown transmitter (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 6. " HIZ_DIS           ,Disable Hi-Z on power down (pwrdn_tx = 1)" "0,1"
bitfld.long 0x00 5. "         IN_TERM_EN        ,Enable internal termination (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 4. " I_INT_EN          ,Both internal and external termination used" "0,1"
bitfld.long 0x00 2. "         BOOSTA_EN         ,Enable fast rise/fall (active high)" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SUB_LVDS_EN       ,Common mode Voltage selection" "0,1"
bitfld.long 0x00 0. "         VODLOW_EN         ,Reduced differential output enable (active high)" "0,1"
group.long 0x4200++0x3
line.long 0x00 "CTRLMMR_TIMER0_CTRL,Controls TIMER0 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4204++0x3
line.long 0x00 "CTRLMMR_TIMER1_CTRL,Controls TIMER1 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER1 to TIMER0" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4208++0x3
line.long 0x00 "CTRLMMR_TIMER2_CTRL,Controls TIMER2 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x420C++0x3
line.long 0x00 "CTRLMMR_TIMER3_CTRL,Controls TIMER3 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER3 to TIMER2" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4210++0x3
line.long 0x00 "CTRLMMR_TIMER4_CTRL,Controls TIMER4 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4214++0x3
line.long 0x00 "CTRLMMR_TIMER5_CTRL,Controls TIMER5 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER5 to TIMER4" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4218++0x3
line.long 0x00 "CTRLMMR_TIMER6_CTRL,Controls TIMER6 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x421C++0x3
line.long 0x00 "CTRLMMR_TIMER7_CTRL,Controls TIMER7 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER7 to TIMER6" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4220++0x3
line.long 0x00 "CTRLMMR_TIMER8_CTRL,Controls TIMER8 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4224++0x3
line.long 0x00 "CTRLMMR_TIMER9_CTRL,Controls TIMER9 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER9 to TIMER8" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4228++0x3
line.long 0x00 "CTRLMMR_TIMER10_CTRL,Controls TIMER10 operation."
bitfld.long 0x00 0.--2. " CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER10 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x422C++0x3
line.long 0x00 "CTRLMMR_TIMER11_CTRL,Controls TIMER11 operation."
bitfld.long 0x00 8. " CASCADE_EN        ,Enables cascading of TIMER11 to TIMER10" "0,1"
bitfld.long 0x00 0.--2. "         CAP_SEL           ,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER11 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h - Use TIMERIO5 pin 6h - Use TIMERIO6 pin 7h - Use TIMERIO7 pin" "0,1,2,3,4,5,6,7"
group.long 0x4280++0x3
line.long 0x00 "CTRLMMR_TIMERIO0_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO0 output 0h - TIMERIO0 is driven by TIMER0 output 1h - TIMERIO0 is driven by TIMER1 output 2h - TIMERIO0 is driven by TIMER2 output 3h - TIMERIO0 is driven by TIMER3 output 4h - TIMERIO0 is driven by TIMER4 output 5h - TIMERIO0 is driven by TIMER5 output 6h - TIMERIO0 is driven by TIMER6 output 7h - TIMERIO0 is driven by TIMER7 output 8h - TIMERIO0 is driven by TIMER8 output 9h - TIMERIO0 is driven by TIMER9 output Ah - TIMERIO0 is driven by TIMER10 output Bh - TIMERIO0 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4284++0x3
line.long 0x00 "CTRLMMR_TIMERIO1_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO1 output 0h - TIMERIO1 is driven by TIMER0 output 1h - TIMERIO1 is driven by TIMER1 output 2h - TIMERIO1 is driven by TIMER2 output 3h - TIMERIO1 is driven by TIMER3 output 4h - TIMERIO1 is driven by TIMER4 output 5h - TIMERIO1 is driven by TIMER5 output 6h - TIMERIO1 is driven by TIMER6 output 7h - TIMERIO1 is driven by TIMER7 output 8h - TIMERIO1 is driven by TIMER8 output 9h - TIMERIO1 is driven by TIMER9 output Ah - TIMERIO1 is driven by TIMER10 output Bh - TIMERIO1 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4288++0x3
line.long 0x00 "CTRLMMR_TIMERIO2_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO2 output 0h - TIMERIO2 is driven by TIMER0 output 1h - TIMERIO2 is driven by TIMER1 output 2h - TIMERIO2 is driven by TIMER2 output 3h - TIMERIO2 is driven by TIMER3 output 4h - TIMERIO2 is driven by TIMER4 output 5h - TIMERIO2 is driven by TIMER5 output 6h - TIMERIO2 is driven by TIMER6 output 7h - TIMERIO2 is driven by TIMER7 output 8h - TIMERIO2 is driven by TIMER8 output 9h - TIMERIO2 is driven by TIMER9 output Ah - TIMERIO2 is driven by TIMER10 output Bh - TIMERIO2 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x428C++0x3
line.long 0x00 "CTRLMMR_TIMERIO3_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO3 output 0h - TIMERIO3 is driven by TIMER0 output 1h - TIMERIO3 is driven by TIMER1 output 2h - TIMERIO3 is driven by TIMER2 output 3h - TIMERIO3 is driven by TIMER3 output 4h - TIMERIO3 is driven by TIMER4 output 5h - TIMERIO3 is driven by TIMER5 output 6h - TIMERIO3 is driven by TIMER6 output 7h - TIMERIO3 is driven by TIMER7 output 8h - TIMERIO3 is driven by TIMER8 output 9h - TIMERIO3 is driven by TIMER9 output Ah - TIMERIO3 is driven by TIMER10 output Bh - TIMERIO3 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4290++0x3
line.long 0x00 "CTRLMMR_TIMERIO4_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO4 output 0h - TIMERIO4 is driven by TIMER0 output 1h - TIMERIO4 is driven by TIMER1 output 2h - TIMERIO4 is driven by TIMER2 output 3h - TIMERIO4 is driven by TIMER3 output 4h - TIMERIO4 is driven by TIMER4 output 5h - TIMERIO4 is driven by TIMER5 output 6h - TIMERIO4 is driven by TIMER6 output 7h - TIMERIO4 is driven by TIMER7 output 8h - TIMERIO4 is driven by TIMER8 output 9h - TIMERIO4 is driven by TIMER9 output Ah - TIMERIO4 is driven by TIMER10 output Bh - TIMERIO4 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4294++0x3
line.long 0x00 "CTRLMMR_TIMERIO5_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO5 output 0h - TIMERIO5 is driven by TIMER0 output 1h - TIMERIO5 is driven by TIMER1 output 2h - TIMERIO5 is driven by TIMER2 output 3h - TIMERIO5 is driven by TIMER3 output 4h - TIMERIO5 is driven by TIMER4 output 5h - TIMERIO5 is driven by TIMER5 output 6h - TIMERIO5 is driven by TIMER6 output 7h - TIMERIO5 is driven by TIMER7 output 8h - TIMERIO5 is driven by TIMER8 output 9h - TIMERIO5 is driven by TIMER9 output Ah - TIMERIO5 is driven by TIMER10 output Bh - TIMERIO5 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4298++0x3
line.long 0x00 "CTRLMMR_TIMERIO6_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO6 output 0h - TIMERIO6 is driven by TIMER0 output 1h - TIMERIO6 is driven by TIMER1 output 2h - TIMERIO6 is driven by TIMER2 output 3h - TIMERIO6 is driven by TIMER3 output 4h - TIMERIO6 is driven by TIMER4 output 5h - TIMERIO6 is driven by TIMER5 output 6h - TIMERIO6 is driven by TIMER6 output 7h - TIMERIO6 is driven by TIMER7 output 8h - TIMERIO6 is driven by TIMER8 output 9h - TIMERIO6 is driven by TIMER9 output Ah - TIMERIO6 is driven by TIMER10 output Bh - TIMERIO6 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x429C++0x3
line.long 0x00 "CTRLMMR_TIMERIO7_CTRL,Controls Timer IO muxing."
bitfld.long 0x00 0.--3. " OUT_SEL           ,Selects the source of the TIMERIO7 output 0h - TIMERIO7 is driven by TIMER0 output 1h - TIMERIO7 is driven by TIMER1 output 2h - TIMERIO7 is driven by TIMER2 output 3h - TIMERIO7 is driven by TIMER3 output 4h - TIMERIO7 is driven by TIMER4 output 5h - TIMERIO7 is driven by TIMER5 output 6h - TIMERIO7 is driven by TIMER6 output 7h - TIMERIO7 is driven by TIMER7 output 8h - TIMERIO7 is driven by TIMER8 output 9h - TIMERIO7 is driven by TIMER9 output Ah - TIMERIO7 is driven by TIMER10 output Bh - TIMERIO7 is driven by TIMER11 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4404++0x3
line.long 0x00 "CTRLMMR_SPARE_CTRL1,"
bitfld.long 0x00 4. " CORE_BGAP_SEL     ,Core bandgap trim source select" "0,1"
bitfld.long 0x00 0. "         USB1_PIPE3_CLKSEL ,USB1 pipe3_txb_clk clock select" "0,1"
group.long 0x4800++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB0_W0,Software writable USB xHCI Transfer Request Block (TRB) 0 word0 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
group.long 0x4804++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB0_W1,Software writable USB xHCI Transfer Request Block (TRB) 0 word1 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
group.long 0x4808++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB0_W2,Software writable USB xHCI Transfer Request Block (TRB) 0 word2 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
group.long 0x480C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB0_W3,Software writable USB xHCI Transfer Request Block (TRB) 0 word3 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
group.long 0x4810++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB1_W0,Software writable USB xHCI Transfer Request Block (TRB) 1 word0 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
group.long 0x4814++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB1_W1,Software writable USB xHCI Transfer Request Block (TRB) 1 word1 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
group.long 0x4818++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB1_W2,Software writable USB xHCI Transfer Request Block (TRB) 1 word2 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
group.long 0x481C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB1_W3,Software writable USB xHCI Transfer Request Block (TRB) 1 word3 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
group.long 0x4820++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB2_W0,Software writable USB xHCI Transfer Request Block (TRB) 2 word0 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
group.long 0x4824++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB2_W1,Software writable USB xHCI Transfer Request Block (TRB) 2 word1 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
group.long 0x4828++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB2_W2,Software writable USB xHCI Transfer Request Block (TRB) 2 word2 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
group.long 0x482C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_TRB2_W3,Software writable USB xHCI Transfer Request Block (TRB) 2 word3 for the SoC trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
rgroup.long 0x4840++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB0_W0,xHC readable USB xHCI Transfer Request Block (TRB) 0 word0 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
rgroup.long 0x4844++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB0_W1,xHC readable USB xHCI Transfer Request Block (TRB) 0 word1 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
rgroup.long 0x4848++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB0_W2,xHC readable USB xHCI Transfer Request Block (TRB) 0 word2 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
rgroup.long 0x484C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB0_W3,xHC readable USB xHCI Transfer Request Block (TRB) 0 word3 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
rgroup.long 0x4850++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB1_W0,xHC readable USB xHCI Transfer Request Block (TRB) 1 word0 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
rgroup.long 0x4854++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB1_W1,xHC readable USB xHCI Transfer Request Block (TRB) 1 word1 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
rgroup.long 0x4858++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB1_W2,xHC readable USB xHCI Transfer Request Block (TRB) 1 word2 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
rgroup.long 0x485C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB1_W3,xHC readable USB xHCI Transfer Request Block (TRB) 1 word3 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
rgroup.long 0x4860++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB2_W0,xHC readable USB xHCI Transfer Request Block (TRB) 2 word0 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
rgroup.long 0x4864++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB2_W1,xHC readable USB xHCI Transfer Request Block (TRB) 2 word1 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
rgroup.long 0x4868++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB2_W2,xHC readable USB xHCI Transfer Request Block (TRB) 2 word2 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
rgroup.long 0x486C++0x3
line.long 0x00 "CTRLMMR_SOCTBR_SHDW_TRB2_W3,xHC readable USB xHCI Transfer Request Block (TRB) 2 word3 for the SoC trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this register are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
group.long 0x4880++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB0_W0,Software writable USB xHCI Transfer Request Block (TRB) 0 word0 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
group.long 0x4884++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB0_W1,Software writable USB xHCI Transfer Request Block (TRB) 0 word1 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
group.long 0x4888++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB0_W2,Software writable USB xHCI Transfer Request Block (TRB) 0 word2 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
group.long 0x488C++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB0_W3,Software writable USB xHCI Transfer Request Block (TRB) 0 word3 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
group.long 0x4890++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB1_W0,Software writable USB xHCI Transfer Request Block (TRB) 1 word0 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
group.long 0x4894++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB1_W1,Software writable USB xHCI Transfer Request Block (TRB) 1 word1 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
group.long 0x4898++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB1_W2,Software writable USB xHCI Transfer Request Block (TRB) 1 word2 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
group.long 0x489C++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB1_W3,Software writable USB xHCI Transfer Request Block (TRB) 1 word3 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
group.long 0x48A0++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB2_W0,Software writable USB xHCI Transfer Request Block (TRB) 2 word0 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
group.long 0x48A4++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB2_W1,Software writable USB xHCI Transfer Request Block (TRB) 2 word1 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
group.long 0x48A8++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB2_W2,Software writable USB xHCI Transfer Request Block (TRB) 2 word2 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
group.long 0x48AC++0x3
line.long 0x00 "CTRLMMR_CCTBR_TRB2_W3,Software writable USB xHCI Transfer Request Block (TRB) 2 word3 for the Compute Cluster trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
rgroup.long 0x48C0++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB0_W0,xHC readable USB xHCI Transfer Request Block (TRB) 0 word0 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
rgroup.long 0x48C4++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB0_W1,xHC readable USB xHCI Transfer Request Block (TRB) 0 word1 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
rgroup.long 0x48C8++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB0_W2,xHC readable USB xHCI Transfer Request Block (TRB) 0 word2 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
rgroup.long 0x48CC++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB0_W3,xHC readable USB xHCI Transfer Request Block (TRB) 0 word3 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
rgroup.long 0x48D0++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB1_W0,xHC readable USB xHCI Transfer Request Block (TRB) 1 word0 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
rgroup.long 0x48D4++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB1_W1,xHC readable USB xHCI Transfer Request Block (TRB) 1 word1 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
rgroup.long 0x48D8++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB1_W2,xHC readable USB xHCI Transfer Request Block (TRB) 1 word2 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
rgroup.long 0x48DC++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB1_W3,xHC readable USB xHCI Transfer Request Block (TRB) 1 word3 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
rgroup.long 0x48E0++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB2_W0,xHC readable USB xHCI Transfer Request Block (TRB) 2 word0 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
rgroup.long 0x48E4++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB2_W1,xHC readable USB xHCI Transfer Request Block (TRB) 2 word1 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
rgroup.long 0x48E8++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB2_W2,xHC readable USB xHCI Transfer Request Block (TRB) 2 word2 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
rgroup.long 0x48EC++0x3
line.long 0x00 "CTRLMMR_CCTBR_SHDW_TRB2_W3,xHC readable USB xHCI Transfer Request Block (TRB) 2 word3 for the Compute Cluster trace buffer transfer descriptor (TD). Reflects the value contained in the corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
group.long 0x4900++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB0_W0,Software writable USB xHCI Transfer Request Block (TRB) 0 word0 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
group.long 0x4904++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB0_W1,Software writable USB xHCI Transfer Request Block (TRB) 0 word1 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
group.long 0x4908++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB0_W2,Software writable USB xHCI Transfer Request Block (TRB) 0 word2 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
group.long 0x490C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB0_W3,Software writable USB xHCI Transfer Request Block (TRB) 0 word3 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
group.long 0x4910++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB1_W0,Software writable USB xHCI Transfer Request Block (TRB) 1 word0 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
group.long 0x4914++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB1_W1,Software writable USB xHCI Transfer Request Block (TRB) 1 word1 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
group.long 0x4918++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB1_W2,Software writable USB xHCI Transfer Request Block (TRB) 1 word2 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
group.long 0x491C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB1_W3,Software writable USB xHCI Transfer Request Block (TRB) 1 word3 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
group.long 0x4920++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB2_W0,Software writable USB xHCI Transfer Request Block (TRB) 2 word0 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
group.long 0x4924++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB2_W1,Software writable USB xHCI Transfer Request Block (TRB) 2 word1 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
group.long 0x4928++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB2_W2,Software writable USB xHCI Transfer Request Block (TRB) 2 word2 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
group.long 0x492C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_TRB2_W3,Software writable USB xHCI Transfer Request Block (TRB) 2 word3 for the MCU trace buffer transfer descriptor (TD). There are three TRBs in each TD. Each TRB consists of 4 consecutive 32-bit words (W[3:0]) defining the buffer address, buffer size and other control, as per the xHCI definition."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
rgroup.long 0x4940++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB0_W0,xHC readable USB xHCI Transfer Request Block (TRB) 0 word0 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 0 Word0"
rgroup.long 0x4944++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB0_W1,xHC readable USB xHCI Transfer Request Block (TRB) 0 word1 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 0 Word1"
rgroup.long 0x4948++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB0_W2,xHC readable USB xHCI Transfer Request Block (TRB) 0 word2 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 0 Word2"
rgroup.long 0x494C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB0_W3,xHC readable USB xHCI Transfer Request Block (TRB) 0 word3 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 0 Word3"
rgroup.long 0x4950++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB1_W0,xHC readable USB xHCI Transfer Request Block (TRB) 1 word0 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 1 Word0"
rgroup.long 0x4954++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB1_W1,xHC readable USB xHCI Transfer Request Block (TRB) 1 word1 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 1 Word1"
rgroup.long 0x4958++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB1_W2,xHC readable USB xHCI Transfer Request Block (TRB) 1 word2 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 1 Word2"
rgroup.long 0x495C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB1_W3,xHC readable USB xHCI Transfer Request Block (TRB) 1 word3 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 1 Word3"
rgroup.long 0x4960++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB2_W0,xHC readable USB xHCI Transfer Request Block (TRB) 2 word0 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W0            ,xHCI TRB 2 Word0"
rgroup.long 0x4964++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB2_W1,xHC readable USB xHCI Transfer Request Block (TRB) 2 word1 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W1            ,xHCI TRB 2 Word1"
rgroup.long 0x4968++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB2_W2,xHC readable USB xHCI Transfer Request Block (TRB) 2 word2 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W2            ,xHCI TRB 2 Word2"
rgroup.long 0x496C++0x3
line.long 0x00 "CTRLMMR_MCUTBR_SHDW_TRB2_W3,xHC readable USB xHCI Transfer Request Block (TRB) 2 word3 for the MCU trace buffer transfer descriptor (TD). Register reflects the value contained in its corresponding register. Writes to this registers are silently ignored (no error generated) allowing the xHC to continuously use the descriptor without software intervention to re-initialize the TRBs."
hexmask.long 0x00 0.--31. 1. " TRB_W3            ,xHCI TRB 2 Word3"
group.long 0x5008++0x3
line.long 0x00 "CTRLMMR_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x500C++0x3
line.long 0x00 "CTRLMMR_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x8000++0x3
line.long 0x00 "CTRLMMR_OBSCLK_CTRL,This register controls which internal clock is made observable on the OBSCLK output pin."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         CLK_DIV           ,OBSCLK pin output divider"
textline "                                      "
bitfld.long 0x00 0.--3. " CLK_SEL           ,OBSCLK pin output clock source selection 0h - HFOSC1_CLK 1h - HFOSC0_CLK 2h - MAIN_PLL 3h - PER0_PLL 4h - LFOSC_CLKOUT 5h - PER1_PLL 6h - DSS_PLL 7h - ARM0_PLL 8h - DDR_PLL 9h - CPSW_PLL Ah - PLLCTRL_OBSCLK Bh - ARM1_PLL Ch - cpts_genf2 Dh - cpts_genf3 Eh - cpts_genf4 Fh - cpts_genf5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8020++0x3
line.long 0x00 "CTRLMMR_SERDES0_REFCLK_SEL,Selects the source of the SERDES0 reference clock."
bitfld.long 0x00 0.--1. " CLK_SEL           ,SERDES0 Internal REFCLK source select mux control 0h - HFOSC0_CLK 1h - HFOSC1_OUT 2h - MAIN_PLL_CLKOUT 3h - MAINHSDIV_CLKOUT4" "0,1,2,3"
group.long 0x8024++0x3
line.long 0x00 "CTRLMMR_SERDES1_REFCLK_SEL,Selects the source of the SERDES1 reference clock."
bitfld.long 0x00 0.--1. " CLK_SEL           ,SERDES1 Internal REFCLK source select mux control 0h - HFOSC0_CLK 1h - HFOSC1_OUT 2h - MAIN_PLL_CLKOUT 3h - MAINHSDIV_CLKOUT4" "0,1,2,3"
group.long 0x8030++0x3
line.long 0x00 "CTRLMMR_GTC_CLKSEL,Selects the timebase clock source for the Global Timebase Counter."
bitfld.long 0x00 0.--2. " CLK_SEL           ,Selects the GTC timebase clock source 0h - CPSWHSDIV_CLKOUT2 1h - MAINHSDIV_CLKOUT3 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - PCIE0_TXI0_CLK 7h - PCIE1_TXI0_CLK" "0,1,2,3,4,5,6,7"
group.long 0x8038++0x3
line.long 0x00 "CTRLMMR_DEBUG_CLKSEL,Selects the Debug trace clock source."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--12. "         CLK_DIV           ,Selects the programmable divider value for the trace clock source for the Debug Subsystem. The clock frequency is PER0_PLL_CLKOUT / (clk_div+1) Supports divide values of 1 to 32 Default is /3. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x803C++0x3
line.long 0x00 "CTRLMMR_EFUSE_CLKSEL,Selects the functional clock source for the MAIN domain eFuse Controller."
bitfld.long 0x00 0. " CLK_SEL           ,Selects the clock source 0h - EFUSE_CLK (from WKUP_PRC) 1h - MAIN_SYSCLK0 / 4" "0,1"
group.long 0x8040++0x3
line.long 0x00 "CTRLMMR_ICSSG0_CLKSEL,Selects the functional clock source for ICSS-G0."
bitfld.long 0x00 16.--18. " IEP_CLKSEL        ,Selects the ICSSG0 IEP clock source 0h - CPSWHSDIV_CLKOUT2 1h - MAINHSDIV_CLKOUT3 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - PCIE0_TXI0_CLK 7h - PCIE1_TXI0_CLK" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         CORE_CLKSEL       ,Selects the ICSSG0 functional clock source 0h - PER1HSDIV_CLKOUT1 1h - CPSWHSDIV_CLKOUT2" "0,1"
group.long 0x8044++0x3
line.long 0x00 "CTRLMMR_ICSSG1_CLKSEL,Selects the functional clock source for ICSS-G1."
bitfld.long 0x00 16.--18. " IEP_CLKSEL        ,Selects the ICSSG1 IEP clock source 0h - CPSWHSDIV_CLKOUT2 1h - MAINHSDIV_CLKOUT3 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - PCIE0_TXI0_CLK 7h - PCIE1_TXI0_CLK" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         CORE_CLKSEL       ,Selects the ICSSG1 functional clock source 0h - PER1HSDIV_CLKOUT1 1h - CPSWHSDIV_CLKOUT2" "0,1"
group.long 0x8048++0x3
line.long 0x00 "CTRLMMR_ICSSG2_CLKSEL,Selects the functional clock source for ICSS-G2."
bitfld.long 0x00 16.--18. " IEP_CLKSEL        ,Selects the ICSSG2 IEP clock source 0h - CPSWHSDIV_CLKOUT2 1h - MAINHSDIV_CLKOUT3 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - PCIE0_TXI0_CLK 7h - PCIE1_TXI0_CLK" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         CORE_CLKSEL       ,Selects the ICSSG2 functional clock source 0h - PER1HSDIV_CLKOUT1 1h - CPSWHSDIV_CLKOUT2" "0,1"
group.long 0x8060++0x3
line.long 0x00 "CTRLMMR_MCASP0_CLKSEL,Selects the functional clock source for McASP0."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--11. "         CLK_DIV           ,Selects the programmable divider value for the ARM1_PLL_CLKOUT clock source for McASP0 The clock frequency is ARM1_PLL_CLKOUT / (clk_div+1) Supports divide values of 1 to 16 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0.--2. " AUXCLK_SEL        ,Selects the McASP0 auxclk clock source Reserved values default to HFOSC1_CLK 0h - HFOSC1_CLK 1h - HFOSC0_CLK 2h - MCU_EXT_REFCLK0 3h - PER1HSDIV_CLKOUT2 4h - Divided ARM1_PLL_CLKOUT (see clkdiv) 5h - EXT_REFCLK1 6h - reserved (HFOSC1_CLK) 7h - reserved (HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
group.long 0x8064++0x3
line.long 0x00 "CTRLMMR_MCASP1_CLKSEL,Selects the functional clock source for McASP1."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--11. "         CLK_DIV           ,Selects the programmable divider value for the ARM1_PLL_CLKOUT clock source for McASP1 The clock frequency is ARM1_PLL_CLKOUT / (clk_div+1) Supports divide values of 1 to 16 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0.--2. " AUXCLK_SEL        ,Selects the McASP1 auxclk clock source Reserved values default to HFOSC1_CLK 0h - HFOSC1_CLK 1h - HFOSC0_CLK 2h - MCU_EXT_REFCLK0 3h - PER1HSDIV_CLKOUT2 4h - Divided ARM1_PLL_CLKOUT (see clkdiv) 5h - EXT_REFCLK1 6h - reserved (HFOSC1_CLK) 7h - reserved (HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
group.long 0x8068++0x3
line.long 0x00 "CTRLMMR_MCASP2_CLKSEL,Selects the functional clock source for McASP2."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--11. "         CLK_DIV           ,Selects the programmable divider value for the ARM1_PLL_CLKOUT clock source for McASP2 The clock frequency is ARM1_PLL_CLKOUT / (clk_div+1) Supports divide values of 1 to 16 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0.--2. " AUXCLK_SEL        ,Selects the McASP2 auxclk clock source Reserved values default to HFOSC1_CLK 0h - HFOSC1_CLK 1h - HFOSC0_CLK 2h - MCU_EXT_REFCLK0 3h - PER1HSDIV_CLKOUT2 4h - Divided ARM1_PLL_CLKOUT (see clkdiv) 5h - EXT_REFCLK1 6h - reserved (HFOSC1_CLK) 7h - reserved (HFOSC1_CLK)" "0,1,2,3,4,5,6,7"
group.long 0x80B0++0x3
line.long 0x00 "CTRLMMR_OLDI_CLKSEL,Selects the functional clock source for OLDI."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--12. "         CLK_DIV           ,Selects the programmable divide value for the OLDI PLL input." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80C0++0x3
line.long 0x00 "CTRLMMR_DSS_CLKSEL,Selects DSS clock sources."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--12. "         CLK_DIV1          ,Selects the programmable divide value for the DSS DPI_1_IN_CLK mux input. The clock frequency is DSS_PLL_CLKOUT / (clk_div1+1) Supports divide values of 1 (default) to 32. To load the new divider value the clk_div_ld bit must be cleared and then set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 0.--1. " DPI1_CLKSEL       ,Selects the clock source for DPI1 (parallel output) 0h - DPI_0_IN_CLK 1h - DSS0EXTPCLKIN (pin) 2h - Divided DSS_PLL_CLKOUT (see clk_div1) 3h - 0'" "0,1,2,3"
group.long 0x80D0++0x3
line.long 0x00 "CTRLMMR_GPMC_CLKSEL,Selects the bus and functional clock source for the GPMC module. This allows the GPMC to run asynchronously to the bus fabric in order to optimize parallel port performance."
bitfld.long 0x00 0.--1. " CLK_SEL           ,Selects the GPMC clock source" "0,1,2,3"
group.long 0x80E0++0x3
line.long 0x00 "CTRLMMR_USB0_CLKSEL,Selects the functional clock sources for USB0."
bitfld.long 0x00 0. " REFCLK_SEL        ,Selects the clock source for the USB0 ref_clk." "0,1"
group.long 0x80E4++0x3
line.long 0x00 "CTRLMMR_USB1_CLKSEL,Selects the functional clock sources for USB1."
bitfld.long 0x00 0. " REFCLK_SEL        ,Selects the clock source for the USB1 ref_clk." "0,1"
group.long 0x8100++0x3
line.long 0x00 "CTRLMMR_TIMER0_CLKSEL,Timer0 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8104++0x3
line.long 0x00 "CTRLMMR_TIMER1_CLKSEL,Timer1 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8108++0x3
line.long 0x00 "CTRLMMR_TIMER2_CLKSEL,Timer2 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x810C++0x3
line.long 0x00 "CTRLMMR_TIMER3_CLKSEL,Timer3 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8110++0x3
line.long 0x00 "CTRLMMR_TIMER4_CLKSEL,Timer4 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8114++0x3
line.long 0x00 "CTRLMMR_TIMER5_CLKSEL,Timer5 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8118++0x3
line.long 0x00 "CTRLMMR_TIMER6_CLKSEL,Timer6 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x811C++0x3
line.long 0x00 "CTRLMMR_TIMER7_CLKSEL,Timer7 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8120++0x3
line.long 0x00 "CTRLMMR_TIMER8_CLKSEL,Timer8 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8124++0x3
line.long 0x00 "CTRLMMR_TIMER9_CLKSEL,Timer9 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8128++0x3
line.long 0x00 "CTRLMMR_TIMER10_CLKSEL,Timer10 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x812C++0x3
line.long 0x00 "CTRLMMR_TIMER11_CLKSEL,Timer11 functional clock selection control."
bitfld.long 0x00 0.--3. " CLK_SEL           ,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) 0h - HFOSC0_CLK 1h - HFOSC1_CLK 2h - MAINHSDIV_CLKOUT3 3h - CLK_12M_RC 4h - CPSWHSDIV_CLKOUT2 5h - MCU_EXT_REFCLK0 6h - EXT_REFCLK1 7h - LFOSC_CLKOUT 8h - CPTS_RFT_CLK (pin) 9h - PER1HSDIV_CLKOUT2 Ah - PER0_PLL_CLKOUT_DIV5 Bh - CLK_32K_RC Ch - CPTS_GENF2 Dh - CPTS_GENF3 Eh - CPTS_GENF4 Fh - CPTS_GENF5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x81C0++0x3
line.long 0x00 "CTRLMMR_USART0_CLK_CTRL,Selects the clock divider of the USART0 functional clock."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 0.--4. "         CLK_DIV           ,Selects the clock divider value. Supports divide values of 1 to 32 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4 4h - Divide by 5 5h - Divide by 6 6h - Divide by 7 7h - Divide by 8 8h - Divide by 9 9h - Divide by 10 Ah - Divide by 11 Bh - Divide by 12 Ch - Divide by 13 Dh - Divide by 14 Eh - Divide by 15 Fh - Divide by 16 10h - Divide by 17 11h - Divide by 18 12h - Divide by 19 13h - Divide by 20 14h - Divide by 21 15h - Divide by 22 16h - Divide by 23 17h - Divide by 24 18h - Divide by 25 19h - Divide by 26 1Ah - Divide by 27 1Bh - Divide by 28 1Ch - Divide by 29 1Dh - Divide by 30 1Eh - Divide by 31 1Fh - Divide by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x81C4++0x3
line.long 0x00 "CTRLMMR_USART1_CLK_CTRL,Selects the clock divider of the USART1 functional clock."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 0.--4. "         CLK_DIV           ,Selects the clock divider value. Supports divide values of 1 to 32 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4 4h - Divide by 5 5h - Divide by 6 6h - Divide by 7 7h - Divide by 8 8h - Divide by 9 9h - Divide by 10 Ah - Divide by 11 Bh - Divide by 12 Ch - Divide by 13 Dh - Divide by 14 Eh - Divide by 15 Fh - Divide by 16 10h - Divide by 17 11h - Divide by 18 12h - Divide by 19 13h - Divide by 20 14h - Divide by 21 15h - Divide by 22 16h - Divide by 23 17h - Divide by 24 18h - Divide by 25 19h - Divide by 26 1Ah - Divide by 27 1Bh - Divide by 28 1Ch - Divide by 29 1Dh - Divide by 30 1Eh - Divide by 31 1Fh - Divide by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x81C8++0x3
line.long 0x00 "CTRLMMR_USART2_CLK_CTRL,Selects the clock divider of the USART2 functional clock."
bitfld.long 0x00 16. " CLK_DIV_LD        ,Load the output divider value" "0,1"
bitfld.long 0x00 0.--4. "         CLK_DIV           ,Selects the clock divider value. Supports divide values of 1 to 32 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4 4h - Divide by 5 5h - Divide by 6 6h - Divide by 7 7h - Divide by 8 8h - Divide by 9 9h - Divide by 10 Ah - Divide by 11 Bh - Divide by 12 Ch - Divide by 13 Dh - Divide by 14 Eh - Divide by 15 Fh - Divide by 16 10h - Divide by 17 11h - Divide by 18 12h - Divide by 19 13h - Divide by 20 14h - Divide by 21 15h - Divide by 22 16h - Divide by 23 17h - Divide by 24 18h - Divide by 25 19h - Divide by 26 1Ah - Divide by 27 1Bh - Divide by 28 1Ch - Divide by 29 1Dh - Divide by 30 1Eh - Divide by 31 1Fh - Divide by 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x9008++0x3
line.long 0x00 "CTRLMMR_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x900C++0x3
line.long 0x00 "CTRLMMR_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers"
group.long 0xC300++0x3
line.long 0x00 "CTRLMMR_FUSE_CRC_CTRL,Controls MAIN efuse chain CRC calculation."
bitfld.long 0x00 5. " CRC_EN_5          ,Enable eFuse CRC calculation for chain 5" "0,1"
bitfld.long 0x00 4. "         CRC_EN_4          ,Enable eFuse CRC calculation for chain 4" "0,1"
textline "                                      "
bitfld.long 0x00 3. " CRC_EN_3          ,Enable eFuse CRC calculation for chain 3" "0,1"
bitfld.long 0x00 2. "         CRC_EN_2          ,Enable eFuse CRC calculation for chain 2" "0,1"
textline "                                      "
bitfld.long 0x00 1. " CRC_EN_1          ,Enable eFuse CRC calculation for chain 1" "0,1"
rgroup.long 0xC304++0x3
line.long 0x00 "CTRLMMR_CHAIN1_CRC_FUSE,Indicates the stored CRC for MAIN fuse chain 1."
hexmask.long 0x00 0.--31. 1. " CRC               ,Stored chain CRC"
rgroup.long 0xC308++0x3
line.long 0x00 "CTRLMMR_CHAIN2_CRC_FUSE,Indicates the stored CRC for MAIN fuse chain 2."
hexmask.long 0x00 0.--31. 1. " CRC               ,Stored chain CRC"
rgroup.long 0xC30C++0x3
line.long 0x00 "CTRLMMR_CHAIN3_CRC_FUSE,Indicates the stored CRC for MAIN fuse chain 3."
hexmask.long 0x00 0.--31. 1. " CRC               ,Stored chain CRC"
rgroup.long 0xC310++0x3
line.long 0x00 "CTRLMMR_CHAIN4_CRC_FUSE,Indicates the stored CRC for MAIN fuse chain 4."
hexmask.long 0x00 0.--31. 1. " CRC               ,Stored chain CRC"
rgroup.long 0xC314++0x3
line.long 0x00 "CTRLMMR_CHAIN5_CRC_FUSE,Indicates the stored CRC for MAIN fuse chain 5."
hexmask.long 0x00 0.--31. 1. " CRC               ,Stored chain CRC"
rgroup.long 0xC320++0x3
line.long 0x00 "CTRLMMR_FUSE_CRC_STAT,Indicates status of fuse chain CRC."
bitfld.long 0x00 5. " CRC_ERR_5         ,Indicates eFuse CRC error on chain 5" "0,1"
bitfld.long 0x00 4. "         CRC_ERR_4         ,Indicates eFuse CRC error on chain 4" "0,1"
textline "                                      "
bitfld.long 0x00 3. " CRC_ERR_3         ,Indicates eFuse CRC error on chain 3" "0,1"
bitfld.long 0x00 2. "         CRC_ERR_2         ,Indicates eFuse CRC error on chain 2" "0,1"
textline "                                      "
bitfld.long 0x00 1. " CRC_ERR_1         ,Indicates eFuse CRC error on chain 1" "0,1"
rgroup.long 0xC324++0x3
line.long 0x00 "CTRLMMR_CHAIN1_CRC_CALC,Indicates the calculated CRC for MAIN fuse chain 1."
hexmask.long 0x00 0.--31. 1. " CRC               ,Calculated chain CRC"
rgroup.long 0xC328++0x3
line.long 0x00 "CTRLMMR_CHAIN2_CRC_CALC,Indicates the calculated CRC for MAIN fuse chain 2."
hexmask.long 0x00 0.--31. 1. " CRC               ,Calculated chain CRC"
rgroup.long 0xC32C++0x3
line.long 0x00 "CTRLMMR_CHAIN3_CRC_CALC,Indicates the calculated CRC for MAIN fuse chain 3."
hexmask.long 0x00 0.--31. 1. " CRC               ,Calculated chain CRC"
rgroup.long 0xC330++0x3
line.long 0x00 "CTRLMMR_CHAIN4_CRC_CALC,Indicates the calculated CRC for MAIN fuse chain 4."
hexmask.long 0x00 0.--31. 1. " CRC               ,Calculated chain CRC"
rgroup.long 0xC334++0x3
line.long 0x00 "CTRLMMR_CHAIN5_CRC_CALC,Indicates the calculated CRC for MAIN fuse chain 5."
hexmask.long 0x00 0.--31. 1. " CRC               ,Calculated chain CRC"
group.long 0xD008++0x3
line.long 0x00 "CTRLMMR_LOCK3_KICK0,Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 3 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0xD00C++0x3
line.long 0x00 "CTRLMMR_LOCK3_KICK1,Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 3 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers"
group.long 0x18030++0x3
line.long 0x00 "CTRLMMR_CORE_SRAM_LDO0_CTRL,Controls operation of the MAIN Core VD SRAM LDO0 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18034++0x3
line.long 0x00 "CTRLMMR_CORE_SRAM_LDO1_CTRL,Controls operation of the MAIN Core VD SRAM LDO1 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18038++0x3
line.long 0x00 "CTRLMMR_CORE_SRAM_LDO2_CTRL,Controls operation of the MAIN Core VD SRAM LDO2 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x1803C++0x3
line.long 0x00 "CTRLMMR_CORE_SRAM_LDO3_CTRL,Controls operation of the MAIN Core VD SRAM LDO3 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18040++0x3
line.long 0x00 "CTRLMMR_CORE_SRAM_LDO4_CTRL,Controls operation of the MAIN Core VD SRAM LDO4 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18050++0x3
line.long 0x00 "CTRLMMR_MPU0_SRAM_LDO0_CTRL,Controls operation of the MAIN MPU0 VD SRAM LDO0 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18054++0x3
line.long 0x00 "CTRLMMR_MPU0_SRAM_LDO1_CTRL,Controls operation of the MAIN MPU0 VD SRAM LDO1 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18058++0x3
line.long 0x00 "CTRLMMR_MPU1_SRAM_LDO0_CTRL,Controls operation of the MAIN MPU1 VD SRAM LDO0 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x1805C++0x3
line.long 0x00 "CTRLMMR_MPU1_SRAM_LDO1_CTRL,Controls operation of the MAIN MPU1 VD SRAM LDO1 module."
hexmask.long.word 0x00 16.--25. 1. " VSET              ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF            ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET        ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF            ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1           ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18060++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP0_CTRL,Controls operation of the MAIN Core VD Bandgap 0 Regulator."
bitfld.long 0x00 0. " BG_EN_LV          ,When set, bandgap regulator is on" "0,1"
group.long 0x18064++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP0_TRIM,Trims the MAIN Core VD Bandgap0 Regulator."
bitfld.long 0x00 16.--19. " DTRBGAPI_LOV      ,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "        DTRBGAPV_LOWV     ,Bandgap output voltage magnitude trim bits"
textline "                                      "
hexmask.long.byte 0x00 0.--7. 1. " DTRBGAPC_LOWV     ,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x18068++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP1_CTRL,Controls operation of the MAIN Core VD Bandgap 1 Regulator."
bitfld.long 0x00 0. " BG_EN_LV          ,When set, bandgap regulator is on" "0,1"
group.long 0x1806C++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP1_TRIM,Trims the MAIN Core VD Bandgap1 Regulator."
bitfld.long 0x00 16.--19. " DTRBGAPI_LOV      ,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "        DTRBGAPV_LOWV     ,Bandgap output voltage magnitude trim bits"
textline "                                      "
hexmask.long.byte 0x00 0.--7. 1. " DTRBGAPC_LOWV     ,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x18070++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP2_CTRL,Controls operation of the MAIN Core VD Bandgap 2 Regulator."
bitfld.long 0x00 0. " BG_EN_LV          ,When set, bandgap regulator is on" "0,1"
group.long 0x18074++0x3
line.long 0x00 "CTRLMMR_CORE_BANDGAP2_TRIM,Trims the MAIN Core VD Bandgap2 Regulator."
bitfld.long 0x00 16.--19. " DTRBGAPI_LOV      ,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "        DTRBGAPV_LOWV     ,Bandgap output voltage magnitude trim bits"
textline "                                      "
hexmask.long.byte 0x00 0.--7. 1. " DTRBGAPC_LOWV     ,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x19008++0x3
line.long 0x00 "CTRLMMR_LOCK6_KICK0,Lower 32-bits of Partition6 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper umlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x1900C++0x3
line.long 0x00 "CTRLMMR_LOCK6_KICK1,Upper 32-bits of Partition 6 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers"
group.long 0x1C000++0x3
line.long 0x00 "CTRLMMR_PADCONFIG0,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C004++0x3
line.long 0x00 "CTRLMMR_PADCONFIG1,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C008++0x3
line.long 0x00 "CTRLMMR_PADCONFIG2,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C00C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG3,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C010++0x3
line.long 0x00 "CTRLMMR_PADCONFIG4,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C014++0x3
line.long 0x00 "CTRLMMR_PADCONFIG5,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C018++0x3
line.long 0x00 "CTRLMMR_PADCONFIG6,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C01C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG7,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C020++0x3
line.long 0x00 "CTRLMMR_PADCONFIG8,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C024++0x3
line.long 0x00 "CTRLMMR_PADCONFIG9,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C028++0x3
line.long 0x00 "CTRLMMR_PADCONFIG10,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C02C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG11,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C030++0x3
line.long 0x00 "CTRLMMR_PADCONFIG12,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C034++0x3
line.long 0x00 "CTRLMMR_PADCONFIG13,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C038++0x3
line.long 0x00 "CTRLMMR_PADCONFIG14,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C03C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG15,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C040++0x3
line.long 0x00 "CTRLMMR_PADCONFIG16,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C044++0x3
line.long 0x00 "CTRLMMR_PADCONFIG17,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C048++0x3
line.long 0x00 "CTRLMMR_PADCONFIG18,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C04C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG19,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C050++0x3
line.long 0x00 "CTRLMMR_PADCONFIG20,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C054++0x3
line.long 0x00 "CTRLMMR_PADCONFIG21,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C058++0x3
line.long 0x00 "CTRLMMR_PADCONFIG22,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C05C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG23,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C060++0x3
line.long 0x00 "CTRLMMR_PADCONFIG24,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C064++0x3
line.long 0x00 "CTRLMMR_PADCONFIG25,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C068++0x3
line.long 0x00 "CTRLMMR_PADCONFIG26,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C06C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG27,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C070++0x3
line.long 0x00 "CTRLMMR_PADCONFIG28,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C074++0x3
line.long 0x00 "CTRLMMR_PADCONFIG29,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C078++0x3
line.long 0x00 "CTRLMMR_PADCONFIG30,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C07C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG31,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C080++0x3
line.long 0x00 "CTRLMMR_PADCONFIG32,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C084++0x3
line.long 0x00 "CTRLMMR_PADCONFIG33,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C088++0x3
line.long 0x00 "CTRLMMR_PADCONFIG34,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C08C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG35,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C090++0x3
line.long 0x00 "CTRLMMR_PADCONFIG36,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C094++0x3
line.long 0x00 "CTRLMMR_PADCONFIG37,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C098++0x3
line.long 0x00 "CTRLMMR_PADCONFIG38,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C09C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG39,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG40,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG41,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG42,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0AC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG43,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG44,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG45,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG46,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0BC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG47,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG48,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG49,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG50,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0CC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG51,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG52,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG53,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG54,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0DC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG55,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG56,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG57,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG58,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0EC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG59,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG60,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG61,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG62,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0FC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG63,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C100++0x3
line.long 0x00 "CTRLMMR_PADCONFIG64,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C104++0x3
line.long 0x00 "CTRLMMR_PADCONFIG65,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C108++0x3
line.long 0x00 "CTRLMMR_PADCONFIG66,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C10C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG67,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C110++0x3
line.long 0x00 "CTRLMMR_PADCONFIG68,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C114++0x3
line.long 0x00 "CTRLMMR_PADCONFIG69,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C118++0x3
line.long 0x00 "CTRLMMR_PADCONFIG70,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C11C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG71,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C120++0x3
line.long 0x00 "CTRLMMR_PADCONFIG72,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C124++0x3
line.long 0x00 "CTRLMMR_PADCONFIG73,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C128++0x3
line.long 0x00 "CTRLMMR_PADCONFIG74,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C12C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG75,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C130++0x3
line.long 0x00 "CTRLMMR_PADCONFIG76,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C134++0x3
line.long 0x00 "CTRLMMR_PADCONFIG77,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C138++0x3
line.long 0x00 "CTRLMMR_PADCONFIG78,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C13C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG79,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C140++0x3
line.long 0x00 "CTRLMMR_PADCONFIG80,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C144++0x3
line.long 0x00 "CTRLMMR_PADCONFIG81,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C148++0x3
line.long 0x00 "CTRLMMR_PADCONFIG82,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C14C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG83,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C150++0x3
line.long 0x00 "CTRLMMR_PADCONFIG84,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C154++0x3
line.long 0x00 "CTRLMMR_PADCONFIG85,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C158++0x3
line.long 0x00 "CTRLMMR_PADCONFIG86,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C15C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG87,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C160++0x3
line.long 0x00 "CTRLMMR_PADCONFIG88,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C164++0x3
line.long 0x00 "CTRLMMR_PADCONFIG89,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C168++0x3
line.long 0x00 "CTRLMMR_PADCONFIG90,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C16C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG91,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C170++0x3
line.long 0x00 "CTRLMMR_PADCONFIG92,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C174++0x3
line.long 0x00 "CTRLMMR_PADCONFIG93,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C178++0x3
line.long 0x00 "CTRLMMR_PADCONFIG94,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C17C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG95,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C180++0x3
line.long 0x00 "CTRLMMR_PADCONFIG96,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C184++0x3
line.long 0x00 "CTRLMMR_PADCONFIG97,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C188++0x3
line.long 0x00 "CTRLMMR_PADCONFIG98,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C18C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG99,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C190++0x3
line.long 0x00 "CTRLMMR_PADCONFIG100,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C194++0x3
line.long 0x00 "CTRLMMR_PADCONFIG101,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C198++0x3
line.long 0x00 "CTRLMMR_PADCONFIG102,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C19C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG103,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1A0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG104,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1A4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG105,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1A8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG106,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1AC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG107,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1B0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG108,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1B4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG109,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1B8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG110,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1BC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG111,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1C0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG112,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1C4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG113,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1C8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG114,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1CC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG115,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1D0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG116,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1D4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG117,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1D8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG118,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1DC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG119,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1E0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG120,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1E4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG121,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1E8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG122,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1EC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG123,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1F0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG124,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1F4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG125,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1F8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG126,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C1FC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG127,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C200++0x3
line.long 0x00 "CTRLMMR_PADCONFIG128,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C204++0x3
line.long 0x00 "CTRLMMR_PADCONFIG129,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C208++0x3
line.long 0x00 "CTRLMMR_PADCONFIG130,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C20C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG131,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C210++0x3
line.long 0x00 "CTRLMMR_PADCONFIG132,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C214++0x3
line.long 0x00 "CTRLMMR_PADCONFIG133,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C218++0x3
line.long 0x00 "CTRLMMR_PADCONFIG134,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C21C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG135,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C220++0x3
line.long 0x00 "CTRLMMR_PADCONFIG136,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C224++0x3
line.long 0x00 "CTRLMMR_PADCONFIG137,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C228++0x3
line.long 0x00 "CTRLMMR_PADCONFIG138,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C22C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG139,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C230++0x3
line.long 0x00 "CTRLMMR_PADCONFIG140,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C234++0x3
line.long 0x00 "CTRLMMR_PADCONFIG141,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C238++0x3
line.long 0x00 "CTRLMMR_PADCONFIG142,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C23C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG143,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C240++0x3
line.long 0x00 "CTRLMMR_PADCONFIG144,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C244++0x3
line.long 0x00 "CTRLMMR_PADCONFIG145,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C248++0x3
line.long 0x00 "CTRLMMR_PADCONFIG146,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C24C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG147,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C250++0x3
line.long 0x00 "CTRLMMR_PADCONFIG148,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C254++0x3
line.long 0x00 "CTRLMMR_PADCONFIG149,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C258++0x3
line.long 0x00 "CTRLMMR_PADCONFIG150,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C25C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG151,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C260++0x3
line.long 0x00 "CTRLMMR_PADCONFIG152,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C264++0x3
line.long 0x00 "CTRLMMR_PADCONFIG153,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C268++0x3
line.long 0x00 "CTRLMMR_PADCONFIG154,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C26C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG155,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C270++0x3
line.long 0x00 "CTRLMMR_PADCONFIG156,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C274++0x3
line.long 0x00 "CTRLMMR_PADCONFIG157,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C278++0x3
line.long 0x00 "CTRLMMR_PADCONFIG158,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C27C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG159,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C280++0x3
line.long 0x00 "CTRLMMR_PADCONFIG160,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C284++0x3
line.long 0x00 "CTRLMMR_PADCONFIG161,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C288++0x3
line.long 0x00 "CTRLMMR_PADCONFIG162,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C28C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG163,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C290++0x3
line.long 0x00 "CTRLMMR_PADCONFIG164,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C294++0x3
line.long 0x00 "CTRLMMR_PADCONFIG165,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C298++0x3
line.long 0x00 "CTRLMMR_PADCONFIG166,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C29C++0x3
line.long 0x00 "CTRLMMR_PADCONFIG167,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2A0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG168,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2A4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG169,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2A8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG170,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2AC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG171,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2B0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG172,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2B4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG173,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2B8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG174,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2BC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG175,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2C0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG176,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2C4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG177,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2C8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG178,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2CC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG179,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2D0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG180,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2D4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG181,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2D8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG182,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2DC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG183,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2E0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG184,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2E8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG186,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2EC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG187,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2F0++0x3
line.long 0x00 "CTRLMMR_PADCONFIG188,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2F4++0x3
line.long 0x00 "CTRLMMR_PADCONFIG189,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2F8++0x3
line.long 0x00 "CTRLMMR_PADCONFIG190,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C2FC++0x3
line.long 0x00 "CTRLMMR_PADCONFIG191,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C300++0x3
line.long 0x00 "CTRLMMR_PADCONFIG192,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C304++0x3
line.long 0x00 "CTRLMMR_PADCONFIG193,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C308++0x3
line.long 0x00 "CTRLMMR_PADCONFIG194,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK              ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT          ,Wakeup event status" "0,1"
textline "                                      "
bitfld.long 0x00 29. " WKUP_EN           ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL   ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                      "
bitfld.long 0x00 27. " DS_PULLUD_EN      ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL         ,Deep Sleep 0 mode output value" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DSOUT_DIS         ,Deep Sleep 0 mode output disable" "0,1"
bitfld.long 0x00 24. "         DS_EN             ,Deep Sleep 0 mode override control" "0,1"
textline "                                      "
bitfld.long 0x00 23. " ISO_BYP           ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR           ,Isolation Override" "0,1"
textline "                                      "
bitfld.long 0x00 21. " TX_DIS            ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE          ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 18. " RXACTIVE          ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL       ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                      "
bitfld.long 0x00 16. " PULLUDEN          ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN       ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                      "
bitfld.long 0x00 0.--3. " MUXMODE           ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1D008++0x3
line.long 0x00 "CTRLMMR_LOCK7_KICK0,Lower 32-bits of Partition7 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 7 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY               ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
bitfld.long 0x00 0. "  UNLOCKED          ,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x1D00C++0x3
line.long 0x00 "CTRLMMR_LOCK7_KICK1,Upper 32-bits of Partition 7 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 7 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY               ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers"
width 0x0B
tree.end
tree.end
tree "MCU_CTRL_MMR"
tree "MCU_CTRL_MMR0_CFG0"
base ad:0x40F00000
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "CTRLMMR_MCU_PID,Peripheral release details."
hexmask.long 0x00 0.--31. 1. " REV             ,TI internal data."
rgroup.long 0x8++0x3
line.long 0x00 "CTRLMMR_MCU_MMR_CFG1,Indicates the MMR configuration."
hexmask.long.byte 0x00 0.--7. 1. " PARTITIONS      ,Indicates present partitions"
group.long 0x100++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_SET0,Generate interprocessor communication interrupt to MCU R5 core0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET         ,Read returns 0" "0,1"
group.long 0x104++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_SET1,Generate interprocessor communication interrupt to MCU R5 core1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET         ,Read returns 0" "0,1"
group.long 0x120++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_SET8,Generate interprocessor communication interrupt to DMSC."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_SET     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_SET         ,Read returns 0" "0,1"
group.long 0x180++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_CLR0,Acknowledge interprocessor communication interrupt to MCU R5 core0."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR         ,Read returns current value" "0,1"
group.long 0x184++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_CLR1,Acknowledge interprocessor communication interrupt to MCU R5 core1."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR         ,Read returns current value" "0,1"
group.long 0x1A0++0x3
line.long 0x00 "CTRLMMR_MCU_IPC_CLR8,Acknowledge interprocessor communication interrupt to DMSC."
hexmask.long 0x00 4.--31. 1. " IPC_SRC_CLR     ,Read returns current value"
bitfld.long 0x00 0. "  IPC_CLR         ,Read returns current value" "0,1"
rgroup.long 0x200++0x3
line.long 0x00 "CTRLMMR_MCU_MAC_ID0,MCU Ethernet MAC address lower 32-bits."
hexmask.long 0x00 0.--31. 1. " MACID_LO        ,32 lsbs of MAC address"
rgroup.long 0x204++0x3
line.long 0x00 "CTRLMMR_MCU_MAC_ID1,MCU Ethernet MAC address upper 16-bits."
hexmask.long.word 0x00 0.--15. 1. " MACID_HI        ,16 msbs of MAC address"
group.long 0x1008++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY             ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
bitfld.long 0x00 0. "  UNLOCKED        ,Unlock status. When set indicates that the proper umlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x100C++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY             ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x1010++0x3
line.long 0x00 "CTRLMMR_MCU_INTR_RAW_STAT,Shows the interupt status (before enabling) and allows setting of the interrupt status (for test)."
bitfld.long 0x00 2. " LOCK_ERR        ,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR        ,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR        ,Protection violation occurred (attempt to to read or write a register with insufficient sucurity or privilege access rights)" "0,1"
group.long 0x1014++0x3
line.long 0x00 "CTRLMMR_MCU_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared."
bitfld.long 0x00 2. " EN_LOCK_ERR     ,Enabled lock interrupt event status" "0,1"
bitfld.long 0x00 1. "         EN_ADDR_ERR     ,Enabled address interrupt event status" "0,1"
textline "                                      "
bitfld.long 0x00 0. " EN_PROT_ERR     ,Enabled protection interrupt event status" "0,1"
group.long 0x1018++0x3
line.long 0x00 "CTRLMMR_MCU_INTR_EN_SET,Allows interrupt enables to be set."
bitfld.long 0x00 2. " LOCK_ERR_EN_SET ,Lock interrupt enable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_SET ,Address interrupt enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR_EN_SET ,Protection interrupt enable" "0,1"
group.long 0x101C++0x3
line.long 0x00 "CTRLMMR_MCU_INTR_EN_CLR,Allows interrupt enables to be cleared."
bitfld.long 0x00 2. " LOCK_ERR_EN_CLR ,Lock interrupt disable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_CLR ,Address interrupt disable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " PROT_ERR_EN_CLR ,Protection interrupt disable" "0,1"
rgroup.long 0x1024++0x3
line.long 0x00 "CTRLMMR_MCU_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur."
hexmask.long 0x00 0.--31. 1. " ADDRESS         ,Address of the faulted access"
rgroup.long 0x1028++0x3
line.long 0x00 "CTRLMMR_MCU_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur."
bitfld.long 0x00 0.--5. " TYPE            ,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x102C++0x3
line.long 0x00 "CTRLMMR_MCU_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur."
hexmask.long.word 0x00 20.--31. 1. " XID             ,Transaction ID"
hexmask.long.word 0x00 8.--19. 1. "      ROUTEID         ,Route ID"
textline "                                      "
hexmask.long.byte 0x00 0.--7. 1. " PRIVID          ,Privilege ID"
group.long 0x1030++0x3
line.long 0x00 "CTRLMMR_MCU_FAULT_CLR,Allows software to clear the current fault Clearing the current fault allows the , , and registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits."
bitfld.long 0x00 0. " CLEAR           ,Fault clear" "0,1"
group.long 0x4030++0x3
line.long 0x00 "CTRLMMR_MCU_MSMC_CFG,Used to configure MSMC reset options."
bitfld.long 0x00 0. " DDR_32B_ADDR_EN ,32-bit DDR Addressing Enabled" "0,1"
group.long 0x4040++0x3
line.long 0x00 "CTRLMMR_MCU_ENET_CTRL,Controls MCU Ethernet Port1 operation."
bitfld.long 0x00 4. " RGMII_ID_MODE   ,Port1 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x00 0.--1. "         MODE_SEL        ,Selects ethernet switch Port1 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII (not supported)" "0,1,2,3"
group.long 0x4060++0x3
line.long 0x00 "CTRLMMR_MCU_SPI1_CTRL,Controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out."
bitfld.long 0x00 0. " SPI1_LINKDIS    ,Disables direct connection of MCU_SPI1 to SPI3 0h - MCU_SPI1 is tied as a slave to SPI3. MCU_SPI1 CLK, DATA1 and CS0 are driven from SPI3, DATA OUT drives SPI3 DATA0 1h - MCU_SPI1 is NOT tied as a slave to SPI3. MCU_SPI1 CLK, DATA0, DATA1 and CS[3:0] are controlled through their respective MCU_SPI1 pins and SPI3 CLK, DATA0, DATA1, and CS[3:0] are controlled through their respective SPI3 pins." "0,1"
group.long 0x40A0++0x3
line.long 0x00 "CTRLMMR_MCU_FSS_CTRL,Controls Flash boot region size and placement."
bitfld.long 0x00 24. " S1_BOOT_SIZE    ,Selects the size of the boot block to be used for the S1 (OSPI1) flash interface" "0,1"
bitfld.long 0x00 16.--21. "         S1_BOOT_SEG     ,Selects the boot block to be used for the S1 (OSPI1) flash interface. If the s1_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap the address of the flash. (e.g. if both ECC and authentication are enabled for 64 MB boot, the highest valid block number is is 49, as sector 50 is only .2M Bytes in size.)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                      "
bitfld.long 0x00 8. " S0_BOOT_SIZE    ,Selects the size of the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface" "0,1"
bitfld.long 0x00 0.--5. "         S0_BOOT_SEG     ,Selects the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap the address of the flash. (e.g. if both ECC and authentication are enabled for 64 MB boot, the highest valid block number is is 49, as sector 50 is only .2M Bytes in size.)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40B0++0x3
line.long 0x00 "CTRLMMR_MCU_ADC0_CTRL,Controls operation of MCU ADC0."
bitfld.long 0x00 0.--4. " TRIG_SEL        ,Selects the source of the ADC hardware event trigger 0h - MCU_ADC0_EXT_TRIGGER pin 1h - MCU_ADC1_EXT_TRIGGER pin 2h - eHRPWM SOCA event 3h - eHRPWM SOCB event 4h - MCU Timer0 PWM output 5h - MCU Timer1 PWM output 6h - MCU Timer2 PWM output 7h - MCU Timer3 PWM output 8h - Timer0 PWM output 9h - Timer1 PWM output Ah - Timer2 PWM output Bh - Timer3 PWM output Ch - Timer4 PWM output Dh - Timer5 PWM output Eh - Timer6 PWM output Fh - Timer7 PWM output 10h - Timer8 PWM output 11h - Timer9 PWM output 12h - Timer10 PWM output 13h - Timer11 PWM output 14h - ICSS-G0 IEP0 CMP15 event 15h - ICSS-G0 IEP1 CMP15 event 16h - ICSS-G1 IEP0 CMP15 event 17h - ICSS-G1 IEP1 CMP15 event 18h - ICSS-G2 IEP0 CMP15 event 19h - ICSS-G2 IEP1 CMP15 event 1Ah - Reserved (tied 1'b0) 1Bh - Reserved (tied 1'b0) 1Ch - Reserved (tied 1'b0) 1Dh - Reserved (tied 1'b0) 1Eh - Reserved (tied 1'b0) 1Fh - Reserved (tied 1'b0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40B4++0x3
line.long 0x00 "CTRLMMR_MCU_ADC1_CTRL,Controls operation of MCU ADC1."
bitfld.long 0x00 0.--4. " TRIG_SEL        ,Selects the source of the ADC hardware event trigger 0h - MCU_ADC0_EXT_TRIGGER pin 1h - MCU_ADC1_EXT_TRIGGER pin 2h - eHRPWM SOCA event 3h - eHRPWM SOCB event 4h - MCU Timer0 PWM output 5h - MCU Timer1 PWM output 6h - MCU Timer2 PWM output 7h - MCU Timer3 PWM output 8h - Timer0 PWM output 9h - Timer1 PWM output Ah - Timer2 PWM output Bh - Timer3 PWM output Ch - Timer4 PWM output Dh - Timer5 PWM output Eh - Timer6 PWM output Fh - Timer7 PWM output 10h - Timer8 PWM output 11h - Timer9 PWM output 12h - Timer10 PWM output 13h - Timer11 PWM output 14h - ICSS-G0 IEP0 CMP15 event 15h - ICSS-G0 IEP1 CMP15 event 16h - ICSS-G1 IEP0 CMP15 event 17h - ICSS-G1 IEP1 CMP15 event 18h - ICSS-G2 IEP0 CMP15 event 19h - ICSS-G2 IEP1 CMP15 event 1Ah - Reserved (tied 1'b0) 1Bh - Reserved (tied 1'b0) 1Ch - Reserved (tied 1'b0) 1Dh - Reserved (tied 1'b0) 1Eh - Reserved (tied 1'b0) 1Fh - Reserved (tied 1'b0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4200++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER0_CTRL,Controls MCU Timer0 operation."
bitfld.long 0x00 0. " CAP_SEL         ,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation." "0,1"
group.long 0x4204++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER1_CTRL,Controls MCU Timer1 operation."
bitfld.long 0x00 8. " CASCADE_EN      ,When set, enables cascading of MCU_TIMER1 to MCU_TIMER0" "0,1"
bitfld.long 0x00 0. "         CAP_SEL         ,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation." "0,1"
group.long 0x4208++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER2_CTRL,Controls MCU Timer2 operation."
bitfld.long 0x00 0. " CAP_SEL         ,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation." "0,1"
group.long 0x420C++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER3_CTRL,Controls MCU Timer3 operation."
bitfld.long 0x00 8. " CASCADE_EN      ,When set, enables cascading of MCU_TIMER3 to MCU_TIMER2" "0,1"
bitfld.long 0x00 0. "         CAP_SEL         ,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation." "0,1"
group.long 0x4280++0x3
line.long 0x00 "CTRLMMR_MCU_TIMERIO0_CTRL,Controls MCU TimerIO muxing."
bitfld.long 0x00 0.--1. " OUT_SEL         ,Selects the source of the MCU_TIMERIO0 output 0h - MCU_TIMERIO0 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO0 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO0 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO0 is driven by MCU_TIMER3 output" "0,1,2,3"
group.long 0x4284++0x3
line.long 0x00 "CTRLMMR_MCU_TIMERIO1_CTRL,Controls MCU TimerIO muxing."
bitfld.long 0x00 0.--1. " OUT_SEL         ,Selects the source of the MCU_TIMERIO1 output 0h - MCU_TIMERIO1 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO1 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO1 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO1 is driven by MCU_TIMER3 output" "0,1,2,3"
group.long 0x5008++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY             ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
bitfld.long 0x00 0. "  UNLOCKED        ,Unlock status. When set indicates that the proper umlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x500C++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY             ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x8010++0x3
line.long 0x00 "CTRLMMR_MCU_CLKOUT0_CTRL,Enables and selects clock source of CPSW MCU_CLKOUT0 pin."
bitfld.long 0x00 4. " CLK_EN          ,When set, enables MCU_CLKOUT0 output" "0,1"
bitfld.long 0x00 0. "         CLK_SEL         ,Selects MCU_CLKOUT0 clock source" "0,1"
group.long 0x8018++0x3
line.long 0x00 "CTRLMMR_MCU_EFUSE_CLKSEL,Selects the functional clock source for the MCU domain eFuse Controller."
bitfld.long 0x00 0. " CLK_SEL         ,Selects the clock source 0h - EFUSE_CLK (HFOSC0_CLKOUT or CLK_12M_RC) 1h - MCU_SYSCLK0 / 8" "0,1"
group.long 0x8020++0x3
line.long 0x00 "CTRLMMR_MCU_MCAN0_CLKSEL,Controls the functional clock source for MCU_MCAN0."
bitfld.long 0x00 0.--1. " CLK_SEL         ,MCU_MCAN MCAN_CLK selection" "0,1,2,3"
group.long 0x8024++0x3
line.long 0x00 "CTRLMMR_MCU_MCAN1_CLKSEL,Controls the functional clock source for MCU_MCAN1."
bitfld.long 0x00 0.--1. " CLK_SEL         ,MCU_MCAN MCAN_CLK selection" "0,1,2,3"
group.long 0x8030++0x3
line.long 0x00 "CTRLMMR_MCU_OSPI0_CLKSEL,Controls the OSPI loopback clock source."
bitfld.long 0x00 4. " LOOPCLK_SEL     ,OBSPI0 Loopback clock source" "0,1"
bitfld.long 0x00 0. "         CLK_SEL         ,OSPI0 reference clock selection" "0,1"
group.long 0x8034++0x3
line.long 0x00 "CTRLMMR_MCU_OSPI1_CLKSEL,Controls the OSPI loopback clock source."
bitfld.long 0x00 4. " LOOPCLK_SEL     ,OBSPI1 Loopback clock source" "0,1"
bitfld.long 0x00 0. "         CLK_SEL         ,OSPI1 reference clock selection" "0,1"
group.long 0x8040++0x3
line.long 0x00 "CTRLMMR_MCU_ADC0_CLKSEL,Controls the functional clock source for the MCU_ADC0."
bitfld.long 0x00 0.--1. " CLK_SEL         ,Selects the sampling clock source for ADC0 0h - HFOSC0_CLKOUT 1h - MCUHSDIV_CLKOUT1 2h - CPSWHSDIV_CLKOUT3 3h - MCU_EXT_REFCLK0" "0,1,2,3"
group.long 0x8044++0x3
line.long 0x00 "CTRLMMR_MCU_ADC1_CLKSEL,Controls the functional clock source for the MCU_ADC1."
bitfld.long 0x00 0.--1. " CLK_SEL         ,Selects the sampling clock source for ADC1 0h - HFOSC0_CLKOUT 1h - MCUHSDIV_CLKOUT1 2h - CPSWHSDIV_CLKOUT3 3h - MCU_EXT_REFCLK0" "0,1,2,3"
group.long 0x8050++0x3
line.long 0x00 "CTRLMMR_MCU_ENET_CLKSEL,Controls selectable clock sources for the MCU Ethernet Port1."
bitfld.long 0x00 0. " RMII_CLK_SEL    ,Selects the rmii clock (rmii_mhz_50_clk) source. This defaults to the internal 50 MHz clock source for proper clockstop operation" "0,1"
group.long 0x8080++0x3
line.long 0x00 "CTRLMMR_MCU_R5_CORE0_CLKSEL,MCU Core 0 functional clock selection control."
bitfld.long 0x00 0. " CLK_SEL         ,Selects the Core 0 functional clock and mcu/interface clock ratio" "0,1"
group.long 0x8084++0x3
line.long 0x00 "CTRLMMR_MCU_R5_CORE1_CLKSEL,MCU Core 1 functional clock selection control."
bitfld.long 0x00 0. " CLK_SEL         ,Selects the Core 1 functional clock and mcu/interface clock ratio" "0,1"
group.long 0x8100++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER0_CLKSEL,MCU Timer0 functional clock selection control."
bitfld.long 0x00 0.--2. " CLK_SEL         ,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 2 2h - CLK_12M_RC 3h - MCU_CPSW_PLL_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x8104++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER1_CLKSEL,MCU Timer1 functional clock selection control."
bitfld.long 0x00 0.--2. " CLK_SEL         ,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 2 2h - CLK_12M_RC 3h - MCU_CPSW_PLL_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x8108++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER2_CLKSEL,MCU Timer2 functional clock selection control."
bitfld.long 0x00 0.--2. " CLK_SEL         ,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 2 2h - CLK_12M_RC 3h - MCU_CPSW_PLL_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x810C++0x3
line.long 0x00 "CTRLMMR_MCU_TIMER3_CLKSEL,MCU Timer3 functional clock selection control."
bitfld.long 0x00 0.--2. " CLK_SEL         ,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 2 2h - CLK_12M_RC 3h - MCU_CPSW_PLL_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x8180++0x3
line.long 0x00 "CTRLMMR_MCU_RTI0_CLKSEL,MCU RTI0 functional clock selection control."
bitfld.long 0x00 31. " WRTLOCK         ,When set, locks further writes to" "0,1"
bitfld.long 0x00 0.--2. "         CLK_SEL         ,RTI functional clock input select mux control. The msb is unused but should be written as 1'b0 to maintain compatibility with future devices. 0h - HFOSC0_CLKOUT 1h - LFOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x8184++0x3
line.long 0x00 "CTRLMMR_MCU_RTI1_CLKSEL,MCU RTI1 functional clock selection control."
bitfld.long 0x00 31. " WRTLOCK         ,When set, locks further writes to" "0,1"
bitfld.long 0x00 0.--2. "         CLK_SEL         ,RTI functional clock input select mux control. The msb is unused but should be written as 1'b0 to maintain compatibility with future devices. 0h - HFOSC0_CLKOUT 1h - LFOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K_RC" "0,1,2,3,4,5,6,7"
group.long 0x81C0++0x3
line.long 0x00 "CTRLMMR_MCU_USART_CLKSEL,Controls the functional clock source for MCU_USART0."
bitfld.long 0x00 0. " CLK_SEL         ,MCU_USART0 FCLK selection" "0,1"
group.long 0x9008++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY             ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
bitfld.long 0x00 0. "  UNLOCKED        ,Unlock status. When set indicates that the proper umlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x900C++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY             ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers"
group.long 0x18030++0x3
line.long 0x00 "CTRLMMR_MCU_SRAM_LDO_CTRL,Controls operation of the MCU VD SRAM LDO module."
hexmask.long.word 0x00 16.--25. 1. " VSET            ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF          ,When set, disables the VSLDO and enabbles IDDQ test mode" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SRAMALLRET      ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF          ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ENFUNC1         ,Control the LDO loop dynamics. Setting enfunc1 decreases loop gain by 6dB." "0,1"
group.long 0x19008++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK6_KICK0,Lower 32-bits of Partition6 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY             ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
bitfld.long 0x00 0. "  UNLOCKED        ,Unlock status. When set indicates that the proper umlock sequence has been performed and the partition is unlocked for writing." "0,1"
group.long 0x1900C++0x3
line.long 0x00 "CTRLMMR_MCU_LOCK6_KICK1,Upper 32-bits of Partition 6 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY             ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers"
width 0x0B
tree.end
tree.end
tree "WKUP_CTRL_MMR"
tree "WKUP_CTRL_MMR0_CFG0"
base ad:0x43000000
width 44.
rgroup.long 0x0++0x3
line.long 0x00 "CTRLMMR_WKUP_PID,Peripheral release details."
hexmask.long 0x00 0.--31. 1. " REV                       ,TI internal data."
rgroup.long 0x8++0x3
line.long 0x00 "CTRLMMR_WKUP_MMR_CFG1,Indicates the MMR configuration."
hexmask.long.byte 0x00 0.--7. 1. " PARTITIONS                ,Indicates present partitions"
rgroup.long 0x14++0x3
line.long 0x00 "CTRLMMR_WKUP_JTAGID,The register must be readable by the configuration bus so that this can be accessed via the JTAG and CPU. In Boundary Scan mode, this ID should also be readable with only TCLK present. This means without a valid CPU clock running and also implies that Fusefarm scan is not necessary. The Variant field should be set in the top metal mask so that this may be changed if a future PG is necessary. All other fields may be hard coded."
bitfld.long 0x00 28.--31. " VARIATN                   ,Used to indicate new PGs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 12.--27. 1. "        PARTNO                    ,Part number for boundary scan"
textline "                                                     "
hexmask.long.word 0x00 1.--11. 1. " MFG                       ,Indicates manufacturer"
bitfld.long 0x00 0. "      LSB                       ,Always 1" "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "CTRLMMR_WKUP_JTAG_DEVICE_ID,This register is used for device identification."
hexmask.long 0x00 0.--31. 1. " DEVICE_ID                 ,Device information"
group.long 0x30++0x3
line.long 0x00 "CTRLMMR_WKUP_DEVSTAT,Indicates MCU bootstrap selection. The default value of this register is determined by the MCU bootstrap pins when the por_boot_cfg_srst_n input is de-asserted."
hexmask.long.word 0x00 0.--9. 1. " BOOTMODE                  ,Indicates MCU boot mode"
rgroup.long 0x34++0x3
line.long 0x00 "CTRLMMR_WKUP_BOOTCFG,Indicates MCU bootstrap selection latched at power-on reset by PORz. The default value of this register is determined by the MCU bootstrap pins when the por_boot_cfg_srst_n input is de-asserted and will remain until the MCU bootstrap pins are re-latched on a subsequent por_boot_cfg_srst_n rising edge."
hexmask.long.word 0x00 0.--9. 1. " BOOTMODE                  ,Indicates MCU boot mode as latched at power-on reset"
group.long 0x44++0x3
line.long 0x00 "CTRLMMR_WKUP_BOOT_PROGRESS,Used by ROM to mark the progress of the boot operation."
hexmask.long 0x00 0.--31. 1. " PROGRESS                  ,Written by ROM to indicate boot progression. Values and their meaning are determined by the ROM."
rgroup.long 0x60++0x3
line.long 0x00 "CTRLMMR_WKUP_DEVICE_FEATURE0,Indicates enabled MPU processing elements on the device."
bitfld.long 0x00 5. " MPU_CLUSTER1_CORE1        ,MPU Cluster1 Core 1 is enabled when set" "0,1"
bitfld.long 0x00 4. "         MPU_CLUSTER1_CORE0        ,MPU Cluster1 Core 0 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " MPU_CLUSTER0_CORE1        ,MPU Cluster0 Core 1 is enabled when set" "0,1"
bitfld.long 0x00 0. "         MPU_CLUSTER0_CORE0        ,MPU Cluster0 Core 0 is enabled when set" "0,1"
rgroup.long 0x68++0x3
line.long 0x00 "CTRLMMR_WKUP_DEVICE_FEATURE2,Indicates enabled MCU domain interface elements on the device."
bitfld.long 0x00 7. " AES_AUTH_EN               ,AES authentication is enabled in MCU_FlashSS and DMSC when set" "0,1"
bitfld.long 0x00 6. "         HYPERBUS                  ,MCU_Hyperbus is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 5. " OSPI1                     ,MCU_OSPI1 is enabled when set" "0,1"
bitfld.long 0x00 4. "         OSPI0                     ,MCU_OSPI0 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 3. " MCAN1                     ,MCU_MCAN1 is enabled when set" "0,1"
bitfld.long 0x00 2. "         MCAN1_FD_MODE             ,FD mode is supported on MCU_MCAN1 when set" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " MCAN0                     ,MCU_MCAN0 is enabled when set" "0,1"
bitfld.long 0x00 0. "         MCAN0_FD_MODE             ,FD mode is supported on MCU_MCAN0 when set" "0,1"
rgroup.long 0x6C++0x3
line.long 0x00 "CTRLMMR_WKUP_DEVICE_FEATURE3,Indicates enabled MAIN domain interface elements on the device."
bitfld.long 0x00 26. " GPU                       ,GPU is enabled when set" "0,1"
bitfld.long 0x00 25. "         GPU_BC                    ,GPU DXT block compression enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 24. " GPU_PBIST                 ,GPU self-test is enabled when set" "0,1"
bitfld.long 0x00 20. "         MMC                       ,MMC/SD is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 18. " CAL                       ,CAL is enabled when set" "0,1"
bitfld.long 0x00 16. "         DSS                       ,DSS is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 14. " ICSS_G2                   ,ICSS_G2 is enabled when set" "0,1"
bitfld.long 0x00 13. "         ICSS_G1                   ,ICSS_G1 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 12. " ICSS_G0                   ,ICSS_G0 is enabled when set" "0,1"
bitfld.long 0x00 9. "         SERDES1                   ,Serdes1 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 8. " SERDES0                   ,Serdes0 is enabled when set" "0,1"
bitfld.long 0x00 5. "         PCIE1                     ,PCIe1 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 4. " PCIE0                     ,PCIe0 is enabled when set" "0,1"
bitfld.long 0x00 1. "         USB1                      ,USB1 is enabled when set" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " USB0                      ,USB0 is enabled when set" "0,1"
group.long 0x1008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0x100C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 0 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x1010++0x3
line.long 0x00 "CTRLMMR_WKUP_INTR_RAW_STAT,Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test)."
bitfld.long 0x00 2. " LOCK_ERR                  ,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR                  ,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " PROT_ERR                  ,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1"
group.long 0x1014++0x3
line.long 0x00 "CTRLMMR_WKUP_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared."
bitfld.long 0x00 2. " EN_LOCK_ERR               ,Enabled lock interrupt event status" "0,1"
bitfld.long 0x00 1. "         EN_ADDR_ERR               ,Enabled address interrupt event status" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " EN_PROT_ERR               ,Enabled protection interrupt event status" "0,1"
group.long 0x1018++0x3
line.long 0x00 "CTRLMMR_WKUP_INTR_EN_SET,Allows interrupt enables to be set."
bitfld.long 0x00 2. " LOCK_ERR_EN_SET           ,Lock interrupt enable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_SET           ,Address interrupt enable" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " PROT_ERR_EN_SET           ,Protection interrupt enable" "0,1"
group.long 0x101C++0x3
line.long 0x00 "CTRLMMR_WKUP_INTR_EN_CLR,Allows interrupt enables to be cleared."
bitfld.long 0x00 2. " LOCK_ERR_EN_CLR           ,Lock interrupt disable" "0,1"
bitfld.long 0x00 1. "         ADDR_ERR_EN_CLR           ,Address interrupt disable" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " PROT_ERR_EN_CLR           ,Protection interrupt disable" "0,1"
rgroup.long 0x1024++0x3
line.long 0x00 "CTRLMMR_WKUP_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur."
hexmask.long 0x00 0.--31. 1. " ADDRESS                   ,Address of the faulted access"
rgroup.long 0x1028++0x3
line.long 0x00 "CTRLMMR_WKUP_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur."
bitfld.long 0x00 0.--5. " TYPE                      ,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x102C++0x3
line.long 0x00 "CTRLMMR_WKUP_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur."
hexmask.long.word 0x00 20.--31. 1. " XID                       ,Transaction ID"
hexmask.long.word 0x00 8.--19. 1. "      ROUTEID                   ,Route ID"
textline "                                                     "
hexmask.long.byte 0x00 0.--7. 1. " PRIVID                    ,Privilege ID"
group.long 0x1030++0x3
line.long 0x00 "CTRLMMR_WKUP_FAULT_CLR,Allows software to clear the current fault Clearing the current fault allows the , , and registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits."
bitfld.long 0x00 0. " CLEAR                     ,Fault clear" "0,1"
group.long 0x4004++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PWR_CTRL,Controls power options for the MAIN voltage domain."
bitfld.long 0x00 0. " PWR_EN                    ,When set, drives the PMIC_PWR_EN1 output to turn on the MAIN voltage domain" "0,1"
group.long 0x4020++0x3
line.long 0x00 "CTRLMMR_WKUP_GPIO_CTRL,Controls operation of the WKUP_GPIO module."
bitfld.long 0x00 0. " WAKEN                     ,Enables WKUP_GPIO wakeup event operation by controling the WKUP_GPIO LPSC clockstop_ack behavior. 0h - No WKUP_GPIO wakeup support. WKUP_GPIO vbus clock is gated on clkstop_ack from WKUP_GPIO to LPSC 1h - WKUP_GPIO wakeup enabled. WKUP_GPIO vbus clock is NOT gated on LPSC clockstop_req. WKUP_GPIO LPSC clkstop_ack input is driven by clkstop_req output." "0,1"
group.long 0x4104++0x3
line.long 0x00 "CTRLMMR_WKUP_SPARE_CTRL1,"
bitfld.long 0x00 3. " MCU_LDOVSET_SRC_SEL       ,Determines the source of the MCU SRAM LDO trim bits" "0,1"
bitfld.long 0x00 2. "         MAIN_POK_CLR              ,When set, resets pgood sticky bits for all MAIN domain voltage POK detection." "0,1"
textline "                                                     "
bitfld.long 0x00 1. " MCU_POK_CLR               ,When set, resets pgood sticky bits for WKUP core, PMIC. MCU core, WKUP 3.3V IO, and WKUP 1.8V IO voltage POK detection." "0,1"
bitfld.long 0x00 0. "         MCU_INHIB_SLEEP           ,Prevents LPSC_MCU_COMMON peripherals from being reset on a MCU warm reset (active low). This bit is inverted and connected to the WKUP PSC mcu_common_inhibitsleep input." "0,1"
group.long 0x4114++0x3
line.long 0x00 "CTRLMMR_WKUP_SPARE_CTRL5,"
bitfld.long 0x00 5. " DS_BLK_FCLKON_MAIN_RST    ,During MAIN domain reset, clocks sourced from the MCU domain must remain (forced) active until reset is complete (efuse scan completed) to ensure reset propogation to MAIN domain modules using those clocks. This bit is used (should be set) to block those clocks from propogating during deep sleep mode." "0,1"
bitfld.long 0x00 1. "         MCU_PLL_IDLE_OVRD         ,MCU PLL idle override." "0,1"
group.long 0x5008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0x500C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 1 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x8000++0x3
line.long 0x00 "CTRLMMR_WKUP_MCU_OBSCLK_CTRL,Controls which internal clock is made observable on the MCU_OBSCLK output pin."
bitfld.long 0x00 16. " CLK_DIV_LD                ,Load the output divider value" "0,1"
bitfld.long 0x00 8.--11. "         CLK_DIV                   ,MCU_OBSCLK pin output divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                     "
bitfld.long 0x00 0.--3. " CLK_SEL                   ,MCU_OBSCLK pin output selection 0h - CLK_12M_RC 1h - HFOSC0_CLK 2h - MCU_PLL_CLKOUT 3h - MCU_PLLCTL_OBSCLK 4h - MCUHSDIV_CLKOUT1 5h - MCUHSDIV_CLKOUT2 6h - MCUHSDIV_CLKOUT3 7h - MCUHSDIV_CLKOUT4 8h - CPSW_PLL_CLKOUT 9h - CLK_32K_RC Ah - CPSWHSDIV_CLKOUT1 Bh - CPSWHSDIV_CLKOUT2 Ch - CPSWHSDIV_CLKOUT3 Dh - CPSWHSDIV_CLKOUT4 Eh - '0' Fh - LPXOSC_CLKOUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8014++0x3
line.long 0x00 "CTRLMMR_WKUP_HFOSC1_CTRL,Added Note for CTRLMMR_WKUP_HFOSC1_CTRL Register Use This register controls high-frequency oscillator ? HFOSC1, located in MAIN domain. Controls the operation of oscillator 1."
bitfld.long 0x00 7. " GZ                        ,Oscillator disable. When GZ=1 the both bypass and oscillation mode are disabled." "0,1"
bitfld.long 0x00 4. "         PWRDN                     ,Oscillator powerdown. When set, places the oscillator in Bypass mode. This has no effect if the GZ bit is set." "0,1"
textline "                                                     "
bitfld.long 0x00 0.--1. " FREQ                      ,Bits 0-1 control the OSC HFENABLE and XHFENABLE inputs, respectively to select the required frequency of oscillation. These bits must be set before oscillator startup and cannot be changed dynamically while the oscillator is running. 0h - <19.2 MHz 1h - 19.2 - 32 MHz 2h - 38 - 52 MHz 3h - 38 - 52 MHz" "0,1,2,3"
group.long 0x8024++0x3
line.long 0x00 "CTRLMMR_WKUP_RC12M_OSC_TRIM,Provides frequency trimming for the 12.5 MHz RC oscillator module."
bitfld.long 0x00 6. " TRIMOSC_COARSE_DIR        ,Coarse adjustment direction. If output is greater than 12.5" "0,1"
bitfld.long 0x00 3.--5. "         TRIMOSC_COARSE            ,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7"
textline "                                                     "
bitfld.long 0x00 0.--2. " TRIMOSC_FINE              ,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7"
group.long 0x8030++0x3
line.long 0x00 "CTRLMMR_WKUP_LFOSC_CTRL,Controls the operation of the low frequency oscillator module."
bitfld.long 0x00 12. " RES_SEL                   ,Oscillator external feedback resistor select" "0,1"
bitfld.long 0x00 8.--10. "         SW                        ,Oscillator gain adjustment" "0,1,2,3,4,5,6,7"
textline "                                                     "
bitfld.long 0x00 7. " GZ                        ,Oscillator disable. When GZ=1 the both bypass and oscillation mode are disabled." "0,1"
group.long 0x8050++0x3
line.long 0x00 "CTRLMMR_WKUP_MCU_PLL_CLKSEL,Controls the clock source for MCU voltage domain PLL[1:0]."
bitfld.long 0x00 8. " CLKLOSS_SWTCH_EN          ,When set, enables automatic switching of MCU PLL[1:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1"
group.long 0x8060++0x3
line.long 0x00 "CTRLMMR_WKUP_PER_CLKSEL,Controls the wakeup peripheral functional clock source. Allows the main oscillator to be used as the functional clock source for the WKUP_USART and WKUP_I2C when PLLs are powered down."
bitfld.long 0x00 0. " MCUPLL_BYPASS             ,Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode)." "0,1"
group.long 0x8064++0x3
line.long 0x00 "CTRLMMR_WKUP_USART_CLKSEL,Controls the functional clock source for WKUP_USART0."
bitfld.long 0x00 0. " CLK_SEL                   ,WKUP_USART0 FCLK selection" "0,1"
group.long 0x8070++0x3
line.long 0x00 "CTRLMMR_WKUP_GPIO_CLKSEL,Controls the functional clock source for WKUP_GPIO."
bitfld.long 0x00 0.--1. " WAKE_CLK_SEL              ,WKUP_GPIO clock selection. Must be set to MCU_SYSCLK0/4 whenever WKUP_GPIO VBUS interface is enabled. Other clock source may be selected as a wake up clock for DeepSleep modes after WKUP_GPIO is gated off through LPSC. 0h - MCU_SYSCLK0 / 4 1h - MCU_SYSCLK0 / 4 2h - CLK_32K_RC 3h - CLK_12M_RC" "0,1,2,3"
group.long 0x8080++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL0_CLKSEL,Controls the clock source for MAIN voltage domain PLL0."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL0" "0,1"
group.long 0x8084++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL1_CLKSEL,Controls the clock source for MAIN voltage domain PLL1."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL1" "0,1"
group.long 0x8088++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL2_CLKSEL,Controls the clock source for MAIN voltage domain PLL2."
bitfld.long 0x00 4. " XREF_SEL                  ,Selects the alternate clock source for PLL2" "0,1"
bitfld.long 0x00 0. "         CLK_SEL                   ,Selects the clock source for PLL2" "0,1"
group.long 0x808C++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL3_CLKSEL,Controls the clock source for MAIN voltage domain PLL3."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL3" "0,1"
group.long 0x8090++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL4_CLKSEL,Controls the clock source for MAIN voltage domain PLL4."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL4" "0,1"
group.long 0x8098++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL6_CLKSEL,Controls the clock source for MAIN voltage domain PLL6."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL6" "0,1"
group.long 0x809C++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL7_CLKSEL,Controls the clock source for MAIN voltage domain PLL7."
bitfld.long 0x00 0. " CLK_SEL                   ,Selects the clock source for PLL7" "0,1"
group.long 0x80C0++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_SYSCLK_CTRL,Controls clock gating of the MAIN PLL Controller SYSCLK outputs."
bitfld.long 0x00 8. " SYSCLK1_GATE              ,When set, gates off SYSCLK1 output of the MAIN PLL Controller" "0,1"
bitfld.long 0x00 0. "         SYSCLK0_GATE              ,When set, gates off SYSCLK0 (CLK1) output of the MAIN PLL Controller" "0,1"
group.long 0x9008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0x900C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 2 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers"
rgroup.long 0xC2C0++0x3
line.long 0x00 "CTRLMMR_WKUP_POST_STAT,Contains the result of power-on self tests."
bitfld.long 0x00 15. " POST_MCU_PBIST_FAIL       ,MCU PBIST failed" "0,1"
bitfld.long 0x00 9. "         POST_MCU_PBIST_TIMEOUT    ,MCU PBIST timed out" "0,1"
textline "                                                     "
bitfld.long 0x00 8. " POST_MCU_PBIST_DONE       ,MCU PBIST done" "0,1"
bitfld.long 0x00 5. "         POST_MCU_LBIST_TIMEOUT    ,MCU LBIST timed out" "0,1"
textline "                                                     "
bitfld.long 0x00 4. " POST_DMSC_LBIST_TIMEOUT   ,DMSC LBIST timed out" "0,1"
bitfld.long 0x00 1. "         POST_MCU_LBIST_DONE       ,MCU LBIST done" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " POST_DMSC_LBIST_DONE      ,DMSC LBIST done" "0,1"
group.long 0xC300++0x3
line.long 0x00 "CTRLMMR_WKUP_FUSE_CRC_CTRL,Controls WKUP efuse chain CRC calculation."
bitfld.long 0x00 3. " CRC_EN_3                  ,Enable eFuse CRC calculation for chain 3" "0,1"
bitfld.long 0x00 2. "         CRC_EN_2                  ,Enable eFuse CRC calculation for chain 2" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " CRC_EN_1                  ,Enable eFuse CRC calculation for chain 1" "0,1"
rgroup.long 0xC304++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN1_CRC_FUSE,Indicates the stored CRC for WKUP fuse chain 1."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Stored chain CRC"
rgroup.long 0xC308++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN2_CRC_FUSE,Indicates the stored CRC for WKUP fuse chain 2."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Stored chain CRC"
rgroup.long 0xC30C++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN3_CRC_FUSE,Indicates the stored CRC for WKUP fuse chain 3."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Stored chain CRC"
rgroup.long 0xC320++0x3
line.long 0x00 "CTRLMMR_WKUP_FUSE_CRC_STAT,Indicates status of fuse chain CRC."
bitfld.long 0x00 3. " CRC_ERR_3                 ,Indicates eFuse CRC error on chain 3" "0,1"
bitfld.long 0x00 2. "         CRC_ERR_2                 ,Indicates eFuse CRC error on chain 2" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " CRC_ERR_1                 ,Indicates eFuse CRC error on chain 1" "0,1"
rgroup.long 0xC324++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN1_CRC_CALC,Indicates the calculated CRC for WKUP fuse chain 1."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Calculated chain CRC"
rgroup.long 0xC328++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN2_CRC_CALC,Indicates the calculated CRC for WKUP fuse chain 2."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Calculated chain CRC"
rgroup.long 0xC32C++0x3
line.long 0x00 "CTRLMMR_WKUP_CHAIN3_CRC_CALC,Indicates the calculated CRC for WKUP fuse chain 3."
hexmask.long 0x00 0.--31. 1. " CRC                       ,Calculated chain CRC"
group.long 0xD008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK3_KICK0,Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 3 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0xD00C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK3_KICK1,Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 3 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers"
group.long 0x18000++0x3
line.long 0x00 "CTRLMMR_WKUP_POR_CTRL,Configures Power-on reset behavior."
bitfld.long 0x00 10. " VDDA_POK_HYS_EN           ,Enable WKUP analog voltage coarse POK hysteresis" "0,1"
bitfld.long 0x00 9. "         MCU_POK_HYS_EN            ,Enable MCU core voltage coarse POK hysteresis" "0,1"
textline "                                                     "
bitfld.long 0x00 8. " WKUP_POK_HYS_EN           ,Enable WKUP core voltage coarse POK hysteresis" "0,1"
bitfld.long 0x00 2. "         VDDA_POK_EN               ,Enable coarse Power-OK detection on WKUP 1.8V analog voltage using the VDDA_MON pin" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " MCU_POK_EN                ,Enable coarse Power-OK detection on MCU core voltage using the VDD_MCU_MON pin" "0,1"
bitfld.long 0x00 0. "         WKUP_POK_EN               ,Enable coarse Power-OK detection on WKUP core voltage using the VDD_WKUP_MON pin" "0,1"
rgroup.long 0x18004++0x3
line.long 0x00 "CTRLMMR_WKUP_POR_STAT,Shows Power-on reset status."
bitfld.long 0x00 2. " VDDA_PWR_BAD              ,WKUP analog voltage coarse POK." "0,1"
bitfld.long 0x00 1. "         COREVDD_PWR_BAD           ,MCU/WKUP core voltage coarse POK." "0,1"
group.long 0x18008++0x3
line.long 0x00 "CTRLMMR_WKUP_PRG_CTRL,Configures the WKUP domain PRG controller."
bitfld.long 0x00 31. " POK_GATERST_EN_SEL        ,Select POK reset gating enable source" "0,1"
bitfld.long 0x00 20. "         WKUP_3P3IO_POK_GATERST_EN ,Enable 3.3 volt voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 19. " WKUP_1P8IO_POK_GATERST_EN ,Enable 1.8 volt voltage POK detection reset gating" "0,1"
bitfld.long 0x00 18. "         MCU_CORE_POK_GATERST_EN   ,Enable MCU core voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 17. " PMIC_POK_GATERST_EN       ,Enable PMIC voltage POK detection reset gating" "0,1"
bitfld.long 0x00 16. "         WKUP_CORE_POK_GATERST_EN  ,Enable WKUP core voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 15. " POK_EN_SEL                ,Select POK enable source" "0,1"
bitfld.long 0x00 4. "         WKUP_3P3IO_POK_EN         ,Enable WKUP 3.3V IO voltage POK detection" "0,1"
textline "                                                     "
bitfld.long 0x00 3. " WKUP_1P8IO_POK_EN         ,Enable WKUP 1.8V IO voltage POK detection" "0,1"
bitfld.long 0x00 2. "         MCU_CORE_POK_EN           ,Enable MCU core voltage POK detection" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " PMIC_POK_EN               ,Enable PMIC voltage POK detection" "0,1"
bitfld.long 0x00 0. "         WKUP_CORE_POK_EN          ,Enable WKUP core voltage POK detection" "0,1"
rgroup.long 0x1800C++0x3
line.long 0x00 "CTRLMMR_WKUP_PRG_STAT,Provides WKUP domain PRG controller status."
bitfld.long 0x00 4. " WKUP_3P3IO_POK            ,WKUP 3.3V IO voltage POK" "0,1"
bitfld.long 0x00 3. "         WKUP_1P8IO_POK            ,WKUP 1.8V IO voltage POK" "0,1"
textline "                                                     "
bitfld.long 0x00 2. " MCU_CORE_POK              ,MCU core voltage POK" "0,1"
bitfld.long 0x00 1. "         PMIC_POK                  ,PMIC voltage POK" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " WKUP_CORE_POK             ,WKUP core voltage POK" "0,1"
group.long 0x18010++0x3
line.long 0x00 "CTRLMMR_WKUP_POKSA_PMIC_VDDA_CTRL,Controls operation of the PMIC (0.5V) voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
bitfld.long 0x00 24. "         HYST_DELAY_SEL            ,Selects the delay time used for POK hysteresis" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
group.long 0x18014++0x3
line.long 0x00 "CTRLMMR_POK1P5V0_WKUP_CORE_VDD_CTRL,Controls operation of the WKUP core (1V) voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18018++0x3
line.long 0x00 "CTRLMMR_WKUP_POK1P5V1_MCU_CORE_VDD_CTRL,Controls operation of the MCU core (1V) voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x1801C++0x3
line.long 0x00 "CTRLMMR_POK3P3V0_WKUP_1P8IO_VDDS_CTRL,Controls operation of the WKUP 1.8 volt IO voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18020++0x3
line.long 0x00 "CTRLMMR_POK3P3V1_WKUP_3P3IO_VDDS_CTRL,Controls operation of the WKUP 3.3 volt IO POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18030++0x3
line.long 0x00 "CTRLMMR_WKUP_LDO_CTRL,Controls operation of the WKUP LDO module."
bitfld.long 0x00 0.--5. " LDO_PROG                  ,LDO output programming bits. Values are not currently defined. LDO specification states that these should be 6'b011001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18034++0x3
line.long 0x00 "CTRLMMR_WKUP_SRAM_LDO_CTRL,Controls operation of the WKUP SRAM LDO module."
hexmask.long.word 0x00 16.--25. 1. " VSET                      ,LDO trim bits"
bitfld.long 0x00 7. "      AIPOFF                    ,When set, disables the VSLDO and enables IDDQ test mode" "0,1"
textline "                                                     "
bitfld.long 0x00 6. " SRAMALLRET                ,When set, places the VSLDO in retention mode" "0,1"
bitfld.long 0x00 5. "         ABBOFF                    ,When set, shorts the VNWA voltage to VDDAR" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " ENFUNC1                   ,Control the LDO loop dynamics. Setting enfunc0 decreases loop gain by 6dB." "0,1"
group.long 0x18044++0x3
line.long 0x00 "CTRLMMR_WKUP_BANDGAP_TRIM,Trims the WKUP LDO Bandgap Regulator."
bitfld.long 0x00 16.--19. " DTRBGAPI_LOWV             ,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "        DTRBGAPV_LOWV             ,Bandgap output voltage magnitude trim bits"
textline "                                                     "
hexmask.long.byte 0x00 0.--7. 1. " DTRBGAPC_LOWV             ,Bandgap slope trim bits. Bit7 is used to calculate the offset"
group.long 0x18060++0x3
line.long 0x00 "CTRLMMR_WKUP_MCU_VDOM_CTRL,Provides MCU voltage domain isolation for deeper sleep operation."
bitfld.long 0x00 8. " DS_PORZ                   ,When low asserts POR_RST_n to the MCU Domain. This bit should be cleared by the DMSC after completing MCU domain isolation to force the MCU domain into reset when implementing DeeperSleep mode. Bit must be set back to 1 by DMSC In order to bring the MCU domain out of reset." "0,1"
group.long 0x18070++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_VDOM_CTRL,Provides MAIN voltage domain isolation for deep sleep operation."
bitfld.long 0x00 8. " DS_PORZ                   ,When low, asserts POR_RST_n to the MAIN Domain. This bit should be cleared by the DMSC after completing MAIN domain isolation to force the MAIN domain into reset when implementing DeeperSleep mode. Bit must be set back to 1 by DMSC In order to bring the MAIN domain out of reset." "0,1"
group.long 0x180A0++0x3
line.long 0x00 "CTRLMMR_WKUP_TEMP_DIODE_TRIM,Trims the silicon junction temperature diode."
hexmask.long.word 0x00 0.--13. 1. " TRIM                      ,Sets the diode non-ideality factor (n), starting from 100th place decimal and going down"
group.long 0x18108++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PRG_CTRL,Configures the MAIN domain PRG controller."
bitfld.long 0x00 31. " POK_GATERST_EN_SEL        ,Select POK reset gating enable source" "0,1"
bitfld.long 0x00 30. "         FINAL_DELAY_SEL           ,Selects the reset output delay" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " V3P3_POK_GATERST_EN       ,Enable 3.3 volt voltage POK detection reset gating" "0,1"
bitfld.long 0x00 20. "         V1P8_POK_GATERST_EN       ,Enable 1.8 volt voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 19. " DDRIO_POK_GATERST_EN      ,Enable DDRIO voltage POK detection reset gating" "0,1"
bitfld.long 0x00 18. "         MPU1_POK_GATERST_EN       ,Enable MPU1 core voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 17. " MPU0_POK_GATERST_EN       ,Enable MPU0 core voltage POK detection reset gating" "0,1"
bitfld.long 0x00 16. "         MAIN_CORE_POK_GATERST_EN  ,Enable MAIN core voltage POK detection reset gating" "0,1"
textline "                                                     "
bitfld.long 0x00 15. " POK_EN_SEL                ,Select POK enable source" "0,1"
bitfld.long 0x00 5. "         V3P3_POK_EN               ,Enable 3.3 volt voltage POK detection" "0,1"
textline "                                                     "
bitfld.long 0x00 4. " V1P8_POK_EN               ,Enable 1.8 volt voltage POK detection" "0,1"
bitfld.long 0x00 3. "         DDRIO_POK_EN              ,Enable DDR IO voltage POK detection" "0,1"
textline "                                                     "
bitfld.long 0x00 2. " MPU1_POK_EN               ,Enable MPU1 voltage POK detection" "0,1"
bitfld.long 0x00 1. "         MPU0_POK_EN               ,Enable MPU0 voltage POK detection" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " MAIN_CORE_POK_EN          ,Enable MAIN core voltage POK detection" "0,1"
rgroup.long 0x1810C++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_PRG_STAT,Provides MAIN domain PRG controller status."
bitfld.long 0x00 5. " V3P3_POK                  ,3.3 volt voltage POK" "0,1"
bitfld.long 0x00 4. "         V1P8_POK                  ,1.8 volt voltage POK" "0,1"
textline "                                                     "
bitfld.long 0x00 3. " DDRIO_POK                 ,DDR IO voltage POK" "0,1"
bitfld.long 0x00 2. "         MPU1_POK                  ,MPU1 voltage POK" "0,1"
textline "                                                     "
bitfld.long 0x00 1. " MPU0_POK                  ,MPU0 voltage POK" "0,1"
bitfld.long 0x00 0. "         MAIN_CORE_POK             ,MAIN core voltage POK" "0,1"
group.long 0x18110++0x3
line.long 0x00 "CTRLMMR_WKUP_POK1P5V2_MAIN_CORE_VDD_CTRL,Controls operation of the MAIN (1V) core voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18114++0x3
line.long 0x00 "CTRLMMR_WKUP_POK1P5V3_MPU0_VDD_CTRL,Controls operation of the MPU0 (1V) voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18118++0x3
line.long 0x00 "CTRLMMR_WKUP_POK1P5V4_MPU1_VDD_CTRL,Controls operation of the MPU1 (1V) voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x1811C++0x3
line.long 0x00 "CTRLMMR_WKUP_POK1P5V5_DDRIO_VDDS_CTRL,Controls operation of the DDR IO voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18120++0x3
line.long 0x00 "CTRLMMR_WKUP_POK3P3V2_MAIN_1P8IO_VDDS_CTRL,Controls operation of the MAIN 1.8 volt IO voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18124++0x3
line.long 0x00 "CTRLMMR_WKUP_POK3P3V3_MAIN_3P3IO_VDDS_CTRL,Controls operation of the MAIN 3.3 volt IO voltage POK module."
bitfld.long 0x00 31. " HYST_EN                   ,Enable POK hysteresis" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TRIM_RSVD                 ,Reserved trim bits."
textline "                                                     "
bitfld.long 0x00 7. " OVER_VOLT_DET             ,Over / under voltage detection mode" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         POK_TRIM                  ,POK trim bits. These bits are used to trim the comparator threshold voltage. Trim granularity is dependent on hyst_en and pok_trim bit settings. See POK spec and Maxwell efuse spec for details"
group.long 0x18170++0x3
line.long 0x00 "CTRLMMR_WKUP_POR_RST_CTRL,Controls power-on reset propagation to the MAIN domain. This allows the DMSC to ensure that the MCU domain is properly isolated before the MAIN domain is reset."
bitfld.long 0x00 31. " SOC_PORZ_MMR              ,Cleared by DMSC after isolation sequence completion to force SOC_PORz assertion. This bit is set to '1' by CHIP_1_RST_n." "0,1"
bitfld.long 0x00 8. "         POR_SOC_GATE_Z            ,Active low signal. Gates propogation of PORz_WKUP to MAIN PRG" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " POR_RST_ISO_DONE_Z        ,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete." "0,1"
group.long 0x18174++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_WARM_RST_CTRL,Controls warm reset propagation to the MAIN domain. This allows the DMSC to ensure that the MCU domain is properly isolated before the MAIN domain is reset."
bitfld.long 0x00 31. " SOC_WARMRST_Z_MMR         ,Cleared by DMSC after isolation sequence completion to force SOC_RESETz assertion. This bit is set to '1' on CHIP_1_RST_n." "0,1"
bitfld.long 0x00 16. "         SW_WARMRST_Z              ,Cleared by software to issue a warm reset to the Main Domain. (Bit will set on reset of the Main Domain)" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " SOC_WARMRST_ISO_DONE_Z    ,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete." "0,1"
rgroup.long 0x18178++0x3
line.long 0x00 "CTRLMMR_WKUP_MAIN_RST_STAT,Shows the reset status of the MAIN domain."
bitfld.long 0x00 0. " MAIN_RST_DONE             ,Indicates MAIN domain reset status." "0,1"
group.long 0x1817C++0x3
line.long 0x00 "CTRLMMR_WKUP_MCU_WARM_RST_CTRL,Controls warm reset propagation to the MCU domain. This allows the DMSC to ensure that the WKUP domain is properly isolated before the MCU domain is reset."
bitfld.long 0x00 31. " MCU_WARMRST_Z_MMR         ,Cleared by DMSC after isolation sequence completion to force MCU_RESETz assertion. This bit is set to '1' on CHIP_1_RST_n" "0,1"
bitfld.long 0x00 16. "         SW_WARMRST_Z              ,Cleared by software to issue a warm reset to the device (all domains). Bit will set on reset completion." "0,1"
textline "                                                     "
bitfld.long 0x00 0. " MCU_WARMRST_ISO_DONE_Z    ,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MCU domain is complete." "0,1"
group.long 0x18180++0x3
line.long 0x00 "CTRLMMR_WKUP_MPU0_GLDTC_CTRL,Controls the MPU cluster0 voltage glitch detector circuit monitoring the VD_MPU0 voltage domain."
bitfld.long 0x00 31. " GLITCH_EN                 ,Enable glitch detect" "0,1"
bitfld.long 0x00 30. "         GLITCH_OUT_EN             ,Output enable" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " GLITCH_RESET              ,When set, resets the glitch output latch" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         GLITCH_FILTER             ,Sets the glitch detector filter response. Only bits[3:0] are used. 0h - R = 70.4K, C = 15pF, Filter Corner = 161.42 KHz 11h - R = 66.0K, C = 15pF, Filter Corner = 172.17 KHz 22h - R = 61.6K, C = 15pF, Filter Corner = 184.47 KHz 23h - R = 57.2K, C = 15pF, Filter Corner = 198.66 KHz 44h - R = 52.8K, C = 15pF, Filter Corner = 215.22 KHz 55h - R = 48.4K, C = 15pF, Filter Corner = 234.78 KHz 66h - R = 44.0K, C = 15pF, Filter Corner = 258.26 KHz 77h - R = 39.6K, C = 15pF, Filter Corner = 286.96 KHz 88h - R = 35.2K, C = 15pF, Filter Corner = 322.83 KHz 99h - R = 30.8K, C = 15pF, Filter Corner = 368.94 KHz AAh - R = 26.4K, C = 15pF, Filter Corner = 430.44 KHz BBh - R = 22.0K, C = 15pF, Filter Corner = 516.52 KHz CCh - R = 17.6K, C = 15pF, Filter Corner = 645.66 KHz EDh - R = 13.2K, C = 15pF, Filter Corner = 860.88 KHz EEh - R = 8.8K, C = 15pF, Filter Corner = 1290.00 KHz FFh - R = 4.4K, C = 15pF, Filter Corner = 2500.00 KHz"
textline "                                                     "
bitfld.long 0x00 15. " THRESH_LATCH              ,Glitch threshold latch. When low, the values in threshold_prog and pol_sel are latched by the Glitch Detector. The user must set thresh_latch back to 1." "0,1"
bitfld.long 0x00 6.--7. "         GLITCH_PRO_RSVD           ,Reserved for future use" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 5. " POL_SEL                   ,Selects the polarity of the glitch detection." "0,1"
bitfld.long 0x00 0.--4. "         THRESHOLD_PROG            ,Programs the glitch threshold as a percentage of the monitored voltage 0h - 0.0% difference from V_Core 1h - 0.2% difference from V_Core 2h - 0.4% difference from V_Core 3h - 0.8% difference from V_Core 4h - 1.2% difference from V_Core 5h - 1.6% difference from V_Core 6h - 2.0% difference from V_Core 7h - 2.8% difference from V_Core 8h - 3.6% difference from V_Core 9h - 4.0% difference from V_Core Ah - 4.4% difference from V_Core Bh - 4.8 % difference from V_Core Ch - 5.2% difference from V_Core Dh - 5.6% difference from V_Core Eh - 6.4% difference from V_Core Fh - 7.2% difference from V_Core 10h - 8.0% difference from V_Core 11h - 8.8% difference from V_Core 12h - 10.4% difference from V_Core 13h - 12.0% difference from V_Core 14h - 14.4% difference from V_Core 15h - 16.8% difference from V_Core 16h - 20.8% difference from V_Core 17h - 30.4% difference from V_Core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18184++0x3
line.long 0x00 "CTRLMMR_WKUP_MPU1_GLDTC_CTRL,Controls the MPU cluster1 voltage glitch detector circuit monitoring the VD_MPU1 voltage domain."
bitfld.long 0x00 31. " GLITCH_EN                 ,Enable glitch detect" "0,1"
bitfld.long 0x00 30. "         GLITCH_OUT_EN             ,Output enable" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " GLITCH_RESET              ,When set, resets the glitch output latch" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         GLITCH_FILTER             ,Sets the glitch detector filter response. Only bits[3:0] are used. 0h - R = 70.4K, C = 15pF, Filter Corner = 161.42 KHz 11h - R = 66.0K, C = 15pF, Filter Corner = 172.17 KHz 22h - R = 61.6K, C = 15pF, Filter Corner = 184.47 KHz 23h - R = 57.2K, C = 15pF, Filter Corner = 198.66 KHz 44h - R = 52.8K, C = 15pF, Filter Corner = 215.22 KHz 55h - R = 48.4K, C = 15pF, Filter Corner = 234.78 KHz 66h - R = 44.0K, C = 15pF, Filter Corner = 258.26 KHz 77h - R = 39.6K, C = 15pF, Filter Corner = 286.96 KHz 88h - R = 35.2K, C = 15pF, Filter Corner = 322.83 KHz 99h - R = 30.8K, C = 15pF, Filter Corner = 368.94 KHz AAh - R = 26.4K, C = 15pF, Filter Corner = 430.44 KHz BBh - R = 22.0K, C = 15pF, Filter Corner = 516.52 KHz CCh - R = 17.6K, C = 15pF, Filter Corner = 645.66 KHz EDh - R = 13.2K, C = 15pF, Filter Corner = 860.88 KHz EEh - R = 8.8K, C = 15pF, Filter Corner = 1290.00 KHz FFh - R = 4.4K, C = 15pF, Filter Corner = 2500.00 KHz"
textline "                                                     "
bitfld.long 0x00 15. " THRESH_LATCH              ,Glitch threshold latch. When low, the values in threshold_prog and pol_sel are latched by the Glitch Detector. The user must set thresh_latch back to 1." "0,1"
bitfld.long 0x00 6.--7. "         GLITCH_PRO_RSVD           ,Reserved for future use" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 5. " POL_SEL                   ,Selects the polarity of the glitch detection." "0,1"
bitfld.long 0x00 0.--4. "         THRESHOLD_PROG            ,Programs the glitch threshold as a percentage of the monitored voltage 0h - 0.0% difference from V_Core 1h - 0.2% difference from V_Core 2h - 0.4% difference from V_Core 3h - 0.8% difference from V_Core 4h - 1.2% difference from V_Core 5h - 1.6% difference from V_Core 6h - 2.0% difference from V_Core 7h - 2.8% difference from V_Core 8h - 3.6% difference from V_Core 9h - 4.0% difference from V_Core Ah - 4.4% difference from V_Core Bh - 4.8 % difference from V_Core Ch - 5.2% difference from V_Core Dh - 5.6% difference from V_Core Eh - 6.4% difference from V_Core Fh - 7.2% difference from V_Core 10h - 8.0% difference from V_Core 11h - 8.8% difference from V_Core 12h - 10.4% difference from V_Core 13h - 12.0% difference from V_Core 14h - 14.4% difference from V_Core 15h - 16.8% difference from V_Core 16h - 20.8% difference from V_Core 17h - 30.4% difference from V_Core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18190++0x3
line.long 0x00 "CTRLMMR_WKUP_CORE_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VD_CORE voltage domain."
bitfld.long 0x00 31. " GLITCH_EN                 ,Enable glitch detect" "0,1"
bitfld.long 0x00 30. "         GLITCH_OUT_EN             ,Output enable" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " GLITCH_RESET              ,When set, resets the glitch output latch" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         GLITCH_FILTER             ,Sets the glitch detector filter response. Only bits[3:0] are used. 0h - R = 70.4K, C = 15pF, Filter Corner = 161.42 KHz 11h - R = 66.0K, C = 15pF, Filter Corner = 172.17 KHz 22h - R = 61.6K, C = 15pF, Filter Corner = 184.47 KHz 23h - R = 57.2K, C = 15pF, Filter Corner = 198.66 KHz 44h - R = 52.8K, C = 15pF, Filter Corner = 215.22 KHz 55h - R = 48.4K, C = 15pF, Filter Corner = 234.78 KHz 66h - R = 44.0K, C = 15pF, Filter Corner = 258.26 KHz 77h - R = 39.6K, C = 15pF, Filter Corner = 286.96 KHz 88h - R = 35.2K, C = 15pF, Filter Corner = 322.83 KHz 99h - R = 30.8K, C = 15pF, Filter Corner = 368.94 KHz AAh - R = 26.4K, C = 15pF, Filter Corner = 430.44 KHz BBh - R = 22.0K, C = 15pF, Filter Corner = 516.52 KHz CCh - R = 17.6K, C = 15pF, Filter Corner = 645.66 KHz EDh - R = 13.2K, C = 15pF, Filter Corner = 860.88 KHz EEh - R = 8.8K, C = 15pF, Filter Corner = 1290.00 KHz FFh - R = 4.4K, C = 15pF, Filter Corner = 2500.00 KHz"
textline "                                                     "
bitfld.long 0x00 15. " THRESH_LATCH              ,Glitch threshold latch. When low, the values in threshold_prog and pol_sel are latched by the Glitch Detector. The user must set thresh_latch back to 1." "0,1"
bitfld.long 0x00 6.--7. "         GLITCH_PRO_RSVD           ,Reserved for future use" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 5. " POL_SEL                   ,Selects the polarity of the glitch detection." "0,1"
bitfld.long 0x00 0.--4. "         THRESHOLD_PROG            ,Programs the glitch threshold as a percentage of the monitored voltage 0h - 0.0% difference from V_Core 1h - 0.2% difference from V_Core 2h - 0.4% difference from V_Core 3h - 0.8% difference from V_Core 4h - 1.2% difference from V_Core 5h - 1.6% difference from V_Core 6h - 2.0% difference from V_Core 7h - 2.8% difference from V_Core 8h - 3.6% difference from V_Core 9h - 4.0% difference from V_Core Ah - 4.4% difference from V_Core Bh - 4.8 % difference from V_Core Ch - 5.2% difference from V_Core Dh - 5.6% difference from V_Core Eh - 6.4% difference from V_Core Fh - 7.2% difference from V_Core 10h - 8.0% difference from V_Core 11h - 8.8% difference from V_Core 12h - 10.4% difference from V_Core 13h - 12.0% difference from V_Core 14h - 14.4% difference from V_Core 15h - 16.8% difference from V_Core 16h - 20.8% difference from V_Core 17h - 30.4% difference from V_Core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x181A0++0x3
line.long 0x00 "CTRLMMR_WKUP_MPU0_GLDTC_STAT,Shows the status of the MPU cluster0 voltage glitch detector circuit monitoring the VD_MPU0 voltage domain."
bitfld.long 0x00 7. " GLITCH_POL                ,Glitch polarity output" "0,1"
bitfld.long 0x00 4. "         GLITCH_COMP               ,(Unlatched) output of the internal glitch comparator" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " GLITCH_DETECT             ,Glitch output latch value" "0,1"
rgroup.long 0x181A4++0x3
line.long 0x00 "CTRLMMR_WKUP_MPU1_GLDTC_STAT,Shows the status of the MPU cluster1 voltage glitch detector circuit monitoring the VD_MPU1 voltage domain."
bitfld.long 0x00 7. " GLITCH_POL                ,Glitch polarity output" "0,1"
bitfld.long 0x00 4. "         GLITCH_COMP               ,(Unlatched) output of the internal glitch comparator" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " GLITCH_DETECT             ,Glitch output latch value" "0,1"
rgroup.long 0x181B0++0x3
line.long 0x00 "CTRLMMR_WKUP_CORE_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VD_CORE voltage domain."
bitfld.long 0x00 7. " GLITCH_POL                ,Glitch polarity output" "0,1"
bitfld.long 0x00 4. "         GLITCH_COMP               ,(Unlatched) output of the internal glitch comparator" "0,1"
textline "                                                     "
bitfld.long 0x00 0. " GLITCH_DETECT             ,Glitch output latch value" "0,1"
group.long 0x19008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK6_KICK0,Lower 32-bits of Partition6 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0x1900C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK6_KICK1,Upper 32-bits of Partition 6 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 6 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers"
group.long 0x1C000++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG0,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C004++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG1,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C008++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG2,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C00C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG3,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C010++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG4,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C014++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG5,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C018++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG6,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C01C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG7,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C020++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG8,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C024++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG9,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C028++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG10,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C02C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG11,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C030++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG12,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C034++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG13,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C038++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG14,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C03C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG15,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C040++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG16,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C044++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG17,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C048++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG18,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C04C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG19,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C050++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG20,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C054++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG21,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C058++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG22,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C05C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG23,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C060++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG24,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C064++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG25,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C068++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG26,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C06C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG27,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C070++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG28,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C074++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG29,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C078++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG30,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C07C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG31,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C080++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG32,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C084++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG33,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C088++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG34,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C08C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG35,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C090++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG36,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C094++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG37,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C098++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG38,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C09C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG39,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG40,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG41,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0A8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG42,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0AC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG43,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG44,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG45,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0B8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG46,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0BC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG47,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG48,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG49,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0C8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG50,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0CC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG51,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG52,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG53,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0D8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG54,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0DC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG55,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG56,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG57,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0E8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG58,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0EC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG59,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F0++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG60,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F4++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG61,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0F8++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG62,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C0FC++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG63,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C100++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG64,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C104++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG65,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C108++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG66,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C10C++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG67,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C110++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG68,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C114++0x3
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG69,Register to control pin configuration and muxing."
bitfld.long 0x00 31. " LOCK                      ,Lock" "0,1"
bitfld.long 0x00 30. "         WKUP_EVT                  ,Wakeup event status" "0,1"
textline "                                                     "
bitfld.long 0x00 29. " WKUP_EN                   ,Wakeup enable" "0,1"
bitfld.long 0x00 28. "         DS_PULLTYPE_SEL           ,Deep Sleep 0 mode pull-up/down selection" "0,1"
textline "                                                     "
bitfld.long 0x00 27. " DS_PULLUD_EN              ,Deep Sleep 0 mode pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "         DSOUT_VAL                 ,Deep Sleep 0 mode output value" "0,1"
textline "                                                     "
bitfld.long 0x00 25. " DSOUT_DIS                 ,Deep Sleep 0 mode output enable" "0,1"
bitfld.long 0x00 24. "         DS_EN                     ,Deep Sleep 0 mode override control" "0,1"
textline "                                                     "
bitfld.long 0x00 23. " ISO_BYP                   ,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "         ISO_OVR                   ,Isolation Override" "0,1"
textline "                                                     "
bitfld.long 0x00 21. " TX_DIS                    ,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "         SLEWRATE                  ,Slew rate control selection (CS1, CS0) 0h - 200 MHz 1h - 150 MHz 2h - 100 MHz 3h - 50 MHz" "0,1,2,3"
textline "                                                     "
bitfld.long 0x00 18. " RXACTIVE                  ,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "         PULLTYPESEL               ,Pad Pullup / Pulldown type selection" "0,1"
textline "                                                     "
bitfld.long 0x00 16. " PULLUDEN                  ,Pad Pullup / Pulldown enable. This is an active low signal." "0,1"
bitfld.long 0x00 15. "         FORCE_DS_EN               ,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
textline "                                                     "
bitfld.long 0x00 0.--3. " MUXMODE                   ,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1D008++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK7_KICK0,Lower 32-bits of Partition7 write lock key. This register must be written with the designated key value followed by a write to with its key value before write-protected Partition 7 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY                       ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
bitfld.long 0x00 0. "  UNLOCKED                  ,Unlock status." "0,1"
group.long 0x1D00C++0x3
line.long 0x00 "CTRLMMR_WKUP_LOCK7_KICK1,Upper 32-bits of Partition 7 write lock key. This register must be written with the designated key value after a write to with its key value before write-protected Partition 7 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY                       ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers"
width 0x0B
tree.end
tree.end
tree "Compute_Cluster"
tree "COMPUTE_CLUSTER0_DMSC_BOOT"
base ad:0x45A00000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "CC_REVISION,Compute Cluster Revision Register"
hexmask.long 0x00 0.--31. 1. " REV                  ,TI internal data."
rgroup.long 0x4++0x3
line.long 0x00 "CC_MSMC_DEF,MSMC Definition Register"
hexmask.long.byte 0x00 0.--7. 1. " NUM_COREPAC          ,Denotes the number of corepacs connected to compute cluster.1h - Two corepacs"
group.long 0x8++0x3
line.long 0x00 "CC_GIC_CONFIG,GIC Configuration Register. GIC0 has input signals cpu_active_X_N (where X = CC_ARMSS number; N = Core number) which indicate when a core is active and available for routing SPIs unlike being in a software-transparent low-power mode in which case SPIs are not routed to, and a core wake-up would result in increased power consumption."
bitfld.long 0x00 12.--15. " CP1_CPU_ACTIVE       ,CC_ARMSS1 Cores activeBits [15-14]: ReservedBit [13]:0h - CC_ARMSS1 Core 1 is in software-transparent low-power mode such as retention1h - CC_ARMSS1 Core1 is active and available for shared SPIsBit [12]:0h - CC_ARMSS1 Core 0 is in software-transparent low-power mode such as retention1h - CC_ARMSS1 Core0 is active and available for shared SPIs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        CP0_CPU_ACTIVE   ,CC_ARMSS0 Cores activeBits [11-10]: ReservedBit [9]:0h - CC_ARMSS0 Core 1 is in software-transparent low-power mode such as retention1h - CC_ARMSS0 Core 1 is active and available for shared SPIsBit [8]:0h - CC_ARMSS0 Core 0 is in software-transparent low-power mode such as retention1h - CC_ARMSS0 Core 0 is active and available for shared SPIs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0. " GIC_SECURE           ,Not used on this SoC" "0,1"
rgroup.long 0x1000++0x3
line.long 0x00 "CC_DEF_j,Compute Cluster Definition Register for CC_ARMSSj Offset = 1000h*(j + 1); where j = 0h to 1h"
bitfld.long 0x00 24.--27. " SRAM_SIZE            ,SRAM size (if present in the corepac)0h - 0 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--17. "        NUM_CORES        ,Number of cores in the corepac (CC_ARMSSj)0h - One core1h - Two cores2h - Four cores3h - Reserved" "0,1,2,3"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " COREPAC_TYPE_DSP     ,Not used on this SoC"
hexmask.long.byte 0x00 0.--7. 1. "        COREPAC_TYPE_ARM ,MSMC port 'j' configuration0h - A53 corepac connected to MSMC port 'j'1h to FEh - ReservedFFh - Port not used for ARM"
group.long 0x1004++0x3
line.long 0x00 "CC_CP_CONFIG_j,Compute Cluster Configuration Register for CC_ARMSSj Offset = 1004h*(j + 1); where j = 0h to 1h"
bitfld.long 0x00 31. " ENDIAN               ,Not used on this SoC" "0,1"
bitfld.long 0x00 25.--28. "         L2ACCESS_LAT     ,Not used on this SoC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 21.--24. " L2PIPELINE_LAT       ,Not used on this SoC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        CP15DISABLE      ,Disable write access to some secure CP15 registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " CONFIGTE             ,Enable T32 exceptions. It sets the initial value of the TE bit in the CP15 SCTLR register. This pin is sampled only during reset of the processor.Bits [7-6]: ReservedBit [5]:0h - TE bit is LOW for core 1 of CC_ARMSSj1h - TE bit is HIGH for core 1 of CC_ARMSSjBit [4]:0h - TE bit is LOW for core 0 of CC_ARMSSj1h - TE bit is HIGH for core 0 of CC_ARMSSj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        AARCH            ,ARM Architecture (Valid only for ARM corepacs)Bits [3-2]: ReservedBit [1]:0h - AArch32 for core 1 of CC_ARMSSj1h - AArch64 for core 1 of CC_ARMSSjBit [0]:0h - AArch32 for core 0 of CC_ARMSSj1h - AArch64 for core 0 of CC_ARMSSj" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1008++0x3
line.long 0x00 "CC_RST_VEC_LO_CP0_j,Core 0 Boot Vector Register (Low) for CC_ARMSSj Offset = 1008h*(j + 1); where j = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " RESET_BASE_VECTOR_LO ,Low reset base vector (bits [33-2]) for Core 0 of CC_ARMSSj"
group.long 0x100C++0x3
line.long 0x00 "CC_RST_VEC_HI_CP0_j,Core 0 Boot Vector Register (High) for CC_ARMSSj Offset = 100Ch*(j + 1); where j = 0h to 1h"
hexmask.long.tbyte 0x00 0.--16. 1. " RESET_BASE_VECTOR_HI ,High reset base vector (bits [39-34]) for Core 0 of CC_ARMSSj"
group.long 0x1010++0x3
line.long 0x00 "CC_RST_VEC_LO_CP1_j,Core 1 Boot Vector Register (Low) for CC_ARMSSj Offset = 1010h*(j + 1); where j = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " RESET_BASE_VECTOR_LO ,Low reset base vector (bits [33-2]) for Core 1 of CC_ARMSSj"
group.long 0x1014++0x3
line.long 0x00 "CC_RST_VEC_HI_CP1_j,Core 1 Boot Vector Register (High) for CC_ARMSSj Offset = 1014h*(j + 1); where j = 0h to 1h"
hexmask.long.tbyte 0x00 0.--16. 1. " RESET_BASE_VECTOR_HI ,High reset base vector (bits [39-34]) for Core 1 of CC_ARMSSj"
group.long 0x1028++0x3
line.long 0x00 "CC_PM_CONFIG_j,Power Management Configuration Register for CC_ARMSSj Offset = 1028h*(j + 1); where j = 0h to 1h"
bitfld.long 0x00 8.--11. " DBGPWRUP0            ,Core power upBits [11-10]: ReservedBit [9]:0h - CC_ARMSSj Core 1 is powered down1h - CC_ARMSSj Core 1 is powered upBit [8]:0h - CC_ARMSSj Core 0 is powered down1h - CC_ARMSSj Core 0 is powered up" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        DBGL1RSTDISABLE0 ,Disable L1 data cache automatic invalidate on reset. This pin is sampled only during reset of the processor.0h - Enable automatic invalidation of L1 data cache on reset1h - Disable automatic invalidation of L1 data cache on reset" "0,1"
textline "                              "
bitfld.long 0x00 6. " CLEAR_MON0           ,Request to clear the external global exclusive monitor. This sends a WFE wake-up event to all cores in the cluster. When set HIGH the global exclusive monitor in the system is requesting the processor EVENT registers to be set HIGH." "0,1"
bitfld.long 0x00 5. "         L2_FLUSHREQ0     ,ARM L2 hardware flush request" "0,1"
textline "                              "
bitfld.long 0x00 4. " BROADCAST_INNER0     ,Enable broadcasting of inner shareable and outer sharable transactions0h - Broadcasting disabled1h - Broadcasting enabled" "0,1"
bitfld.long 0x00 3. "         CACHE_BROADCAST0 ,Enable Broadcasting of cache maintenance transactions0h - Broadcasting disabled1h - Broadcasting enabled" "0,1"
textline "                              "
bitfld.long 0x00 2. " SYS_BARR0            ,Disable broadcasting of barriers0h - Broadcasting enabled1h - Broadcasting disabled" "0,1"
bitfld.long 0x00 1. "         ACP_MASTER0      ,ACP master is inactive and is not participating in coherency0h - ACP Master is active1h - ACP Master is inactiveNOTE: There must be no outstanding transactions when the master asserts this signal, and while it is asserted the master must not send any new transactions" "0,1"
textline "                              "
bitfld.long 0x00 0. " SNOOP_IF0            ,Snoop interface is inactive and not participating in coherency0h - Snoop interface is active1h - Snoop interface is inactive" "0,1"
rgroup.long 0x102C++0x3
line.long 0x00 "CC_PM_STATUS_j,Power Management Status Register for CC_ARMSSj Offset = 102Ch*(j + 1); where j = 0h to 1h"
bitfld.long 0x00 14. " CLEAR_MONITOR_ACK0   ,Clearing of the external global exclusive monitor acknowledge. When set HIGH the processor EVENT registers have been set HIGH." "0,1"
bitfld.long 0x00 13. "         STANDBY_WFI_L20  ,L2 in WFI low power state indication" "0,1"
textline "                              "
bitfld.long 0x00 12. " L2_HW_FLUSH0         ,L2 hardware flush complete" "0,1"
bitfld.long 0x00 8.--10. "         SMPEN0           ,Corepac taking part in coherency indication" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 7. " CPU3_WFE0            ,Reserved" "0,1"
bitfld.long 0x00 6. "         CPU2_WFE0        ,Reserved" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU1_WFE0            ,CPU in WFE state" "0,1"
bitfld.long 0x00 4. "         CPU0_WFE0        ,CPU in WFE state" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU3_WFI0            ,Reserved" "0,1"
bitfld.long 0x00 2. "         CPU2_WFI0        ,Reserved" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU1_WFI0            ,CPU in WFI state" "0,1"
bitfld.long 0x00 0. "         CPU0_WFI0        ,CPU in WFI state" "0,1"
width 0x0B
tree.end
tree.end
tree "DRU"
tree "COMPUTE_CLUSTER0_DRU"
base ad:0x6D000000
width 27.
rgroup.quad 0x0++0x7
line.quad 0x00 "DRU_PID,Peripheral ID Register"
hexmask.quad.long 0x00 32.--63. 1. " RSVD              ,"
hexmask.quad.long 0x00 0.--31. 1. "          REVISION        ,"
rgroup.quad 0x8++0x7
line.quad 0x00 "DRU_CAPABILITIES,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions"
hexmask.quad.tbyte 0x00 46.--63. 1. " RSVD              ,"
bitfld.quad 0x00 42.--45. "            SECTR           ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.quad 0x00 39.--41. " DFMT              ," "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 35.--38. "                 ELTYPE          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.quad 0x00 32.--34. " AMODE             ," "0,1,2,3,4,5,6,7"
hexmask.quad.word 0x00 20.--31. 1. "                 RSVD_CONF_SPEC  ,"
textline "                                            "
bitfld.quad 0x00 19. " GLOBAL_TRIG       ," "0,1"
bitfld.quad 0x00 18. "                 LOCAL_TRIG      ," "0,1"
textline "                                            "
bitfld.quad 0x00 17. " EOL               ," "0,1"
bitfld.quad 0x00 16. "                 TRSTATIC        ," "0,1"
textline "                                            "
bitfld.quad 0x00 15. " TYPE15            ," "0,1"
bitfld.quad 0x00 14. "                 TYPE14          ," "0,1"
textline "                                            "
bitfld.quad 0x00 13. " TYPE13            ," "0,1"
bitfld.quad 0x00 12. "                 TYPE12          ," "0,1"
textline "                                            "
bitfld.quad 0x00 11. " TYPE11            ," "0,1"
bitfld.quad 0x00 10. "                 TYPE10          ," "0,1"
textline "                                            "
bitfld.quad 0x00 9. " TYPE9             ," "0,1"
bitfld.quad 0x00 8. "                 TYPE8           ," "0,1"
textline "                                            "
bitfld.quad 0x00 7. " TYPE7             ," "0,1"
bitfld.quad 0x00 6. "                 TYPE6           ," "0,1"
textline "                                            "
bitfld.quad 0x00 5. " TYPE5             ," "0,1"
bitfld.quad 0x00 4. "                 TYPE4           ," "0,1"
textline "                                            "
bitfld.quad 0x00 3. " TYPE3             ," "0,1"
bitfld.quad 0x00 2. "                 TYPE2           ," "0,1"
textline "                                            "
bitfld.quad 0x00 1. " TYPE1             ," "0,1"
bitfld.quad 0x00 0. "                 TYPE0           ," "0,1"
group.quad 0x4000++0x7
line.quad 0x00 "DRU_SHARED_EVT_SET,DRU Shared Event Set Register"
hexmask.quad 0x00 1.--63. 1. " RSVD              ,"
bitfld.quad 0x00 0. "  PROT_ERR        ," "0,1"
wgroup.quad 0x4040++0x7
line.quad 0x00 "DRU_COMP_EVT_SET0,DRU Completion Event Set Register"
bitfld.quad 0x00 63. " COMP_EVT63        ," "0,1"
bitfld.quad 0x00 62. "                 COMP_EVT62      ," "0,1"
textline "                                            "
bitfld.quad 0x00 61. " COMP_EVT61        ," "0,1"
bitfld.quad 0x00 60. "                 COMP_EVT60      ," "0,1"
textline "                                            "
bitfld.quad 0x00 59. " COMP_EVT59        ," "0,1"
bitfld.quad 0x00 58. "                 COMP_EVT58      ," "0,1"
textline "                                            "
bitfld.quad 0x00 57. " COMP_EVT57        ," "0,1"
bitfld.quad 0x00 56. "                 COMP_EVT56      ," "0,1"
textline "                                            "
bitfld.quad 0x00 55. " COMP_EVT55        ," "0,1"
bitfld.quad 0x00 54. "                 COMP_EVT54      ," "0,1"
textline "                                            "
bitfld.quad 0x00 53. " COMP_EVT53        ," "0,1"
bitfld.quad 0x00 52. "                 COMP_EVT52      ," "0,1"
textline "                                            "
bitfld.quad 0x00 51. " COMP_EVT51        ," "0,1"
bitfld.quad 0x00 50. "                 COMP_EVT50      ," "0,1"
textline "                                            "
bitfld.quad 0x00 49. " COMP_EVT49        ," "0,1"
bitfld.quad 0x00 48. "                 COMP_EVT48      ," "0,1"
textline "                                            "
bitfld.quad 0x00 47. " COMP_EVT47        ," "0,1"
bitfld.quad 0x00 46. "                 COMP_EVT46      ," "0,1"
textline "                                            "
bitfld.quad 0x00 45. " COMP_EVT45        ," "0,1"
bitfld.quad 0x00 44. "                 COMP_EVT44      ," "0,1"
textline "                                            "
bitfld.quad 0x00 43. " COMP_EVT43        ," "0,1"
bitfld.quad 0x00 42. "                 COMP_EVT42      ," "0,1"
textline "                                            "
bitfld.quad 0x00 41. " COMP_EVT41        ," "0,1"
bitfld.quad 0x00 40. "                 COMP_EVT40      ," "0,1"
textline "                                            "
bitfld.quad 0x00 39. " COMP_EVT39        ," "0,1"
bitfld.quad 0x00 38. "                 COMP_EVT38      ," "0,1"
textline "                                            "
bitfld.quad 0x00 37. " COMP_EVT37        ," "0,1"
bitfld.quad 0x00 36. "                 COMP_EVT36      ," "0,1"
textline "                                            "
bitfld.quad 0x00 35. " COMP_EVT35        ," "0,1"
bitfld.quad 0x00 34. "                 COMP_EVT34      ," "0,1"
textline "                                            "
bitfld.quad 0x00 33. " COMP_EVT33        ," "0,1"
bitfld.quad 0x00 32. "                 COMP_EVT32      ," "0,1"
textline "                                            "
bitfld.quad 0x00 31. " COMP_EVT31        ," "0,1"
bitfld.quad 0x00 30. "                 COMP_EVT30      ," "0,1"
textline "                                            "
bitfld.quad 0x00 29. " COMP_EVT29        ," "0,1"
bitfld.quad 0x00 28. "                 COMP_EVT28      ," "0,1"
textline "                                            "
bitfld.quad 0x00 27. " COMP_EVT27        ," "0,1"
bitfld.quad 0x00 26. "                 COMP_EVT26      ," "0,1"
textline "                                            "
bitfld.quad 0x00 25. " COMP_EVT25        ," "0,1"
bitfld.quad 0x00 24. "                 COMP_EVT24      ," "0,1"
textline "                                            "
bitfld.quad 0x00 23. " COMP_EVT23        ," "0,1"
bitfld.quad 0x00 22. "                 COMP_EVT22      ," "0,1"
textline "                                            "
bitfld.quad 0x00 21. " COMP_EVT21        ," "0,1"
bitfld.quad 0x00 20. "                 COMP_EVT20      ," "0,1"
textline "                                            "
bitfld.quad 0x00 19. " COMP_EVT19        ," "0,1"
bitfld.quad 0x00 18. "                 COMP_EVT18      ," "0,1"
textline "                                            "
bitfld.quad 0x00 17. " COMP_EVT17        ," "0,1"
bitfld.quad 0x00 16. "                 COMP_EVT16      ," "0,1"
textline "                                            "
bitfld.quad 0x00 15. " COMP_EVT15        ," "0,1"
bitfld.quad 0x00 14. "                 COMP_EVT14      ," "0,1"
textline "                                            "
bitfld.quad 0x00 13. " COMP_EVT13        ," "0,1"
bitfld.quad 0x00 12. "                 COMP_EVT12      ," "0,1"
textline "                                            "
bitfld.quad 0x00 11. " COMP_EVT11        ," "0,1"
bitfld.quad 0x00 10. "                 COMP_EVT10      ," "0,1"
textline "                                            "
bitfld.quad 0x00 9. " COMP_EVT9         ," "0,1"
bitfld.quad 0x00 8. "                 COMP_EVT8       ," "0,1"
textline "                                            "
bitfld.quad 0x00 7. " COMP_EVT7         ," "0,1"
bitfld.quad 0x00 6. "                 COMP_EVT6       ," "0,1"
textline "                                            "
bitfld.quad 0x00 5. " COMP_EVT5         ," "0,1"
bitfld.quad 0x00 4. "                 COMP_EVT4       ," "0,1"
textline "                                            "
bitfld.quad 0x00 3. " COMP_EVT3         ," "0,1"
bitfld.quad 0x00 2. "                 COMP_EVT2       ," "0,1"
textline "                                            "
bitfld.quad 0x00 1. " COMP_EVT1         ," "0,1"
bitfld.quad 0x00 0. "                 COMP_EVT0       ," "0,1"
wgroup.quad 0x4080++0x7
line.quad 0x00 "DRU_ERR_EVT_SET0,DRU Error Event Set Register"
bitfld.quad 0x00 63. " ERR_EVT63         ," "0,1"
bitfld.quad 0x00 62. "                 ERR_EVT62       ," "0,1"
textline "                                            "
bitfld.quad 0x00 61. " ERR_EVT61         ," "0,1"
bitfld.quad 0x00 60. "                 ERR_EVT60       ," "0,1"
textline "                                            "
bitfld.quad 0x00 59. " ERR_EVT59         ," "0,1"
bitfld.quad 0x00 58. "                 ERR_EVT58       ," "0,1"
textline "                                            "
bitfld.quad 0x00 57. " ERR_EVT57         ," "0,1"
bitfld.quad 0x00 56. "                 ERR_EVT56       ," "0,1"
textline "                                            "
bitfld.quad 0x00 55. " ERR_EVT55         ," "0,1"
bitfld.quad 0x00 54. "                 ERR_EVT54       ," "0,1"
textline "                                            "
bitfld.quad 0x00 53. " ERR_EVT53         ," "0,1"
bitfld.quad 0x00 52. "                 ERR_EVT52       ," "0,1"
textline "                                            "
bitfld.quad 0x00 51. " ERR_EVT51         ," "0,1"
bitfld.quad 0x00 50. "                 ERR_EVT50       ," "0,1"
textline "                                            "
bitfld.quad 0x00 49. " ERR_EVT49         ," "0,1"
bitfld.quad 0x00 48. "                 ERR_EVT48       ," "0,1"
textline "                                            "
bitfld.quad 0x00 47. " ERR_EVT47         ," "0,1"
bitfld.quad 0x00 46. "                 ERR_EVT46       ," "0,1"
textline "                                            "
bitfld.quad 0x00 45. " ERR_EVT45         ," "0,1"
bitfld.quad 0x00 44. "                 ERR_EVT44       ," "0,1"
textline "                                            "
bitfld.quad 0x00 43. " ERR_EVT43         ," "0,1"
bitfld.quad 0x00 42. "                 ERR_EVT42       ," "0,1"
textline "                                            "
bitfld.quad 0x00 41. " ERR_EVT41         ," "0,1"
bitfld.quad 0x00 40. "                 ERR_EVT40       ," "0,1"
textline "                                            "
bitfld.quad 0x00 39. " ERR_EVT39         ," "0,1"
bitfld.quad 0x00 38. "                 ERR_EVT38       ," "0,1"
textline "                                            "
bitfld.quad 0x00 37. " ERR_EVT37         ," "0,1"
bitfld.quad 0x00 36. "                 ERR_EVT36       ," "0,1"
textline "                                            "
bitfld.quad 0x00 35. " ERR_EVT35         ," "0,1"
bitfld.quad 0x00 34. "                 ERR_EVT34       ," "0,1"
textline "                                            "
bitfld.quad 0x00 33. " ERR_EVT33         ," "0,1"
bitfld.quad 0x00 32. "                 ERR_EVT32       ," "0,1"
textline "                                            "
bitfld.quad 0x00 31. " ERR_EVT31         ," "0,1"
bitfld.quad 0x00 30. "                 ERR_EVT30       ," "0,1"
textline "                                            "
bitfld.quad 0x00 29. " ERR_EVT29         ," "0,1"
bitfld.quad 0x00 28. "                 ERR_EVT28       ," "0,1"
textline "                                            "
bitfld.quad 0x00 27. " ERR_EVT27         ," "0,1"
bitfld.quad 0x00 26. "                 ERR_EVT26       ," "0,1"
textline "                                            "
bitfld.quad 0x00 25. " ERR_EVT25         ," "0,1"
bitfld.quad 0x00 24. "                 ERR_EVT24       ," "0,1"
textline "                                            "
bitfld.quad 0x00 23. " ERR_EVT23         ," "0,1"
bitfld.quad 0x00 22. "                 ERR_EVT22       ," "0,1"
textline "                                            "
bitfld.quad 0x00 21. " ERR_EVT21         ," "0,1"
bitfld.quad 0x00 20. "                 ERR_EVT20       ," "0,1"
textline "                                            "
bitfld.quad 0x00 19. " ERR_EVT19         ," "0,1"
bitfld.quad 0x00 18. "                 ERR_EVT18       ," "0,1"
textline "                                            "
bitfld.quad 0x00 17. " ERR_EVT17         ," "0,1"
bitfld.quad 0x00 16. "                 ERR_EVT16       ," "0,1"
textline "                                            "
bitfld.quad 0x00 15. " ERR_EVT15         ," "0,1"
bitfld.quad 0x00 14. "                 ERR_EVT14       ," "0,1"
textline "                                            "
bitfld.quad 0x00 13. " ERR_EVT13         ," "0,1"
bitfld.quad 0x00 12. "                 ERR_EVT12       ," "0,1"
textline "                                            "
bitfld.quad 0x00 11. " ERR_EVT11         ," "0,1"
bitfld.quad 0x00 10. "                 ERR_EVT10       ," "0,1"
textline "                                            "
bitfld.quad 0x00 9. " ERR_EVT9          ," "0,1"
bitfld.quad 0x00 8. "                 ERR_EVT8        ," "0,1"
textline "                                            "
bitfld.quad 0x00 7. " ERR_EVT7          ," "0,1"
bitfld.quad 0x00 6. "                 ERR_EVT6        ," "0,1"
textline "                                            "
bitfld.quad 0x00 5. " ERR_EVT5          ," "0,1"
bitfld.quad 0x00 4. "                 ERR_EVT4        ," "0,1"
textline "                                            "
bitfld.quad 0x00 3. " ERR_EVT3          ," "0,1"
bitfld.quad 0x00 2. "                 ERR_EVT2        ," "0,1"
textline "                                            "
bitfld.quad 0x00 1. " ERR_EVT1          ," "0,1"
bitfld.quad 0x00 0. "                 ERR_EVT0        ," "0,1"
wgroup.quad 0x40C0++0x7
line.quad 0x00 "DRU_LOCAL_EVT_SET0,DRU Local Event Set Register"
bitfld.quad 0x00 63. " COMP_EVT63        ," "0,1"
bitfld.quad 0x00 62. "                 COMP_EVT62      ," "0,1"
textline "                                            "
bitfld.quad 0x00 61. " COMP_EVT61        ," "0,1"
bitfld.quad 0x00 60. "                 COMP_EVT60      ," "0,1"
textline "                                            "
bitfld.quad 0x00 59. " COMP_EVT59        ," "0,1"
bitfld.quad 0x00 58. "                 COMP_EVT58      ," "0,1"
textline "                                            "
bitfld.quad 0x00 57. " COMP_EVT57        ," "0,1"
bitfld.quad 0x00 56. "                 COMP_EVT56      ," "0,1"
textline "                                            "
bitfld.quad 0x00 55. " COMP_EVT55        ," "0,1"
bitfld.quad 0x00 54. "                 COMP_EVT54      ," "0,1"
textline "                                            "
bitfld.quad 0x00 53. " COMP_EVT53        ," "0,1"
bitfld.quad 0x00 52. "                 COMP_EVT52      ," "0,1"
textline "                                            "
bitfld.quad 0x00 51. " COMP_EVT51        ," "0,1"
bitfld.quad 0x00 50. "                 COMP_EVT50      ," "0,1"
textline "                                            "
bitfld.quad 0x00 49. " COMP_EVT49        ," "0,1"
bitfld.quad 0x00 48. "                 COMP_EVT48      ," "0,1"
textline "                                            "
bitfld.quad 0x00 47. " COMP_EVT47        ," "0,1"
bitfld.quad 0x00 46. "                 COMP_EVT46      ," "0,1"
textline "                                            "
bitfld.quad 0x00 45. " COMP_EVT45        ," "0,1"
bitfld.quad 0x00 44. "                 COMP_EVT44      ," "0,1"
textline "                                            "
bitfld.quad 0x00 43. " COMP_EVT43        ," "0,1"
bitfld.quad 0x00 42. "                 COMP_EVT42      ," "0,1"
textline "                                            "
bitfld.quad 0x00 41. " COMP_EVT41        ," "0,1"
bitfld.quad 0x00 40. "                 COMP_EVT40      ," "0,1"
textline "                                            "
bitfld.quad 0x00 39. " COMP_EVT39        ," "0,1"
bitfld.quad 0x00 38. "                 COMP_EVT38      ," "0,1"
textline "                                            "
bitfld.quad 0x00 37. " COMP_EVT37        ," "0,1"
bitfld.quad 0x00 36. "                 COMP_EVT36      ," "0,1"
textline "                                            "
bitfld.quad 0x00 35. " COMP_EVT35        ," "0,1"
bitfld.quad 0x00 34. "                 COMP_EVT34      ," "0,1"
textline "                                            "
bitfld.quad 0x00 33. " COMP_EVT33        ," "0,1"
bitfld.quad 0x00 32. "                 COMP_EVT32      ," "0,1"
textline "                                            "
bitfld.quad 0x00 31. " COMP_EVT31        ," "0,1"
bitfld.quad 0x00 30. "                 COMP_EVT30      ," "0,1"
textline "                                            "
bitfld.quad 0x00 29. " COMP_EVT29        ," "0,1"
bitfld.quad 0x00 28. "                 COMP_EVT28      ," "0,1"
textline "                                            "
bitfld.quad 0x00 27. " COMP_EVT27        ," "0,1"
bitfld.quad 0x00 26. "                 COMP_EVT26      ," "0,1"
textline "                                            "
bitfld.quad 0x00 25. " COMP_EVT25        ," "0,1"
bitfld.quad 0x00 24. "                 COMP_EVT24      ," "0,1"
textline "                                            "
bitfld.quad 0x00 23. " COMP_EVT23        ," "0,1"
bitfld.quad 0x00 22. "                 COMP_EVT22      ," "0,1"
textline "                                            "
bitfld.quad 0x00 21. " COMP_EVT21        ," "0,1"
bitfld.quad 0x00 20. "                 COMP_EVT20      ," "0,1"
textline "                                            "
bitfld.quad 0x00 19. " COMP_EVT19        ," "0,1"
bitfld.quad 0x00 18. "                 COMP_EVT18      ," "0,1"
textline "                                            "
bitfld.quad 0x00 17. " COMP_EVT17        ," "0,1"
bitfld.quad 0x00 16. "                 COMP_EVT16      ," "0,1"
textline "                                            "
bitfld.quad 0x00 15. " COMP_EVT15        ," "0,1"
bitfld.quad 0x00 14. "                 COMP_EVT14      ," "0,1"
textline "                                            "
bitfld.quad 0x00 13. " COMP_EVT13        ," "0,1"
bitfld.quad 0x00 12. "                 COMP_EVT12      ," "0,1"
textline "                                            "
bitfld.quad 0x00 11. " COMP_EVT11        ," "0,1"
bitfld.quad 0x00 10. "                 COMP_EVT10      ," "0,1"
textline "                                            "
bitfld.quad 0x00 9. " COMP_EVT9         ," "0,1"
bitfld.quad 0x00 8. "                 COMP_EVT8       ," "0,1"
textline "                                            "
bitfld.quad 0x00 7. " COMP_EVT7         ," "0,1"
bitfld.quad 0x00 6. "                 COMP_EVT6       ," "0,1"
textline "                                            "
bitfld.quad 0x00 5. " COMP_EVT5         ," "0,1"
bitfld.quad 0x00 4. "                 COMP_EVT4       ," "0,1"
textline "                                            "
bitfld.quad 0x00 3. " COMP_EVT3         ," "0,1"
bitfld.quad 0x00 2. "                 COMP_EVT2       ," "0,1"
textline "                                            "
bitfld.quad 0x00 1. " COMP_EVT1         ," "0,1"
bitfld.quad 0x00 0. "                 COMP_EVT0       ," "0,1"
group.quad 0x8000++0x7
line.quad 0x00 "DRU_CFG_y,Configuration Register for Queue 'y' Offset = 8000h + (y * 8h); where y = 0h to 4h"
hexmask.quad.long 0x00 32.--63. 1. " RSVD              ,"
hexmask.quad.byte 0x00 24.--31. 1. "          REARB_WAIT      ,"
textline "                                            "
hexmask.quad.byte 0x00 16.--23. 1. " CONSECUTIVE_TRANS ,"
bitfld.quad 0x00 8.--10. "                QOS             ," "0,1,2,3,4,5,6,7"
textline "                                            "
bitfld.quad 0x00 4.--7. " ORDERID           ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0.--2. "                PRI             ," "0,1,2,3,4,5,6,7"
rgroup.quad 0x8040++0x7
line.quad 0x00 "DRU_STATUS_y,Status Register for Queue 'y' Offset = 8040h + (y * 8h); where y = 0h to 4h"
hexmask.quad.long 0x00 36.--63. 1. " RSVD              ,"
hexmask.quad.word 0x00 27.--35. 1. "          RD_TOTAL        ,"
textline "                                            "
hexmask.quad.word 0x00 18.--26. 1. " RD_TOP            ,"
hexmask.quad.word 0x00 9.--17. 1. "              WR_TOTAL        ,"
textline "                                            "
hexmask.quad.word 0x00 0.--8. 1. " WR_TOP            ,"
group.long 0x10000++0x3
line.long 0x00 "DRU_MEMATTR64K_y,The Memory Attribute register contains the attributes for all the 64K mapped regions. Offset = 10000h + (y * 4h); where y = 0h to 7Fh"
bitfld.long 0x00 6.--7. "         MEMTYPE           ,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "                 SDOMAIN         ,Defines the shareability domain of the memory" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " OUTER             ,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "                 INNER           ,Defines the inner allocatability of the memory" "0,1,2,3"
group.long 0x20000++0x3
line.long 0x00 "DRU_MEMATTR16M1_y,The Memory Attribute register contains the attributes for all the second 16M mapped regions. Offset = 20000h + (y * 4h); where y = 0h to 7FFh"
bitfld.long 0x00 6.--7. "         MEMTYPE           ,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "                 SDOMAIN         ,Defines the shareability domain of the memory" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " OUTER             ,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "                 INNER           ,Defines the inner allocatability of the memory" "0,1,2,3"
group.long 0x30000++0x3
line.long 0x00 "DRU_MEMATTR16M0_y,The Memory Attribute register contains the attributes for all the first 16M mapped regions. Offset = 30000h + (y * 4h); where y = 0h to 7Fh"
bitfld.long 0x00 6.--7. "         MEMTYPE           ,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "                 SDOMAIN         ,Defines the shareability domain of the memory" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " OUTER             ,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "                 INNER           ,Defines the inner allocatability of the memory" "0,1,2,3"
group.quad 0x40000++0x7
line.quad 0x00 "DRU_CFG_j,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is disable in the ch_enable field in the REALTIME CONTROL register is 0. Offset = 40000h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.long 0x00 32.--63. 1. " RSVD              ,"
bitfld.quad 0x00 31. "          PAUSE_ON_ERR    ," "0,1"
textline "                                            "
bitfld.quad 0x00 19. " CHAN_TYPE_OWNER   ," "0,1"
bitfld.quad 0x00 16.--18. "                 CHAN_TYPE       ," "0,1,2,3,4,5,6,7"
group.quad 0x40020++0x7
line.quad 0x00 "DRU_CHOES0_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the corresponding register will be generated. This register is provided in order to allow security SW to lock down which events in the global space any given channel/ thread is allowed to generate Offset = 40020h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.quad 0x00 16.--63. 1. " RSVD              ,"
hexmask.quad.word 0x00 0.--15. 1. "  EVT_NUM         ,"
group.quad 0x40060++0x7
line.quad 0x00 "DRU_CHST_SCHED_j,Channel Static Scheduler Config Register Offset = 40060h + (j * 100h); where j = 0h to 3Fh"
bitfld.quad 0x00 0.--2. " QUEUE             ," "0,1,2,3,4,5,6,7"
group.quad 0x60000++0x7
line.quad 0x00 "DRU_CHRT_CTL_j,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in operation. Offset = 60000h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.long 0x00 32.--63. 1. " RSVD              ,"
bitfld.quad 0x00 31. "          ENABLE          ," "0,1"
textline "                                            "
bitfld.quad 0x00 30. " TEARDOWN          ," "0,1"
bitfld.quad 0x00 29. "                 PAUSE           ," "0,1"
group.quad 0x60008++0x7
line.quad 0x00 "DRU_CHRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. Offset = 60008h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad 0x00 3.--63. 1. " RSVD              ,"
bitfld.quad 0x00 2. "  LOCAL_TRIGGER0  ," "0,1"
textline "                                            "
bitfld.quad 0x00 1. " GLOBAL_TRIGGER1   ," "0,1"
bitfld.quad 0x00 0. "                 GLOBAL_TRIGGER0 ," "0,1"
rgroup.quad 0x60010++0x7
line.quad 0x00 "DRU_CHRT_STATUS_DET_j,The channel status details Offset = 60010h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.byte 0x00 8.--15. 1. " CMD_ID            ,"
bitfld.quad 0x00 4.--7. "                INFO            ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.quad 0x00 0.--3. " STATUS_TYPE       ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.quad 0x60018++0x7
line.quad 0x00 "DRU_CHRT_STATUS_CNT_j,The channel count details Offset = 60018h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x00 48.--63. 1. " ICNT3             ,"
hexmask.quad.word 0x00 32.--47. 1. "              ICNT2           ,"
textline "                                            "
hexmask.quad.word 0x00 16.--31. 1. " ICNT1             ,"
hexmask.quad.word 0x00 0.--15. 1. "              ICNT0           ,"
rgroup.quad 0x80040++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD0_1_j_k,The first TR submission word Offset = 80040h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " ICNT1             ,"
hexmask.quad.word 0x00 32.--47. 1. "              ICNT0           ,"
textline "                                            "
hexmask.quad.long 0x00 0.--31. 1. " FLAGS             ,"
rgroup.quad 0x80048++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD2_3_j_k,The second TR submission word Offset = 80048h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " RSVD              ,"
hexmask.quad.quad 0x00 0.--47. 1. "              SRC_ADDR        ,"
rgroup.quad 0x80050++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD4_5_j_k,The third TR submission word Offset = 80050h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " ICNT3             ,"
hexmask.quad.word 0x00 32.--47. 1. "              ICNT2           ,"
textline "                                            "
hexmask.quad.long 0x00 0.--31. 1. " DIM1              ,"
rgroup.quad 0x80058++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD6_7_j_k,The fourth TR submission word Offset = 80058h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DIM3              ,"
hexmask.quad.long 0x00 0.--31. 1. "          DIM2            ,"
rgroup.quad 0x80060++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD8_9_j_k,The fifth TR submission word Offset = 80060h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DDIM1             ,"
hexmask.quad.long 0x00 0.--31. 1. "          FMTFLAGS        ,"
rgroup.quad 0x80068++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD10_11_j_k,The sixth TR submission word Offset = 80068h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " RSVD              ,"
hexmask.quad.quad 0x00 0.--47. 1. "              DADDR           ,"
rgroup.quad 0x80070++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD12_13_j_k,The seventh TR submission word Offset = 80070h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DDIM3             ,"
hexmask.quad.long 0x00 0.--31. 1. "          DDIM2           ,"
rgroup.quad 0x80078++0x7
line.quad 0x00 "DRU_NEXT_TR_WORD14_15_j_k,The eight TR submission word Offset = 80078h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " DICNT3            ,"
hexmask.quad.word 0x00 32.--47. 1. "              DICNT2          ,"
textline "                                            "
hexmask.quad.word 0x00 16.--31. 1. " DICNT1            ,"
hexmask.quad.word 0x00 0.--15. 1. "              DICNT0          ,"
group.quad 0xA0000++0x7
line.quad 0x00 "DRU_SUBMIT_WORD0_1_j_k,The first TR submission word Offset = A0000h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " ICNT1             ,"
hexmask.quad.word 0x00 32.--47. 1. "              ICNT0           ,"
textline "                                            "
hexmask.quad.long 0x00 0.--31. 1. " FLAGS             ,"
group.quad 0xA0008++0x7
line.quad 0x00 "DRU_SUBMIT_WORD2_3_j_k,The second TR submission word Offset = A0008h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " RSVD              ,"
hexmask.quad.quad 0x00 0.--47. 1. "              SRC_ADDR        ,"
group.quad 0xA0010++0x7
line.quad 0x00 "DRU_SUBMIT_WORD4_5_j_k,The third TR submission word Offset = A0010h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " ICNT3             ,"
hexmask.quad.word 0x00 32.--47. 1. "              ICNT2           ,"
textline "                                            "
hexmask.quad.long 0x00 0.--31. 1. " DIM1              ,"
group.quad 0xA0018++0x7
line.quad 0x00 "DRU_SUBMIT_WORD6_7_j_k,The fourth TR submission word Offset = A0018h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DIM3              ,"
hexmask.quad.long 0x00 0.--31. 1. "          DIM2            ,"
group.quad 0xA0020++0x7
line.quad 0x00 "DRU_SUBMIT_WORD8_9_j_k,The fifth TR submission word Offset = A0020h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DDIM1             ,"
hexmask.quad.long 0x00 0.--31. 1. "          FMTFLAGS        ,"
group.quad 0xA0028++0x7
line.quad 0x00 "DRU_SUBMIT_WORD10_11_j_k,The sixth TR submission word Offset = A0028h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " RSVD              ,"
hexmask.quad.quad 0x00 0.--47. 1. "              DADDR           ,"
group.quad 0xA0030++0x7
line.quad 0x00 "DRU_SUBMIT_WORD12_13_j_k,The seventh TR submission word Offset = A0030h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.long 0x00 32.--63. 1. " DDIM3             ,"
hexmask.quad.long 0x00 0.--31. 1. "          DDIM2           ,"
group.quad 0xA0038++0x7
line.quad 0x00 "DRU_SUBMIT_WORD14_15_j_k,The eight TR submission word Offset = A0038h + (j * 100h) + (k * 40h); where j = 0h to 3Fh, k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. " DICNT3            ,"
hexmask.quad.word 0x00 32.--47. 1. "              DICNT2          ,"
textline "                                            "
hexmask.quad.word 0x00 16.--31. 1. " DICNT1            ,"
hexmask.quad.word 0x00 0.--15. 1. "              DICNT0          ,"
rgroup.quad 0xE0000++0x7
line.quad 0x00 "DRU_CAUSE_y,Offset = E0000h + (y * 8h); where y = 0h to 3h"
bitfld.quad 0x00 63. " R_ERR15           ,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 62. "                 R_PEND15        ,Masked completion ring pending bit for Rx channel n+15" "0,1"
textline "                                            "
bitfld.quad 0x00 61. " T_ERR15           ,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 60. "                 T_PEND15        ,Masked completion ring pending bit for Tx channel n+15" "0,1"
textline "                                            "
bitfld.quad 0x00 59. " R_ERR14           ,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 58. "                 R_PEND14        ,Masked completion ring pending bit for Rx channel n+14" "0,1"
textline "                                            "
bitfld.quad 0x00 57. " T_ERR14           ,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 56. "                 T_PEND14        ,Masked completion ring pending bit for Tx channel n+14" "0,1"
textline "                                            "
bitfld.quad 0x00 55. " R_ERR13           ,Masked error bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 54. "                 R_PEND13        ,Masked completion ring pending bit for Rx channel n+13" "0,1"
textline "                                            "
bitfld.quad 0x00 53. " T_ERR13           ,Masked error bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 52. "                 T_PEND13        ,Masked completion ring pending bit for Tx channel n+13" "0,1"
textline "                                            "
bitfld.quad 0x00 51. " R_ERR12           ,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 50. "                 R_PEND12        ,Masked completion ring pending bit for Rx channel n+12" "0,1"
textline "                                            "
bitfld.quad 0x00 49. " T_ERR12           ,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 48. "                 T_PEND12        ,Masked completion ring pending bit for Tx channel n+12" "0,1"
textline "                                            "
bitfld.quad 0x00 47. " R_ERR11           ,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 46. "                 R_PEND11        ,Masked completion ring pending bit for Rx channel n+11" "0,1"
textline "                                            "
bitfld.quad 0x00 45. " T_ERR11           ,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 44. "                 T_PEND11        ,Masked completion ring pending bit for Tx channel n+11" "0,1"
textline "                                            "
bitfld.quad 0x00 43. " R_ERR10           ,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 42. "                 R_PEND10        ,Masked completion ring pending bit for Rx channel n+10" "0,1"
textline "                                            "
bitfld.quad 0x00 41. " T_ERR10           ,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 40. "                 T_PEND10        ,Masked completion ring pending bit for Tx channel n+10" "0,1"
textline "                                            "
bitfld.quad 0x00 39. " R_ERR9            ,Masked error bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 38. "                 R_PEND9         ,Masked completion ring pending bit for Rx channel n+9" "0,1"
textline "                                            "
bitfld.quad 0x00 37. " T_ERR9            ,Masked error bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 36. "                 T_PEND9         ,Masked completion ring pending bit for Tx channel n+9" "0,1"
textline "                                            "
bitfld.quad 0x00 35. " R_ERR8            ,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 34. "                 R_PEND8         ,Masked completion ring pending bit for Rx channel n+8" "0,1"
textline "                                            "
bitfld.quad 0x00 33. " T_ERR8            ,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 32. "                 T_PEND8         ,Masked completion ring pending bit for Tx channel n+8" "0,1"
textline "                                            "
bitfld.quad 0x00 31. " R_ERR7            ,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 30. "                 R_PEND7         ,Masked completion ring pending bit for Rx channel n+7" "0,1"
textline "                                            "
bitfld.quad 0x00 29. " T_ERR7            ,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 28. "                 T_PEND7         ,Masked completion ring pending bit for Tx channel n+7" "0,1"
textline "                                            "
bitfld.quad 0x00 27. " R_ERR6            ,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 26. "                 R_PEND6         ,Masked completion ring pending bit for Rx channel n+6" "0,1"
textline "                                            "
bitfld.quad 0x00 25. " T_ERR6            ,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 24. "                 T_PEND6         ,Masked completion ring pending bit for Tx channel n+6" "0,1"
textline "                                            "
bitfld.quad 0x00 23. " R_ERR5            ,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 22. "                 R_PEND5         ,Masked completion ring pending bit for Rx channel n+5" "0,1"
textline "                                            "
bitfld.quad 0x00 21. " T_ERR5            ,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 20. "                 T_PEND5         ,Masked completion ring pending bit for Tx channel n+5" "0,1"
textline "                                            "
bitfld.quad 0x00 19. " R_ERR4            ,Masked error bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 18. "                 R_PEND4         ,Masked completion ring pending bit for Rx channel n+4" "0,1"
textline "                                            "
bitfld.quad 0x00 17. " T_ERR4            ,Masked error bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 16. "                 T_PEND4         ,Masked completion ring pending bit for Tx channel n+4" "0,1"
textline "                                            "
bitfld.quad 0x00 15. " R_ERR3            ,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 14. "                 R_PEND3         ,Masked completion ring pending bit for Rx channel n+3" "0,1"
textline "                                            "
bitfld.quad 0x00 13. " T_ERR3            ,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 12. "                 T_PEND3         ,Masked completion ring pending bit for Tx channel n+3" "0,1"
textline "                                            "
bitfld.quad 0x00 11. " R_ERR2            ,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 10. "                 R_PEND2         ,Masked completion ring pending bit for Rx channel n+2" "0,1"
textline "                                            "
bitfld.quad 0x00 9. " T_ERR2            ,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 8. "                 T_PEND2         ,Masked completion ring pending bit for Tx channel n+2" "0,1"
textline "                                            "
bitfld.quad 0x00 7. " R_ERR1            ,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 6. "                 R_PEND1         ,Masked completion ring pending bit for Rx channel n+1" "0,1"
textline "                                            "
bitfld.quad 0x00 5. " T_ERR1            ,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 4. "                 T_PEND1         ,Masked completion ring pending bit for Tx channel n+1" "0,1"
textline "                                            "
bitfld.quad 0x00 3. " R_ERR0            ,Masked error bit for Tx channel n" "0,1"
bitfld.quad 0x00 2. "                 R_PEND0         ,Masked completion ring pending bit for Rx channel n" "0,1"
textline "                                            "
bitfld.quad 0x00 1. " T_ERR0            ,Masked error bit for Tx channel n" "0,1"
bitfld.quad 0x00 0. "                 T_PEND0         ,Masked completion ring pending bit for Tx channel n" "0,1"
width 0x0B
tree.end
tree.end
tree "DRU_DMA_FW"
tree "COMPUTE_CLUSTER0_DRU_FW"
base ad:0x45047000
width 34.
group.long 0x0++0x3
line.long 0x00 "FW0_FW_REGION_0_CONTROL,The FW Region 0 Control Register defines the control fields for the slave fw0 region 0 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "FW0_FW_REGION_0_PERMISSION_0,The FW Region 0 Permission 0 Register defines the permissions for the slave fw0 region 0 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8++0x3
line.long 0x00 "FW0_FW_REGION_0_PERMISSION_1,The FW Region 0 Permission 1 Register defines the permissions for the slave fw0 region 0 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xC++0x3
line.long 0x00 "FW0_FW_REGION_0_PERMISSION_2,The FW Region 0 Permission 2 Register defines the permissions for the slave fw0 region 0 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "FW0_FW_REGION_0_START_ADDRESS_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 0 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "FW0_FW_REGION_0_START_ADDRESS_H,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 0 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "FW0_FW_REGION_0_END_ADDRESS_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 0 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "FW0_FW_REGION_0_END_ADDRESS_H,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 0 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x20++0x3
line.long 0x00 "FW0_FW_REGION_1_CONTROL,The FW Region 1 Control Register defines the control fields for the slave fw0 region 1 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x3
line.long 0x00 "FW0_FW_REGION_1_PERMISSION_0,The FW Region 1 Permission 0 Register defines the permissions for the slave fw0 region 1 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x28++0x3
line.long 0x00 "FW0_FW_REGION_1_PERMISSION_1,The FW Region 1 Permission 1 Register defines the permissions for the slave fw0 region 1 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x2C++0x3
line.long 0x00 "FW0_FW_REGION_1_PERMISSION_2,The FW Region 1 Permission 2 Register defines the permissions for the slave fw0 region 1 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x30++0x3
line.long 0x00 "FW0_FW_REGION_1_START_ADDRESS_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 1 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x34++0x3
line.long 0x00 "FW0_FW_REGION_1_START_ADDRESS_H,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 1 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x38++0x3
line.long 0x00 "FW0_FW_REGION_1_END_ADDRESS_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 1 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x3C++0x3
line.long 0x00 "FW0_FW_REGION_1_END_ADDRESS_H,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 1 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x40++0x3
line.long 0x00 "FW0_FW_REGION_2_CONTROL,The FW Region 2 Control Register defines the control fields for the slave fw0 region 2 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x3
line.long 0x00 "FW0_FW_REGION_2_PERMISSION_0,The FW Region 2 Permission 0 Register defines the permissions for the slave fw0 region 2 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x48++0x3
line.long 0x00 "FW0_FW_REGION_2_PERMISSION_1,The FW Region 2 Permission 1 Register defines the permissions for the slave fw0 region 2 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x4C++0x3
line.long 0x00 "FW0_FW_REGION_2_PERMISSION_2,The FW Region 2 Permission 2 Register defines the permissions for the slave fw0 region 2 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x50++0x3
line.long 0x00 "FW0_FW_REGION_2_START_ADDRESS_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 2 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x54++0x3
line.long 0x00 "FW0_FW_REGION_2_START_ADDRESS_H,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 2 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x58++0x3
line.long 0x00 "FW0_FW_REGION_2_END_ADDRESS_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 2 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x5C++0x3
line.long 0x00 "FW0_FW_REGION_2_END_ADDRESS_H,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 2 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x60++0x3
line.long 0x00 "FW0_FW_REGION_3_CONTROL,The FW Region 3 Control Register defines the control fields for the slave fw0 region 3 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x3
line.long 0x00 "FW0_FW_REGION_3_PERMISSION_0,The FW Region 3 Permission 0 Register defines the permissions for the slave fw0 region 3 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x68++0x3
line.long 0x00 "FW0_FW_REGION_3_PERMISSION_1,The FW Region 3 Permission 1 Register defines the permissions for the slave fw0 region 3 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x6C++0x3
line.long 0x00 "FW0_FW_REGION_3_PERMISSION_2,The FW Region 3 Permission 2 Register defines the permissions for the slave fw0 region 3 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x70++0x3
line.long 0x00 "FW0_FW_REGION_3_START_ADDRESS_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 3 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x74++0x3
line.long 0x00 "FW0_FW_REGION_3_START_ADDRESS_H,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 3 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x78++0x3
line.long 0x00 "FW0_FW_REGION_3_END_ADDRESS_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 3 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x7C++0x3
line.long 0x00 "FW0_FW_REGION_3_END_ADDRESS_H,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 3 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x80++0x3
line.long 0x00 "FW0_FW_REGION_4_CONTROL,The FW Region 4 Control Register defines the control fields for the slave fw0 region 4 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x84++0x3
line.long 0x00 "FW0_FW_REGION_4_PERMISSION_0,The FW Region 4 Permission 0 Register defines the permissions for the slave fw0 region 4 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x88++0x3
line.long 0x00 "FW0_FW_REGION_4_PERMISSION_1,The FW Region 4 Permission 1 Register defines the permissions for the slave fw0 region 4 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x8C++0x3
line.long 0x00 "FW0_FW_REGION_4_PERMISSION_2,The FW Region 4 Permission 2 Register defines the permissions for the slave fw0 region 4 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x90++0x3
line.long 0x00 "FW0_FW_REGION_4_START_ADDRESS_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 4 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x94++0x3
line.long 0x00 "FW0_FW_REGION_4_START_ADDRESS_H,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 4 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x98++0x3
line.long 0x00 "FW0_FW_REGION_4_END_ADDRESS_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 4 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x9C++0x3
line.long 0x00 "FW0_FW_REGION_4_END_ADDRESS_H,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 4 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0xA0++0x3
line.long 0x00 "FW0_FW_REGION_5_CONTROL,The FW Region 5 Control Register defines the control fields for the slave fw0 region 5 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA4++0x3
line.long 0x00 "FW0_FW_REGION_5_PERMISSION_0,The FW Region 5 Permission 0 Register defines the permissions for the slave fw0 region 5 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xA8++0x3
line.long 0x00 "FW0_FW_REGION_5_PERMISSION_1,The FW Region 5 Permission 1 Register defines the permissions for the slave fw0 region 5 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xAC++0x3
line.long 0x00 "FW0_FW_REGION_5_PERMISSION_2,The FW Region 5 Permission 2 Register defines the permissions for the slave fw0 region 5 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xB0++0x3
line.long 0x00 "FW0_FW_REGION_5_START_ADDRESS_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 5 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0xB4++0x3
line.long 0x00 "FW0_FW_REGION_5_START_ADDRESS_H,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 5 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0xB8++0x3
line.long 0x00 "FW0_FW_REGION_5_END_ADDRESS_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 5 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0xBC++0x3
line.long 0x00 "FW0_FW_REGION_5_END_ADDRESS_H,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 5 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0xC0++0x3
line.long 0x00 "FW0_FW_REGION_6_CONTROL,The FW Region 6 Control Register defines the control fields for the slave fw0 region 6 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4++0x3
line.long 0x00 "FW0_FW_REGION_6_PERMISSION_0,The FW Region 6 Permission 0 Register defines the permissions for the slave fw0 region 6 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xC8++0x3
line.long 0x00 "FW0_FW_REGION_6_PERMISSION_1,The FW Region 6 Permission 1 Register defines the permissions for the slave fw0 region 6 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xCC++0x3
line.long 0x00 "FW0_FW_REGION_6_PERMISSION_2,The FW Region 6 Permission 2 Register defines the permissions for the slave fw0 region 6 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xD0++0x3
line.long 0x00 "FW0_FW_REGION_6_START_ADDRESS_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 6 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0xD4++0x3
line.long 0x00 "FW0_FW_REGION_6_START_ADDRESS_H,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 6 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0xD8++0x3
line.long 0x00 "FW0_FW_REGION_6_END_ADDRESS_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 6 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0xDC++0x3
line.long 0x00 "FW0_FW_REGION_6_END_ADDRESS_H,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 6 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0xE0++0x3
line.long 0x00 "FW0_FW_REGION_7_CONTROL,The FW Region 7 Control Register defines the control fields for the slave fw0 region 7 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE4++0x3
line.long 0x00 "FW0_FW_REGION_7_PERMISSION_0,The FW Region 7 Permission 0 Register defines the permissions for the slave fw0 region 7 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xE8++0x3
line.long 0x00 "FW0_FW_REGION_7_PERMISSION_1,The FW Region 7 Permission 1 Register defines the permissions for the slave fw0 region 7 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xEC++0x3
line.long 0x00 "FW0_FW_REGION_7_PERMISSION_2,The FW Region 7 Permission 2 Register defines the permissions for the slave fw0 region 7 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0xF0++0x3
line.long 0x00 "FW0_FW_REGION_7_START_ADDRESS_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 7 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0xF4++0x3
line.long 0x00 "FW0_FW_REGION_7_START_ADDRESS_H,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 7 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0xF8++0x3
line.long 0x00 "FW0_FW_REGION_7_END_ADDRESS_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 7 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0xFC++0x3
line.long 0x00 "FW0_FW_REGION_7_END_ADDRESS_H,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 7 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x100++0x3
line.long 0x00 "FW0_FW_REGION_8_CONTROL,The FW Region 8 Control Register defines the control fields for the slave fw0 region 8 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x3
line.long 0x00 "FW0_FW_REGION_8_PERMISSION_0,The FW Region 8 Permission 0 Register defines the permissions for the slave fw0 region 8 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x108++0x3
line.long 0x00 "FW0_FW_REGION_8_PERMISSION_1,The FW Region 8 Permission 1 Register defines the permissions for the slave fw0 region 8 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10C++0x3
line.long 0x00 "FW0_FW_REGION_8_PERMISSION_2,The FW Region 8 Permission 2 Register defines the permissions for the slave fw0 region 8 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x110++0x3
line.long 0x00 "FW0_FW_REGION_8_START_ADDRESS_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 8 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x114++0x3
line.long 0x00 "FW0_FW_REGION_8_START_ADDRESS_H,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 8 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x118++0x3
line.long 0x00 "FW0_FW_REGION_8_END_ADDRESS_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 8 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x11C++0x3
line.long 0x00 "FW0_FW_REGION_8_END_ADDRESS_H,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 8 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x120++0x3
line.long 0x00 "FW0_FW_REGION_9_CONTROL,The FW Region 9 Control Register defines the control fields for the slave fw0 region 9 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x124++0x3
line.long 0x00 "FW0_FW_REGION_9_PERMISSION_0,The FW Region 9 Permission 0 Register defines the permissions for the slave fw0 region 9 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x128++0x3
line.long 0x00 "FW0_FW_REGION_9_PERMISSION_1,The FW Region 9 Permission 1 Register defines the permissions for the slave fw0 region 9 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x12C++0x3
line.long 0x00 "FW0_FW_REGION_9_PERMISSION_2,The FW Region 9 Permission 2 Register defines the permissions for the slave fw0 region 9 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x130++0x3
line.long 0x00 "FW0_FW_REGION_9_START_ADDRESS_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 9 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x134++0x3
line.long 0x00 "FW0_FW_REGION_9_START_ADDRESS_H,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 9 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x138++0x3
line.long 0x00 "FW0_FW_REGION_9_END_ADDRESS_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 9 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x13C++0x3
line.long 0x00 "FW0_FW_REGION_9_END_ADDRESS_H,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 9 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x140++0x3
line.long 0x00 "FW0_FW_REGION_10_CONTROL,The FW Region 10 Control Register defines the control fields for the slave fw0 region 10 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x144++0x3
line.long 0x00 "FW0_FW_REGION_10_PERMISSION_0,The FW Region 10 Permission 0 Register defines the permissions for the slave fw0 region 10 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x148++0x3
line.long 0x00 "FW0_FW_REGION_10_PERMISSION_1,The FW Region 10 Permission 1 Register defines the permissions for the slave fw0 region 10 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x14C++0x3
line.long 0x00 "FW0_FW_REGION_10_PERMISSION_2,The FW Region 10 Permission 2 Register defines the permissions for the slave fw0 region 10 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x150++0x3
line.long 0x00 "FW0_FW_REGION_10_START_ADDRESS_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 10 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x154++0x3
line.long 0x00 "FW0_FW_REGION_10_START_ADDRESS_H,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 10 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x158++0x3
line.long 0x00 "FW0_FW_REGION_10_END_ADDRESS_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 10 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x15C++0x3
line.long 0x00 "FW0_FW_REGION_10_END_ADDRESS_H,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 10 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x160++0x3
line.long 0x00 "FW0_FW_REGION_11_CONTROL,The FW Region 11 Control Register defines the control fields for the slave fw0 region 11 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x164++0x3
line.long 0x00 "FW0_FW_REGION_11_PERMISSION_0,The FW Region 11 Permission 0 Register defines the permissions for the slave fw0 region 11 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x168++0x3
line.long 0x00 "FW0_FW_REGION_11_PERMISSION_1,The FW Region 11 Permission 1 Register defines the permissions for the slave fw0 region 11 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x16C++0x3
line.long 0x00 "FW0_FW_REGION_11_PERMISSION_2,The FW Region 11 Permission 2 Register defines the permissions for the slave fw0 region 11 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x170++0x3
line.long 0x00 "FW0_FW_REGION_11_START_ADDRESS_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 11 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x174++0x3
line.long 0x00 "FW0_FW_REGION_11_START_ADDRESS_H,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 11 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x178++0x3
line.long 0x00 "FW0_FW_REGION_11_END_ADDRESS_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 11 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x17C++0x3
line.long 0x00 "FW0_FW_REGION_11_END_ADDRESS_H,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 11 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x180++0x3
line.long 0x00 "FW0_FW_REGION_12_CONTROL,The FW Region 12 Control Register defines the control fields for the slave fw0 region 12 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x184++0x3
line.long 0x00 "FW0_FW_REGION_12_PERMISSION_0,The FW Region 12 Permission 0 Register defines the permissions for the slave fw0 region 12 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x188++0x3
line.long 0x00 "FW0_FW_REGION_12_PERMISSION_1,The FW Region 12 Permission 1 Register defines the permissions for the slave fw0 region 12 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x18C++0x3
line.long 0x00 "FW0_FW_REGION_12_PERMISSION_2,The FW Region 12 Permission 2 Register defines the permissions for the slave fw0 region 12 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x190++0x3
line.long 0x00 "FW0_FW_REGION_12_START_ADDRESS_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 12 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x194++0x3
line.long 0x00 "FW0_FW_REGION_12_START_ADDRESS_H,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 12 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x198++0x3
line.long 0x00 "FW0_FW_REGION_12_END_ADDRESS_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 12 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x19C++0x3
line.long 0x00 "FW0_FW_REGION_12_END_ADDRESS_H,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 12 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x1A0++0x3
line.long 0x00 "FW0_FW_REGION_13_CONTROL,The FW Region 13 Control Register defines the control fields for the slave fw0 region 13 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1A4++0x3
line.long 0x00 "FW0_FW_REGION_13_PERMISSION_0,The FW Region 13 Permission 0 Register defines the permissions for the slave fw0 region 13 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1A8++0x3
line.long 0x00 "FW0_FW_REGION_13_PERMISSION_1,The FW Region 13 Permission 1 Register defines the permissions for the slave fw0 region 13 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1AC++0x3
line.long 0x00 "FW0_FW_REGION_13_PERMISSION_2,The FW Region 13 Permission 2 Register defines the permissions for the slave fw0 region 13 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1B0++0x3
line.long 0x00 "FW0_FW_REGION_13_START_ADDRESS_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 13 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x1B4++0x3
line.long 0x00 "FW0_FW_REGION_13_START_ADDRESS_H,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 13 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x1B8++0x3
line.long 0x00 "FW0_FW_REGION_13_END_ADDRESS_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 13 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1BC++0x3
line.long 0x00 "FW0_FW_REGION_13_END_ADDRESS_H,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 13 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x1C0++0x3
line.long 0x00 "FW0_FW_REGION_14_CONTROL,The FW Region 14 Control Register defines the control fields for the slave fw0 region 14 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C4++0x3
line.long 0x00 "FW0_FW_REGION_14_PERMISSION_0,The FW Region 14 Permission 0 Register defines the permissions for the slave fw0 region 14 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1C8++0x3
line.long 0x00 "FW0_FW_REGION_14_PERMISSION_1,The FW Region 14 Permission 1 Register defines the permissions for the slave fw0 region 14 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1CC++0x3
line.long 0x00 "FW0_FW_REGION_14_PERMISSION_2,The FW Region 14 Permission 2 Register defines the permissions for the slave fw0 region 14 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1D0++0x3
line.long 0x00 "FW0_FW_REGION_14_START_ADDRESS_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 14 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x1D4++0x3
line.long 0x00 "FW0_FW_REGION_14_START_ADDRESS_H,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 14 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x1D8++0x3
line.long 0x00 "FW0_FW_REGION_14_END_ADDRESS_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 14 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1DC++0x3
line.long 0x00 "FW0_FW_REGION_14_END_ADDRESS_H,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 14 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x1E0++0x3
line.long 0x00 "FW0_FW_REGION_15_CONTROL,The FW Region 15 Control Register defines the control fields for the slave fw0 region 15 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                           "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1E4++0x3
line.long 0x00 "FW0_FW_REGION_15_PERMISSION_0,The FW Region 15 Permission 0 Register defines the permissions for the slave fw0 region 15 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1E8++0x3
line.long 0x00 "FW0_FW_REGION_15_PERMISSION_1,The FW Region 15 Permission 1 Register defines the permissions for the slave fw0 region 15 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1EC++0x3
line.long 0x00 "FW0_FW_REGION_15_PERMISSION_2,The FW Region 15 Permission 2 Register defines the permissions for the slave fw0 region 15 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                           "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                           "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x1F0++0x3
line.long 0x00 "FW0_FW_REGION_15_START_ADDRESS_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 15 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x1F4++0x3
line.long 0x00 "FW0_FW_REGION_15_START_ADDRESS_H,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 15 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x1F8++0x3
line.long 0x00 "FW0_FW_REGION_15_END_ADDRESS_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 15 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1FC++0x3
line.long 0x00 "FW0_FW_REGION_15_END_ADDRESS_H,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 15 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
width 0x0B
tree.end
tree.end
tree "DRU_DMA_FW_GLB"
tree "COMPUTE_CLUSTER0_DRU_FW_GLB"
base ad:0x45B17000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                    "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                    "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                    "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                    "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x44++0x3
hide.long 0x00 "EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
in
textline "                                    "
width 0x0B
tree.end
tree.end
tree "DRU_MMR_FW"
tree "COMPUTE_CLUSTER0_DRU_MMR_FW"
base ad:0x45048000
width 46.
group.long 0x0++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_CONTROL,The FW Region 0 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 8. "       BACKGROUND        ,Background enable for region.There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " LOCK                  ,Lock region.Once set region values cannot be modified." "0,1"
bitfld.long 0x00 0.--3. "       ENABLE            ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_PERMISSION_0,The FW Region 0 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x10++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_START_ADDRESS_L,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave mmr.dru_mmr_cfg region 0 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " START_ADDRESS_L       ,Start address bits 31 to 12.Lowest 12 bits are forced to 0 as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  START_ADDRESS_LSB ,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned."
group.long 0x14++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_START_ADDRESS_H,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave mmr.dru_mmr_cfg region 0 firewall."
hexmask.long.word 0x00 0.--15. 1. " START_ADDRESS_H       ,Start address bits 47 to 32."
group.long 0x18++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_END_ADDRESS_L,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave mmr.dru_mmr_cfg region 0 firewall."
hexmask.long.tbyte 0x00 12.--31. 1. " END_ADDRESS_L         ,End address bits 31 to 12 to include in the match.Lowest 12 bits are forced to 1s as address must be 4KB aligned."
hexmask.long.word 0x00 0.--11. 1. "  END_ADDRESS_LSB   ,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1."
group.long 0x1C++0x3
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_END_ADDRESS_H,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave mmr.dru_mmr_cfg region 0 firewall."
hexmask.long.word 0x00 0.--15. 1. " END_ADDRESS_H         ,End address bits 47 to 32 to include in the match."
group.long 0x27FBC000++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_0_CONTROL,The FW Region 0 Channel 0 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 0 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC004++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_0_PERMISSION_0,The FW Region 0 Channel 0 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 0 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC020++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_1_CONTROL,The FW Region 0 Channel 1 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 1 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC024++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_1_PERMISSION_0,The FW Region 0 Channel 1 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 1 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC040++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_2_CONTROL,The FW Region 0 Channel 2 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 2 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC044++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_2_PERMISSION_0,The FW Region 0 Channel 2 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 2 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC060++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_3_CONTROL,The FW Region 0 Channel 3 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 3 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC064++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_3_PERMISSION_0,The FW Region 0 Channel 3 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 3 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC080++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_4_CONTROL,The FW Region 0 Channel 4 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 4 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC084++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_4_PERMISSION_0,The FW Region 0 Channel 4 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 4 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC0A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_5_CONTROL,The FW Region 0 Channel 5 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 5 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC0A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_5_PERMISSION_0,The FW Region 0 Channel 5 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 5 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC0C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_6_CONTROL,The FW Region 0 Channel 6 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 6 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC0C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_6_PERMISSION_0,The FW Region 0 Channel 6 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 6 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC0E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_7_CONTROL,The FW Region 0 Channel 7 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 7 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC0E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_7_PERMISSION_0,The FW Region 0 Channel 7 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 7 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC100++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_8_CONTROL,The FW Region 0 Channel 8 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 8 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC104++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_8_PERMISSION_0,The FW Region 0 Channel 8 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 8 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC120++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_9_CONTROL,The FW Region 0 Channel 9 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 9 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC124++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_9_PERMISSION_0,The FW Region 0 Channel 9 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 9 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC140++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_10_CONTROL,The FW Region 0 Channel 10 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 10 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC144++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_10_PERMISSION_0,The FW Region 0 Channel 10 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 10 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC160++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_11_CONTROL,The FW Region 0 Channel 11 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 11 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC164++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_11_PERMISSION_0,The FW Region 0 Channel 11 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 11 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC180++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_12_CONTROL,The FW Region 0 Channel 12 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 12 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC184++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_12_PERMISSION_0,The FW Region 0 Channel 12 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 12 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC1A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_13_CONTROL,The FW Region 0 Channel 13 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 13 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC1A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_13_PERMISSION_0,The FW Region 0 Channel 13 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 13 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC1C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_14_CONTROL,The FW Region 0 Channel 14 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 14 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC1C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_14_PERMISSION_0,The FW Region 0 Channel 14 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 14 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC1E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_15_CONTROL,The FW Region 0 Channel 15 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 15 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC1E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_15_PERMISSION_0,The FW Region 0 Channel 15 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 15 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC200++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_16_CONTROL,The FW Region 0 Channel 16 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 16 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC204++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_16_PERMISSION_0,The FW Region 0 Channel 16 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 16 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC220++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_17_CONTROL,The FW Region 0 Channel 17 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 17 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC224++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_17_PERMISSION_0,The FW Region 0 Channel 17 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 17 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC240++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_18_CONTROL,The FW Region 0 Channel 18 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 18 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC244++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_18_PERMISSION_0,The FW Region 0 Channel 18 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 18 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC260++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_19_CONTROL,The FW Region 0 Channel 19 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 19 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC264++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_19_PERMISSION_0,The FW Region 0 Channel 19 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 19 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC280++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_20_CONTROL,The FW Region 0 Channel 20 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 20 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC284++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_20_PERMISSION_0,The FW Region 0 Channel 20 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 20 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC2A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_21_CONTROL,The FW Region 0 Channel 21 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 21 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC2A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_21_PERMISSION_0,The FW Region 0 Channel 21 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 21 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC2C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_22_CONTROL,The FW Region 0 Channel 22 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 22 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC2C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_22_PERMISSION_0,The FW Region 0 Channel 22 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 22 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC2E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_23_CONTROL,The FW Region 0 Channel 23 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 23 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC2E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_23_PERMISSION_0,The FW Region 0 Channel 23 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 23 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC300++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_24_CONTROL,The FW Region 0 Channel 24 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 24 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC304++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_24_PERMISSION_0,The FW Region 0 Channel 24 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 24 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC320++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_25_CONTROL,The FW Region 0 Channel 25 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 25 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC324++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_25_PERMISSION_0,The FW Region 0 Channel 25 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 25 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC340++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_26_CONTROL,The FW Region 0 Channel 26 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 26 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC344++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_26_PERMISSION_0,The FW Region 0 Channel 26 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 26 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC360++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_27_CONTROL,The FW Region 0 Channel 27 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 27 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC364++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_27_PERMISSION_0,The FW Region 0 Channel 27 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 27 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC380++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_28_CONTROL,The FW Region 0 Channel 28 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 28 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC384++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_28_PERMISSION_0,The FW Region 0 Channel 28 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 28 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC3A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_29_CONTROL,The FW Region 0 Channel 29 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 29 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC3A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_29_PERMISSION_0,The FW Region 0 Channel 29 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 29 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC3C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_30_CONTROL,The FW Region 0 Channel 30 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 30 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC3C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_30_PERMISSION_0,The FW Region 0 Channel 30 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 30 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC3E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_31_CONTROL,The FW Region 0 Channel 31 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 31 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC3E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_31_PERMISSION_0,The FW Region 0 Channel 31 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 31 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC400++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_32_CONTROL,The FW Region 0 Channel 32 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 32 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC404++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_32_PERMISSION_0,The FW Region 0 Channel 32 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 32 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC420++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_33_CONTROL,The FW Region 0 Channel 33 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 33 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC424++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_33_PERMISSION_0,The FW Region 0 Channel 33 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 33 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC440++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_34_CONTROL,The FW Region 0 Channel 34 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 34 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC444++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_34_PERMISSION_0,The FW Region 0 Channel 34 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 34 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC460++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_35_CONTROL,The FW Region 0 Channel 35 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 35 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC464++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_35_PERMISSION_0,The FW Region 0 Channel 35 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 35 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC480++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_36_CONTROL,The FW Region 0 Channel 36 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 36 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC484++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_36_PERMISSION_0,The FW Region 0 Channel 36 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 36 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC4A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_37_CONTROL,The FW Region 0 Channel 37 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 37 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC4A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_37_PERMISSION_0,The FW Region 0 Channel 37 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 37 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC4C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_38_CONTROL,The FW Region 0 Channel 38 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 38 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC4C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_38_PERMISSION_0,The FW Region 0 Channel 38 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 38 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC4E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_39_CONTROL,The FW Region 0 Channel 39 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 39 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC4E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_39_PERMISSION_0,The FW Region 0 Channel 39 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 39 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC500++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_40_CONTROL,The FW Region 0 Channel 40 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 40 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC504++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_40_PERMISSION_0,The FW Region 0 Channel 40 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 40 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC520++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_41_CONTROL,The FW Region 0 Channel 41 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 41 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC524++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_41_PERMISSION_0,The FW Region 0 Channel 41 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 41 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC540++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_42_CONTROL,The FW Region 0 Channel 42 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 42 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC544++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_42_PERMISSION_0,The FW Region 0 Channel 42 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 42 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC560++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_43_CONTROL,The FW Region 0 Channel 43 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 43 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC564++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_43_PERMISSION_0,The FW Region 0 Channel 43 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 43 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC580++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_44_CONTROL,The FW Region 0 Channel 44 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 44 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC584++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_44_PERMISSION_0,The FW Region 0 Channel 44 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 44 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC5A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_45_CONTROL,The FW Region 0 Channel 45 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 45 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC5A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_45_PERMISSION_0,The FW Region 0 Channel 45 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 45 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC5C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_46_CONTROL,The FW Region 0 Channel 46 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 46 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC5C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_46_PERMISSION_0,The FW Region 0 Channel 46 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 46 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC5E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_47_CONTROL,The FW Region 0 Channel 47 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 47 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC5E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_47_PERMISSION_0,The FW Region 0 Channel 47 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 47 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC600++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_48_CONTROL,The FW Region 0 Channel 48 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 48 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC604++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_48_PERMISSION_0,The FW Region 0 Channel 48 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 48 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC620++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_49_CONTROL,The FW Region 0 Channel 49 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 49 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC624++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_49_PERMISSION_0,The FW Region 0 Channel 49 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 49 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC640++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_50_CONTROL,The FW Region 0 Channel 50 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 50 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC644++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_50_PERMISSION_0,The FW Region 0 Channel 50 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 50 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC660++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_51_CONTROL,The FW Region 0 Channel 51 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 51 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC664++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_51_PERMISSION_0,The FW Region 0 Channel 51 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 51 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC680++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_52_CONTROL,The FW Region 0 Channel 52 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 52 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC684++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_52_PERMISSION_0,The FW Region 0 Channel 52 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 52 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC6A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_53_CONTROL,The FW Region 0 Channel 53 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 53 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC6A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_53_PERMISSION_0,The FW Region 0 Channel 53 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 53 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC6C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_54_CONTROL,The FW Region 0 Channel 54 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 54 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC6C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_54_PERMISSION_0,The FW Region 0 Channel 54 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 54 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC6E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_55_CONTROL,The FW Region 0 Channel 55 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 55 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC6E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_55_PERMISSION_0,The FW Region 0 Channel 55 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 55 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC700++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_56_CONTROL,The FW Region 0 Channel 56 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 56 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC704++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_56_PERMISSION_0,The FW Region 0 Channel 56 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 56 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC720++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_57_CONTROL,The FW Region 0 Channel 57 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 57 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC724++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_57_PERMISSION_0,The FW Region 0 Channel 57 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 57 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC740++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_58_CONTROL,The FW Region 0 Channel 58 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 58 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC744++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_58_PERMISSION_0,The FW Region 0 Channel 58 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 58 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC760++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_59_CONTROL,The FW Region 0 Channel 59 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 59 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC764++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_59_PERMISSION_0,The FW Region 0 Channel 59 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 59 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC780++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_60_CONTROL,The FW Region 0 Channel 60 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 60 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC784++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_60_PERMISSION_0,The FW Region 0 Channel 60 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 60 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC7A0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_61_CONTROL,The FW Region 0 Channel 61 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 61 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC7A4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_61_PERMISSION_0,The FW Region 0 Channel 61 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 61 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC7C0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_62_CONTROL,The FW Region 0 Channel 62 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 62 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC7C4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_62_PERMISSION_0,The FW Region 0 Channel 62 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 62 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
group.long 0x27FBC7E0++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_63_CONTROL,The FW Region 0 Channel 63 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 63 firewall."
bitfld.long 0x00 9. " CACHE_MODE            ,Cache mode for region.Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1"
bitfld.long 0x00 4. "       LOCK              ,Lock region.Once set region values cannot be modified." "0,1"
textline "                                                       "
bitfld.long 0x00 0.--3. " ENABLE                ,Enable region.A value of 0xA enables, others disable." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27FBC7E4++0x3
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_63_PERMISSION_0,The FW Region 0 Channel 63 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 63 firewall."
hexmask.long.byte 0x00 16.--23. 1. " PRIV_ID               ,Allowed privid."
bitfld.long 0x00 15. "      NONSEC_USER_DEBUG ,Non-secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 14. " NONSEC_USER_CACHEABLE ,Non-secure user cacheable allowed." "0,1"
bitfld.long 0x00 13. "       NONSEC_USER_READ  ,Non-secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 12. " NONSEC_USER_WRITE     ,Non-secure user write allowed." "0,1"
bitfld.long 0x00 11. "       NONSEC_SUPV_DEBUG ,Non-secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 10. " NONSEC_SUPV_CACHEABLE ,Non-secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 9. "       NONSEC_SUPV_READ  ,Non-secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 8. " NONSEC_SUPV_WRITE     ,Non-secure supervisor write allowed." "0,1"
bitfld.long 0x00 7. "       SEC_USER_DEBUG    ,Secure user debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 6. " SEC_USER_CACHEABLE    ,Secure user cacheable allowed." "0,1"
bitfld.long 0x00 5. "       SEC_USER_READ     ,Secure user read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 4. " SEC_USER_WRITE        ,Secure user write allowed." "0,1"
bitfld.long 0x00 3. "       SEC_SUPV_DEBUG    ,Secure supervisor debug allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 2. " SEC_SUPV_CACHEABLE    ,Secure supervisor cacheable allowed." "0,1"
bitfld.long 0x00 1. "       SEC_SUPV_READ     ,Secure supervisor read allowed." "0,1"
textline "                                                       "
bitfld.long 0x00 0. " SEC_SUPV_WRITE        ,Secure supervisor write allowed." "0,1"
width 0x0B
tree.end
tree.end
tree "DRU_MMR_FW_GLB"
tree "COMPUTE_CLUSTER0_DRU_MMR_FW_GLB"
base ad:0x45B18000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x20++0x3
line.long 0x00 "EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_PEND ,Disables logging pending when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                    "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x28++0x3
line.long 0x00 "EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code."
rgroup.long 0x2C++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x30++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 16 bits."
rgroup.long 0x34++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                    "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                    "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                    "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x38++0x3
line.long 0x00 "EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x40++0x3
line.long 0x00 "EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x44++0x3
hide.long 0x00 "EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal."
in
textline "                                    "
width 0x0B
tree.end
tree.end
tree "DDR_Controller"
tree "DDRSS0_CTL_CFG"
base ad:0x2980000
width 24.
group.long 0x0++0x3
line.long 0x00 "DDRCTL_MSTR,Master Register0"
bitfld.long 0x00 30.--31. " DEVICE_CONFIG                     ,Indicates the configuration of the device used in the system.- 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 device Programming Mode: Static" "0,1,2,3"
bitfld.long 0x00 29. "         FREQUENCY_MODE                   ,Choose which registers are used.- 0 - Original registers - 1 - When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers When UMCTL2_FREQUENCY_NUM>2: Choosen by MSTR2.target_frequency register Programming Mode: Quasi-dynamic Group 2" "0,1"
textline "                                 "
bitfld.long 0x00 24.--25. " ACTIVE_RANKS                      ,Only present for multi-rank configurations.Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - One rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ranks - 0111 - Three ranks - 1111 - Four ranks Programming Mode: Static" "0,1,2,3"
bitfld.long 0x00 16.--19. "         BURST_RDWR                       ,SDRAM burst length used: -0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. Burst length of 2 is only supported when the controller is operating in 1:1 frequency mode. For DDR3, DDR4 and LPDDR3, this must be set to 0x0100 (BL8). For LPDDR4, this must be set to 0x1000 (BL16). Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 15. " DLL_OFF_MODE                      ,Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation.Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (DDRCTL_CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and this bit must be set to '0'. Programming Mode: Quasi-dynamic Group 2" "0,1"
bitfld.long 0x00 12.--13. "         DATA_BUS_WIDTH                   ,Selects proportion of DQ bus width that is used by the SDRAM -00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). Programming Mode: Static" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 11. " GEARDOWN_MODE                     ,1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N).This register can be changed, only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported if the configuration parameter UMCTL2_SHARED_AC is set (in Shared-AC mode) and the register value is don't care Programming Mode: Quasi-dynamic Group 2" "0,1"
bitfld.long 0x00 10. "         EN_2T_TIMING_MODE                ,If 1, then uMCTL2 uses 2T timing.Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported in Shared-AC dual channel mode and the register value is don't care. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 9. " BURSTCHOP                         ,When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4.Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (DDRCTL_MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is exercised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (DDRCTL_CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (DDRCTL_CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported. Programming Mode: Static" "0,1"
bitfld.long 0x00 8. "         BURST_MODE                       ,Indicates burst mode.0 - Sequential burst mode 1 - Interleaved burst mode For LPDDR3 and LPDDR4, this must be set to 0 (sequential mode). Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 5. " LPDDR4                            ,Select LPDDR4 SDRAM -1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "0,1"
bitfld.long 0x00 4. "         DDR4                             ,Select DDR4 SDRAM -1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 3. " LPDDR3                            ,Select LPDDR3 SDRAM -1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "0,1"
bitfld.long 0x00 2. "         LPDDR2                           ,Select LPDDR2 SDRAM -1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 0. " DDR3                              ,Select DDR3 SDRAM -1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. Programming Mode: Static" "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "DDRCTL_STAT,Operating Mode Status Register"
bitfld.long 0x00 12. " SELFREF_CAM_NOT_EMPTY             ,Self refresh with CAMs not empty.Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 8.--9. "         SELFREF_STATE                    ,Self refresh state.This indicates self refresh or self refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. - 00 - SDRAM is not in Self Refresh. - 01 - Self refresh 1 - 10 - Self refresh power down - 11 - Self refresh 2 Programming Mode: Dynamic" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 4.--5. " SELFREF_TYPE                      ,Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not.- 00 - SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress. - 11 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. - 10 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (DDRCTL_PWRCTL.selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity error. - 01 - SDRAM is in Self Refresh, which was caused by PHY Master Request. Programming Mode: Dynamic" "0,1,2,3"
bitfld.long 0x00 0.--2. "         OPERATING_MODE                   ,Operating mode.This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self refresh mDDR/LPDDR2/LPDDR3 or DDR4 designs: - 000 - Init - 001 - Normal - 010 - Power-down - 011 - Self refresh - 1XX - Deep power-down / Maximum Power Saving Mode LPDDR4 designs: - 000 - Init - 001 - Normal - 010 - Power-down - 011 - Self refresh / Self refresh power-down Programming Mode: Dynamic" "0,1,2,3,4,5,6,7"
group.long 0x10++0x3
line.long 0x00 "DDRCTL_MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en"
bitfld.long 0x00 31. " MR_WR                             ,Setting this register bit to 1 triggers a mode register read or write operation.When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 30. "         PBA_MODE                         ,Indicates whether PBA access is executed.When setting this bit to 1 along with setting pda_en to 1, uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by DDRCTL_MRSTAT.pda_done in the same way as PDA. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 12.--15. " MR_ADDR                           ,Address of the mode register that is to be written to.- 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see DDRCTL_MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is also used for writing to control words of the register chip on RDIMMs/LRDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM/LRDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs/LRDIMMs and the Output Inversion of RDIMMs/LRDIMMs. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--5. "        MR_RANK                          ,Controls which rank is accessed byDDRCTL_MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. Examples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 Programming Mode: Dynamic" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 3. " SW_INIT_INT                       ,Indicates whether Software intervention is allowed viaDDRCTL_MRCTRL0/DDRCTL_MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 dual channel mode, note that this must be programmed to both channels beforehand. Note that this must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software intervention is not allowed - 1 - Software intervention is allowed Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 2. "         PDA_EN                           ,Indicates whether the mode register operation is MRS in PDA mode or not -0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1, PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 1. " MPR_EN                            ,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) -0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         MR_TYPE                          ,Indicates whether the mode register operation is read or write.Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "0,1"
group.long 0x14++0x3
line.long 0x00 "DDRCTL_MRCTRL1,Mode Register Read/Write Control Register 1"
hexmask.long.tbyte 0x00 0.--17. 1. " MR_DATA                           ,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes.For LPDDR2/LPDDR3/LPDDR4, DDRCTL_MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic"
rgroup.long 0x18++0x3
line.long 0x00 "DDRCTL_MRSTAT,Mode Register Read/Write Status Register"
bitfld.long 0x00 8. " PDA_DONE                          ,The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low.This signal goes high when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM. This signal goes low when DDRCTL_MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write DDRCTL_MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time. - 0 - Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. - 1 - Indicates that mode register write operation related to PDA/PBA has competed. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         MR_WR_BUSY                       ,The SoC core may initiate a MR write operation only if this signal is low.This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'DDRCTL_MRSTAT.mr_wr_busy' is high. - 0 - Indicates that the SoC core can initiate a mode register write operation - 1 - Indicates that mode register write operation is in progress Programming Mode: Dynamic" "0,1"
group.long 0x1C++0x3
line.long 0x00 "DDRCTL_MRCTRL2,Mode Register Read/Write Control Register 2"
hexmask.long 0x00 0.--31. 1. " MR_DEVICE_SEL                     ,Indicates the device(s) to be selected during the MRS that happens in PDA mode.Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied to that device. A '0' indicates that the MRS commands should be skipped for that device. Programming Mode: Dynamic"
group.long 0x20++0x3
line.long 0x00 "DDRCTL_DERATEEN,Temperature Derate Enable Register"
bitfld.long 0x00 8.--10. " RC_DERATE_VALUE                   ,Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--7. "         DERATE_BYTE                      ,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating.The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 1.--2. " DERATE_VALUE                      ,Derate value -0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1 otherwise it should be set to 0. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0. "         DERATE_ENABLE                    ,Enables derating -0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. Programming Mode: Dynamic" "0,1"
group.long 0x24++0x3
line.long 0x00 "DDRCTL_DERATEINT,Temperature Derate Interval Register"
hexmask.long 0x00 0.--31. 1. " MR4_READ_INTERVAL                 ,Interval between two MR4 reads, used to derate the timing parameters.Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycle. Programming Mode: Static"
group.long 0x30++0x3
line.long 0x00 "DDRCTL_PWRCTL,Low Power Control Register"
bitfld.long 0x00 8. " LPDDR4_SR_ALLOWED                 ,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed.This register field cannot be modified while DDRCTL_PWRCTL.selfref_sw==1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 7. "         DIS_CAM_DRAIN_SELFREF            ,Indicates whether skipping CAM draining is allowed when entering Self-Refresh.This register field cannot be modified while DDRCTL_PWRCTL.selfref_sw==1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before entering SR Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 6. " STAY_IN_SELFREF                   ,Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4.This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow transition from Self refresh state Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 5. "         SELFREF_SW                       ,A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode.This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Software Exit from Self Refresh Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 4. " MPSM_EN                           ,When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty.This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 3. "         EN_DFI_DRAM_CLK_DISABLE          ,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM.If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in following: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asserted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 2. " DEEPPOWERDOWN_EN                  ,When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty.This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 1. "         POWERDOWN_EN                     ,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (DDRCTL_PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 0. " SELFREF_EN                        ,If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Self Refresh (DDRCTL_PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. Programming Mode: Dynamic" "0,1"
group.long 0x34++0x3
line.long 0x00 "DDRCTL_PWRTMG,Low Power Timing Register"
hexmask.long.byte 0x00 16.--23. 1. " SELFREF_TO_X32                    ,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into Self Refresh.The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the DDRCTL_PWRCTL.selfref_en. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. Programming Mode: Static"
hexmask.long.byte 0x00 8.--15. 1. "        T_DPD_X4096                      ,Minimum deep power-down time.For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after DDRCTL_PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. Programming Mode: Static"
textline "                                 "
bitfld.long 0x00 0.--4. " POWERDOWN_TO_X32                  ,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down.The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the DDRCTL_PWRCTL.powerdown_en. Unit: Multiples of 32 DFI clocks FOR PERFORMANCE ONLY. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x3
line.long 0x00 "DDRCTL_HWLPCTL,Hardware Low Power Control Register"
hexmask.long.word 0x00 16.--27. 1. " HW_LP_IDLE_X32                    ,Hardware idle period.The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. Programming Mode: Static"
bitfld.long 0x00 1. "      HW_LP_EXIT_IDLE_EN               ,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes.Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (DDRCTL_PWRCTL.selfref_sw). Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 0. " HW_LP_EN                          ,Enable for Hardware Low Power Interface.Programming Mode: Quasi-dynamic Group 3" "0,1"
group.long 0x50++0x3
line.long 0x00 "DDRCTL_RFSHCTL0,Refresh Control Register 0"
bitfld.long 0x00 20.--23. " REFRESH_MARGIN                    ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires.A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 may be equal to DDRCTL_RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DDRCTL_DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to DDRCTL_RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--16. "        REFRESH_TO_X32                   ,If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (DDRCTL_RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this DDRCTL_RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 4.--8. " REFRESH_BURST                     ,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute.Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of DDRCTL_RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PER_BANK_REFRESH                 ,-1 - Per bank refresh - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Programming Mode: Static" "0,1"
group.long 0x54++0x3
line.long 0x00 "DDRCTL_RFSHCTL1,Refresh Control Register 1"
hexmask.long.word 0x00 16.--27. 1. " REFRESH_TIMER1_START_VALUE_X32    ,Refresh timer start for rank 1 (only present in multi-rank configurations).This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY. Programming Mode: Dynamic - Refresh Related"
hexmask.long.word 0x00 0.--11. 1. "      REFRESH_TIMER0_START_VALUE_X32   ,Refresh timer start for rank 0 (only present in multi-rank configurations).This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY. Programming Mode: Dynamic - Refresh Related"
group.long 0x60++0x3
line.long 0x00 "DDRCTL_RFSHCTL3,Refresh Control Register 3"
bitfld.long 0x00 4.--6. " REFRESH_MODE                      ,Fine Granularity Refresh Mode -000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if DDRCTL_RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in future version of the uMCTL2. Note: This register field has effect only if a DDR4 SDRAM device is in use (DDRCTL_MSTR.ddr4 = 1). Programming Mode: Quasi-dynamic Group 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         REFRESH_UPDATE_LEVEL             ,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated.refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when exiting reset. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 0. " DIS_AUTO_REFRESH                  ,When '1', disable auto-refresh generated by the uMCTL2.When auto-refresh is disabled, the SoC core must generate refreshes using the registers DDRCTL_DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry is enabled (DDRCTL_CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled (DDRCTL_RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This register field is changeable on the fly. Programming Mode: Dynamic - Refresh Related" "0,1"
group.long 0x64++0x3
line.long 0x00 "DDRCTL_RFSHTMG,Refresh Timing Register"
hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32                     ,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4.See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (DDRCTL_RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (DDRCTL_RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that DDRCTL_RFSHTMG.t_rfc_nom_x32 * 32 must be greater than DDRCTL_RFSHTMG.t_rfc_min, and DDRCTL_RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or DDR4 Fixed 1x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed 2x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. Programming Mode: Dynamic - Refresh Related"
bitfld.long 0x00 15. "      LPDDR3_TREFBW_EN                 ,Used only when LPDDR3 memory type is connected.Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN                         ,tRFC (min): Minimum time from refresh to refresh or activate.When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. Programming Mode: Dynamic - Refresh Related"
group.long 0x70++0x3
line.long 0x00 "DDRCTL_ECCCFG0,ECC Configuration Register 0"
bitfld.long 0x00 4. " DIS_SCRUB                         ,Disable ECC scrubs.Valid only when DDRCTL_ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1"
bitfld.long 0x00 3. "         TEST_MODE                        ,If this bit is set to 1, no ECC is performed, and the ECC byte is accessed directly from co_wu_rxdata_ecc and ra_co_resp_ecc_data.This test mode is only supported with the HIF interface - it is disabled if UMCTL2_INCL_ARB is enabled. This test mode is only supported in full bus width mode. In other words, if DDRCTL_MSTR.data_bus_width is non-zero, this test_mode field must be set to 0. If test_mode is set to 1, the ecc_mode field is ignored. If MEMC_ECC_SUPPORT is 2 (Advanced ECC mode), this test_mode field must be set to 0. Note: test_mode is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 0.--2. " ECC_MODE                          ,ECC mode indicator -000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC - all other settings are reserved for future use Programming Mode: Static" "0,1,2,3,4,5,6,7"
group.long 0x74++0x3
line.long 0x00 "DDRCTL_ECCCFG1,ECC Configuration Register 1"
bitfld.long 0x00 1. " DATA_POISON_BIT                   ,Selects whether to poison 1 or 2 bits - if0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poisoning, if DDRCTL_ECCCFG1.data_poison_en=1. Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode: Quasi-dynamic Group 3" "0,1"
bitfld.long 0x00 0. "         DATA_POISON_EN                   ,Enable ECC data poisoning - introduces ECC errors on writes to address specified by the" "0,1"
rgroup.long 0x78++0x3
line.long 0x00 "DDRCTL_ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))"
bitfld.long 0x00 16.--19. " ECC_UNCORRECTED_ERR               ,Double-bit error indicators.In sideband ECC mode, 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode, there are only two lanes, so only the lower two bits are used. In inline ECC mode, the register always is 1 bit to indicate uncorrectable error on any lane. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        ECC_CORRECTED_ERR                ,Single-bit error indicators.In sideband ECC mode, 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode, there are only two lanes, so only the lower two bits are used. In inline ECC mode, the register always is 1 bit to indicate correctable error on any lane. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
hexmask.long.byte 0x00 0.--6. 1. " ECC_CORRECTED_BIT_NUM             ,Bit number corrected by single-bit ECC error.If more than one data lane has an error, the lower data lane is selected. This register is 7 bits wide in order to handle 72 bits of the data present in a single lane. Programming Mode: Static"
hgroup.long 0x7C++0x3
hide.long 0x00 "DDRCTL_ECCCLR,ECC Clear Register"
in
textline "                                 "
rgroup.long 0x80++0x3
line.long 0x00 "DDRCTL_ECCERRCNT,ECC Error Counter Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_UNCORR_ERR_CNT                ,Number of uncorrectable ECC errors detected.Note that the saturation behavior of this register is different, depending on whether SECDED ECC or advanced ECC is enabled. For advanced ECC, it saturates at 0xFFFF, while for SECDED ECC, it saturates at 0xFFFC or above. Programming Mode: Dynamic"
hexmask.long.word 0x00 0.--15. 1. "      ECC_CORR_ERR_CNT                 ,Number of correctable ECC errors detected.Note that the saturation behavior of this register is different, depending on whether SECDED ECC or advanced ECC is enabled. For advanced ECC, it saturates at 0xFFFF, while for SECDED ECC, it saturates at 0xFFFC or above. Programming Mode: Dynamic"
rgroup.long 0x84++0x3
line.long 0x00 "DDRCTL_ECCCADDR0,ECC Corrected Error Address Register 0"
bitfld.long 0x00 24. " ECC_CORR_RANK                     ,Rank number of a read resulting in a corrected ECC error Programming Mode: Dynamic" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "         ECC_CORR_ROW                     ,Page/row number of a read resulting in a corrected ECC error.This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic"
rgroup.long 0x88++0x3
line.long 0x00 "DDRCTL_ECCCADDR1,ECC Corrected Error Address Register 1"
bitfld.long 0x00 24.--25. " ECC_CORR_BG                       ,Bank Group number of a read resulting in a corrected ECC error Programming Mode: Dynamic" "0,1,2,3"
bitfld.long 0x00 16.--18. "         ECC_CORR_BANK                    ,Bank number of a read resulting in a corrected ECC error Programming Mode: Dynamic" "0,1,2,3,4,5,6,7"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " ECC_CORR_COL                      ,Block number of a read resulting in a corrected ECC error (lowest bit not assigned here) Programming Mode: Dynamic"
rgroup.long 0x8C++0x3
line.long 0x00 "DDRCTL_ECCCSYN0,ECC Corrected Syndrome Register 0"
hexmask.long 0x00 0.--31. 1. " ECC_CORR_SYNDROMES_31_0           ,Data pattern that resulted in a corrected error.For 16-bit ECC, only bits [15:0] are used Programming Mode: Dynamic"
rgroup.long 0x94++0x3
line.long 0x00 "DDRCTL_ECCCSYN2,ECC Corrected Syndrome Register 2"
hexmask.long.byte 0x00 0.--7. 1. " ECC_CORR_SYNDROMES_71_64          ,Data pattern that resulted in a corrected error one for each ECC lane, all concatenated together This register refers to the ECC byte, which is bits[71:64] for 64-bit ECC, [39:32] for 32-bit ECC, or [23:16] for 16-bit ECC Programming Mode: Dynamic"
rgroup.long 0x98++0x3
line.long 0x00 "DDRCTL_ECCBITMASK0,ECC Corrected Data Bit Mask Register 0"
hexmask.long 0x00 0.--31. 1. " ECC_CORR_BIT_MASK_31_0            ,Mask for the corrected data portion - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates data over multiple ECC errors, to give an overall indication of which bits are being fixed.It is cleared by writing a 1 to DDRCTL_ECCCLR.ecc_clr_corr_err. For 16-bit ECC, only bits [15:0] are used Programming Mode: Dynamic"
rgroup.long 0xA0++0x3
line.long 0x00 "DDRCTL_ECCBITMASK2,ECC Corrected Data Bit Mask Register 2"
hexmask.long.byte 0x00 0.--7. 1. " ECC_CORR_BIT_MASK_71_64           ,Mask for the corrected data portion - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates data over multiple ECC errors, to give an overall indication of which bits are being fixed.It is cleared by writing a 1 to DDRCTL_ECCCLR.ecc_clr_corr_err. This register refers to the ECC byte, which is bits [71:64] for 64-bit ECC, [39:32] for 32-bit ECC, or [23:16] for 16-bit ECC Programming Mode: Dynamic"
rgroup.long 0xA4++0x3
line.long 0x00 "DDRCTL_ECCUADDR0,ECC Uncorrected Error Address Register 0"
bitfld.long 0x00 24. " ECC_UNCORR_RANK                   ,Rank number of a read resulting in an uncorrected ECC error Programming Mode: Dynamic" "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "         ECC_UNCORR_ROW                   ,Page/row number of a read resulting in an uncorrected ECC error.This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic"
rgroup.long 0xA8++0x3
line.long 0x00 "DDRCTL_ECCUADDR1,ECC Uncorrected Error Address Register 1"
bitfld.long 0x00 24.--25. " ECC_UNCORR_BG                     ,Bank Group number of a read resulting in an uncorrected ECC error Programming Mode: Dynamic" "0,1,2,3"
bitfld.long 0x00 16.--18. "         ECC_UNCORR_BANK                  ,Bank number of a read resulting in an uncorrected ECC error Programming Mode: Dynamic" "0,1,2,3,4,5,6,7"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " ECC_UNCORR_COL                    ,Block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here) Programming Mode: Dynamic"
rgroup.long 0xAC++0x3
line.long 0x00 "DDRCTL_ECCUSYN0,ECC Uncorrected Syndrome Register 0"
hexmask.long 0x00 0.--31. 1. " ECC_UNCORR_SYNDROMES_31_0         ,Data pattern that resulted in an uncorrected error, one for each ECC lane, all concatenated together.For 16-bit ECC, only bits [15:0] are used Programming Mode: Dynamic"
rgroup.long 0xB4++0x3
line.long 0x00 "DDRCTL_ECCUSYN2,ECC Uncorrected Syndrome Register 2"
hexmask.long.byte 0x00 0.--7. 1. " ECC_UNCORR_SYNDROMES_71_64        ,Data pattern that resulted in an uncorrected error one for each ECC lane, all concatenated together.This register refers to the ECC byte, which is bits [71:64] for 64-bit ECC, [39:32] for 32-bit ECC, or [23:16] for 16-bit ECC Programming Mode: Dynamic"
group.long 0xB8++0x3
line.long 0x00 "DDRCTL_ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register, an ECC error will be introduced on that transaction (write/RMW), if .data_poison_en=1"
bitfld.long 0x00 24. " ECC_POISON_RANK                   ,Rank address for ECC poisoning Programming Mode: Static" "0,1"
hexmask.long.word 0x00 0.--11. 1. "         ECC_POISON_COL                   ,Column address for ECC poisoning.Note that this column address must be burst aligned: - In full bus width mode, ecc_poison_col[2:0] must be set to 0 - In half bus width mode, ecc_poison_col[3:0] must be set to 0 - In quarter bus width mode, ecc_poison_col[4:0] must be set to 0 Programming Mode: Static"
group.long 0xBC++0x3
line.long 0x00 "DDRCTL_ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register, an ECC error will be introduced on that transaction (write/RMW), if .data_poison_en=1"
bitfld.long 0x00 28.--29. " ECC_POISON_BG                     ,Bank Group address for ECC poisoning Programming Mode: Static" "0,1,2,3"
bitfld.long 0x00 24.--26. "         ECC_POISON_BANK                  ,Bank address for ECC poisoning Programming Mode: Static" "0,1,2,3,4,5,6,7"
textline "                                 "
hexmask.long.tbyte 0x00 0.--17. 1. " ECC_POISON_ROW                    ,Row address for ECC poisoning.This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static"
hgroup.long 0xC0++0x3
hide.long 0x00 "DDRCTL_CRCPARCTL0,CRC Parity Control Register0"
in
textline "                                 "
group.long 0xC4++0x3
line.long 0x00 "DDRCTL_CRCPARCTL1,CRC Parity Control Register1"
hexmask.long.byte 0x00 24.--30. 1. " DFI_T_PHY_RDLAT                   ,The maximum time allowed from the assertion of the dfi_rddata_en signal to the assertion of each of the corresponding bits of the dfi_rddata_valid signal.This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY specification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by DDRCTL_CRCPARCTL1.crc_parity_retry_enable=1. When the controller is operating in 1:2 frequency ratio mode, program this to the DFI timing parameter tphy_rdlat/2, and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode: Static"
bitfld.long 0x00 16.--18. "        RETRY_ADD_RD_LAT                 ,Retry additional read latency value.Delay value used is retry_add_rd_lat+1. Only used if DDRCTL_CRCPARCTL1.retry_add_rd_lat_en is enabled. Selects the number of pipeline stages to dfi_rddata_valid/dfi_rddata/dfi_rddata_dbi before rest of internal uMCTL2 logic observes it. Required to compensate for fact delay in PHY/PCB for generating dfi_alert_n for retry may be more than the delay in PHY/PCB on read data path. Recommended settings (in terms of core_ddrc_core_clk): (Maximum Alert delay through PHY/PCB from erroneous read command including tPAR_UNKNOWN) - (Minimum Read data delay through PHY/PCB from erroneous read command) + (PHY's max granularity of dfi_rddata beats that may be corrupted before erroneous Read) Note: This calculation depends on various items such as RL, tPAR_ALERT_ON/tPAR_UNKNOWN/RCD/PHY/PCB behavior. Unit: DFI clock cycles. Programming Mode: Static" "0,1,2,3,4,5,6,7"
textline "                                 "
bitfld.long 0x00 15. " RETRY_ADD_RD_LAT_EN               ,Retry additional read latency enable.Number of pipeline stages selected is defined as DDRCTL_CRCPARCTL1.retry_add_lat+1. Only set if DDRCTL_CRCPARCTL1.crc_parity_retry_enable = 1 Programming Mode: Static" "0,1"
bitfld.long 0x00 12. "         CAPARITY_DISABLE_BEFORE_SR       ,If DDR4-SDRAM's CA parity is enabled by DDRCTL_INIT6.mr5[2:0]!=0 and this register is set to 1, CA parity is automatically disabled before Self-Refresh entry and enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by DDRCTL_MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DDRCTL_DRAMTMG5.t_ckesr and DDRCTL_DRAMTMG5.t_cksre must be increased by PL(Parity latency) Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 9. " ALERT_WAIT_FOR_SW                 ,After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DRAM before the hardware begins the retry process -1: Wait for software to read/write the mode registers before hardware begins the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (CRCPARCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register after handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of Parity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode register bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in the Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is done for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don't care'. Programming Mode: Static" "0,1"
bitfld.long 0x00 8. "         CRC_PARITY_RETRY_ENABLE          ,-1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity or CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (DDRCTL_MSTR.burstchop = 1) and/or disable auto-refresh is enabled (DDRCTL_RFSHCTL3.dis_auto_refresh = 1) Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 7. " CRC_INC_DM                        ,CRC Calculation setting register -1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "0,1"
bitfld.long 0x00 4. "         CRC_ENABLE                       ,CRC enable Register -1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 0. " PARITY_ENABLE                     ,C/A Parity enable register -1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, this register should be 1. Programming Mode: Static" "0,1"
group.long 0xC8++0x3
line.long 0x00 "DDRCTL_CRCPARCTL2,CRC Parity Control Register2"
hexmask.long.word 0x00 16.--24. 1. " T_PAR_ALERT_PW_MAX                ,Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs.Recommended values: - tPAR_ALERT_PW.MAX When the controller is operating in 1:2 frequency ratio mode, program this to tPAR_ALERT_PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are illegal. This value must be greater than DDRCTL_CRCPARCTL2.t_crc_alert_pw_max. Programming Mode: Static"
bitfld.long 0x00 8.--12. "      T_CRC_ALERT_PW_MAX               ,Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs.Recommended values: - tCRC_ALERT_PW.MAX When the controller is operating in 1:2 frequency ratio mode, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are illegal. This value must be less than DDRCTL_CRCPARCTL2.t_par_alert_pw_max. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 0.--5. " RETRY_FIFO_MAX_HOLD_TIMER_X4      ,Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO before it is popped out.Every location in the Command Retry FIFO has an associated down counting timer that will use this register as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cycles. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC error occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recommended(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RCD delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay + PHY's max granularity of dfi_rddata beats that may be corrupted before erroneous Read) / 4) + 2 - Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RCD delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - If both C/A Parity and CRC are enabled. Use max of (Only C/A Parity is enabled, Only CRC is enabled) Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The Recommended values are minimum value to be set. Note 5: RCD delay above refers to RDIMMs and LRDIMMs. Note 6: PHY's max granularity of dfi_rddata beats that may be corrupted before erroneous Read is depends on the internal architecture of the PHY. Max value can be set to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 2 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 12 - MEMC_BURST_LENGTH != 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 2 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 3 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH - 6 Values of 0, 1 and 2 are illegal. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xCC++0x3
line.long 0x00 "DDRCTL_CRCPARSTAT,CRC Parity Status Register"
bitfld.long 0x00 29. " CMD_IN_ERR_WINDOW                 ,Indicate if commands are in the parity/crc error window.- 0 - No command is in the parity/crc error window. - 1 - One or more commands are in the parity/crc error window or retry is in progress. This register is valid when CRCPARCTRL1.crc_parity_retry_enable=1. Programming Mode: Static" "0,1"
bitfld.long 0x00 28. "         RETRY_OPERATING_MODE             ,Operating mode of retry -0 - Normal - 1 - Retry due to CRC/Parity error is in progress Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 24.--27. " RETRY_CURRENT_STATE               ,Indicate current retry state for debug purposes only -0000 - IDLE:Retry is not enabled - 0001 - MON_DFI:Retry is enabled and monitoring DFI - 0010 - DETECTED ALERT:Detected dfi_alert_n - 0011 - WAKE_UP:Waking up from self-refresh state - 0100 - PRECHRGING:Pre-charging banks - 0101 - SEND_REF1:Sending extra REFs before software intervention time - 0110 - CTRLUPD:Issuing control update from retry logic - 0111 - WAIT_SW:Software intervention time - 1000 - SEND_REF2:Sending extra REFs before retrying commands - 1001 - RETRY_COMMANDS:Retrying commands - 1010 - RESTART_RETRY:Restarting retry due to alert_n detection during retry - 1111 - FATL_ERR:Fatal error detected FOR DEBUG PURPOSE ONLY Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--22. "        DFI_ALERT_ERR_FATL_CODE          ,Indicate reason of dfi_alert_err_fatl_int assertion - [22] MPSMX caused parity error.(RCD's parity error detection only) - [21] Parity error happens again during software intervention time - [20] MRS was in retry_fifo_max_hold_timer_x4 window from alert_n=0 or DDRCTL_STAT.operating_mode is Init. Two or more reason can be available at the same time It remains set until cleared by DDRCTL_CRCPARCTL0.dfi_alert_err_fatl_clr. Programming Mode: Static" "0,1,2,3,4,5,6,7"
textline "                                 "
bitfld.long 0x00 19. " DFI_ALERT_ERR_NO_SW               ,Indicate whether software can perform MRS/MPR/PDA during software intervention time.- 0 - MRS/MPR/PDA can be performed during software intervention time - 1 - MRS/MPR/PDA can NOT be performed during software intervention time If DDRCTL_CRCPARCTL1.alert_wait_for_sw=1 and dfi_alert_err_no_sw=1, software can not perform MRS/MPR/PDA until dfi_alert_err_int is cleared by dfi_alert_err_int_clr. It remains set until cleared by DDRCTL_CRCPARCTL0.dfi_alert_err_int_clr. Programming Mode: Static" "0,1"
bitfld.long 0x00 18. "         DFI_ALERT_ERR_MAX_REACHED_INT    ,DFI alert error counter max reached interrupt.If the DDRCTL_CRCPARSTAT.dfi_alert_err_cnt reaches it maximum value, this interrupt bit is set. It remains set until cleared by DDRCTL_CRCPARCTL0.dfi_alert_err_int_clr Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 17. " DFI_ALERT_ERR_FATL_INT            ,Fatal parity error interrupt.One or more these situation below happens, this interrupt bit is set. - MPSMX caused parity error. (RCD's parity error detection only) - Parity error happens again during software intervention time - MRS was in retry_fifo_max_hold_timer_x4 window from alert_n=0 or DDRCTL_STAT.operating_mode is Init. It remains set until cleared by DDRCTL_CRCPARCTL0.dfi_alert_err_fatl_clr. If this interrupt is asserted, system reset is strongly recommended. Programming Mode: Static" "0,1"
bitfld.long 0x00 16. "         DFI_ALERT_ERR_INT                ,DFI alert error interrupt.If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by DDRCTL_CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by DDRCTL_CRCPARCTL0.dfi_alert_err_int_clr Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.word 0x00 0.--15. 1. " DFI_ALERT_ERR_CNT                 ,DFI alert error count.If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of DDRCTL_CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting DDRCTL_CRCPARCTL0.dfi_alert_err_cnt_clr. Programming Mode: Static"
group.long 0xD0++0x3
line.long 0x00 "DDRCTL_INIT0,SDRAM Initialization Register 0"
bitfld.long 0x00 30.--31. " SKIP_DRAM_INIT                    ,If lower bit is enabled the SDRAM initialization routine is skipped.The upper bit decides what state the controller starts up in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skipped after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Programming Mode: Quasi-dynamic Group 2" "0,1,2,3"
hexmask.long.word 0x00 16.--25. 1. "         POST_CKE_X1024                   ,Cycles to wait after driving CKE high to start the SDRAM initialization sequence.Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Programming Mode: Static"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " PRE_CKE_X1024                     ,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence.Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this should include the time needed to satisfy tSTAB Programming Mode: Static"
group.long 0xD4++0x3
line.long 0x00 "DDRCTL_INIT1,SDRAM Initialization Register 1"
hexmask.long.word 0x00 16.--24. 1. " DRAM_RSTN_X1024                   ,Number of cycles to assert SDRAM reset signal during init sequence.This is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 1024 DFI clock cycles. Programming Mode: Static"
bitfld.long 0x00 0.--3. "      PRE_OCD_X32                      ,Wait period before driving the OCD complete command to SDRAM.Unit: Counts of a global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for this it may be set to zero. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD8++0x3
line.long 0x00 "DDRCTL_INIT2,SDRAM Initialization Register 2"
hexmask.long.byte 0x00 8.--15. 1. " IDLE_AFTER_RESET_X32              ,Idle time after the reset command, tINIT4.Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles. Programming Mode: Static"
bitfld.long 0x00 0.--3. "        MIN_STABLE_CLOCK_X1              ,Time to wait after the first CKE high, tINIT2.Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xDC++0x3
line.long 0x00 "DDRCTL_INIT3,SDRAM Initialization Register 3"
hexmask.long.word 0x00 16.--31. 1. " MR                                ,DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register Programming Mode: Quasi-dynamic Group 1 and Group 4"
hexmask.long.word 0x00 0.--15. 1. "      EMR                              ,DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register Programming Mode: Quasi-dynamic Group 4"
group.long 0xE0++0x3
line.long 0x00 "DDRCTL_INIT4,SDRAM Initialization Register 4"
hexmask.long.word 0x00 16.--31. 1. " EMR2                              ,DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused Programming Mode: Quasi-dynamic Group 4"
hexmask.long.word 0x00 0.--15. 1. "      EMR3                             ,DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0xE4++0x3
line.long 0x00 "DDRCTL_INIT5,SDRAM Initialization Register 5"
hexmask.long.byte 0x00 16.--23. 1. " DEV_ZQINIT_X32                    ,ZQ initial calibration, tZQINIT.Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles. Programming Mode: Static"
hexmask.long.word 0x00 0.--9. 1. "        MAX_AUTO_INIT_X1024              ,Maximum duration of the auto initialization, tINIT5.Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI clock cycles. Programming Mode: Static"
group.long 0xE8++0x3
line.long 0x00 "DDRCTL_INIT6,SDRAM Initialization Register 6"
hexmask.long.word 0x00 16.--31. 1. " MR4                               ,DDR4- Value to be loaded into SDRAM MR4 registers. LPDDR4- Value to be loaded into SDRAM MR11 registers. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.word 0x00 0.--15. 1. "      MR5                              ,DDR4- Value to be loaded into SDRAM MR5 registers. LPDDR4- Value to be loaded into SDRAM MR12 registers. Programming Mode: Quasi-dynamic Group 1 and Group 4"
group.long 0xEC++0x3
line.long 0x00 "DDRCTL_INIT7,SDRAM Initialization Register 7"
hexmask.long.word 0x00 16.--31. 1. " MR22                              ,LPDDR4- Value to be loaded into SDRAM MR22 registers. Used in LPDDR4 designs only. Programming Mode: Quasi-dynamic Group 4"
hexmask.long.word 0x00 0.--15. 1. "      MR6                              ,DDR4- Value to be loaded into SDRAM MR6 registers. LPDDR4- Value to be loaded into SDRAM MR14 registers. Programming Mode: Quasi-dynamic Group 4"
group.long 0xF0++0x3
line.long 0x00 "DDRCTL_DIMMCTL,DIMM Control Register"
bitfld.long 0x00 6. " LRDIMM_BCOM_CMD_PROT              ,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification.When using DDR4 LRDIMM, this bit must be set to 1. Otherwise, this bit must be set to 0. Programming Mode: Static" "0,1"
bitfld.long 0x00 5. "         DIMM_DIS_BG_MIRRORING            ,Disabling Address Mirroring for BG bits.When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. Programming Mode: Static" "0,1"
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bitfld.long 0x00 4. " MRS_BG1_EN                        ,Enable for BG1 bit of MRS command.BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled Programming Mode: Static" "0,1"
bitfld.long 0x00 3. "         MRS_A17_EN                       ,Enable for A17 bit of MRS command.A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 2. " DIMM_OUTPUT_INV_EN                ,Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only).DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initialization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. For B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM/LRDIMM inversion. It is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. Programming Mode: Static" "0,1"
bitfld.long 0x00 1. "         DIMM_ADDR_MIRR_EN                ,Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations).Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) - 0 - Do not implement address mirroring Programming Mode: Static" "0,1"
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bitfld.long 0x00 0. " DIMM_STAGGER_CS_EN                ,Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only).This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via DDRCTL_MRCTRL0/DDRCTL_MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands to each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses Programming Mode: Static" "0,1"
group.long 0xF4++0x3
line.long 0x00 "DDRCTL_RANKCTL,Rank Control Register"
bitfld.long 0x00 8.--11. " DIFF_RANK_WR_GAP                  ,Only present for multi-rank configurations.Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4 only), should be increased by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification. Programming Mode: Quasi-dynamic Group 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DIFF_RANK_RD_GAP                 ,Only present for multi-rank configurations.Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap If read preamble is set to 2tCK(DDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--3. " MAX_RANK_RD                       ,Only present for multi-rank configurations.Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register DDRCTL_RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis therefore after a read is scheduled, there are few clock cycles (determined by the value on DDRCTL_RANKCTL.diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to DDRCTL_RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x100++0x3
line.long 0x00 "DDRCTL_DRAMTMG0,SDRAM Timing Register 0"
hexmask.long.byte 0x00 24.--30. 1. " WR2PRE                            ,Minimum time between write and precharge to same bank.Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4"
bitfld.long 0x00 16.--21. "        T_FAW                            ,tFAW Valid only when 8 or more banks(or banks x bank groups) are present.In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX                         ,tRAS(max): Maximum time between activate and precharge to same bank.This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 0.--5. "        T_RAS_MIN                        ,tRAS(min): Minimum time between activate and precharge to the same bank.When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x104++0x3
line.long 0x00 "DDRCTL_DRAMTMG1,SDRAM Timing Register 1"
bitfld.long 0x00 16.--20. " T_XP                              ,tXP: Minimum time after power-down exit to any operation.For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. If LPDDR4 is selected and its spec has tCKELPD parameter, set to the larger of tXP and tCKELPD instead. When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. Units: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RD2PRE                           ,tRTP: Minimum time from read to precharge of same bank.- DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.byte 0x00 0.--6. 1. " T_RC                              ,tRC: Minimum time between activates to same bank.When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x108++0x3
line.long 0x00 "DDRCTL_DRAMTMG2,SDRAM Timing Register 2"
bitfld.long 0x00 24.--29. " WRITE_LATENCY                     ,Set to WL Time from write command to write data on SDRAM interface.This must be set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DDRCTL_DFITMG0 and DDRCTL_DFITMG1 are sufficient for those protocols Unit: clocks Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        READ_LATENCY                     ,Set to RL Time from read command to read data on SDRAM interface.This must be set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DDRCTL_DFITMG0 and DDRCTL_DFITMG1 are sufficient for those protocols Unit: clocks Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 8.--13. " RD2WR                             ,DDR2/3/mDDR: RL + BL/2 +2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DDRCTL_DERATEEN.derate_enable=1), derated tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        WR2RD                            ,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - WL = Write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10C++0x3
line.long 0x00 "DDRCTL_DRAMTMG3,SDRAM Timing Register 3"
hexmask.long.word 0x00 20.--29. 1. " T_MRW                             ,Time to wait after a mode register write or read (MRW or MRR).Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 12.--17. "      T_MRD                            ,tMRD: Cycles to wait after a mode register write or read.Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.word 0x00 0.--9. 1. " T_MOD                             ,tMOD: Parameter used only in DDR3 and DDR4.Cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. If MPR writes for DDR4 are used, set to tMOD + AL (or tMPD_PAR + AL if C/A parity is also used). Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x110++0x3
line.long 0x00 "DDRCTL_DRAMTMG4,SDRAM Timing Register 4"
bitfld.long 0x00 24.--28. " T_RCD                             ,tRCD - tAL: Minimum time from activate to read or write command to same bank.When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. Unit: Clocks. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--19. "        T_CCD                            ,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " T_RRD                             ,DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        T_RP                             ,tRP: Minimum time from precharge to activate of same bank.When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x114++0x3
line.long 0x00 "DDRCTL_DRAMTMG5,SDRAM Timing Register 5"
bitfld.long 0x00 24.--27. " T_CKSRX                           ,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX.Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        T_CKSRE                          ,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKELCK - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) (*)Only if DDRCTL_CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--13. " T_CKESR                           ,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles.Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKE, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity latency)(*)) (*)Only if DDRCTL_CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--4. "        T_CKE                            ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh.- LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x118++0x3
line.long 0x00 "DDRCTL_DRAMTMG6,SDRAM Timing Register 6"
bitfld.long 0x00 24.--27. " T_CKDPDE                          ,This is the time after Deep Power Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        T_CKDPDX                         ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX.Specifies the clock stable time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--3. " T_CKCSX                           ,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit.Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11C++0x3
line.long 0x00 "DDRCTL_DRAMTMG7,SDRAM Timing Register 7"
bitfld.long 0x00 8.--11. " T_CKPDE                           ,This is the time after Power Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKELCK When using DDR2/3/4 SDRAM, this register should be set to the same value as DDRCTL_DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        T_CKPDX                          ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX.Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the same value as DDRCTL_DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x120++0x3
line.long 0x00 "DDRCTL_DRAMTMG8,SDRAM Timing Register 8"
hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32                     ,tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode).When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.byte 0x00 16.--22. 1. "        T_XS_ABORT_X32                   ,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32. Programming Mode: Quasi-dynamic Group 2 and Group 4"
textline "                                 "
hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32                      ,tXSDLL: Exit Self Refresh to commands requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.byte 0x00 0.--6. 1. "        T_XS_X32                         ,tXS: Exit Self Refresh to commands not requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x124++0x3
line.long 0x00 "DDRCTL_DRAMTMG9,SDRAM Timing Register 9"
bitfld.long 0x00 30. " DDR4_WR_PREAMBLE                  ,DDR4 Write preamble mode -0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
bitfld.long 0x00 16.--18. "         T_CCD_S                          ,tCCD_S: This is the minimum time between two reads or two writes for different bank group.For bank switching (from bank 'a' to bank 'b'), the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
textline "                                 "
bitfld.long 0x00 8.--11. " T_RRD_S                           ,tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group.When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "        WR2RD_S                          ,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group.Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x3
line.long 0x00 "DDRCTL_DRAMTMG10,SDRAM Timing Register 10"
bitfld.long 0x00 16.--20. " T_SYNC_GEAR                       ,Indicates the time between MRS command and the sync pulse time.This must be even number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        T_CMD_GEAR                       ,Sync pulse to first valid command.For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 2.--3. " T_GEAR_SETUP                      ,Geardown setup time.Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--1. "         T_GEAR_HOLD                      ,Geardown hold time.Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
group.long 0x12C++0x3
line.long 0x00 "DDRCTL_DRAMTMG11,SDRAM Timing Register 11"
hexmask.long.byte 0x00 24.--30. 1. " POST_MPSM_GAP_X32                 ,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Multiples of 32 clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 16.--20. "        T_MPX_LH                         ,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge.When the controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--9. " T_MPX_S                           ,tMPX_S: Minimum time CS setup time to CKE.When the controller is operating in 1:2 frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--4. "         T_CKMPE                          ,tCKMPE: Minimum valid clock requirement after MPSM entry.Present only in designs configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x130++0x3
line.long 0x00 "DDRCTL_DRAMTMG12,SDRAM Timing Register 12"
bitfld.long 0x00 16.--17. " T_CMDCKE                          ,tCMDCKE: Delay from valid command to CKE input LOW.Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--4. "         T_MRD_PDA                        ,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up to the next integer value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x134++0x3
line.long 0x00 "DDRCTL_DRAMTMG13,SDRAM Timing Register 13"
hexmask.long.byte 0x00 24.--30. 1. " ODTLOFF                           ,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 16.--21. "        T_CCD_MW                         ,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 0.--2. " T_PPD                             ,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
group.long 0x138++0x3
line.long 0x00 "DDRCTL_DRAMTMG14,SDRAM Timing Register 14"
hexmask.long.word 0x00 0.--11. 1. " T_XSR                             ,tXSR: Exit Self Refresh to any command.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x13C++0x3
line.long 0x00 "DDRCTL_DRAMTMG15,SDRAM Timing Register 15"
bitfld.long 0x00 31. " EN_DFI_LP_T_STAB                  ,-1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         T_STAB_X32                       ,tSTAB: Stabilization time.It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of input clock frequency change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock cycles. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x180++0x3
line.long 0x00 "DDRCTL_ZQCTL0,ZQ Control Register 0"
bitfld.long 0x00 31. " DIS_AUTO_ZQ                       ,-1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DDRCTL_DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on DDRCTL_ZQCTL1.t_zq_short_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 30. "         DIS_SRX_ZQCL                     ,-1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
textline "                                 "
bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED                ,-1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static" "0,1"
bitfld.long 0x00 28. "         DIS_MPSMX_ZQCL                   ,-1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the UMCTL2_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode. Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP                     ,tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
hexmask.long.word 0x00 0.--9. 1. "      T_ZQ_SHORT_NOP                   ,tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
group.long 0x184++0x3
line.long 0x00 "DDRCTL_ZQCTL1,ZQ Control Register 1"
hexmask.long.word 0x00 20.--29. 1. " T_ZQ_RESET_NOP                    ,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM.When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
hexmask.long.tbyte 0x00 0.--19. 1. "      T_ZQ_SHORT_INTERVAL_X1024        ,Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.Meaningless, if DDRCTL_ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
group.long 0x188++0x3
line.long 0x00 "DDRCTL_ZQCTL2,ZQ Control Register 2"
bitfld.long 0x00 0. " ZQ_RESET                          ,Setting this register bit to 1 triggers a ZQ Reset operation.When the ZQ Reset operation is complete, the uMCTL2 automatically clears this bit. It is recommended NOT to set this signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Dynamic" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "DDRCTL_ZQSTAT,ZQ Status Register"
bitfld.long 0x00 0. " ZQ_RESET_BUSY                     ,SoC core may initiate a ZQ Reset operation only if this signal is low.This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQ Reset operation - 1 - Indicates that ZQ Reset operation is in progress Programming Mode: Dynamic" "0,1"
group.long 0x190++0x3
line.long 0x00 "DDRCTL_DFITMG0,DFI Timing Register 0"
bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY                  ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion.If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "        DFI_RDDATA_USE_DFI_PHY_CLK       ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values.Selects whether value in DDRCTL_DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. If using a DWC DDR3/2 PHY, DWC DDR2/3-Lite/mDDR PHY, DWC DDR multiPHY or DWC Gen2 DDR multiPHY, this field must be set to 0 otherwise: - If MEMC_PROG_FREQ_RATIO=1 and DDRCTL_MSTR.frequency_ratio=1, this field should be set to 0 - Else, it must be set to 1 Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN                   ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal.Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_rddata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 1 and Group 4"
bitfld.long 0x00 15. "        DFI_WRDATA_USE_DFI_PHY_CLK       ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value inDDRCTL_DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in DDRCTL_DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. If using a DWC DDR3/2 PHY, DWC DDR2/3-Lite/mDDR PHY, DWC DDR multiPHY or DWC Gen2 DDR multiPHY, this field must be set to 0 otherwise: - If MEMC_PROG_FREQ_RATIO=1 and DDRCTL_MSTR.frequency_ratio=1, this field should be set to 0 - Else, it must be set to 1 Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA                   ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal.This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DFI_TPHY_WRLAT                   ,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en).This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. For LPDDR4, dfi_tphy_wrlat>60 is not supported. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x194++0x3
line.long 0x00 "DDRCTL_DFITMG1,DFI Timing Register 1"
bitfld.long 0x00 28.--31. " DFI_T_CMD_LAT                     ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven.This field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "        DFI_T_PARIN_LAT                  ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven.Programming Mode: Quasi-dynamic Group 4" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 16.--20. " DFI_T_WRDATA_DELAY                ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value. Unit: Clocks Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        DFI_T_DRAM_CLK_DISABLE           ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value.If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 0.--4. " DFI_T_DRAM_CLK_ENABLE             ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary.If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x198++0x3
line.long 0x00 "DDRCTL_DFILPCFG0,DFI Low Power Configuration Register 0"
bitfld.long 0x00 24.--28. " DFI_TLP_RESP                      ,Setting in DFI clock cycles for DFI's tlp_resp time.Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--23. "        DFI_LP_WAKEUP_DPD                ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered.Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 16. " DFI_LP_EN_DPD                     ,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit.- 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "0,1"
bitfld.long 0x00 12.--15. "         DFI_LP_WAKEUP_SR                 ,Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered.Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8. " DFI_LP_EN_SR                      ,Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit.- 0 - Disabled - 1 - Enabled Programming Mode: Static" "0,1"
bitfld.long 0x00 4.--7. "         DFI_LP_WAKEUP_PD                 ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered.Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0. " DFI_LP_EN_PD                      ,Enables DFI Low Power interface handshaking during Power Down Entry/Exit.- 0 - Disabled - 1 - Enabled Programming Mode: Static" "0,1"
group.long 0x19C++0x3
line.long 0x00 "DDRCTL_DFILPCFG1,DFI Low Power Configuration Register 1"
bitfld.long 0x00 4.--7. " DFI_LP_WAKEUP_MPSM                ,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered.Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        DFI_LP_EN_MPSM                   ,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit.- 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "0,1"
group.long 0x1A0++0x3
line.long 0x00 "DDRCTL_DFIUPD0,DFI Update Register 0"
bitfld.long 0x00 31. " DIS_AUTO_CTRLUPD                  ,When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2.The core must issue the dfi_ctrlupd_req signal using register DDRCTL_DBGCMD.ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode: Quasi-dynamic Group 3" "0,1"
bitfld.long 0x00 30. "         DIS_AUTO_CTRLUPD_SRX             ,When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit.When '0', uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DDRCTL_DFIUPD0.ctrlupd_pre_srx. Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 29. " CTRLUPD_PRE_SRX                   ,Selects dfi_ctrlupd_req requirements at SRX: -0 : send ctrlupd after SRX - 1 : send ctrlupd before SRX If DDRCTL_DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX. Programming Mode: Static" "0,1"
hexmask.long.word 0x00 16.--25. 1. "         DFI_T_CTRLUP_MAX                 ,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert.Lowest value to assign to this variable is 0x40. Programming Mode: Static"
textline "                                 "
hexmask.long.word 0x00 0.--9. 1. " DFI_T_CTRLUP_MIN                  ,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted.The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. Programming Mode: Static"
group.long 0x1A4++0x3
line.long 0x00 "DDRCTL_DFIUPD1,DFI Update Register 1"
hexmask.long.byte 0x00 16.--23. 1. " DFI_T_CTRLUPD_INTERVAL_MIN_X1024  ,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle).Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI clock cycles Programming Mode: Static"
hexmask.long.byte 0x00 0.--7. 1. "        DFI_T_CTRLUPD_INTERVAL_MAX_X1024 ,This is the maximum amount of time between uMCTL2 initiated DFI update requests.This timer resets with each update request when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. Note: Value programmed for DDRCTL_DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DDRCTL_DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles Programming Mode: Static"
group.long 0x1A8++0x3
line.long 0x00 "DDRCTL_DFIUPD2,DFI Update Register 2"
bitfld.long 0x00 31. " DFI_PHYUPD_EN                     ,Enables the support for acknowledging PHY-initiated updates: -0 - Disabled - 1 - Enabled Programming Mode: Static" "0,1"
group.long 0x1B0++0x3
line.long 0x00 "DDRCTL_DFIMISC,DFI Miscellaneous Control Register"
bitfld.long 0x00 8.--12. " DFI_FREQUENCY                     ,Indicates the operating frequency of the system.The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "        DFI_INIT_START                   ,PHY init start request signal.When asserted it triggers the PHY init start request Programming Mode: Quasi-dynamic Group 3" "0,1"
textline "                                 "
bitfld.long 0x00 4. " CTL_IDLE_EN                       ,Enables support of ctl_idle signal, which is non-DFI related pin.See signal description of ctl_idle signal for further details of ctl_idle functionality. Programming Mode: Static" "0,1"
bitfld.long 0x00 2. "         DFI_DATA_CS_POLARITY             ,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.- 0: Signals are active low - 1: Signals are active high Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 1. " PHY_DBI_MODE                      ,DBI implemented in DDRC or PHY.- 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "0,1"
bitfld.long 0x00 0. "         DFI_INIT_COMPLETE_EN             ,PHY initialization complete enable signal.When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1"
group.long 0x1B4++0x3
line.long 0x00 "DDRCTL_DFITMG2,DFI Timing Register 2"
hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT                  ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted.This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 0.--5. "        DFI_TPHY_WRCSLAT                 ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted.This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B8++0x3
line.long 0x00 "DDRCTL_DFITMG3,DFI Timing Register 3"
bitfld.long 0x00 0.--4. " DFI_T_GEARDOWN_DELAY              ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands.Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x1BC++0x3
line.long 0x00 "DDRCTL_DFISTAT,DFI Status Register"
bitfld.long 0x00 1. " DFI_LP_ACK                        ,Stores the value of the dfi_lp_ack input to the controller.Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         DFI_INIT_COMPLETE                ,The status flag register which announces when the DFI initialization has been completed.The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. Programming Mode: Dynamic" "0,1"
group.long 0x1C0++0x3
line.long 0x00 "DDRCTL_DBICTL,DM/DBI Control Register"
bitfld.long 0x00 2. " RD_DBI_EN                         ,Read DBI enable signal in DDRC.- 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] Programming Mode: Quasi-dynamic Group 1" "0,1"
bitfld.long 0x00 1. "         WR_DBI_EN                        ,Write DBI enable signal in DDRC.- 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] Programming Mode: Quasi-dynamic Group 1" "0,1"
textline "                                 "
bitfld.long 0x00 0. " DM_EN                             ,DM enable signal in DDRC.- 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal Programming Mode: Quasi-dynamic Group 3" "0,1"
group.long 0x1C4++0x3
line.long 0x00 "DDRCTL_DFIPHYMSTR,DFI PHY Master"
bitfld.long 0x00 0. " DFI_PHYMSTR_EN                    ,Enables the PHY Master Interface: -0 - Disabled - 1 - Enabled Programming Mode: Dynamic" "0,1"
group.long 0x200++0x3
line.long 0x00 "DDRCTL_ADDRMAP0,Address Map Register 0"
bitfld.long 0x00 0.--4. " ADDRMAP_CS_BIT0                   ,Selects the HIF address bit used as rank address bit 0.Valid Range: 0 to 29, and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then rank address bit 0 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x204++0x3
line.long 0x00 "DDRCTL_ADDRMAP1,Address Map Register 1"
bitfld.long 0x00 16.--21. " ADDRMAP_BANK_B2                   ,Selects the HIF address bit used as bank address bit 2.Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 63 and then bank address bit 2 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        ADDRMAP_BANK_B1                  ,Selects the HIF address bits used as bank address bit 1.Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If unused, set to 63 and then bank address bit 1 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 0.--5. " ADDRMAP_BANK_B0                   ,Selects the HIF address bits used as bank address bit 0.Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If unused, set to 63 and then bank address bit 0 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x208++0x3
line.long 0x00 "DDRCTL_ADDRMAP2,Address Map Register 2"
bitfld.long 0x00 24.--27. " ADDRMAP_COL_B5                    ,- Full bus width mode: Selects the HIF address bit used as column address bit 5.- Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then this column address bit is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        ADDRMAP_COL_B4                   ,- Full bus width mode: Selects the HIF address bit used as column address bit 4.- Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then this column address bit is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " ADDRMAP_COL_B3                    ,- Full bus width mode: Selects the HIF address bit used as column address bit 3.- Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if UMCTL2_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width (DDRCTL_MSTR.data_bus_width=00) and BL16 (DDRCTL_MSTR.burst_rdwr=1000), it is recommended to program this to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_COL_B2                   ,- Full bus width mode: Selects the HIF address bit used as column address bit 2.- Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to program this to 0 unless: - in Half or Quarter bus width (DDRCTL_MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and either - In DDR4 and DDRCTL_ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and DDRCTL_ADDRMAP1.addrmap_bank_b0==0 If UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0 unless: - in Half or Quarter bus width (DDRCTL_MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and - In DDR4 and DDRCTL_ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus Width (DDRCTL_MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (DDRCTL_MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Half Bus Width (DDRCTL_MSTR.data_bus_width==01), it is recommended to program this to 0 so that HIF[2] maps to column address bit 3. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20C++0x3
line.long 0x00 "DDRCTL_ADDRMAP3,Address Map Register 3"
bitfld.long 0x00 24.--28. " ADDRMAP_COL_B9                    ,- Full bus width mode: Selects the HIF address bit used as column address bit 9.- Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. Internal Base: 9 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (DDRCTL_ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. If column bit 9 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) If column bit 9 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) If column bit 9 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) if it is unused, set to 31. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        ADDRMAP_COL_B8                   ,- Full bus width mode: Selects the HIF address bit used as column address bit 8.- Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. Internal Base: 8 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (DDRCTL_ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. If column bit 8 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) If column bit 8 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) if it is unused, set to 31. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--12. " ADDRMAP_COL_B7                    ,- Full bus width mode: Selects the HIF address bit used as column address bit 7.- Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then this column address bit is set to 0. In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (DDRCTL_ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. If column bit 7 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) if it is unused, set to 31. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        ADDRMAP_COL_B6                   ,- Full bus width mode: Selects the HIF address bit used as column address bit 6.- Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then this column address bit is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x210++0x3
line.long 0x00 "DDRCTL_ADDRMAP4,Address Map Register 4"
bitfld.long 0x00 8.--12. " ADDRMAP_COL_B11                   ,- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode).- Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. Internal Base: 11 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (DDRCTL_ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. If column bit 11 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) If column bit 11 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) If column bit 11 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) if it is unused, set to 31. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        ADDRMAP_COL_B10                  ,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode).- Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration. Internal Base: 10 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 31 and then this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled (DDRCTL_ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid HIF address bits. If column bit 10 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base) If column bit 10 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base) If column bit 10 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base) if it is unused, set to 31. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x214++0x3
line.long 0x00 "DDRCTL_ADDRMAP5,Address Map Register 5"
bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B11                   ,Selects the HIF address bit used as row address bit 11.Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 11 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        ADDRMAP_ROW_B2_10                ,Selects the HIF address bits used as row address bits 2 to 10.Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 15 is used the values of row address bits 2 to 10 are defined by registers DDRCTL_ADDRMAP9, DDRCTL_ADDRMAP10, DDRCTL_ADDRMAP11. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B1                    ,Selects the HIF address bits used as row address bit 1.Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_ROW_B0                   ,Selects the HIF address bits used as row address bit 0.Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x218++0x3
line.long 0x00 "DDRCTL_ADDRMAP6,Address Map Register 6"
bitfld.long 0x00 31. " LPDDR3_6GB_12GB                   ,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use.- 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs configured to support LPDDR3. Programming Mode: Static" "0,1"
bitfld.long 0x00 29.--30. "         LPDDR4_6GB_12GB_24GB             ,Indicates what type of LPDDR4 SDRAM device is in use.- 2'b00: No LPDDR4 SDRAM 6Gb/12Gb/24Gb device in use. All addresses are valid - 2'b01: LPDDR4 SDRAM 6Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 2'b10: LPDDR4 SDRAM 12Gb device in use. Every address having row[15:14]==2'b11 is considered as invalid - 2'b11: LPDDR4 SDRAM 24Gb device in use. Unsupported Present only in designs configured to support LPDDR4. Programming Mode: Static" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B15                   ,Selects the HIF address bit used as row address bit 15.Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 15 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        ADDRMAP_ROW_B14                  ,Selects the HIF address bit used as row address bit 14.Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 14 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B13                   ,Selects the HIF address bit used as row address bit 13.Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 13 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_ROW_B12                  ,Selects the HIF address bit used as row address bit 12.Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 12 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21C++0x3
line.long 0x00 "DDRCTL_ADDRMAP7,Address Map Register 7"
bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B17                   ,Selects the HIF address bit used as row address bit 17.Valid Range: 0 to 11, and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 17 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_ROW_B16                  ,Selects the HIF address bit used as row address bit 16.Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused, set to 15 and then row address bit 16 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x220++0x3
line.long 0x00 "DDRCTL_ADDRMAP8,Address Map Register 8"
bitfld.long 0x00 8.--13. " ADDRMAP_BG_B1                     ,Selects the HIF address bits used as bank group address bit 1.Valid Range: 0 to 32, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If unused, set to 63 and then bank group address bit 1 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        ADDRMAP_BG_B0                    ,Selects the HIF address bits used as bank group address bit 0.Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If unused, set to 63 and then bank group address bit 0 is set to 0. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x224++0x3
line.long 0x00 "DDRCTL_ADDRMAP9,Address Map Register 9"
bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B5                    ,Selects the HIF address bits used as row address bit 5.Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        ADDRMAP_ROW_B4                   ,Selects the HIF address bits used as row address bit 4.Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B3                    ,Selects the HIF address bits used as row address bit 3.Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_ROW_B2                   ,Selects the HIF address bits used as row address bit 2.Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x228++0x3
line.long 0x00 "DDRCTL_ADDRMAP10,Address Map Register 10"
bitfld.long 0x00 24.--27. " ADDRMAP_ROW_B9                    ,Selects the HIF address bits used as row address bit 9.Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        ADDRMAP_ROW_B8                   ,Selects the HIF address bits used as row address bit 8.Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " ADDRMAP_ROW_B7                    ,Selects the HIF address bits used as row address bit 7.Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        ADDRMAP_ROW_B6                   ,Selects the HIF address bits used as row address bit 6.Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x22C++0x3
line.long 0x00 "DDRCTL_ADDRMAP11,Address Map Register 11"
bitfld.long 0x00 0.--3. " ADDRMAP_ROW_B10                   ,Selects the HIF address bits used as row address bit 10.Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when DDRCTL_ADDRMAP5.addrmap_row_b2_10 is set to value 15. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x3
line.long 0x00 "DDRCTL_ODTCFG,ODT Configuration Register"
bitfld.long 0x00 24.--27. " WR_ODT_HOLD                       ,DFI PHY clock cycles to hold ODT for a write command.The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        WR_ODT_DELAY                     ,The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command.ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation. DDR3: - 0x0 DDR4: - DDRCTL_DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--11. " RD_ODT_HOLD                       ,DFI PHY clock cycles to hold ODT for a read command.The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--6. "        RD_ODT_DELAY                     ,The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command.ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DDRCTL_DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x244++0x3
line.long 0x00 "DDRCTL_ODTMAP,ODT/Rank Map Register"
bitfld.long 0x00 12.--13. " RANK1_RD_ODT                      ,Indicates which remote ODTs must be turned on during a read from rank 1.Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks Programming Mode: Static" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RANK1_WR_ODT                     ,Indicates which remote ODTs must be turned on during a write to rank 1.Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks Programming Mode: Static" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 4.--5. " RANK0_RD_ODT                      ,Indicates which remote ODTs must be turned on during a read from rank 0.Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Programming Mode: Static" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RANK0_WR_ODT                     ,Indicates which remote ODTs must be turned on during a write to rank 0.Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Programming Mode: Static" "0,1,2,3"
group.long 0x250++0x3
line.long 0x00 "DDRCTL_SCHED,Scheduler Control Register"
hexmask.long.byte 0x00 24.--30. 1. " RDWR_IDLE_GAP                     ,When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty.The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. FOR PERFORMANCE ONLY Programming Mode: Static"
hexmask.long.byte 0x00 16.--23. 1. "        GO2CRITICAL_HYSTERESIS           ,UNUSED Programming Mode: Static"
textline "                                 "
bitfld.long 0x00 8.--12. " LPR_NUM_ENTRIES                   ,Number of entries in the low priority transaction store is this value + 1.(MEMC_NO_OF_ENTRY - (DDRCTL_SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PAGECLOSE                        ,If true, bank is kept open only while there are page hit transactions available in the CAM to that bank.The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if DDRCTL_SCHED1.pageclose_timer=0. Even if this register set to 1 and DDRCTL_SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3" "0,1"
textline "                                 "
bitfld.long 0x00 1. " PREFER_WRITE                      ,If set then the bank selector prefers writes over reads.FOR DEBUG ONLY. Programming Mode: Static" "0,1"
bitfld.long 0x00 0. "         FORCE_LOW_PRI_N                  ,Active low signal.When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. Programming Mode: Static" "0,1"
group.long 0x254++0x3
line.long 0x00 "DDRCTL_SCHED1,Scheduler Control Register 1"
hexmask.long.byte 0x00 0.--7. 1. " PAGECLOSE_TIMER                   ,This field works in conjunction withDDRCTL_SCHED.pageclose. It only has meaning if DDRCTL_SCHED.pageclose==1. If DDRCTL_SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See DDRCTL_SCHED.pageclose for details of when this may happen. If DDRCTL_SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. Programming Mode: Static"
group.long 0x25C++0x3
line.long 0x00 "DDRCTL_PERFHPR1,High Priority Read CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. " HPR_XACT_RUN_LENGTH               ,Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available.Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
hexmask.long.word 0x00 0.--15. 1. "        HPR_MAX_STARVE                   ,Number of DFI clocks that the HPR queue can be starved before it goes critical.The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
group.long 0x264++0x3
line.long 0x00 "DDRCTL_PERFLPR1,Low Priority Read CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. " LPR_XACT_RUN_LENGTH               ,Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available.Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
hexmask.long.word 0x00 0.--15. 1. "        LPR_MAX_STARVE                   ,Number of DFI clocks that the LPR queue can be starved before it goes critical.The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
group.long 0x26C++0x3
line.long 0x00 "DDRCTL_PERFWR1,Write CAM Register 1"
hexmask.long.byte 0x00 24.--31. 1. " W_XACT_RUN_LENGTH                 ,Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available.Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
hexmask.long.word 0x00 0.--15. 1. "        W_MAX_STARVE                     ,Number of DFI clocks that the WR queue can be starved before it goes critical.The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic Group 3"
group.long 0x280++0x3
line.long 0x00 "DDRCTL_DQMAP0,DQ Map Register 0"
hexmask.long.byte 0x00 24.--31. 1. " DQ_NIBBLE_MAP_12_15               ,DQ nibble map for DQ bits[12-15] Present only in designs configured to support DDR4. Programming Mode: Static"
hexmask.long.byte 0x00 16.--23. 1. "        DQ_NIBBLE_MAP_8_11               ,DQ nibble map for DQ bits[8-11] Present only in designs configured to support DDR4. Programming Mode: Static"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " DQ_NIBBLE_MAP_4_7                 ,DQ nibble map for DQ bits[4-7] Present only in designs configured to support DDR4. Programming Mode: Static"
hexmask.long.byte 0x00 0.--7. 1. "        DQ_NIBBLE_MAP_0_3                ,DQ nibble map for DQ bits[0-3] Present only in designs configured to support DDR4. Programming Mode: Static"
group.long 0x284++0x3
line.long 0x00 "DDRCTL_DQMAP1,DQ Map Register 1"
hexmask.long.byte 0x00 24.--31. 1. " DQ_NIBBLE_MAP_28_31               ,DQ nibble map for DQ bits[28-31] Present only in designs configured to support DDR4. Programming Mode: Static"
hexmask.long.byte 0x00 16.--23. 1. "        DQ_NIBBLE_MAP_24_27              ,DQ nibble map for DQ bits[24-27] Present only in designs configured to support DDR4. Programming Mode: Static"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " DQ_NIBBLE_MAP_20_23               ,DQ nibble map for DQ bits[20-23] Present only in designs configured to support DDR4. Programming Mode: Static"
hexmask.long.byte 0x00 0.--7. 1. "        DQ_NIBBLE_MAP_16_19              ,DQ nibble map for DQ bits[16-19] Present only in designs configured to support DDR4. Programming Mode: Static"
group.long 0x290++0x3
line.long 0x00 "DDRCTL_DQMAP4,DQ Map Register 4"
hexmask.long.byte 0x00 8.--15. 1. " DQ_NIBBLE_MAP_CB_4_7              ,DQ nibble map for DIMM ECC check bits[4-7] Present only in designs configured to support DDR4. Programming Mode: Static"
hexmask.long.byte 0x00 0.--7. 1. "        DQ_NIBBLE_MAP_CB_0_3             ,DQ nibble map for DIMM ECC check bits[0-3] Present only in designs configured to support DDR4. Programming Mode: Static"
group.long 0x294++0x3
line.long 0x00 "DDRCTL_DQMAP5,DQ Map Register 5"
bitfld.long 0x00 0. " DIS_DQ_RANK_SWAP                  ,All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to support DDR4. Programming Mode: Static" "0,1"
group.long 0x300++0x3
line.long 0x00 "DDRCTL_DBG0,Debug Register 0"
bitfld.long 0x00 4. " DIS_COLLISION_PAGE_OPT            ,When this is set to '0', auto-precharge is disabled for the flushed command in a collision case.Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DDRCTL_DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. Programming Mode: Static" "0,1"
bitfld.long 0x00 0. "         DIS_WC                           ,When 1, disable write combine.FOR DEBUG ONLY Programming Mode: Static" "0,1"
group.long 0x304++0x3
line.long 0x00 "DDRCTL_DBG1,Debug Register 1"
bitfld.long 0x00 1. " DIS_HIF                           ,When 1, uMCTL2 asserts the HIF command signal hif_cmd_stall.uMCTL2 will ignore the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         DIS_DQ                           ,When 1, uMCTL2 will not de-queue any transactions from the CAM.Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes. After setting this bit, it is strongly recommended to poll DDRCTL_DBGCAM.wr_data_pipeline_empty and DDRCTL_DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1"
rgroup.long 0x308++0x3
line.long 0x00 "DDRCTL_DBGCAM,CAM Debug Register"
bitfld.long 0x00 29. " WR_DATA_PIPELINE_EMPTY            ,This bit indicates that the write data pipeline on the DFI interface is empty.This register is intended to be polled at least twice after setting DDRCTL_DBG1.dis_dq, to ensure that all remaining commands/data have completed. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 28. "         RD_DATA_PIPELINE_EMPTY           ,This bit indicates that the read data pipeline on the DFI interface is empty.This register is intended to be polled at least twice after setting DDRCTL_DBG1.dis_dq, to ensure that all remaining commands/data have completed. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 26. " DBG_WR_Q_EMPTY                    ,When 1, all the Write command queues and Write data buffers inside DDRC are empty.This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 25. "         DBG_RD_Q_EMPTY                   ,When 1, all the Read command queues and Read data buffers inside DDRC are empty.This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 24. " DBG_STALL                         ,Stall FOR DEBUG ONLY Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 16.--21. "         DBG_W_Q_DEPTH                    ,Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation.This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 8.--13. " DBG_LPR_Q_DEPTH                   ,Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation.This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DBG_HPR_Q_DEPTH                  ,High priority read queue depth FOR DEBUG ONLY Programming Mode: Dynamic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30C++0x3
line.long 0x00 "DDRCTL_DBGCMD,Command Debug Register"
bitfld.long 0x00 5. " CTRLUPD                           ,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY.When this request is stored in the uMCTL2, the bit is automatically cleared. This operation must only be performed when DDRCTL_DFIUPD0.dis_auto_ctrlupd=1. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 4. "         ZQ_CALIB_SHORT                   ,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM.When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only when DDRCTL_ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mode. Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 1. " RANK1_REFRESH                     ,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1.Writing to this bit causes DDRCTL_DBGSTAT.rank1_refresh_busy to be set. When DDRCTL_DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. For 3DS configuration, refresh is sent to rank index 1. This operation can be performed only when DDRCTL_RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         RANK0_REFRESH                    ,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0.Writing to this bit causes DDRCTL_DBGSTAT.rank0_refresh_busy to be set. When DDRCTL_DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. For 3DS configuration, refresh is sent to rank index 0. This operation can be performed only when DDRCTL_RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. Programming Mode: Dynamic" "0,1"
rgroup.long 0x310++0x3
line.long 0x00 "DDRCTL_DBGSTAT,Status Debug Register"
bitfld.long 0x00 5. " CTRLUPD_BUSY                      ,SoC core may initiate a ctrlupd operation only if this signal is low.This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1 - Indicates that ctrlupd operation has not been initiated yet in the uMCTL2 Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 4. "         ZQ_CALIB_SHORT_BUSY              ,SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low.This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS operation - 1 - Indicates that ZQCS operation has not been initiated yet in the uMCTL2 Programming Mode: Dynamic" "0,1"
textline "                                 "
bitfld.long 0x00 1. " RANK1_REFRESH_BUSY                ,SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low.This signal goes high in the clock after DDRCTL_DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in the uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh operation has not been stored yet in the uMCTL2 Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 0. "         RANK0_REFRESH_BUSY               ,SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low.This signal goes high in the clock after DDRCTL_DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh operation has not been stored yet in the uMCTL2 Programming Mode: Dynamic" "0,1"
group.long 0x320++0x3
line.long 0x00 "DDRCTL_SWCTL,Software Register Programming Control Enable"
bitfld.long 0x00 0. " SW_DONE                           ,Enable quasi-dynamic register programming outside reset.Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1"
rgroup.long 0x324++0x3
line.long 0x00 "DDRCTL_SWSTAT,Software Register Programming Control Status"
bitfld.long 0x00 0. " SW_DONE_ACK                       ,Register programming done.This register is the echo of DDRCTL_SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. Programming Mode: Static" "0,1"
group.long 0x374++0x3
line.long 0x00 "DDRCTL_ADVECCINDEX,Advanced ECC Index Register"
bitfld.long 0x00 5.--8. " ECC_POISON_BEATS_SEL              ,Selector of which DRAM beat's poison pattern will be set byDDRCTL_ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode, 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given DDRCTL_ECCPOISONPAT0/1/2 to set 1st beat's poison pattern set ecc_poison_beats_sel to 1 and given DDRCTL_ECCPOISONPAT0/1/2 to set 2nd beat's poison pattern. For frequency ratio 1:2 mode, 4 DRAM beats can be poisoned. Set ecc_poison_beats_sel from 0~3 to set 1st to 4th beat's poison pattern. The other value is reserved. Programming Mode: Quasi-dynamic Group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--4. "        ECC_ERR_SYMBOL_SEL               ,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits.The default is first error symbol. The value should be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode: Quasi-dynamic Group 1" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 0.--2. " ECC_SYNDROME_SEL                  ,Selector of which DRAM beat data output toDDRCTL_ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC, the syndrome consist of number of DRAM beats. This register select which beats of data will be output to DDRCTL_ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers. Programming Mode: Quasi-dynamic Group 1" "0,1,2,3,4,5,6,7"
group.long 0x37C++0x3
line.long 0x00 "DDRCTL_ECCPOISONPAT0,ECC Poison Pattern 0 Register"
hexmask.long 0x00 0.--31. 1. " ECC_POISON_DATA_31_0              ,Poison pattern for DRAM data[31:0].Only bit is set to 1 indicate poison (invert) corresponding DRAM bit. It is indirect register. Selector is DDRCTL_ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Static"
group.long 0x384++0x3
line.long 0x00 "DDRCTL_ECCPOISONPAT2,ECC Poison Pattern 2 Register"
hexmask.long.byte 0x00 0.--7. 1. " ECC_POISON_DATA_71_64             ,Poison pattern for DRAM data[71:64]. Only bit is set to 1 indicate poison (invert) corresponding DRAM bit. It is indirect register. Selector is DDRCTL_ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Static"
group.long 0x3A0++0x3
line.long 0x00 "DDRCTL_CAPARPOISONCTL,CA parity poison contrl Register"
bitfld.long 0x00 8.--9. " CAPAR_POISON_CMDTYPE              ,Command type to be poisoned.- 0 - Write or Read command - 1 - Write command - 2 - Read command - 3 - Reserved Programming Mode: Dynamic" "0,1,2,3"
bitfld.long 0x00 0. "         CAPAR_POISON_INJECT_EN           ,Setting this register bit to 1 triggers the CA parity poisoning.Once parity is poisoned to a command which is specified by DDRCTL_CAPARPOISONCTL.capar_poison_cmd_type, the CA parity poisoning is completed automatically and DDRCTL_CAPARPOISONSTAT.capar_poison_complete becomes 1. Please make sure that DDRCTL_CAPARPOISONSTAT.capar_poison_complete==0 before writing this register to 1. This feature only supports DDR4 SDRAM. Programming Mode: Dynamic" "0,1"
rgroup.long 0x3A4++0x3
line.long 0x00 "DDRCTL_CAPARPOISONSTAT,CA parity poison status Register"
bitfld.long 0x00 0. " CAPAR_POISON_COMPLETE             ,Indicates CA parity poisoning operation is done.- 0 - CA parity poisoning is not completed - 1 - CA parity poisoning is completed Programming Mode: Dynamic" "0,1"
group.long 0x2020++0x3
line.long 0x00 "DDRCTL_DERATEEN_SHDW,[FREQ1] Temperature Derate Enable Register"
bitfld.long 0x00 8.--10. " RC_DERATE_VALUE                   ,Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--7. "         DERATE_BYTE                      ,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating.The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 1.--2. " DERATE_VALUE                      ,Derate value -0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1 otherwise it should be set to 0. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0. "         DERATE_ENABLE                    ,Enables derating -0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. Programming Mode: Dynamic" "0,1"
group.long 0x2024++0x3
line.long 0x00 "DDRCTL_DERATEINT_SHDW,[FREQ1] Temperature Derate Interval Register"
hexmask.long 0x00 0.--31. 1. " MR4_READ_INTERVAL                 ,Interval between two MR4 reads, used to derate the timing parameters.Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycle. Programming Mode: Static"
group.long 0x2050++0x3
line.long 0x00 "DDRCTL_RFSHCTL0_SHDW,[FREQ1] Refresh Control Register 0"
bitfld.long 0x00 20.--23. " REFRESH_MARGIN                    ,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires.A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 may be equal to DDRCTL_RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DDRCTL_DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to DDRCTL_RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--16. "        REFRESH_TO_X32                   ,If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (DDRCTL_RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this DDRCTL_RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 4.--8. " REFRESH_BURST                     ,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute.Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of DDRCTL_RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete. Programming Mode: Dynamic - Refresh Related" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PER_BANK_REFRESH                 ,-1 - Per bank refresh - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Programming Mode: Static" "0,1"
group.long 0x2064++0x3
line.long 0x00 "DDRCTL_RFSHTMG_SHDW,[FREQ1] Refresh Timing Register"
hexmask.long.word 0x00 16.--27. 1. " T_RFC_NOM_X32                     ,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4.See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (DDRCTL_RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (DDRCTL_RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that DDRCTL_RFSHTMG.t_rfc_nom_x32 * 32 must be greater than DDRCTL_RFSHTMG.t_rfc_min, and DDRCTL_RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or DDR4 Fixed 1x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed 2x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: DDRCTL_RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. Programming Mode: Dynamic - Refresh Related"
bitfld.long 0x00 15. "      LPDDR3_TREFBW_EN                 ,Used only when LPDDR3 memory type is connected.Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.word 0x00 0.--9. 1. " T_RFC_MIN                         ,tRFC (min): Minimum time from refresh to refresh or activate.When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. Programming Mode: Dynamic - Refresh Related"
group.long 0x20DC++0x3
line.long 0x00 "DDRCTL_INIT3_SHDW,[FREQ1] SDRAM Initialization Register 3"
hexmask.long.word 0x00 16.--31. 1. " MR                                ,DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register Programming Mode: Quasi-dynamic Group 1 and Group 4"
hexmask.long.word 0x00 0.--15. 1. "      EMR                              ,DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register Programming Mode: Quasi-dynamic Group 4"
group.long 0x20E0++0x3
line.long 0x00 "DDRCTL_INIT4_SHDW,[FREQ1] SDRAM Initialization Register 4"
hexmask.long.word 0x00 16.--31. 1. " EMR2                              ,DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused Programming Mode: Quasi-dynamic Group 4"
hexmask.long.word 0x00 0.--15. 1. "      EMR3                             ,DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x20E8++0x3
line.long 0x00 "DDRCTL_INIT6_SHDW,[FREQ1] SDRAM Initialization Register 6"
hexmask.long.word 0x00 16.--31. 1. " MR4                               ,DDR4- Value to be loaded into SDRAM MR4 registers. LPDDR4- Value to be loaded into SDRAM MR11 registers. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.word 0x00 0.--15. 1. "      MR5                              ,DDR4- Value to be loaded into SDRAM MR5 registers. LPDDR4- Value to be loaded into SDRAM MR12 registers. Programming Mode: Quasi-dynamic Group 1 and Group 4"
group.long 0x20EC++0x3
line.long 0x00 "DDRCTL_INIT7_SHDW,[FREQ1] SDRAM Initialization Register 7"
hexmask.long.word 0x00 16.--31. 1. " MR22                              ,LPDDR4- Value to be loaded into SDRAM MR22 registers. Used in LPDDR4 designs only. Programming Mode: Quasi-dynamic Group 4"
hexmask.long.word 0x00 0.--15. 1. "      MR6                              ,DDR4- Value to be loaded into SDRAM MR6 registers. LPDDR4- Value to be loaded into SDRAM MR14 registers. Programming Mode: Quasi-dynamic Group 4"
group.long 0x2100++0x3
line.long 0x00 "DDRCTL_DRAMTMG0_SHDW,[FREQ1] SDRAM Timing Register 0"
hexmask.long.byte 0x00 24.--30. 1. " WR2PRE                            ,Minimum time between write and precharge to same bank.Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4"
bitfld.long 0x00 16.--21. "        T_FAW                            ,tFAW Valid only when 8 or more banks(or banks x bank groups) are present.In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.byte 0x00 8.--14. 1. " T_RAS_MAX                         ,tRAS(max): Maximum time between activate and precharge to same bank.This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 0.--5. "        T_RAS_MIN                        ,tRAS(min): Minimum time between activate and precharge to the same bank.When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2104++0x3
line.long 0x00 "DDRCTL_DRAMTMG1_SHDW,[FREQ1] SDRAM Timing Register 1"
bitfld.long 0x00 16.--20. " T_XP                              ,tXP: Minimum time after power-down exit to any operation.For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. If LPDDR4 is selected and its spec has tCKELPD parameter, set to the larger of tXP and tCKELPD instead. When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. Units: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RD2PRE                           ,tRTP: Minimum time from read to precharge of same bank.- DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.byte 0x00 0.--6. 1. " T_RC                              ,tRC: Minimum time between activates to same bank.When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x2108++0x3
line.long 0x00 "DDRCTL_DRAMTMG2_SHDW,[FREQ1] SDRAM Timing Register 2"
bitfld.long 0x00 24.--29. " WRITE_LATENCY                     ,Set to WL Time from write command to write data on SDRAM interface.This must be set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DDRCTL_DFITMG0 and DDRCTL_DFITMG1 are sufficient for those protocols Unit: clocks Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        READ_LATENCY                     ,Set to RL Time from read command to read data on SDRAM interface.This must be set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DDRCTL_DFITMG0 and DDRCTL_DFITMG1 are sufficient for those protocols Unit: clocks Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 8.--13. " RD2WR                             ,DDR2/3/mDDR: RL + BL/2 +2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DDRCTL_DERATEEN.derate_enable=1), derated tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        WR2RD                            ,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - WL = Write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x210C++0x3
line.long 0x00 "DDRCTL_DRAMTMG3_SHDW,[FREQ1] SDRAM Timing Register 3"
hexmask.long.word 0x00 20.--29. 1. " T_MRW                             ,Time to wait after a mode register write or read (MRW or MRR).Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 12.--17. "      T_MRD                            ,tMRD: Cycles to wait after a mode register write or read.Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
hexmask.long.word 0x00 0.--9. 1. " T_MOD                             ,tMOD: Parameter used only in DDR3 and DDR4.Cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. If MPR writes for DDR4 are used, set to tMOD + AL (or tMPD_PAR + AL if C/A parity is also used). Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x2110++0x3
line.long 0x00 "DDRCTL_DRAMTMG4_SHDW,[FREQ1] SDRAM Timing Register 4"
bitfld.long 0x00 24.--28. " T_RCD                             ,tRCD - tAL: Minimum time from activate to read or write command to same bank.When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. Unit: Clocks. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--19. "        T_CCD                            ,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--11. " T_RRD                             ,DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        T_RP                             ,tRP: Minimum time from precharge to activate of same bank.When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2114++0x3
line.long 0x00 "DDRCTL_DRAMTMG5_SHDW,[FREQ1] SDRAM Timing Register 5"
bitfld.long 0x00 24.--27. " T_CKSRX                           ,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX.Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        T_CKSRE                          ,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKELCK - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) (*)Only if DDRCTL_CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 8.--13. " T_CKESR                           ,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles.Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKE, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity latency)(*)) (*)Only if DDRCTL_CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--4. "        T_CKE                            ,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh.- LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2118++0x3
line.long 0x00 "DDRCTL_DRAMTMG6_SHDW,[FREQ1] SDRAM Timing Register 6"
bitfld.long 0x00 24.--27. " T_CKDPDE                          ,This is the time after Deep Power Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        T_CKDPDX                         ,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX.Specifies the clock stable time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--3. " T_CKCSX                           ,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit.Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x211C++0x3
line.long 0x00 "DDRCTL_DRAMTMG7_SHDW,[FREQ1] SDRAM Timing Register 7"
bitfld.long 0x00 8.--11. " T_CKPDE                           ,This is the time after Power Down Entry that CK is maintained as a valid clock.Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKELCK When using DDR2/3/4 SDRAM, this register should be set to the same value as DDRCTL_DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        T_CKPDX                          ,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX.Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the same value as DDRCTL_DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2120++0x3
line.long 0x00 "DDRCTL_DRAMTMG8_SHDW,[FREQ1] SDRAM Timing Register 8"
hexmask.long.byte 0x00 24.--30. 1. " T_XS_FAST_X32                     ,tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode).When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.byte 0x00 16.--22. 1. "        T_XS_ABORT_X32                   ,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32. Programming Mode: Quasi-dynamic Group 2 and Group 4"
textline "                                 "
hexmask.long.byte 0x00 8.--14. 1. " T_XS_DLL_X32                      ,tXSDLL: Exit Self Refresh to commands requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. Programming Mode: Quasi-dynamic Group 2 and Group 4"
hexmask.long.byte 0x00 0.--6. 1. "        T_XS_X32                         ,tXS: Exit Self Refresh to commands not requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x2124++0x3
line.long 0x00 "DDRCTL_DRAMTMG9_SHDW,[FREQ1] SDRAM Timing Register 9"
bitfld.long 0x00 30. " DDR4_WR_PREAMBLE                  ,DDR4 Write preamble mode -0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
bitfld.long 0x00 16.--18. "         T_CCD_S                          ,tCCD_S: This is the minimum time between two reads or two writes for different bank group.For bank switching (from bank 'a' to bank 'b'), the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
textline "                                 "
bitfld.long 0x00 8.--11. " T_RRD_S                           ,tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group.When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "        WR2RD_S                          ,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group.Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 1 and Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2128++0x3
line.long 0x00 "DDRCTL_DRAMTMG10_SHDW,[FREQ1] SDRAM Timing Register 10"
bitfld.long 0x00 16.--20. " T_SYNC_GEAR                       ,Indicates the time between MRS command and the sync pulse time.This must be even number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        T_CMD_GEAR                       ,Sync pulse to first valid command.For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 2.--3. " T_GEAR_SETUP                      ,Geardown setup time.Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--1. "         T_GEAR_HOLD                      ,Geardown hold time.Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
group.long 0x212C++0x3
line.long 0x00 "DDRCTL_DRAMTMG11_SHDW,[FREQ1] SDRAM Timing Register 11"
hexmask.long.byte 0x00 24.--30. 1. " POST_MPSM_GAP_X32                 ,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Multiples of 32 clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 16.--20. "        T_MPX_LH                         ,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge.When the controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--9. " T_MPX_S                           ,tMPX_S: Minimum time CS setup time to CKE.When the controller is operating in 1:2 frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--4. "         T_CKMPE                          ,tCKMPE: Minimum valid clock requirement after MPSM entry.Present only in designs configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2130++0x3
line.long 0x00 "DDRCTL_DRAMTMG12_SHDW,[FREQ1] SDRAM Timing Register 12"
bitfld.long 0x00 16.--17. " T_CMDCKE                          ,tCMDCKE: Delay from valid command to CKE input LOW.Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3"
bitfld.long 0x00 0.--4. "         T_MRD_PDA                        ,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up to the next integer value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2134++0x3
line.long 0x00 "DDRCTL_DRAMTMG13_SHDW,[FREQ1] SDRAM Timing Register 13"
hexmask.long.byte 0x00 24.--30. 1. " ODTLOFF                           ,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 16.--21. "        T_CCD_MW                         ,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                 "
bitfld.long 0x00 0.--2. " T_PPD                             ,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to the next integer value. Unit: Clocks. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7"
group.long 0x2138++0x3
line.long 0x00 "DDRCTL_DRAMTMG14_SHDW,[FREQ1] SDRAM Timing Register 14"
hexmask.long.word 0x00 0.--11. 1. " T_XSR                             ,tXSR: Exit Self Refresh to any command.When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x213C++0x3
line.long 0x00 "DDRCTL_DRAMTMG15_SHDW,[FREQ1] SDRAM Timing Register 15"
bitfld.long 0x00 31. " EN_DFI_LP_T_STAB                  ,-1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         T_STAB_X32                       ,tSTAB: Stabilization time.It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of input clock frequency change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock cycles. Programming Mode: Quasi-dynamic Group 2 and Group 4"
group.long 0x2180++0x3
line.long 0x00 "DDRCTL_ZQCTL0_SHDW,[FREQ1] ZQ Control Register 0"
bitfld.long 0x00 31. " DIS_AUTO_ZQ                       ,-1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DDRCTL_DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on DDRCTL_ZQCTL1.t_zq_short_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Dynamic" "0,1"
bitfld.long 0x00 30. "         DIS_SRX_ZQCL                     ,-1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1"
textline "                                 "
bitfld.long 0x00 29. " ZQ_RESISTOR_SHARED                ,-1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static" "0,1"
bitfld.long 0x00 28. "         DIS_MPSMX_ZQCL                   ,-1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the UMCTL2_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode. Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.word 0x00 16.--26. 1. " T_ZQ_LONG_NOP                     ,tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
hexmask.long.word 0x00 0.--9. 1. "      T_ZQ_SHORT_NOP                   ,tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. Programming Mode: Static"
group.long 0x2190++0x3
line.long 0x00 "DDRCTL_DFITMG0_SHDW,[FREQ1] DFI Timing Register 0"
bitfld.long 0x00 24.--28. " DFI_T_CTRL_DELAY                  ,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion.If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "        DFI_RDDATA_USE_DFI_PHY_CLK       ,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values.Selects whether value in DDRCTL_DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. If using a DWC DDR3/2 PHY, DWC DDR2/3-Lite/mDDR PHY, DWC DDR multiPHY or DWC Gen2 DDR multiPHY, this field must be set to 0 otherwise: - If MEMC_PROG_FREQ_RATIO=1 and DDRCTL_MSTR.frequency_ratio=1, this field should be set to 0 - Else, it must be set to 1 Programming Mode: Static" "0,1"
textline "                                 "
hexmask.long.byte 0x00 16.--22. 1. " DFI_T_RDDATA_EN                   ,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal.Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_rddata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 1 and Group 4"
bitfld.long 0x00 15. "        DFI_WRDATA_USE_DFI_PHY_CLK       ,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value inDDRCTL_DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in DDRCTL_DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value. If using a DWC DDR3/2 PHY, DWC DDR2/3-Lite/mDDR PHY, DWC DDR multiPHY or DWC Gen2 DDR multiPHY, this field must be set to 0 otherwise: - If MEMC_PROG_FREQ_RATIO=1 and DDRCTL_MSTR.frequency_ratio=1, this field should be set to 0 - Else, it must be set to 1 Programming Mode: Static" "0,1"
textline "                                 "
bitfld.long 0x00 8.--13. " DFI_TPHY_WRDATA                   ,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal.This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DFI_TPHY_WRLAT                   ,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en).This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. For LPDDR4, dfi_tphy_wrlat>60 is not supported. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk. Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2194++0x3
line.long 0x00 "DDRCTL_DFITMG1_SHDW,[FREQ1] DFI Timing Register 1"
bitfld.long 0x00 28.--31. " DFI_T_CMD_LAT                     ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven.This field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "        DFI_T_PARIN_LAT                  ,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven.Programming Mode: Quasi-dynamic Group 4" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 16.--20. " DFI_T_WRDATA_DELAY                ,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DDRCTL_DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value. Unit: Clocks Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        DFI_T_DRAM_CLK_DISABLE           ,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value.If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 0.--4. " DFI_T_DRAM_CLK_ENABLE             ,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary.If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21B4++0x3
line.long 0x00 "DDRCTL_DFITMG2_SHDW,[FREQ1] DFI Timing Register 2"
hexmask.long.byte 0x00 8.--14. 1. " DFI_TPHY_RDCSLAT                  ,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted.This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. Programming Mode: Quasi-dynamic Group 2 and Group 4"
bitfld.long 0x00 0.--5. "        DFI_TPHY_WRCSLAT                 ,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted.This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. Programming Mode: Quasi-dynamic Group 2 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x21B8++0x3
line.long 0x00 "DDRCTL_DFITMG3_SHDW,[FREQ1] DFI Timing Register 3"
bitfld.long 0x00 0.--4. " DFI_T_GEARDOWN_DELAY              ,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands.Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to the next integer value. Unit: Clocks Programming Mode: Static" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2240++0x3
line.long 0x00 "DDRCTL_ODTCFG_SHDW,[FREQ1] ODT Configuration Register"
bitfld.long 0x00 24.--27. " WR_ODT_HOLD                       ,DFI PHY clock cycles to hold ODT for a write command.The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        WR_ODT_DELAY                     ,The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command.ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation. DDR3: - 0x0 DDR4: - DDRCTL_DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--11. " RD_ODT_HOLD                       ,DFI PHY clock cycles to hold ODT for a read command.The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--6. "        RD_ODT_DELAY                     ,The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command.ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DDRCTL_DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) Programming Mode: Quasi-dynamic Group 1 and Group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "ECC_Aggregator"
tree "DDRSS0_ECC_AGGR_CTL"
base ad:0x2A20000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "DDRECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                    ,bu" "0,1,2,3"
textline "                                     "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID             ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                     "
bitfld.long 0x00 8.--10. " REVMAJ                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                ,Custom version" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--5. " REVMIN                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "DDRECC_VECTOR,ECC Vector Register"
in
textline "                                     "
rgroup.long 0xC++0x3
line.long 0x00 "DDRECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS              ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "DDRECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "DDRECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " HSAFE_1_SI_PEND       ,Interrupt Pending Status for hsafe_1_si_pend" "0,1"
bitfld.long 0x00 2. "     HSAFE_0_SI_PEND       ,Interrupt Pending Status for hsafe_0_si_pend" "0,1"
textline "                                     "
bitfld.long 0x00 1. " CRCMEM_PEND           ,Interrupt Pending Status for crcmem_pend" "0,1"
bitfld.long 0x00 0. "     WRMEM_PEND            ,Interrupt Pending Status for wrmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "DDRECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " HSAFE_1_SI_ENABLE_SET ,Interrupt Enable Set Register for hsafe_1_si_pend" "0,1"
bitfld.long 0x00 2. "     HSAFE_0_SI_ENABLE_SET ,Interrupt Enable Set Register for hsafe_0_si_pend" "0,1"
textline "                                     "
bitfld.long 0x00 1. " CRCMEM_ENABLE_SET     ,Interrupt Enable Set Register for crcmem_pend" "0,1"
bitfld.long 0x00 0. "     WRMEM_ENABLE_SET      ,Interrupt Enable Set Register for wrmem_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "DDRECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                     "
group.long 0x13C++0x3
line.long 0x00 "DDRECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "DDRECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " HSAFE_1_SI_PEND       ,Interrupt Pending Status for hsafe_1_si_pend" "0,1"
bitfld.long 0x00 2. "     HSAFE_0_SI_PEND       ,Interrupt Pending Status for hsafe_0_si_pend" "0,1"
textline "                                     "
bitfld.long 0x00 1. " CRCMEM_PEND           ,Interrupt Pending Status for crcmem_pend" "0,1"
bitfld.long 0x00 0. "     WRMEM_PEND            ,Interrupt Pending Status for wrmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "DDRECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " HSAFE_1_SI_ENABLE_SET ,Interrupt Enable Set Register for hsafe_1_si_pend" "0,1"
bitfld.long 0x00 2. "     HSAFE_0_SI_ENABLE_SET ,Interrupt Enable Set Register for hsafe_0_si_pend" "0,1"
textline "                                     "
bitfld.long 0x00 1. " CRCMEM_ENABLE_SET     ,Interrupt Enable Set Register for crcmem_pend" "0,1"
bitfld.long 0x00 0. "     WRMEM_ENABLE_SET      ,Interrupt Enable Set Register for wrmem_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "DDRECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                     "
group.long 0x200++0x3
line.long 0x00 "DDRECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT               ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "DDRECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                     "
group.long 0x208++0x3
line.long 0x00 "DDRECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "DDRECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "VBUSMC_ECC_Aggregator"
tree "DDRSS0_ECC_AGGR_VBUS"
base ad:0x2A21000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "DDRECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME              ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,bu" "0,1,2,3"
textline "                                     "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID           ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                     "
bitfld.long 0x00 8.--10. " REVMAJ              ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom version" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--5. " REVMIN              ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "DDRECC_VECTOR,ECC Vector Register"
in
textline "                                     "
rgroup.long 0xC++0x3
line.long 0x00 "DDRECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS            ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "DDRECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR              ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "DDRECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 0. " VSAFE_SI_PEND       ,Interrupt Pending Status for vsafe_si_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "DDRECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " VSAFE_SI_ENABLE_SET ,Interrupt Enable Set Register for vsafe_si_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "DDRECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                     "
group.long 0x13C++0x3
line.long 0x00 "DDRECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR              ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "DDRECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 0. " VSAFE_SI_PEND       ,Interrupt Pending Status for vsafe_si_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "DDRECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " VSAFE_SI_ENABLE_SET ,Interrupt Enable Set Register for vsafe_si_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "DDRECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                     "
group.long 0x200++0x3
line.long 0x00 "DDRECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT             ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY           ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "DDRECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                     "
group.long 0x208++0x3
line.long 0x00 "DDRECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT             ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "DDRECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT             ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "DDR_PHY"
tree "DDRSS0_PHY_CFG"
base ad:0x2988000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "DDRPHY_RIDR,Revision Identification Register"
hexmask.long.byte 0x00 24.--31. 1. " UDRID                  ,User-Defined Revision ID"
bitfld.long 0x00 20.--23. "        PHYMJR              ,PHY Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " PHYMDR                 ,PHY Moderate Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        PHYMNR              ,PHY Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " PUBMJR                 ,PUB Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        PUBMDR              ,PUB Moderate Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " PUBMNR                 ,PUB Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x4++0x3
hide.long 0x00 "DDRPHY_PIR,PHY Initialization Register"
in
textline "                              "
group.long 0x10++0x3
line.long 0x00 "DDRPHY_PGCR0,PHY General Configuration Register 0"
bitfld.long 0x00 31. " ADCP                   ,Address Copy" "0,1"
bitfld.long 0x00 26. "         PHYFRST             ,PHY FIFO Reset" "0,1"
textline "                              "
bitfld.long 0x00 24.--25. " OSCACDL                ,Oscillator Mode Address/Command Delay Line Select" "0,1,2,3"
bitfld.long 0x00 14.--18. "         DTOSEL              ,Digital Test Output Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 9.--12. " OSCDIV                 ,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "        OSCEN               ,Oscillator Enable" "0,1"
hgroup.long 0x14++0x3
hide.long 0x00 "DDRPHY_PGCR1,PHY General Configuration Register 1"
in
textline "                              "
hgroup.long 0x18++0x3
hide.long 0x00 "DDRPHY_PGCR2,PHY General Configuration Register 2"
in
textline "                              "
group.long 0x1C++0x3
line.long 0x00 "DDRPHY_PGCR3,PHY General Configuration Register 3"
hexmask.long.byte 0x00 24.--31. 1. " CKNEN                  ,CKN Enable"
hexmask.long.byte 0x00 16.--23. 1. "        CKEN                ,CK Enable"
textline "                              "
bitfld.long 0x00 13.--14. " GATEACRDCLK            ,Enable Clock Gating for AC [0] ctl_rd_clk" "0,1,2,3"
bitfld.long 0x00 11.--12. "         GATEACDDRCLK        ,Enable Clock Gating for AC [0] ddr_clk" "0,1,2,3"
textline "                              "
bitfld.long 0x00 9.--10. " GATEACCTLCLK           ,Enable Clock Gating for AC [0] ctl_clk" "0,1,2,3"
bitfld.long 0x00 6.--7. "         DDLBYPMODE          ,Controls DDL Bypass Modes" "0,1,2,3"
textline "                              "
bitfld.long 0x00 5. " IOLB                   ,IO Loop-Back Select" "0,1"
bitfld.long 0x00 3.--4. "         RDMODE              ,AC Receive FIFO Read Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2. " DISRST                 ,Read FIFO Reset Disable" "0,1"
bitfld.long 0x00 0.--1. "         CLKLEVEL            ,Clock Level when Clock Gating" "0,1,2,3"
group.long 0x20++0x3
line.long 0x00 "DDRPHY_PGCR4,PHY General Configuration Register 4"
bitfld.long 0x00 29. " ACDDLLD                ,AC DDL Delay Select Dymainc Load" "0,1"
bitfld.long 0x00 24.--28. "         ACDDLBYP            ,AC DDL Bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 23. " OEDDLBYP               ,AC OE DDL Bypass" "0,1"
bitfld.long 0x00 22. "         TEDDLBYP            ,AC ODT DDL Bypass" "0,1"
textline "                              "
bitfld.long 0x00 21. " PDRDDLBYP              ,AC PDR DDL Bypass" "0,1"
bitfld.long 0x00 20. "         RRRMODE             ,Read Path Rise-to-Rise Mode" "0,1"
textline "                              "
bitfld.long 0x00 19. " WRRMODE                ,Write Path Rise-to-Rise Mode" "0,1"
bitfld.long 0x00 18. "         PDAMODE             ,Set PDA mode timing" "0,1"
textline "                              "
bitfld.long 0x00 17. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 8.--16. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
textline "                              "
bitfld.long 0x00 4.--7. " LPWAKEUP_THRSH         ,AC Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "        LPPLLPD             ,AC Low Power PLL Power Down" "0,1"
textline "                              "
bitfld.long 0x00 0. " LPIOPD                 ,AC Low Power IO Power Down" "0,1"
group.long 0x24++0x3
line.long 0x00 "DDRPHY_PGCR5,PHY General Configuration Register 5"
hexmask.long.byte 0x00 24.--31. 1. " FRQBT                  ,Frequency B Ratio Term"
hexmask.long.byte 0x00 16.--23. 1. "        FRQAT               ,Frequency A Ratio Term"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " DISCNPERIOD            ,DFI Disconnect Time Period"
bitfld.long 0x00 4.--7. "        VREF_RBCTRL         ,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 2. " DXREFISELRANGE         ,Internal VREF generator REFSEL ragne select" "0,1"
bitfld.long 0x00 1. "         DDLPGACT            ,DDL Page Read Write select" "0,1"
textline "                              "
bitfld.long 0x00 0. " DDLPGRW                ,DDL Page Read Write select" "0,1"
group.long 0x28++0x3
line.long 0x00 "DDRPHY_PGCR6,PHY General Configuration Register 6"
hexmask.long.byte 0x00 16.--23. 1. " DLDLMT                 ,Delay Line VT Drift Limit"
bitfld.long 0x00 13. "        ACDLVT              ,AC Address/Command Delay LCDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 12. " ACBVT                  ,Address/Command Bit Delay VT Compensation" "0,1"
bitfld.long 0x00 11. "         ODTBVT              ,ODT Bit Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 10. " CKEBVT                 ,CKE Bit Delay VT Compensation" "0,1"
bitfld.long 0x00 9. "         CSNBVT              ,CSN Bit Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 8. " CKBVT                  ,CK Bit Delay VT Compensation" "0,1"
bitfld.long 0x00 1. "         FVT                 ,Forced VT Compensation Trigger" "0,1"
textline "                              "
bitfld.long 0x00 0. " INHVT                  ,VT Calculation Inhibit" "0,1"
group.long 0x2C++0x3
line.long 0x00 "DDRPHY_PGCR7,PHY General Configuration Register 7"
bitfld.long 0x00 6.--7. " ACRSVD_7_6             ,These bits are reserved for future AC special PHY modes but the registers are already connected to existing (unused) AC phy_mode bits." "0,1,2,3"
bitfld.long 0x00 5. "         ACCALCLK            ,AC Calibration Clock Select" "0,1"
textline "                              "
bitfld.long 0x00 4. " ACRCLKMD               ,AC Read Clock Mode" "0,1"
bitfld.long 0x00 3. "         ACDLDT              ,AC DDL Load Type" "0,1"
textline "                              "
bitfld.long 0x00 2. " ACRSVD_2               ,This bit is reserved for future AC special PHY modes but the register is already connected to existing (unused) AC phy_mode bits." "0,1"
bitfld.long 0x00 1. "         ACDTOSEL            ,AC Digital Test Output Select" "0,1"
textline "                              "
bitfld.long 0x00 0. " ACTMODE                ,AC Test Mode" "0,1"
rgroup.long 0x30++0x3
line.long 0x00 "DDRPHY_PGSR0,PHY General Status Register 0"
bitfld.long 0x00 31. " APLOCK                 ,AC PLL Lock" "0,1"
bitfld.long 0x00 30. "         SRDERR              ,Static Read Error" "0,1"
textline "                              "
bitfld.long 0x00 29. " CAWRN                  ,CA Training Warning" "0,1"
bitfld.long 0x00 28. "         CAERR               ,CA Training Error" "0,1"
textline "                              "
bitfld.long 0x00 27. " WEERR                  ,Write Eye Training Error" "0,1"
bitfld.long 0x00 26. "         REERR               ,Read Eye Training Error" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 24. "         RDERR               ,Read Bit Deskew Error" "0,1"
textline "                              "
bitfld.long 0x00 23. " WLAERR                 ,Write Leveling Adjustment Error" "0,1"
bitfld.long 0x00 22. "         QSGERR              ,DQS Gate Training Error" "0,1"
textline "                              "
bitfld.long 0x00 21. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 20. "         ZCERR               ,Impedance Calibration Error" "0,1"
textline "                              "
bitfld.long 0x00 19. " VERR                   ,VREF Training Error" "0,1"
bitfld.long 0x00 18. "         DQS2DQERR           ,Write DQS2DQ Training Error" "0,1"
textline "                              "
bitfld.long 0x00 15. " DQS2DQDONE             ,Write DQS2DQ Training Done" "0,1"
bitfld.long 0x00 14. "         VDONE               ,VREF Training Done" "0,1"
textline "                              "
bitfld.long 0x00 13. " SRDDONE                ,Static Read Done" "0,1"
bitfld.long 0x00 12. "         CADONE              ,CA Training Done" "0,1"
textline "                              "
bitfld.long 0x00 11. " WEDONE                 ,Write Eye Training Done" "0,1"
bitfld.long 0x00 10. "         REDONE              ,Read Eye Training Done" "0,1"
textline "                              "
bitfld.long 0x00 9. " WDDONE                 ,Write Bit Deskew Done" "0,1"
bitfld.long 0x00 8. "         RDDONE              ,Read Bit Deskew Done" "0,1"
textline "                              "
bitfld.long 0x00 7. " WLADONE                ,Write Leveling Adjustment Done" "0,1"
bitfld.long 0x00 6. "         QSGDONE             ,DQS Gate Training Done" "0,1"
textline "                              "
bitfld.long 0x00 5. " WLDONE                 ,Write Leveling Done" "0,1"
bitfld.long 0x00 4. "         DIDONE              ,DRAM Initialization Done" "0,1"
textline "                              "
bitfld.long 0x00 3. " ZCDONE                 ,Impedance Calibration Done" "0,1"
bitfld.long 0x00 2. "         DCDONE              ,Digital Delay Line (DDL) Calibration Done" "0,1"
textline "                              "
bitfld.long 0x00 1. " PLDONE                 ,PLL Lock Done" "0,1"
bitfld.long 0x00 0. "         IDONE               ,Initialization Done" "0,1"
rgroup.long 0x34++0x3
line.long 0x00 "DDRPHY_PGSR1,PHY General Status Register 1"
bitfld.long 0x00 31. " PARERR                 ,RDIMM Parity Error" "0,1"
bitfld.long 0x00 30. "         VTSTOP              ,VT Stop" "0,1"
textline "                              "
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code for AC macro 0"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done for AC macro 0" "0,1"
rgroup.long 0x38++0x3
line.long 0x00 "DDRPHY_PGSR2,PHY General Status Register 2"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code for AC macro 1"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done for AC macro 1" "0,1"
group.long 0x40++0x3
line.long 0x00 "DDRPHY_PTR0,PHY Timing Register 0"
hexmask.long.word 0x00 21.--31. 1. " TPLLPD                 ,PLL Power-Down Time"
hexmask.long.word 0x00 6.--20. 1. "      TPLLGS              ,PLL Gear Shift Time"
textline "                              "
bitfld.long 0x00 0.--5. " TPHYRST                ,PHY Reset Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x44++0x3
line.long 0x00 "DDRPHY_PTR1,PHY Timing Register 1"
hexmask.long.word 0x00 16.--31. 1. " TPLLLOCK               ,PLL Lock Time"
hexmask.long.word 0x00 0.--12. 1. "      TPLLRST             ,PLL Reset Time"
group.long 0x48++0x3
line.long 0x00 "DDRPHY_PTR2,PHY Timing Register 2"
bitfld.long 0x00 15.--19. " TWLDLYS                ,Write Leveling Delay Settling Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "        TCALH               ,Calibration Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 5.--9. " TCALS                  ,Calibration Setup Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        TCALON              ,Calibration On Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x3
line.long 0x00 "DDRPHY_PTR3,PHY Timing Register 3"
hexmask.long.tbyte 0x00 0.--22. 1. " TDINIT0                ,DRAM Initialization Time 0"
group.long 0x50++0x3
line.long 0x00 "DDRPHY_PTR4,PHY Timing Register 4"
hexmask.long.word 0x00 0.--12. 1. " TDINIT1                ,DRAM Initialization Time 1"
group.long 0x54++0x3
line.long 0x00 "DDRPHY_PTR5,PHY Timing Register 5"
hexmask.long.tbyte 0x00 0.--18. 1. " TDINIT2                ,DRAM Initialization Time 1"
group.long 0x58++0x3
line.long 0x00 "DDRPHY_PTR6,PHY Timing Register 6"
hexmask.long.byte 0x00 20.--26. 1. " TDINIT4                ,DRAM Initialization Time 4"
hexmask.long.word 0x00 0.--11. 1. "        TDINIT3             ,DRAM Initialization Time 3"
group.long 0x68++0x3
line.long 0x00 "DDRPHY_PLLCR0,PLL Control Register 0 (Type B PLL Only)"
bitfld.long 0x00 31. " PLLBYP                 ,PLL Bypass" "0,1"
bitfld.long 0x00 30. "         PLLRST              ,PLL Reset" "0,1"
textline "                              "
bitfld.long 0x00 29. " PLLPD                  ,PLL Power Down" "0,1"
bitfld.long 0x00 28. "         RSTOPM              ,Reference Stop Mode" "0,1"
textline "                              "
bitfld.long 0x00 24.--27. " FRQSEL                 ,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RLOCKM              ,Relock Mode" "0,1"
textline "                              "
bitfld.long 0x00 17.--22. " CPPC                   ,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 13.--16. "        CPIC                ,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12. " GSHIFT                 ,Gear Shift" "0,1"
bitfld.long 0x00 8. "         ATOEN               ,Analog Test Enable" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " ATC                    ,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DTC                 ,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88++0x3
line.long 0x00 "DDRPHY_DXCCR,DATX8 Common Configuration Register"
bitfld.long 0x00 29. " RKLOOP                 ,Rank looping (per-rank eye centering) enable" "0,1"
bitfld.long 0x00 3.--6. "         DQS2DQMPER          ,Write DQS2DQ Training Measurement Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x90++0x3
line.long 0x00 "DDRPHY_DSGCR,DDR System General Configuration Register"
bitfld.long 0x00 27. " RDBICLSEL              ,When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use default calculation." "0,1"
bitfld.long 0x00 24.--26. "         RDBICL              ,When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value." "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 23. " PHYZUEN                ,PHY Impedance Update Enable" "0,1"
bitfld.long 0x00 21. "         RSTOE               ,SDRAM Reset Output Enable" "0,1"
textline "                              "
bitfld.long 0x00 19.--20. " SDRMODE                ,Single Data Rate Mode" "0,1,2,3"
bitfld.long 0x00 17. "         ATOAE               ,ATO Analog Test Enable" "0,1"
textline "                              "
bitfld.long 0x00 16. " DTOOE                  ,DTO Output Enable" "0,1"
bitfld.long 0x00 15. "         DTOIOM              ,DTO I/O Mode" "0,1"
textline "                              "
bitfld.long 0x00 14. " DTOPDR                 ,DTO Power Down Receiver" "0,1"
bitfld.long 0x00 12. "         DTOODT              ,DTO On-Die Termination" "0,1"
textline "                              "
bitfld.long 0x00 6.--11. " PUAD                   ,PHY Update Acknowledge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        CUAEN               ,Controller Update Acknowledge Enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " MSTRVER                ,Master Version" "0,1"
bitfld.long 0x00 2. "         CTLZUEN             ,Controller Impedance Update Enable" "0,1"
textline "                              "
bitfld.long 0x00 1. " MREN                   ,Master Request Enable" "0,1"
bitfld.long 0x00 0. "         PUREN               ,PHY Update Request Enable" "0,1"
group.long 0x98++0x3
line.long 0x00 "DDRPHY_ODTCR,ODT Configuration Register"
hexmask.long.word 0x00 18.--27. 1. " WRODT_RSVD             ,Reserved.Return zeroes on reads."
bitfld.long 0x00 16.--17. "      WRODT               ,Write ODT." "0,1,2,3"
textline "                              "
hexmask.long.word 0x00 2.--11. 1. " RDODT_RSVD             ,Reserved.Return zeroes on reads."
bitfld.long 0x00 0.--1. "      RDODT               ,Read ODT." "0,1,2,3"
group.long 0xC0++0x3
line.long 0x00 "DDRPHY_GPR0,General Purpose Register 0"
hexmask.long 0x00 0.--31. 1. " GPR0                   ,General Purpose Register 0"
group.long 0xC4++0x3
line.long 0x00 "DDRPHY_GPR1,General Purpose Register 1"
hexmask.long 0x00 0.--31. 1. " GPR1                   ,General Purpose Register 1"
group.long 0x100++0x3
line.long 0x00 "DDRPHY_DCR,DRAM Configuration Register"
bitfld.long 0x00 31. " GEARDN                 ,DDR4 Gear Down Timing." "0,1"
bitfld.long 0x00 30. "         UBG                 ,Un-used Bank Group" "0,1"
textline "                              "
bitfld.long 0x00 29. " UDIMM                  ,Un-buffered DIMM Address Mirroring" "0,1"
bitfld.long 0x00 28. "         DDR2T               ,DDR 2T Timing" "0,1"
textline "                              "
bitfld.long 0x00 27. " NOSRA                  ,No Simultaneous Rank Access" "0,1"
hexmask.long.byte 0x00 10.--17. 1. "         BYTEMASK            ,Byte Mask"
textline "                              "
bitfld.long 0x00 8.--9. " DDRTYPE                ,DDR Type" "0,1,2,3"
bitfld.long 0x00 7. "         MPRDQ               ,Multi-Purpose Register (MPR) DQ (DDR3 Only)" "0,1"
textline "                              "
bitfld.long 0x00 4.--6. " PDQ                    ,Primary DQ (DDR3 Only)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         DDR8BNK             ,DDR8-Bank" "0,1"
textline "                              "
bitfld.long 0x00 0.--2. " DDRMD                  ,DDR Mode" "0,1,2,3,4,5,6,7"
group.long 0x110++0x3
line.long 0x00 "DDRPHY_DTPR0,DRAM Timing Parameters Register 0"
bitfld.long 0x00 24.--28. " TRRD                   ,Activate to activate command delay (different banks)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--22. 1. "        TRAS                ,Activate to precharge command delay"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " TRP                    ,Precharge command period"
bitfld.long 0x00 0.--4. "        TRTP                ,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x114++0x3
line.long 0x00 "DDRPHY_DTPR1,DRAM Timing Parameters Register 1"
hexmask.long.byte 0x00 24.--30. 1. " TWLMRD                 ,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge."
hexmask.long.byte 0x00 16.--22. 1. "        TFAW                ,4-bank activate period"
textline "                              "
bitfld.long 0x00 8.--10. " TMOD                   ,Load mode update delay (DDR4 and DDR3 only)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TMRD                ,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x118++0x3
line.long 0x00 "DDRPHY_DTPR2,DRAM Timing Parameters Register 2"
bitfld.long 0x00 28. " TRTW                   ,Read to Write command delay.Valid values are" "0,1"
bitfld.long 0x00 24. "         TRTODT              ,Read to ODT delay (DDR3 only)" "0,1"
textline "                              "
bitfld.long 0x00 20.--23. " TCMDCKE                ,Delay from Valid command to CKE Input low (LPDDR4 mode only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        TCKE                ,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 13.--15. " TVRCG                  ,tVRCG Enable." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "         TXS                 ,Self refresh exit delay"
group.long 0x11C++0x3
line.long 0x00 "DDRPHY_DTPR3,DRAM Timing Parameters Register 3"
bitfld.long 0x00 29.--31. " TOFDX                  ,ODT turn-off delay extension" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "         TCCD                ,Read to read and write to write command delay" "0,1,2,3,4,5,6,7"
textline "                              "
hexmask.long.word 0x00 16.--25. 1. " TDLLK                  ,DLL locking time"
bitfld.long 0x00 8.--11. "      TDQSCKMAX           ,Maximum DQS output access time from CK/CK# (LPDDR2/3 only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--2. " TDQSCK                 ,DQS output access time from CK/CK# (LPDDR2/3 only)" "0,1,2,3,4,5,6,7"
group.long 0x120++0x3
line.long 0x00 "DDRPHY_DTPR4,DRAM Timing Parameters Register 4"
bitfld.long 0x00 28.--29. " TAOND_TAOFD            ,ODT turn-on/turn-off delays (DDR2 only)" "0,1,2,3"
hexmask.long.word 0x00 16.--25. 1. "         TRFC                ,Refresh-to-Refresh"
textline "                              "
bitfld.long 0x00 8.--13. " TWLO                   ,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--4. "        TXP                 ,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x124++0x3
line.long 0x00 "DDRPHY_DTPR5,DRAM Timing Parameters Register 5"
hexmask.long.byte 0x00 24.--31. 1. " TODTUP                 ,ODT CA Value Update Time"
hexmask.long.byte 0x00 16.--23. 1. "        TRC                 ,Activate to activate command delay (same bank)"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " TRCD                   ,Activate to read or write delay"
bitfld.long 0x00 0.--4. "        TWTR                ,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x128++0x3
line.long 0x00 "DDRPHY_DTPR6,DRAM Timing Parameters Register 6"
bitfld.long 0x00 31. " PUBWLEN                ,PUB Write Latency Enable" "0,1"
bitfld.long 0x00 30. "         PUBRLEN             ,PUB Read Latency Enable" "0,1"
textline "                              "
bitfld.long 0x00 8.--13. " PUBWL                  ,Write Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        PUBRL               ,Read Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x168++0x3
hide.long 0x00 "DDRPHY_SCHCR0,Scheduler Command Register 0"
in
textline "                              "
group.long 0x16C++0x3
line.long 0x00 "DDRPHY_SCHCR1,Scheduler Command Register 1"
bitfld.long 0x00 28.--31. " SCRNK                  ,Scheduler Rank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 8.--27. 1. "        SCADDR              ,Scheduler Command Address Specifies the value to be driven on the address bus."
textline "                              "
bitfld.long 0x00 6.--7. " SCBG                   ,Scheduler Command Bank Group" "0,1,2,3"
bitfld.long 0x00 4.--5. "         SCBK                ,Scheduler Command Bank Address" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2. " ALLRANK                ,All Ranks enabled" "0,1"
group.long 0x180++0x3
line.long 0x00 "DDRPHY_MR0,LPDDR4 Mode Register 0"
hexmask.long.byte 0x00 8.--15. 1. " RSVD_15_8              ,Reserved.Return zeroes on reads."
bitfld.long 0x00 7. "        CATR                ,CA Terminating Rank" "0,1"
textline "                              "
bitfld.long 0x00 5.--6. " RSVD_6_5               ,Reserved.These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
bitfld.long 0x00 3.--4. "         RZQI                ,Built-in Self-Test for RZQ" "0,1,2,3"
textline "                              "
bitfld.long 0x00 0.--2. " RSVD_2_0               ,Reserved.These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
group.long 0x180++0x3
line.long 0x00 "DDRPHY_MR0_DDR3,DDR3 Mode Register 0"
bitfld.long 0x00 13.--15. " RSVD                   ,Reserved.These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         PD                  ,Power-Down Control" "0,1"
textline "                              "
bitfld.long 0x00 9.--11. " WR                     ,Write Recovery and Read to Precharge" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "         DR                  ,DLL Reset" "0,1"
textline "                              "
bitfld.long 0x00 7. " TM                     ,Operating Mode" "0,1"
bitfld.long 0x00 4.--6. "         CL_6_4              ,CAS Latency" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 3. " BT                     ,Burst Type" "0,1"
bitfld.long 0x00 2. "         CL_2                ,CAS Latency" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " BL                     ,Burst Length" "0,1,2,3"
group.long 0x180++0x3
line.long 0x00 "DDRPHY_MR0_DDR4,DDR4 Mode Register 0"
bitfld.long 0x00 14.--15. " RSVD                   ,Reserved.These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
bitfld.long 0x00 13. "         WR_13               ,Write Recovery and Read to Precharge" "0,1"
textline "                              "
bitfld.long 0x00 12. " CL_12                  ,CAS Latency" "0,1"
bitfld.long 0x00 9.--11. "         WR_11_9             ,Write Recovery and Read to Precharge" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 8. " DR                     ,DLL Reset" "0,1"
bitfld.long 0x00 7. "         TM                  ,Operating Mode" "0,1"
textline "                              "
bitfld.long 0x00 4.--6. " CL_6_4                 ,CAS Latency" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         BT                  ,Burst Type" "0,1"
textline "                              "
bitfld.long 0x00 2. " CL_2                   ,CAS Latency" "0,1"
bitfld.long 0x00 0.--1. "         BL                  ,Burst Length" "0,1,2,3"
group.long 0x184++0x3
line.long 0x00 "DDRPHY_MR1,LPDDR4 Mode Register 1"
hexmask.long.byte 0x00 8.--15. 1. " RSVD                   ,Reserved.Return zeroes on reads."
bitfld.long 0x00 7. "        RDPST               ,Read Postamble Length" "0,1"
textline "                              "
bitfld.long 0x00 4.--6. " NWR                    ,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RDPRE               ,Read Preamble Length" "0,1"
textline "                              "
bitfld.long 0x00 2. " WRPRE                  ,Write Preamble Length" "0,1"
bitfld.long 0x00 0.--1. "         BL                  ,Burst Length" "0,1,2,3"
group.long 0x184++0x3
line.long 0x00 "DDRPHY_MR1_DDR3,DDR3 Mode Register 1"
bitfld.long 0x00 13.--15. " RSVD_15_13             ,Reserved.These are JEDEC reserved bits for DDR3 and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         QOFF                ,Output Enable/Disable" "0,1"
textline "                              "
bitfld.long 0x00 11. " TDQS                   ,Termination Data Strobe" "0,1"
bitfld.long 0x00 10. "         RSVD_10             ,Reserved.This is a JEDEC reserved bit for DDR3 and is recommended by JEDEC to be programmed to 0x0." "0,1"
textline "                              "
bitfld.long 0x00 9. " RTT_9                  ,On Die Termination" "0,1"
bitfld.long 0x00 8. "         RSVD_8              ,Reserved.This is a JEDEC reserved bit for DDR3 and is recommended by JEDEC to be programmed to 0x0." "0,1"
textline "                              "
bitfld.long 0x00 7. " LEVEL                  ,Write Leveling Enable" "0,1"
bitfld.long 0x00 6. "         RTT_6               ,On Die Termination" "0,1"
textline "                              "
bitfld.long 0x00 5. " DIC_5                  ,Output Driver Impedance Control" "0,1"
bitfld.long 0x00 3.--4. "         AL                  ,Posted CAS Additive Latency" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2. " RTT_2                  ,On Die Termination" "0,1"
bitfld.long 0x00 1. "         DIC_1               ,Output Driver Impedance Control" "0,1"
textline "                              "
bitfld.long 0x00 0. " DE                     ,DLL Enable/Disable" "0,1"
group.long 0x184++0x3
line.long 0x00 "DDRPHY_MR1_DDR4,DDR4 Mode Register 1"
bitfld.long 0x00 13.--15. " RSVD_15_13             ,Reserved.These are JEDEC reserved bits for DDR4 and is recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         QOFF                ,Output Enable/Disable" "0,1"
textline "                              "
bitfld.long 0x00 11. " TDQS                   ,Termination Data Strobe" "0,1"
bitfld.long 0x00 8.--10. "         RTT                 ,On Die Termination" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 7. " LEVEL                  ,Write Leveling Enable" "0,1"
bitfld.long 0x00 5.--6. "         RSVD_6_5            ,Reserved.These are JEDEC reserved bits for DDR4 and is recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
textline "                              "
bitfld.long 0x00 3.--4. " AL                     ,Posted CAS Additive Latency" "0,1,2,3"
bitfld.long 0x00 1.--2. "         DIC                 ,Output Driver Impedance Control" "0,1,2,3"
textline "                              "
bitfld.long 0x00 0. " DE                     ,DLL Enable/Disable" "0,1"
group.long 0x188++0x3
line.long 0x00 "DDRPHY_MR2,LPDDR4 Mode Register 2"
hexmask.long.byte 0x00 8.--15. 1. " RSVD                   ,Reserved.Return zeroes on reads."
bitfld.long 0x00 7. "        WRL                 ,Write Leveling" "0,1"
textline "                              "
bitfld.long 0x00 6. " WLS                    ,Write Latency Set" "0,1"
bitfld.long 0x00 3.--5. "         WL                  ,Write Latency" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 0.--2. " RL                     ,Read Latency" "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "DDRPHY_MR2_DDR3,DDR3 Mode Register 2"
bitfld.long 0x00 11.--15. " RSVD_15_13             ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "        RTTWR               ,Dynamic ODT" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " RSVD_8                 ,Reserved.This bit is JEDEC reserved and is recommended by JEDEC to be programmed to 0x0." "0,1"
bitfld.long 0x00 7. "         SRT                 ,Self-Refresh Temperature Range" "0,1"
textline "                              "
bitfld.long 0x00 6. " ASR                    ,Auto Self-Refresh" "0,1"
bitfld.long 0x00 3.--5. "         CWL                 ,CAS Write Latency" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 0.--2. " PASR                   ,Partial Array Self Refresh" "0,1,2,3,4,5,6,7"
group.long 0x188++0x3
line.long 0x00 "DDRPHY_MR2_DDR4,DDR4 Mode Register 2"
bitfld.long 0x00 14.--15. " RSVD_15_14             ,Reserved.This bit is JEDEC reserved and is recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
bitfld.long 0x00 13. "         TRR                 ,TRR Mode setting" "0,1"
textline "                              "
bitfld.long 0x00 12. " WRCRC                  ,Write CRC.When 1b1, CRC is enabled for write operation." "0,1"
bitfld.long 0x00 9.--11. "         RTTWR               ,Dynamic ODT" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 8. " TRR_BGN_8              ,Defines the bank group (BGn) to which TRR will be applied" "0,1"
bitfld.long 0x00 6.--7. "         LPASR               ,Low Power Array Self Refresh (LP ASR)" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3.--5. " CWL                    ,CAS Write Latency" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "         TRR_BGN_2           ,Define the bank group (BGn) to which TRR will be applied" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TRR_BAN                ,Define which bank (BAn) the target row is located" "0,1,2,3"
group.long 0x18C++0x3
line.long 0x00 "DDRPHY_MR3,LPDDR4 Mode Register 3"
bitfld.long 0x00 7. " DBIWR                  ,DBI-Write Enable" "0,1"
bitfld.long 0x00 6. "         DBIRD               ,DBI-Read Enable" "0,1"
textline "                              "
bitfld.long 0x00 3.--5. " PDDS                   ,Pull-down Drive Strength" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "         RSVD                ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
textline "                              "
bitfld.long 0x00 1. " WRPST                  ,Write Postamble Length" "0,1"
bitfld.long 0x00 0. "         PUCAL               ,Pull-up Calibration Point" "0,1"
group.long 0x18C++0x3
line.long 0x00 "DDRPHY_MR3_DDR3,DDR3 Mode Register 3"
hexmask.long.word 0x00 3.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
bitfld.long 0x00 2. "      MPR                 ,Multi-Purpose Register Enable" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " MPRLOC                 ,Multi-Purpose Register (MPR) Location" "0,1,2,3"
group.long 0x18C++0x3
line.long 0x00 "DDRPHY_MR3_DDR4,DDR4 Mode Register 3"
bitfld.long 0x00 13.--15. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11.--12. "         MPRRF               ,Multi-Purpose Register Read Format" "0,1,2,3"
textline "                              "
bitfld.long 0x00 9.--10. " WCL                    ,Write Command Latency when CRC and DM are enabled" "0,1,2,3"
bitfld.long 0x00 6.--8. "         FGRM                ,Fine Granularity Refresh Mode" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 5. " TSR                    ,Temp sensor readout" "0,1"
bitfld.long 0x00 4. "         PDA                 ,Per DRAM Addressability" "0,1"
textline "                              "
bitfld.long 0x00 3. " GDM                    ,Geardown Mode" "0,1"
bitfld.long 0x00 2. "         MPRO                ,Multi-Purpose Operation" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " MPRPSEL                ,Multi-Purpose Register (MPR) Page Selection" "0,1,2,3"
group.long 0x190++0x3
line.long 0x00 "DDRPHY_MR4,LPDDR4 Mode Register 4"
hexmask.long.byte 0x00 0.--7. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x190++0x3
line.long 0x00 "DDRPHY_MR4_DDR3,DDR3 Mode Register 4"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x190++0x3
line.long 0x00 "DDRPHY_MR4_DDR4,DDR4 Mode Register 4"
bitfld.long 0x00 13.--15. " RSVD_15_13             ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         WRP                 ,Write Preamble" "0,1"
textline "                              "
bitfld.long 0x00 11. " RDP                    ,Read Preamble" "0,1"
bitfld.long 0x00 10. "         RPTM                ,Read Preamble Training Mode" "0,1"
textline "                              "
bitfld.long 0x00 9. " SRA                    ,Self Refresh Abort" "0,1"
bitfld.long 0x00 6.--8. "         CS2CMDL             ,CS to Command Latency Mode" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 5. " RSVD1                  ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
bitfld.long 0x00 4. "         IVM                 ,Internal VREF Monitor" "0,1"
textline "                              "
bitfld.long 0x00 3. " TCRM                   ,Temperature Controlled Refresh Mode" "0,1"
bitfld.long 0x00 2. "         TCRR                ,Temperature Controlled Refresh Range" "0,1"
textline "                              "
bitfld.long 0x00 1. " MPDM                   ,Maximum Power Down Mode" "0,1"
bitfld.long 0x00 0. "         RSVD_0              ,This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0." "0,1"
group.long 0x194++0x3
line.long 0x00 "DDRPHY_MR5,LPDDR4 Mode Register 5"
hexmask.long.byte 0x00 0.--7. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x194++0x3
line.long 0x00 "DDRPHY_MR5_DDR3,DDR3 Mode Register 5"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x194++0x3
line.long 0x00 "DDRPHY_MR5_DDR4,DDR4 Mode Register 5"
bitfld.long 0x00 13.--15. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         RDBI                ,Read DBI" "0,1"
textline "                              "
bitfld.long 0x00 11. " WDBI                   ,Write DBI" "0,1"
bitfld.long 0x00 10. "         DM                  ,Data Mask" "0,1"
textline "                              "
bitfld.long 0x00 9. " CAPPE                  ,CA Parity Persistent Error" "0,1"
bitfld.long 0x00 6.--8. "         RTTPARK             ,RTT_PARK" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 5. " ODTIBPD                ,ODT Input Buffer during Power Down mode" "0,1"
bitfld.long 0x00 4. "         CAPES               ,C/A Parity Error Status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CRCEC                  ,CRC Error Clear" "0,1"
bitfld.long 0x00 0.--2. "         CAPM                ,C/A Parity Latency Mode" "0,1,2,3,4,5,6,7"
group.long 0x198++0x3
line.long 0x00 "DDRPHY_MR6,LPDDR4 Mode Register 6"
hexmask.long.byte 0x00 0.--7. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x198++0x3
line.long 0x00 "DDRPHY_MR6_DDR3,DDR3 Mode Register 6"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x198++0x3
line.long 0x00 "DDRPHY_MR6_DDR4,DDR4 Mode Register 6"
bitfld.long 0x00 13.--15. " RSVD_15_13             ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--12. "         TCCDL               ,CAS_n to CAS_n command delay for same bank group (tCCD_L)" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 8.--9. " RSVD_9_8               ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
bitfld.long 0x00 7. "         VDDQTEN             ,VrefDQ Training Enable" "0,1"
textline "                              "
bitfld.long 0x00 6. " VDQTRG                 ,VrefDQ Training Range" "0,1"
bitfld.long 0x00 0.--5. "         VDQTVAL             ,VrefDQ Training Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x19C++0x3
line.long 0x00 "DDRPHY_MR7,LPDDR4 Mode Register 7"
hexmask.long.byte 0x00 0.--7. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x19C++0x3
line.long 0x00 "DDRPHY_MR7_DDR3,LPDDR2 Mode Register 7"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x19C++0x3
line.long 0x00 "DDRPHY_MR7_DDR4,DDR4 Mode Register 7"
hexmask.long.word 0x00 0.--15. 1. " RSVD_15_0              ,Reserve for future use."
group.long 0x1AC++0x3
line.long 0x00 "DDRPHY_MR11,LPDDR4 Mode Register 11"
hexmask.long.byte 0x00 8.--15. 1. " RSVD_15_8              ,Reserved.Return zeroes on reads."
bitfld.long 0x00 7. "        RSVD_7              ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
textline "                              "
bitfld.long 0x00 4.--6. " CAODT                  ,CA Bus Receiver On-Die-Termination" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RSVD_3              ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
textline "                              "
bitfld.long 0x00 0.--2. " DQODT                  ,DQ Bus Receiver On-Die-Termination" "0,1,2,3,4,5,6,7"
group.long 0x1AC++0x3
line.long 0x00 "DDRPHY_MR11_DDR3,DDR3 Mode Register 11"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1AC++0x3
line.long 0x00 "DDRPHY_MR11_DDR4,DDR4 Mode Register 11"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B0++0x3
line.long 0x00 "DDRPHY_MR12,LPDDR4 Mode Register 12"
bitfld.long 0x00 7. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
bitfld.long 0x00 6. "         VR_CA               ,VREF_CA Range Select." "0,1"
textline "                              "
bitfld.long 0x00 0.--5. " VREF_CA                ,Controls the VREF(ca) levels for Frequency-Set-Point[1:0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B0++0x3
line.long 0x00 "DDRPHY_MR12_DDR3,DDR3 Mode Register 12"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B0++0x3
line.long 0x00 "DDRPHY_MR12_DDR4,DDR4 Mode Register 12"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B4++0x3
line.long 0x00 "DDRPHY_MR13,LPDDR4 Mode Register 13"
bitfld.long 0x00 7. " FSPOP                  ,Frequency Set Point Operation Mode" "0,1"
bitfld.long 0x00 6. "         FSPWR               ,Frequency Set Point Write Enable" "0,1"
textline "                              "
bitfld.long 0x00 5. " DMD                    ,Data Mask Enable" "0,1"
bitfld.long 0x00 4. "         RRO                 ,Refresh Rate Option" "0,1"
textline "                              "
bitfld.long 0x00 3. " VRCG                   ,VREF Current Generator" "0,1"
bitfld.long 0x00 2. "         VRO                 ,VREF Output" "0,1"
textline "                              "
bitfld.long 0x00 1. " RPT                    ,Read Preamble Training Mode" "0,1"
bitfld.long 0x00 0. "         CBT                 ,Command Bus Training" "0,1"
group.long 0x1B4++0x3
line.long 0x00 "DDRPHY_MR13_DDR3,DDR3 Mode Register 13"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B4++0x3
line.long 0x00 "DDRPHY_MR13_DDR4,DDR4 Mode Register 13"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B8++0x3
line.long 0x00 "DDRPHY_MR14,LPDDR4 Mode Register 14"
bitfld.long 0x00 7. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1"
bitfld.long 0x00 6. "         VR_DQ               ,VREFDQ Range Selects." "0,1"
textline "                              "
bitfld.long 0x00 0.--5. " VREF_DQ                ,Reserved.Return zeroes on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1B8++0x3
line.long 0x00 "DDRPHY_MR14_DDR3,DDR3 Mode Register 14"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1B8++0x3
line.long 0x00 "DDRPHY_MR14_DDR4,DDR4 Mode Register 14"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1D8++0x3
line.long 0x00 "DDRPHY_MR22,LPDDR4 Mode Register 22"
bitfld.long 0x00 6.--7. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0." "0,1,2,3"
bitfld.long 0x00 5. "         ODTD_CA             ,CA ODT termination disable." "0,1"
textline "                              "
bitfld.long 0x00 4. " ODTE_CS                ,ODT CS override." "0,1"
bitfld.long 0x00 3. "         ODTE_CK             ,ODT CK override." "0,1"
textline "                              "
bitfld.long 0x00 0.--2. " CODT                   ,Controller ODT value for VOH calibration." "0,1,2,3,4,5,6,7"
group.long 0x1D8++0x3
line.long 0x00 "DDRPHY_MR22_DDR3,DDR3 Mode Register 22"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
group.long 0x1D8++0x3
line.long 0x00 "DDRPHY_MR22_DDR4,DDR4 Mode Register 22"
hexmask.long.word 0x00 0.--15. 1. " RSVD                   ,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0."
hgroup.long 0x200++0x3
hide.long 0x00 "DDRPHY_DTCR0,Data Training Configuration Register 0"
in
textline "                              "
group.long 0x204++0x3
line.long 0x00 "DDRPHY_DTCR1,Data Training Configuration Register 1"
hexmask.long.word 0x00 18.--31. 1. " RANKEN_RSVD            ,Rank Enable."
bitfld.long 0x00 16.--17. "      RANKEN              ,Rank Enable." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DTRANK                 ,Data Training Rank" "0,1,2,3"
bitfld.long 0x00 8.--10. "         RDLVLGDIFF          ,Read Leveling Gate Sampling Difference" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 4.--6. " RDLVLGS                ,Read Leveling Gate Shift" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "         RDPRMVL_TRN         ,Read Preamble Training enable" "0,1"
textline "                              "
bitfld.long 0x00 1. " RDLVLEN                ,Read Leveling Enable" "0,1"
bitfld.long 0x00 0. "         BSTEN               ,Basic Gate Training Enable" "0,1"
group.long 0x208++0x3
line.long 0x00 "DDRPHY_DTAR0,Data Training Address Register 0"
bitfld.long 0x00 28.--29. " MPRLOC                 ,Multi-Purpose Register (MPR) Location" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DTBGBK1             ,Data Training Bank Group and Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " DTBGBK0                ,Data Training Bank Group and Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--17. 1. "        DTROW               ,Data Training Row Address"
group.long 0x20C++0x3
line.long 0x00 "DDRPHY_DTAR1,Data Training Address Register 1"
hexmask.long.word 0x00 16.--24. 1. " DTCOL1                 ,Data Training Column Address"
hexmask.long.word 0x00 0.--8. 1. "      DTCOL0              ,Data Training Column Address"
group.long 0x210++0x3
line.long 0x00 "DDRPHY_DTAR2,Data Training Address Register 2"
hexmask.long.word 0x00 16.--24. 1. " DTCOL3                 ,Data Training Column Address"
hexmask.long.word 0x00 0.--8. 1. "      DTCOL2              ,Data Training Column Address"
group.long 0x218++0x3
line.long 0x00 "DDRPHY_DTDR0,Data Training Data Register 0"
hexmask.long.byte 0x00 24.--31. 1. " DTBYTE3                ,Data Training Data"
hexmask.long.byte 0x00 16.--23. 1. "        DTBYTE2             ,Data Training Data"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " DTBYTE1                ,Data Training Data"
hexmask.long.byte 0x00 0.--7. 1. "        DTBYTE0             ,Data Training Data"
group.long 0x21C++0x3
line.long 0x00 "DDRPHY_DTDR1,Data Training Data Register 1"
hexmask.long.byte 0x00 24.--31. 1. " DTBYTE7                ,Data Training Data"
hexmask.long.byte 0x00 16.--23. 1. "        DTBYTE6             ,Data Training Data"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " DTBYTE5                ,Data Training Data"
hexmask.long.byte 0x00 0.--7. 1. "        DTBYTE4             ,Data Training Data"
rgroup.long 0x230++0x3
line.long 0x00 "DDRPHY_DTEDR0,Data Training Eye Data Register 0"
hexmask.long.byte 0x00 24.--31. 1. " WDQBMX                 ,Data Training Write BDL Shift Maximum."
bitfld.long 0x00 18.--23. "        WDQBMN              ,Data Training Write BDL Shift Minimum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
hexmask.long.word 0x00 9.--17. 1. " WDQLMX                 ,Data Training WDQ LCDL Maximum."
hexmask.long.word 0x00 0.--8. 1. "      WDQLMN              ,Data Training WDQ LCDL Minimum."
rgroup.long 0x234++0x3
line.long 0x00 "DDRPHY_DTEDR1,Data Training Eye Data Register 1"
hexmask.long.byte 0x00 24.--31. 1. " RDQSBMX                ,Data Training Read BDL Shift Maximum."
bitfld.long 0x00 18.--23. "        RDQSBMN             ,Data Training Read BDL Shift Minimum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
hexmask.long.word 0x00 9.--17. 1. " RDQSLMX                ,Data Training RDQS LCDL Maximum."
hexmask.long.word 0x00 0.--8. 1. "      RDQSLMN             ,Data Training RDQS LCDL Minimum."
rgroup.long 0x238++0x3
line.long 0x00 "DDRPHY_DTEDR2,Data Training Eye Data Register 2"
hexmask.long.byte 0x00 24.--31. 1. " RDQSNBMX               ,Data Training Read BDL Shift Maximum."
bitfld.long 0x00 18.--23. "        RDQSNBMN            ,Data Training Read BDL Shift Minimum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
hexmask.long.word 0x00 9.--17. 1. " RDQSNLMX               ,Data Training RDQSN LCDL Maximum."
hexmask.long.word 0x00 0.--8. 1. "      RDQSNLMN            ,Data Training RDQSN LCDL Minimum."
rgroup.long 0x23C++0x3
line.long 0x00 "DDRPHY_VTDR,VREF Training Data Register"
hexmask.long.byte 0x00 24.--30. 1. " HVREFMX                ,DRAM DQ VREF Maximum."
hexmask.long.byte 0x00 16.--22. 1. "        HVREFMN             ,DRAM DQ VREF Minimum."
textline "                              "
bitfld.long 0x00 8.--13. " DVREFMX                ,DRAM DQ VREF Maximum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DVREFMN             ,DRAM DQ VREF Minimum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x248++0x3
line.long 0x00 "DDRPHY_PGCR8,PHY General Configuration Register 8"
bitfld.long 0x00 28.--31. " INC_DQS2DQ_CF          ,Counter Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 20.--27. 1. "        INC_DQS2DQ_CM       ,Counter Cycle Multiplier"
textline "                              "
bitfld.long 0x00 18.--19. " INC_DQS2DQ_RANKEN_RSVD ,Rank Enable" "0,1,2,3"
bitfld.long 0x00 16.--17. "         INC_DQS2DQ_RANKEN   ,Rank Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 15. " INC_DQS2DQ_MODE        ,Self Incremental DQS2DQ Training" "0,1"
bitfld.long 0x00 14. "         INC_DQS2DQ_EN       ,Incremental DQS2DQ Training" "0,1"
textline "                              "
hexmask.long.word 0x00 0.--8. 1. " BSWAPMSB               ,When a bit is set, it indicates that the corresponding PHY byte lane is connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to."
group.long 0x250++0x3
line.long 0x00 "DDRPHY_DQSDR0,DQS Drift Register 0"
bitfld.long 0x00 28.--31. " DFTDLY                 ,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "        DFTZQUP             ,Drift Impedance Update" "0,1"
textline "                              "
bitfld.long 0x00 26. " DFTDDLUP               ,Drift DDL Update" "0,1"
bitfld.long 0x00 20.--21. "         DFTRDSPC            ,Drift Read Spacing" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--19. " DFTB2BRD               ,Drift Back-to-Back Reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        DFTIDLRD            ,Drift Idle Reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DFTGPULSE              ,Gate Pulse Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--3. "        DFTUPMODE           ,DQS Drift Update Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " DFTDTMODE              ,DQS Drift Detection Mode" "0,1"
bitfld.long 0x00 0. "         DFTDTEN             ,DQS Drift Detection Enable" "0,1"
group.long 0x254++0x3
line.long 0x00 "DDRPHY_DQSDR1,DQS Drift Register 1"
bitfld.long 0x00 29.--31. " DFTUPDACKF             ,Drift DFI Update Request ACK to DQS Drift FSM issing IDLE REad Cycles Factor" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "         DFTUPDACKC          ,Drift DFI Update ACK to DQS Drift FSM issuing IDLE Read Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 20.--23. " DFTRDB2BF              ,Drift Back-to-Back Read Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        DFTRDIDLF           ,Drift Idle Read Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " DFTRDB2BC              ,Drift Back-to-Back Read Cycles"
hexmask.long.byte 0x00 0.--7. 1. "        DFTRDIDLC           ,Drift Idle Read Cycles"
group.long 0x258++0x3
line.long 0x00 "DDRPHY_DQSDR2,DQS Drift Register 2"
hexmask.long.byte 0x00 16.--23. 1. " DFTTHRSH               ,Drift Threshold"
hexmask.long.word 0x00 0.--15. 1. "        DFTMNTPRD           ,Drift Monitor Period"
group.long 0x400++0x3
line.long 0x00 "DDRPHY_BISTRR,BIST Run Register"
bitfld.long 0x00 29. " BPRBST                 ,BIST PRBS Type." "0,1"
bitfld.long 0x00 28. "         BSOMA               ,BIST Stop on Maximum Address" "0,1"
textline "                              "
bitfld.long 0x00 26.--27. " BACDPAT                ,BIST AC Data Pattern" "0,1,2,3"
bitfld.long 0x00 25. "         BCCSEL              ,BIST Clock Cycle Select" "0,1"
textline "                              "
bitfld.long 0x00 23.--24. " BCKSEL                 ,BIST CK Select" "0,1,2,3"
bitfld.long 0x00 19.--22. "         BDXSEL              ,BIST DATX8 Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 17.--18. " BDXDPAT                ,BIST Data Pattern" "0,1,2,3"
bitfld.long 0x00 16. "         BDMEN               ,BIST Data Mask Enable" "0,1"
textline "                              "
bitfld.long 0x00 15. " BACEN                  ,BIST AC Enable" "0,1"
bitfld.long 0x00 14. "         BDXEN               ,BIST DATX8 Enable" "0,1"
textline "                              "
bitfld.long 0x00 13. " BSONF                  ,BIST Stop On Nth Fail" "0,1"
hexmask.long.byte 0x00 5.--12. 1. "         NFAIL               ,Number of Failures"
textline "                              "
bitfld.long 0x00 4. " BINF                   ,BIST Infinite Run" "0,1"
bitfld.long 0x00 3. "         BMODE               ,BIST Mode" "0,1"
textline "                              "
bitfld.long 0x00 0.--2. " BINST                  ,BIST Instruction" "0,1,2,3,4,5,6,7"
group.long 0x404++0x3
line.long 0x00 "DDRPHY_BISTWCR,BIST Word Count Register"
hexmask.long.word 0x00 16.--31. 1. " BACWCNT                ,BIST AC Word Count"
hexmask.long.word 0x00 0.--15. 1. "      BDXWCNT             ,BIST DX Word Count"
group.long 0x408++0x3
line.long 0x00 "DDRPHY_BISTMSKR0,BIST Mask Register 0"
hexmask.long.word 0x00 22.--31. 1. " CSMSK_RSVD             ,Reserved.Return zeros on reads."
bitfld.long 0x00 20.--21. "      CSMSK               ,Mask bit for each of the up to 12 CS_N bits." "0,1,2,3"
textline "                              "
bitfld.long 0x00 19. " ACTMSK                 ,Mask bit for the RAS." "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "         AMSK                ,Mask bit for each of the up to 16 address bits."
group.long 0x40C++0x3
line.long 0x00 "DDRPHY_BISTMSKR1,BIST Mask Register 1"
bitfld.long 0x00 28.--31. " DMMSK                  ,Mask bit for the data mask (DM) bit." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "        PARINMSK            ,Mask bit for the PAR_IN." "0,1"
textline "                              "
bitfld.long 0x00 25.--26. " CIDMSK_RSVD            ,Reserved.Return zeros on reads." "0,1,2,3"
bitfld.long 0x00 24. "         CIDMSK              ,Mask bits for each of the up to 3 Chip IP bits." "0,1"
textline "                              "
bitfld.long 0x00 18.--23. " ODTMSK_RSVD            ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--17. "        ODTMSK              ,Mask bit for each of the up to 8 ODT bits." "0,1,2,3"
textline "                              "
bitfld.long 0x00 10.--15. " CKEMSK_RSVD            ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "        CKEMSK              ,Mask bit for each of the up to 8 CKE bits." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--7. " BAMSK                  ,Mask bit for each of the up to 4 bank address bits." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x410++0x3
line.long 0x00 "DDRPHY_BISTMSKR2,BIST Mask Register 2"
hexmask.long 0x00 0.--31. 1. " DQMSK                  ,Mask bit for each of the 8 data (DQ) bits"
group.long 0x414++0x3
line.long 0x00 "DDRPHY_BISTLSR,BIST LFSR Seed Register"
hexmask.long 0x00 0.--31. 1. " SEED                   ,LFSR seed for pseudo-random BIST patterns"
group.long 0x418++0x3
line.long 0x00 "DDRPHY_BISTAR0,BIST Address Register 0"
bitfld.long 0x00 28.--31. " BBANK                  ,BIST Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "        BCOL                ,BIST Column Address"
group.long 0x41C++0x3
line.long 0x00 "DDRPHY_BISTAR1,BIST Address Register 1"
bitfld.long 0x00 16.--19. " BMRANK                 ,BIST Maximum Rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "        BAINC               ,BIST Address Increment"
textline "                              "
bitfld.long 0x00 0.--3. " BRANK                  ,BIST Rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x420++0x3
line.long 0x00 "DDRPHY_BISTAR2,BIST Address Register 2"
bitfld.long 0x00 28.--31. " BMBANK                 ,BIST Maximum Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "        BMCOL               ,BIST Maximum Column Address"
group.long 0x424++0x3
line.long 0x00 "DDRPHY_BISTAR3,BIST Address Register 3"
hexmask.long.tbyte 0x00 0.--17. 1. " BROW                   ,BIST Row Address"
group.long 0x428++0x3
line.long 0x00 "DDRPHY_BISTAR4,BIST Address Register 4"
hexmask.long.tbyte 0x00 0.--17. 1. " BMROW                  ,BIST Maximum Row Address"
group.long 0x42C++0x3
line.long 0x00 "DDRPHY_BISTUDPR,BIST User Data Pattern Register"
hexmask.long.word 0x00 16.--31. 1. " BUDP1                  ,BIST User Data Pattern 1"
hexmask.long.word 0x00 0.--15. 1. "      BUDP0               ,BIST User Data Pattern 0"
rgroup.long 0x430++0x3
line.long 0x00 "DDRPHY_BISTGSR,BIST General Status Register"
bitfld.long 0x00 28.--29. " RASBER                 ,RAS_n/ACT_n Bit Error" "0,1,2,3"
hexmask.long.byte 0x00 20.--27. 1. "         DMBER               ,DM Bit Error"
textline "                              "
hexmask.long.word 0x00 2.--10. 1. " BDXERR                 ,BIST Data Error"
bitfld.long 0x00 1. "      BACERR              ,BIST Address/Command Error" "0,1"
textline "                              "
bitfld.long 0x00 0. " BDONE                  ,BIST Done" "0,1"
rgroup.long 0x434++0x3
line.long 0x00 "DDRPHY_BISTWER0,BIST Word Error Register 0"
hexmask.long.tbyte 0x00 0.--17. 1. " ACWER                  ,Address/Command Word Error"
rgroup.long 0x438++0x3
line.long 0x00 "DDRPHY_BISTWER1,BIST Word Error Register 1"
hexmask.long.word 0x00 0.--15. 1. " DXWER                  ,Byte Word Error"
rgroup.long 0x43C++0x3
line.long 0x00 "DDRPHY_BISTBER0,BIST Bit Error Register 0"
hexmask.long 0x00 0.--31. 1. " ABER                   ,Address Bit Error"
rgroup.long 0x440++0x3
line.long 0x00 "DDRPHY_BISTBER1,BIST Bit Error Register 1"
hexmask.long.tbyte 0x00 12.--31. 1. " CSBER_RSVD             ,Reserved.Return zeros on reads."
bitfld.long 0x00 8.--11. "    CSBER               ,CS_N Bit Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " BABER                  ,Bank Address Bit Error"
rgroup.long 0x444++0x3
line.long 0x00 "DDRPHY_BISTBER2,BIST Bit Error Register 2"
hexmask.long 0x00 0.--31. 1. " DQBER0                 ,Data Bit Error"
rgroup.long 0x448++0x3
line.long 0x00 "DDRPHY_BISTBER3,BIST Bit Error Register 3"
hexmask.long 0x00 0.--31. 1. " DQBER1                 ,Data Bit Error"
rgroup.long 0x44C++0x3
line.long 0x00 "DDRPHY_BISTBER4,BIST Bit Error Register 4"
bitfld.long 0x00 10.--13. " CIDBER_RSVD            ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--9. "        CIDBER              ,Chip ID Bit Error." "0,1,2,3"
textline "                              "
bitfld.long 0x00 0.--3. " ABER                   ,Address Bit Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x450++0x3
line.long 0x00 "DDRPHY_BISTWCSR,BIST Word Count Status Register"
hexmask.long.word 0x00 16.--31. 1. " DXWCNT                 ,Byte Word Count"
hexmask.long.word 0x00 0.--15. 1. "      ACWCNT              ,Address/Command Word Count"
rgroup.long 0x454++0x3
line.long 0x00 "DDRPHY_BISTFWR0,BIST Fail Word Register 0"
hexmask.long.word 0x00 22.--31. 1. " CSWEBS_RSVD            ,Reserved.Return zeros on reads."
bitfld.long 0x00 20.--21. "      CSWEBS              ,Bit status during a word error for each of the up to 12 CS# bits." "0,1,2,3"
textline "                              "
bitfld.long 0x00 18. " ACTWEBS                ,Bit status during a word error for the RAS." "0,1"
hexmask.long.tbyte 0x00 0.--17. 1. "         AWEBS               ,Bit status during a word error for each of the up to 16 address bits"
rgroup.long 0x458++0x3
line.long 0x00 "DDRPHY_BISTFWR1,BIST Fail Word Register 1"
bitfld.long 0x00 28.--31. " DMWEBS                 ,Bit status during a word error for the data mask (DM) bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21.--22. "        CIDWEBS_RSVD        ,Reserved.Return zeros on reads." "0,1,2,3"
textline "                              "
bitfld.long 0x00 20. " CIDWEBS                ,Bit status during a word error for each of the up to 3 chip ID bits." "0,1"
bitfld.long 0x00 16.--19. "         BAWEBS              ,Bit status during a word error for each of the bank address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 10.--15. " ODTWEBS_RSVD           ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "        ODTWEBS             ,Bit status during a word error for each of the up to 8 ODT bits." "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--7. " CKEWEBS_RSVD           ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "        CKEWEBS             ,Bit status during a word error for each of the up to 8 CKE bits." "0,1,2,3"
rgroup.long 0x45C++0x3
line.long 0x00 "DDRPHY_BISTFWR2,BIST Fail Word Register 2"
hexmask.long 0x00 0.--31. 1. " DQWEBS                 ,Bit status during a word error for each of the 8 data (DQ) bits"
rgroup.long 0x460++0x3
line.long 0x00 "DDRPHY_BISTBER5,BIST Bit Error Register 5"
hexmask.long.word 0x00 20.--31. 1. " ODTBER_RSVD            ,Reserved.Return zeros on reads."
bitfld.long 0x00 16.--19. "      ODTBER              ,ODT Bit Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
hexmask.long.word 0x00 4.--15. 1. " CKEBER_RSVD            ,Reserved.Return zeros on reads."
bitfld.long 0x00 0.--3. "      CKEBER              ,CKE Bit Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4DC++0x3
line.long 0x00 "DDRPHY_RANKIDR,Rank ID Register"
bitfld.long 0x00 16.--19. " RANKRID                ,Rank Read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RANKWID             ,Rank Write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4E0++0x3
line.long 0x00 "DDRPHY_RIOCR0,Rank I/O Configuration Register 0"
group.long 0x4E4++0x3
line.long 0x00 "DDRPHY_RIOCR1,Rank I/O Configuration Register 1"
group.long 0x4E8++0x3
line.long 0x00 "DDRPHY_RIOCR2,Rank I/O Configuration Register 2"
bitfld.long 0x00 26.--29. " COEMODE_RSVD           ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "        COEMODE             ,SDRAM C Output Enable (OE) Mode Selection." "0,1,2,3"
textline "                              "
hexmask.long.tbyte 0x00 4.--23. 1. " CSOEMODE_RSVD          ,Reserved.Return zeros on reads."
bitfld.long 0x00 0.--3. "    CSOEMODE            ,SDRAM CS_n Output Enable (OE) Mode Selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4EC++0x3
line.long 0x00 "DDRPHY_RIOCR3,Rank I/O Configuration Register 3"
group.long 0x4F0++0x3
line.long 0x00 "DDRPHY_RIOCR4,Rank I/O Configuration Register 4"
hexmask.long.word 0x00 4.--15. 1. " CKEOEMODE_RSVD         ,Reserved.Return zeros on reads."
bitfld.long 0x00 0.--3. "      CKEOEMODE           ,SDRAM CKE Output Enable (OE) Mode Selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4F4++0x3
line.long 0x00 "DDRPHY_RIOCR5,Rank I/O Configuration Register 5"
hexmask.long.word 0x00 4.--15. 1. " ODTOEMODE_RSVD         ,Reserved.Return zeros on reads."
bitfld.long 0x00 0.--3. "      ODTOEMODE           ,SDRAM On-die Termination Output Enable (OE) Mode Selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x500++0x3
line.long 0x00 "DDRPHY_ACIOCR0,AC I/O Configuration Register 0"
bitfld.long 0x00 30.--31. " ACSR                   ,Address/Command Slew Rate (D3F I/O Only)" "0,1,2,3"
bitfld.long 0x00 29. "         RSTIOM              ,SDRAM Reset I/O Mode" "0,1"
textline "                              "
bitfld.long 0x00 28. " RSTPDR                 ,SDRAM Reset Power Down Receiver" "0,1"
bitfld.long 0x00 26. "         RSTODT              ,SDRAM Reset On-Die Termination" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--23. 1. " ESR                    ,Decoupling Capacitance ESR Control in D5M I/O ring"
bitfld.long 0x00 10.--11. "        ACPNUMSEL           ,Address/Command custom pin mapping configuration" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6.--9. " CKDCC                  ,CK Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--5. "        ACPDRMODE           ,AC Power Down Receiver Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--3. " ACODTMODE              ,AC On-die Termination Mode" "0,1,2,3"
bitfld.long 0x00 0. "         ACRANKCLKSEL        ,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices." "0,1"
group.long 0x504++0x3
line.long 0x00 "DDRPHY_ACIOCR1,AC I/O Configuration Register 1"
hexmask.long 0x00 0.--31. 1. " AOEMODE                ,SDRAM Address Output Enable (OE) Mode Selection"
group.long 0x508++0x3
line.long 0x00 "DDRPHY_ACIOCR2,AC I/O Configuration Register 2"
bitfld.long 0x00 31. " CLKGENCLKGATE          ,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "0,1"
bitfld.long 0x00 30. "         ACOECLKGATE0        ,Clock gating for Output Enable D slices [0]" "0,1"
textline "                              "
bitfld.long 0x00 29. " ACPDRCLKGATE0          ,Clock gating for Power Down Receiver D slices [0]" "0,1"
bitfld.long 0x00 28. "         ACTECLKGATE0        ,Clock gating for Termination Enable D slices [0]" "0,1"
textline "                              "
bitfld.long 0x00 26.--27. " CKNCLKGATE0            ,Clock gating for CK# D slices[1:0]" "0,1,2,3"
bitfld.long 0x00 24.--25. "         CKCLKGATE0          ,Clock gating for CK D slices[1:0]" "0,1,2,3"
textline "                              "
hexmask.long.tbyte 0x00 0.--23. 1. " ACCLKGATE0             ,Clock gating for AC D slices[23:0]"
group.long 0x50C++0x3
line.long 0x00 "DDRPHY_ACIOCR3,AC I/O Configuration Register 3"
bitfld.long 0x00 30.--31. " PAROEMODE              ,SDRAM Parity Output Enable (OE) Mode Selection" "0,1,2,3"
bitfld.long 0x00 26.--29. "         BGOEMODE            ,SDRAM Bank Group Output Enable (OE) Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 22.--25. " BAOEMODE               ,SDRAM Bank Address Output Enable (OE) Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--21. "        A17OEMODE           ,SDRAM A[17] Output Enable (OE) Mode Selection" "0,1,2,3"
textline "                              "
bitfld.long 0x00 18.--19. " A16OEMODE              ,SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection" "0,1,2,3"
bitfld.long 0x00 16.--17. "         ACTOEMODE           ,SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)" "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--7. " CKOEMODE_RSVD          ,Reserved.Return zeros on reads." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CKOEMODE            ,SDRAM CK Output Enable (OE) Mode Selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x510++0x3
line.long 0x00 "DDRPHY_ACIOCR4,AC I/O Configuration Register 4"
bitfld.long 0x00 31. " LBCLKGATE              ,Clock gating for AC LB slices and loopback read valid slices" "0,1"
bitfld.long 0x00 30. "         ACOECLKGATE1        ,Clock gating for Output Enable D slices [1]" "0,1"
textline "                              "
bitfld.long 0x00 29. " ACPDRCLKGATE1          ,Clock gating for Power Down Receiver D slices [1]" "0,1"
bitfld.long 0x00 28. "         ACTECLKGATE1        ,Clock gating for Termination Enable D slices [1]" "0,1"
textline "                              "
bitfld.long 0x00 26.--27. " CKNCLKGATE1            ,Clock gating for CK# D slices[3:2]" "0,1,2,3"
bitfld.long 0x00 24.--25. "         CKCLKGATE1          ,Clock gating for CK D slices[3:2]" "0,1,2,3"
textline "                              "
hexmask.long.tbyte 0x00 0.--23. 1. " ACCLKGATE1             ,Clock gating for AC D slices[47:24]"
group.long 0x514++0x3
line.long 0x00 "DDRPHY_ACIOCR5,AC I/O Configuration Register 5"
bitfld.long 0x00 25.--27. " ACVREFIOM              ,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--24. "         ACXIOM              ,AC IO Mode" "0,1,2,3,4,5,6,7"
textline "                              "
hexmask.long.word 0x00 11.--21. 1. " ACTXM                  ,AC IO Transmitter Mode"
hexmask.long.word 0x00 0.--10. 1. "      ACRXM               ,AC IO Receiver Mode"
group.long 0x520++0x3
line.long 0x00 "DDRPHY_IOVCR0,IO VREF Control Register 0"
bitfld.long 0x00 28. " ACREFPEN               ,Address/command lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         ACREFEEN            ,Address/command lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " ACREFSEN               ,Address/command lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 24. "         ACREFIEN            ,Address/command lane Internal VREF Enable" "0,1"
textline "                              "
bitfld.long 0x00 23. " ACREFESELRANGE         ,External VREF generato REFSEL range select" "0,1"
hexmask.long.byte 0x00 16.--22. 1. "         ACREFESEL           ,Address/command lane External VREF Select"
textline "                              "
bitfld.long 0x00 15. " ACREFSSELRANGE         ,Single ended VREF generator REFSEL range select" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "         ACREFSSEL           ,Address/command lane Single-End VREF Select"
textline "                              "
bitfld.long 0x00 7. " ACVREFISELRANGE        ,Internal VREF generator REFSEL ragne select" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         ACVREFISEL          ,REFSEL Control for internal AC IOs"
group.long 0x528++0x3
line.long 0x00 "DDRPHY_VTCR0,VREF Training Control Register 0"
bitfld.long 0x00 29.--31. " TVREF                  ,Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "         DVEN                ,DRAM DQ VREF training Enable" "0,1"
textline "                              "
bitfld.long 0x00 27. " PDAEN                  ,Per Device Addressability Enable" "0,1"
bitfld.long 0x00 22.--25. "         VWCR                ,VREF Word Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 18.--21. " DVSS                   ,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--17. "        DVMAX               ,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 6.--11. " DVMIN                  ,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DVINIT              ,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x52C++0x3
line.long 0x00 "DDRPHY_VTCR1,VREF Training Control Register 1"
bitfld.long 0x00 28.--31. " HVSS                   ,Host VREF step size used during VREF training.The register value of N indicates step size of (N+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 20.--26. 1. "        HVMAX               ,Maximum VREF limit value used during DRAM VREF training."
textline "                              "
hexmask.long.byte 0x00 12.--18. 1. " HVMIN                  ,Minimum VREF limit value used during DRAM VREF training."
bitfld.long 0x00 9.--10. "        SHRNK               ,Static Host Vref Rank Value" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " SHREN                  ,Static Host Vref Rank Enable" "0,1"
bitfld.long 0x00 5.--7. "         TVREFIO             ,Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 3.--4. " EOFF                   ,Eye LCDL Offset value for VREF training" "0,1,2,3"
bitfld.long 0x00 2. "         ENUM                ,Number of LCDL Eye points for which VREF training is repeated" "0,1"
textline "                              "
bitfld.long 0x00 1. " HVEN                   ,HOST (IO) internal VREF training Enable" "0,1"
bitfld.long 0x00 0. "         HVIO                ,Host IO Type Control" "0,1"
group.long 0x540++0x3
line.long 0x00 "DDRPHY_ACBDLR0,AC Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " CK3BD                  ,CK3 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CK2BD               ,CK2 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CK1BD                  ,CK1 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CK0BD               ,CK0 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x544++0x3
line.long 0x00 "DDRPHY_ACBDLR1,AC Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " PARBD                  ,Delay select for the BDL on Parity." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        A16BD               ,Delay select for the BDL on Address A[16].In DDR3 mode this pin is connected to WE." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " A17BD                  ,Delay select for the BDL on Address A[17].When not in DDR4 modemode this pin is connected to CAS." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        ACTBD               ,Delay select for the BDL on ACTN." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x548++0x3
line.long 0x00 "DDRPHY_ACBDLR2,AC Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " BG1BD                  ,Delay select for the BDL on BG[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        BG0BD               ,Delay select for the BDL on BG[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " BA1BD                  ,Delay select for the BDL on BA[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        BA0BD               ,Delay select for the BDL on BA[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54C++0x3
line.long 0x00 "DDRPHY_ACBDLR3,AC Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " CS3BD                  ,Delay select for the BDL on CS[3]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CS2BD               ,Delay select for the BDL on CS[2]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CS1BD                  ,Delay select for the BDL on CS[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CS0BD               ,Delay select for the BDL on CS[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x550++0x3
line.long 0x00 "DDRPHY_ACBDLR4,AC Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " ODT3BD                 ,Delay select for the BDL on ODT[3]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        ODT2BD              ,Delay select for the BDL on ODT[2]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " ODT1BD                 ,Delay select for the BDL on ODT[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        ODT0BD              ,Delay select for the BDL on ODT[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x554++0x3
line.long 0x00 "DDRPHY_ACBDLR5,AC Bit Delay Line Register 5"
bitfld.long 0x00 24.--29. " CKE3BD                 ,Delay select for the BDL on CKE[3]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CKE2BD              ,Delay select for the BDL on CKE[2]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CKE1BD                 ,Delay select for the BDL on CKE[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CKE0BD              ,Delay select for the BDL on CKE[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x558++0x3
line.long 0x00 "DDRPHY_ACBDLR6,AC Bit Delay Line Register 6"
bitfld.long 0x00 24.--29. " A03BD                  ,Delay select for the BDL on Address A[3]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        A02BD               ,Delay select for the BDL on Address A[2]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " A01BD                  ,Delay select for the BDL on Address A[1]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        A00BD               ,Delay select for the BDL on Address A[0]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x55C++0x3
line.long 0x00 "DDRPHY_ACBDLR7,AC Bit Delay Line Register 7"
bitfld.long 0x00 24.--29. " A07BD                  ,Delay select for the BDL on Address A[7]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        A06BD               ,Delay select for the BDL on Address A[6]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " A05BD                  ,Delay select for the BDL on Address A[5]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        A04BD               ,Delay select for the BDL on Address A[4]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x560++0x3
line.long 0x00 "DDRPHY_ACBDLR8,AC Bit Delay Line Register 8"
bitfld.long 0x00 24.--29. " A11BD                  ,Delay select for the BDL on Address A[11]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        A10BD               ,Delay select for the BDL on Address A[10]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " A09BD                  ,Delay select for the BDL on Address A[9]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        A08BD               ,Delay select for the BDL on Address A[8]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x564++0x3
line.long 0x00 "DDRPHY_ACBDLR9,AC Bit Delay Line Register 9"
bitfld.long 0x00 24.--29. " A15BD                  ,Delay select for the BDL on Address A[15]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        A14BD               ,Delay select for the BDL on Address A[14]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " A13BD                  ,Delay select for the BDL on Address A[13]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        A12BD               ,Delay select for the BDL on Address A[12]." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x568++0x3
line.long 0x00 "DDRPHY_ACBDLR10,AC Bit Delay Line Register 10"
bitfld.long 0x00 24.--29. " CID2BD                 ,Delay select for the BDL on Chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CID1BD              ,Delay select for the BDL on Chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CID0BD                 ,Delay select for the BDL on Chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x56C++0x3
line.long 0x00 "DDRPHY_ACBDLR11,AC Bit Delay Line Register 11"
bitfld.long 0x00 24.--29. " CS7BD                  ,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CS6BD               ,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CS5BD                  ,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CS4BD               ,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x570++0x3
line.long 0x00 "DDRPHY_ACBDLR12,AC Bit Delay Line Register 12"
bitfld.long 0x00 24.--29. " CS11BD                 ,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CS10BD              ,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CS9BD                  ,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CS8BD               ,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x574++0x3
line.long 0x00 "DDRPHY_ACBDLR13,AC Bit Delay Line Register 13"
bitfld.long 0x00 24.--29. " ODT7BD                 ,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        ODT6BD              ,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " ODT5BD                 ,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        ODT4BD              ,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x578++0x3
line.long 0x00 "DDRPHY_ACBDLR14,AC Bit Delay Line Register 14"
bitfld.long 0x00 24.--29. " CKE7BD                 ,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CKE6BD              ,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CKE5BD                 ,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CKE4BD              ,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x57C++0x3
line.long 0x00 "DDRPHY_ACBDLR15,AC Bit Delay Line Register 15"
bitfld.long 0x00 16.--21. " OEBD                   ,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        TEBD                ,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " PDRBD                  ,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x580++0x3
line.long 0x00 "DDRPHY_ACBDLR16,AC Bit Delay Line Register 16"
bitfld.long 0x00 24.--29. " CKN3BD                 ,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CKN2BD              ,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " CKN1BD                 ,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CKN0BD              ,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x584++0x3
line.long 0x00 "DDRPHY_ACLCDLR,AC Local Calibrated Delay Line Register"
hexmask.long.word 0x00 16.--24. 1. " ACD1                   ,Address/Command Delay for AC Macro 1"
hexmask.long.word 0x00 0.--8. 1. "      ACD                 ,Address/Command Delay for AC Macro 0"
group.long 0x5A0++0x3
line.long 0x00 "DDRPHY_ACMDLR0,AC Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0x5A4++0x3
line.long 0x00 "DDRPHY_ACMDLR1,AC Master Delay Line Register 1"
hexmask.long.word 0x00 16.--24. 1. " MDLD1                  ,MDL Delay for AC Macro 1"
hexmask.long.word 0x00 0.--8. 1. "      MDLD                ,MDL Delay for AC Macro 0"
group.long 0x680++0x3
line.long 0x00 "DDRPHY_ZQCR,ZQ Impedance Control Register"
bitfld.long 0x00 25. " ZQREFISELRANGE         ,ZQ VREF Range" "0,1"
bitfld.long 0x00 19.--24. "         PGWAIT_FRQB         ,Programmable Wait for Frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 13.--18. " PGWAIT_FRQA            ,Programmable Wait for Frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 12. "        ZQREFPEN            ,ZQ VREF Pad Enable" "0,1"
textline "                              "
bitfld.long 0x00 11. " ZQREFIEN               ,ZQ Internal VREF Enable" "0,1"
bitfld.long 0x00 9.--10. "         ODT_MODE            ,Choice of termination mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " FORCE_ZCAL_VT_UPDATE   ,Force ZCAL VT update" "0,1"
bitfld.long 0x00 5.--7. "         IODLMT              ,IO VT Drift Limit" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 4. " AVGEN                  ,Averaging algorithm enable, if set, enables averaging algorithm" "0,1"
bitfld.long 0x00 2.--3. "         AVGMAX              ,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " ZCALT                  ,ZQ Calibration Type" "0,1"
bitfld.long 0x00 0. "         ZQPD                ,ZQ Power Down" "0,1"
group.long 0x684++0x3
line.long 0x00 "DDRPHY_ZQ0PR0,ZQ n Impedance Control Program Register 0"
bitfld.long 0x00 31. " PD_DRV_ZDEN            ,Pull-down drive strength ZCTRL over-ride enable" "0,1"
bitfld.long 0x00 30. "         PU_DRV_ZDEN         ,Pull-up drive strength ZCTRL over-ride enable" "0,1"
textline "                              "
bitfld.long 0x00 29. " PD_ODT_ZDEN            ,Pull-down termination ZCTRL over-ride enable" "0,1"
bitfld.long 0x00 28. "         PU_ODT_ZDEN         ,Pull-up termination ZCTRL over-ride enable" "0,1"
textline "                              "
bitfld.long 0x00 27. " ZSEGBYP                ,Calibration segment bypass" "0,1"
bitfld.long 0x00 25.--26. "         ZLE_MODE            ,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22.--24. " ODT_ADJUST             ,Termination adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19.--21. "         PD_DRV_ADJUST       ,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 16.--18. " PU_DRV_ADJUST          ,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--15. "         ZPROG_DRAM_ODT      ,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT         ,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        ZPROG_ASYM_DRV_PD   ,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU      ,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x688++0x3
line.long 0x00 "DDRPHY_ZQ0PR1,ZQ n Impedance Control Program Register 1"
hexmask.long.byte 0x00 8.--14. 1. " PU_REFSEL              ,Pull-up REFSEL for PZCTRL cell"
hexmask.long.byte 0x00 0.--6. 1. "        PD_REFSEL           ,Pull-down REFSEL for PZCTRL cell"
rgroup.long 0x68C++0x3
line.long 0x00 "DDRPHY_ZQ0DR0,ZQ n Impedance Control Data Register 0"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT    ,Pull-up drive strength calibration code result"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result"
rgroup.long 0x690++0x3
line.long 0x00 "DDRPHY_ZQ0DR1,ZQ n Impedance Control Data Register 1"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_ODT_RESULT    ,Pull-up termination calibration code result"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result"
group.long 0x694++0x3
line.long 0x00 "DDRPHY_ZQ0OR0,ZQ n Impedance Control Override Data Register 0"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD      ,Override value for the pull-up output impedance"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_DRV_OVRD   ,Override value for the pull-down output impedance"
group.long 0x698++0x3
line.long 0x00 "DDRPHY_ZQ0OR1,ZQ n Impedance Control Override Data Register 1"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_ODT_OVRD      ,Override value for the pull-up termination"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_ODT_OVRD   ,Override value for the pull-down termination"
rgroup.long 0x69C++0x3
line.long 0x00 "DDRPHY_ZQ0SR,ZQ n Impedance Control Status Register"
bitfld.long 0x00 13. " PD_ODT_SAT             ,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
bitfld.long 0x00 12. "         PU_ODT_SAT          ,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
textline "                              "
bitfld.long 0x00 11. " PD_DRV_SAT             ,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
bitfld.long 0x00 10. "         PU_DRV_SAT          ,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
textline "                              "
bitfld.long 0x00 9. " ZDONE                  ,Impedance Calibration Done" "0,1"
bitfld.long 0x00 8. "         ZERR                ,Impedance Calibration Error" "0,1"
textline "                              "
bitfld.long 0x00 6.--7. " OPU                    ,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
bitfld.long 0x00 4.--5. "         OPD                 ,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--3. " ZPU                    ,Output impedance pull-up calibration status" "0,1,2,3"
bitfld.long 0x00 0.--1. "         ZPD                 ,Output impedance pull-down calibration status" "0,1,2,3"
group.long 0x6A4++0x3
line.long 0x00 "DDRPHY_ZQ1PR0,ZQ n Impedance Control Program Register 0"
bitfld.long 0x00 31. " PD_DRV_ZDEN            ,Pull-down drive strength ZCTRL over-ride enable" "0,1"
bitfld.long 0x00 30. "         PU_DRV_ZDEN         ,Pull-up drive strength ZCTRL over-ride enable" "0,1"
textline "                              "
bitfld.long 0x00 29. " PD_ODT_ZDEN            ,Pull-down termination ZCTRL over-ride enable" "0,1"
bitfld.long 0x00 28. "         PU_ODT_ZDEN         ,Pull-up termination ZCTRL over-ride enable" "0,1"
textline "                              "
bitfld.long 0x00 27. " ZSEGBYP                ,Calibration segment bypass" "0,1"
bitfld.long 0x00 25.--26. "         ZLE_MODE            ,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22.--24. " ODT_ADJUST             ,Termination adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19.--21. "         PD_DRV_ADJUST       ,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 16.--18. " PU_DRV_ADJUST          ,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--15. "         ZPROG_DRAM_ODT      ,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " ZPROG_HOST_ODT         ,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        ZPROG_ASYM_DRV_PD   ,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " ZPROG_ASYM_DRV_PU      ,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6A8++0x3
line.long 0x00 "DDRPHY_ZQ1PR1,ZQ n Impedance Control Program Register 1"
hexmask.long.byte 0x00 8.--14. 1. " PU_REFSEL              ,Pull-up REFSEL for PZCTRL cell"
hexmask.long.byte 0x00 0.--6. 1. "        PD_REFSEL           ,Pull-down REFSEL for PZCTRL cell"
rgroup.long 0x6AC++0x3
line.long 0x00 "DDRPHY_ZQ1DR0,ZQ n Impedance Control Data Register 0"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_RESULT    ,Pull-up drive strength calibration code result"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_DRV_RESULT ,Pull-down drive strength calibration code result"
rgroup.long 0x6B0++0x3
line.long 0x00 "DDRPHY_ZQ1DR1,ZQ n Impedance Control Data Register 1"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_ODT_RESULT    ,Pull-up termination calibration code result"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_ODT_RESULT ,Pull-down termination calibration code result"
group.long 0x6B4++0x3
line.long 0x00 "DDRPHY_ZQ1OR0,ZQ n Impedance Control Override Data Register 0"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_DRV_OVRD      ,Override value for the pull-up output impedance"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_DRV_OVRD   ,Override value for the pull-down output impedance"
group.long 0x6B8++0x3
line.long 0x00 "DDRPHY_ZQ1OR1,ZQ n Impedance Control Override Data Register 1"
hexmask.long.word 0x00 16.--25. 1. " ZDATA_PU_ODT_OVRD      ,Override value for the pull-up termination"
hexmask.long.word 0x00 0.--9. 1. "      ZDATA_PD_ODT_OVRD   ,Override value for the pull-down termination"
rgroup.long 0x6BC++0x3
line.long 0x00 "DDRPHY_ZQ1SR,ZQ n Impedance Control Status Register"
bitfld.long 0x00 13. " PD_ODT_SAT             ,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
bitfld.long 0x00 12. "         PU_ODT_SAT          ,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
textline "                              "
bitfld.long 0x00 11. " PD_DRV_SAT             ,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
bitfld.long 0x00 10. "         PU_DRV_SAT          ,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
textline "                              "
bitfld.long 0x00 9. " ZDONE                  ,Impedance Calibration Done" "0,1"
bitfld.long 0x00 8. "         ZERR                ,Impedance Calibration Error" "0,1"
textline "                              "
bitfld.long 0x00 6.--7. " OPU                    ,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
bitfld.long 0x00 4.--5. "         OPD                 ,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--3. " ZPU                    ,Output impedance pull-up calibration status" "0,1,2,3"
bitfld.long 0x00 0.--1. "         ZPD                 ,Output impedance pull-down calibration status" "0,1,2,3"
group.long 0x700++0x3
line.long 0x00 "DDRPHY_DX0GCR0,DATX8 n General Configuration Register 0"
bitfld.long 0x00 31. " CALBYP                 ,Calibration Bypass" "0,1"
bitfld.long 0x00 30. "         MDLEN               ,Master Delay Line Enable" "0,1"
textline "                              "
bitfld.long 0x00 28.--29. " CODTSHFT               ,Configurable ODT(TE) Phase Shift" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DQSDCC              ,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " RDDLY                  ,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "        DQSNSEPDR           ,DQSNSE Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 12. " DQSSEPDR               ,DQSSE Power Down Receiver" "0,1"
bitfld.long 0x00 11. "         RTTOAL              ,RTT On Additive Latency" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " RTTOH                  ,RTT Output Hold" "0,1,2,3"
bitfld.long 0x00 7.--8. "         CPDRSHFT            ,Configurable PDR Phase Shift" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6. " DQSRPD                 ,DQSR Power Down" "0,1"
bitfld.long 0x00 5. "         DQSGPDR             ,DQSG Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 3. " DQSGODT                ,DQSG On-Die Termination" "0,1"
bitfld.long 0x00 2. "         DQSGOE              ,DQSG Output Enable" "0,1"
group.long 0x704++0x3
line.long 0x00 "DDRPHY_DX0GCR1,DATX8 n General Configuration Register 1"
hexmask.long.word 0x00 16.--31. 1. " DXPDRMODE              ,Enables the PDR mode for DQ[7:0]"
bitfld.long 0x00 14. "      QSNSEL              ,Select the delayed or non-delayed read data strobe #" "0,1"
textline "                              "
bitfld.long 0x00 13. " QSSEL                  ,Select the delayed or non-delayed read data strobe" "0,1"
bitfld.long 0x00 12. "         OEEN                ,Enables Read Data Strobe in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 11. " PDREN                  ,Enables PDR in a byte lane" "0,1"
bitfld.long 0x00 10. "         TEEN                ,Enables ODT/TE in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 9. " DSEN                   ,Enables Write Data strobe in a byte lane" "0,1"
bitfld.long 0x00 8. "         DMEN                ,Enables DM pin in a byte lane" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DQEN                   ,Enables DQ corresponding to each bit in a byte"
group.long 0x708++0x3
line.long 0x00 "DDRPHY_DX0GCR2,DATX8 n General Configuration Register 2"
hexmask.long.word 0x00 16.--31. 1. " DXOEMODE               ,Enables the OE mode values for DQ[7:0]"
hexmask.long.word 0x00 0.--15. 1. "      DXTEMODE            ,Enables the TE (ODT) mode values for DQ[7:0]"
group.long 0x70C++0x3
line.long 0x00 "DDRPHY_DX0GCR3,DATX8 n General Configuration Register 3"
bitfld.long 0x00 31. " OEBVT                  ,Output Enable BDL VT Compensation" "0,1"
bitfld.long 0x00 30. "         TEBVT               ,Termination Enable BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 29. " RDBVT                  ,Read Data BDL VT Compensation" "0,1"
bitfld.long 0x00 28. "         WDBVT               ,Write Data BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 27. " RGLVT                  ,Read DQS Gating LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 26. "         RDLVT               ,Read DQS LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDLVT                  ,Write DQ LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 24. "         WLLVT               ,Write Leveling LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 23. " RGSLVT                 ,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 22. "         PDRBVT              ,Power Down Receiver BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DSNOEMODE              ,Enables the OE mode for DQs" "0,1,2,3"
bitfld.long 0x00 18.--19. "         DSNTEMODE           ,Enables the TE mode for DQS" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--17. " DSNPDRMODE             ,Enables the PDR mode for DQS" "0,1,2,3"
bitfld.long 0x00 14.--15. "         DMOEMODE            ,Enables the OE mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DMTEMODE               ,Enables the TE mode values for DM." "0,1,2,3"
bitfld.long 0x00 10.--11. "         DMPDRMODE           ,Enables the PDR mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " WDSBVT                 ,Write Data Strobe BDL VT Compensation" "0,1"
bitfld.long 0x00 6.--7. "         DSOEMODE            ,Enables the OE mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--5. " DSTEMODE               ,Enables the TE mode values for DQS." "0,1,2,3"
bitfld.long 0x00 2.--3. "         DSPDRMODE           ,Enables the PDR mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " RDMBVT                 ,Read Data Mask BDL VT Compensation" "0,1"
bitfld.long 0x00 0. "         WDMBVT              ,Write Data Mask BDL VT Compensation" "0,1"
group.long 0x710++0x3
line.long 0x00 "DDRPHY_DX0GCR4,DATX8 n General Configuration Register 4"
bitfld.long 0x00 28. " DXREFPEN               ,Byte Lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         DXREFEEN            ,Byte Lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " DXREFSEN               ,Byte Lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 23. "         DXREFESELRANGE      ,External VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--22. 1. " DXREFESEL              ,Byte Lane External VREF Select"
bitfld.long 0x00 15. "        DXREFSSELRANGE      ,Single ended VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFSSEL              ,Byte Lane Single-End VREF Select"
bitfld.long 0x00 2.--5. "        DXREFIEN            ,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--1. " DXREFIMON              ,VRMON control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3"
group.long 0x714++0x3
line.long 0x00 "DDRPHY_DX0GCR5,DATX8 n General Configuration Register 5"
hexmask.long.byte 0x00 24.--30. 1. " DXREFISELR3            ,Byte Lane internal VREF Select for Rank 3"
hexmask.long.byte 0x00 16.--22. 1. "        DXREFISELR2         ,Byte Lane internal VREF Select for Rank 2"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFISELR1            ,Byte Lane internal VREF Select for Rank 1"
hexmask.long.byte 0x00 0.--6. 1. "        DXREFISELR0         ,Byte Lane internal VREF Select for Rank 0"
group.long 0x718++0x3
line.long 0x00 "DDRPHY_DX0GCR6,DATX8 n General Configuration Register 6"
bitfld.long 0x00 24.--29. " DXDQVREFR3             ,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DXDQVREFR2          ,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DXDQVREFR1             ,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DXDQVREFR0          ,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x71C++0x3
line.long 0x00 "DDRPHY_DX0GCR7,DATX8 n General Configuration Register 7"
bitfld.long 0x00 9. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 0.--8. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
group.long 0x720++0x3
line.long 0x00 "DDRPHY_DX0GCR8,DATX8 n General Configuration Register 8"
group.long 0x724++0x3
line.long 0x00 "DDRPHY_DX0GCR9,DATX8 n General Configuration Register 9"
group.long 0x728++0x3
line.long 0x00 "DDRPHY_DX0DQMAP0,DATX8 n DQ/DM Mapping Register 0"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 16.--19. "         DQ4MAP              ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12.--15. " DQ3MAP                 ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        DQ2MAP              ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DQ1MAP                 ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DQ0MAP              ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x72C++0x3
line.long 0x00 "DDRPHY_DX0DQMAP1,DATX8 n DQ/DM Mapping Register 1"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 12.--15. "         DMMAP               ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " DQ7MAP                 ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DQ6MAP              ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQ5MAP                 ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x740++0x3
line.long 0x00 "DDRPHY_DX0BDLR0,DATX8 n Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " DQ3WBD                 ,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2WBD              ,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1WBD                 ,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0WBD              ,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x744++0x3
line.long 0x00 "DDRPHY_DX0BDLR1,DATX8 n Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " DQ7WBD                 ,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6WBD              ,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5WBD                 ,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4WBD              ,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x748++0x3
line.long 0x00 "DDRPHY_DX0BDLR2,DATX8 n Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " DSNWBD                 ,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DSOEBD              ,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DSWBD                  ,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DMWBD               ,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x750++0x3
line.long 0x00 "DDRPHY_DX0BDLR3,DATX8 n Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " DQ3RBD                 ,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2RBD              ,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1RBD                 ,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0RBD              ,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x754++0x3
line.long 0x00 "DDRPHY_DX0BDLR4,DATX8 n Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " DQ7RBD                 ,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6RBD              ,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5RBD                 ,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4RBD              ,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x758++0x3
line.long 0x00 "DDRPHY_DX0BDLR5,DATX8 n Bit Delay Line Register 5"
bitfld.long 0x00 0.--5. " DMRBD                  ,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x760++0x3
line.long 0x00 "DDRPHY_DX0BDLR6,DATX8 n Bit Delay Line Register 6"
bitfld.long 0x00 16.--21. " TERBD                  ,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        PDRBD               ,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x764++0x3
line.long 0x00 "DDRPHY_DX0BDLR7,DATX8 n Bit Delay Line Register 7"
group.long 0x768++0x3
line.long 0x00 "DDRPHY_DX0BDLR8,DATX8 n Bit Delay Line Register 8"
group.long 0x76C++0x3
line.long 0x00 "DDRPHY_DX0BDLR9,DATX8 n Bit Delay Line Register 9"
group.long 0x780++0x3
line.long 0x00 "DDRPHY_DX0LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
hexmask.long.word 0x00 0.--8. 1. " WLD                    ,Write Leveling Delay"
group.long 0x784++0x3
line.long 0x00 "DDRPHY_DX0LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " WDQD                   ,Write Data Delay"
group.long 0x788++0x3
line.long 0x00 "DDRPHY_DX0LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
hexmask.long.word 0x00 0.--8. 1. " DQSGD                  ,Read DQS Gating Delay"
group.long 0x78C++0x3
line.long 0x00 "DDRPHY_DX0LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
hexmask.long.word 0x00 0.--8. 1. " RDQSD                  ,Read DQS Delay"
group.long 0x790++0x3
line.long 0x00 "DDRPHY_DX0LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
hexmask.long.word 0x00 0.--8. 1. " RDQSND                 ,Read DQSN Delay"
group.long 0x794++0x3
line.long 0x00 "DDRPHY_DX0LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
hexmask.long.word 0x00 0.--8. 1. " DQSGSD                 ,DQS Gating Status Delay"
group.long 0x7A0++0x3
line.long 0x00 "DDRPHY_DX0MDLR0,DATX8 n Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0x7A4++0x3
line.long 0x00 "DDRPHY_DX0MDLR1,DATX8 n Master Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " MDLD                   ,MDL Delay"
group.long 0x7C0++0x3
line.long 0x00 "DDRPHY_DX0GTR0,DATX8 n General Timing Register 0"
bitfld.long 0x00 24.--26. " WDQSL                  ,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         WLSL                ,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--4. " DGSL                   ,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x7D0++0x3
line.long 0x00 "DDRPHY_DX0RSR0,DATX8 n Rank Status Register 0"
hexmask.long.word 0x00 0.--15. 1. " QSGERR                 ,DQS Gate Training Error"
rgroup.long 0x7D4++0x3
line.long 0x00 "DDRPHY_DX0RSR1,DATX8 n Rank Status Register 1"
hexmask.long.word 0x00 0.--15. 1. " RDLVLERR               ,Read Leveling Error"
rgroup.long 0x7D8++0x3
line.long 0x00 "DDRPHY_DX0RSR2,DATX8 n Rank Status Register 2"
hexmask.long.word 0x00 0.--15. 1. " WLAWN                  ,Write Latency Adjustment (DQS off on some DQ lines) Warning"
rgroup.long 0x7DC++0x3
line.long 0x00 "DDRPHY_DX0RSR3,DATX8 n Rank Status Register 3"
hexmask.long.word 0x00 0.--15. 1. " WLAERR                 ,Write Leveling Adjustment Error"
rgroup.long 0x7E0++0x3
line.long 0x00 "DDRPHY_DX0GSR0,DATX8 n General Status Register 0"
bitfld.long 0x00 30. " WLDQ                   ,Write Leveling DQ Status" "0,1"
hexmask.long.word 0x00 17.--25. 1. "         GDQSPRD             ,Read DQS gating Period"
textline "                              "
bitfld.long 0x00 16. " DPLOCK                 ,DATX8 PLL Lock" "0,1"
hexmask.long.word 0x00 7.--15. 1. "         WLPRD               ,Write Leveling Period"
textline "                              "
bitfld.long 0x00 6. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 5. "         WLDONE              ,Write Leveling Done" "0,1"
textline "                              "
bitfld.long 0x00 4. " WLCAL                  ,Write Leveling Calibration" "0,1"
bitfld.long 0x00 3. "         GDQSCAL             ,Read DQS gating Calibration" "0,1"
textline "                              "
bitfld.long 0x00 2. " RDQSNCAL               ,Read DQS# Calibration" "0,1"
bitfld.long 0x00 1. "         RDQSCAL             ,Read DQS Calibration" "0,1"
textline "                              "
bitfld.long 0x00 0. " WDQCAL                 ,Write DQ Calibration" "0,1"
rgroup.long 0x7E4++0x3
line.long 0x00 "DDRPHY_DX0GSR1,DATX8 n General Status Register 1"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done" "0,1"
rgroup.long 0x7E8++0x3
line.long 0x00 "DDRPHY_DX0GSR2,DATX8 n General Status Register 2"
hexmask.long.word 0x00 23.--31. 1. " GSDQSPRD               ,Read DQS gating Status Period"
bitfld.long 0x00 22. "      GSDQSCAL            ,Read DQS Gating Status Calibration" "0,1"
textline "                              "
bitfld.long 0x00 20. " SRDERR                 ,Static Read Error" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "         DQS2DQERR           ,Write DQS2DQ Training Error"
textline "                              "
bitfld.long 0x00 8.--11. " ESTAT                  ,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        WEWN                ,Write Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 6. " WEERR                  ,Write Eye Centering Error" "0,1"
bitfld.long 0x00 5. "         REWN                ,Read Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 4. " REERR                  ,Read Eye Centering Error" "0,1"
bitfld.long 0x00 3. "         WDWN                ,Write Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 2. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 1. "         RDWN                ,Read Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 0. " RDERR                  ,Read Bit Deskew Error" "0,1"
rgroup.long 0x7EC++0x3
line.long 0x00 "DDRPHY_DX0GSR3,DATX8 n General Status Register 3"
bitfld.long 0x00 24.--26. " ESTAT                  ,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         DVWRN               ,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " DVERR                  ,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        HVWRN               ,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " HVERR                  ,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        SRDPC               ,Static Read Delay Pass Count" "0,1,2,3"
group.long 0x7F0++0x3
line.long 0x00 "DDRPHY_DX0GSR4,DATX8 n General Status Register 4"
group.long 0x7F4++0x3
line.long 0x00 "DDRPHY_DX0GSR5,DATX8 n General Status Register 5"
rgroup.long 0x7F8++0x3
line.long 0x00 "DDRPHY_DX0GSR6,DATX8 n General Status Register 6"
hexmask.long.byte 0x00 24.--31. 1. " DBDQ                   ,Capture DB DQ[7:0], bits [31:28] is for DQ[[7:4] for upper nibble, bits [27:24] is for DQ[3:0] for lower nibble."
group.long 0x800++0x3
line.long 0x00 "DDRPHY_DX1GCR0,DATX8 n General Configuration Register 0"
bitfld.long 0x00 31. " CALBYP                 ,Calibration Bypass" "0,1"
bitfld.long 0x00 30. "         MDLEN               ,Master Delay Line Enable" "0,1"
textline "                              "
bitfld.long 0x00 28.--29. " CODTSHFT               ,Configurable ODT(TE) Phase Shift" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DQSDCC              ,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " RDDLY                  ,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "        DQSNSEPDR           ,DQSNSE Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 12. " DQSSEPDR               ,DQSSE Power Down Receiver" "0,1"
bitfld.long 0x00 11. "         RTTOAL              ,RTT On Additive Latency" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " RTTOH                  ,RTT Output Hold" "0,1,2,3"
bitfld.long 0x00 7.--8. "         CPDRSHFT            ,Configurable PDR Phase Shift" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6. " DQSRPD                 ,DQSR Power Down" "0,1"
bitfld.long 0x00 5. "         DQSGPDR             ,DQSG Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 3. " DQSGODT                ,DQSG On-Die Termination" "0,1"
bitfld.long 0x00 2. "         DQSGOE              ,DQSG Output Enable" "0,1"
group.long 0x804++0x3
line.long 0x00 "DDRPHY_DX1GCR1,DATX8 n General Configuration Register 1"
hexmask.long.word 0x00 16.--31. 1. " DXPDRMODE              ,Enables the PDR mode for DQ[7:0]"
bitfld.long 0x00 14. "      QSNSEL              ,Select the delayed or non-delayed read data strobe #" "0,1"
textline "                              "
bitfld.long 0x00 13. " QSSEL                  ,Select the delayed or non-delayed read data strobe" "0,1"
bitfld.long 0x00 12. "         OEEN                ,Enables Read Data Strobe in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 11. " PDREN                  ,Enables PDR in a byte lane" "0,1"
bitfld.long 0x00 10. "         TEEN                ,Enables ODT/TE in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 9. " DSEN                   ,Enables Write Data strobe in a byte lane" "0,1"
bitfld.long 0x00 8. "         DMEN                ,Enables DM pin in a byte lane" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DQEN                   ,Enables DQ corresponding to each bit in a byte"
group.long 0x808++0x3
line.long 0x00 "DDRPHY_DX1GCR2,DATX8 n General Configuration Register 2"
hexmask.long.word 0x00 16.--31. 1. " DXOEMODE               ,Enables the OE mode values for DQ[7:0]"
hexmask.long.word 0x00 0.--15. 1. "      DXTEMODE            ,Enables the TE (ODT) mode values for DQ[7:0]"
group.long 0x80C++0x3
line.long 0x00 "DDRPHY_DX1GCR3,DATX8 n General Configuration Register 3"
bitfld.long 0x00 31. " OEBVT                  ,Output Enable BDL VT Compensation" "0,1"
bitfld.long 0x00 30. "         TEBVT               ,Termination Enable BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 29. " RDBVT                  ,Read Data BDL VT Compensation" "0,1"
bitfld.long 0x00 28. "         WDBVT               ,Write Data BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 27. " RGLVT                  ,Read DQS Gating LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 26. "         RDLVT               ,Read DQS LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDLVT                  ,Write DQ LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 24. "         WLLVT               ,Write Leveling LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 23. " RGSLVT                 ,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 22. "         PDRBVT              ,Power Down Receiver BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DSNOEMODE              ,Enables the OE mode for DQs" "0,1,2,3"
bitfld.long 0x00 18.--19. "         DSNTEMODE           ,Enables the TE mode for DQS" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--17. " DSNPDRMODE             ,Enables the PDR mode for DQS" "0,1,2,3"
bitfld.long 0x00 14.--15. "         DMOEMODE            ,Enables the OE mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DMTEMODE               ,Enables the TE mode values for DM." "0,1,2,3"
bitfld.long 0x00 10.--11. "         DMPDRMODE           ,Enables the PDR mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " WDSBVT                 ,Write Data Strobe BDL VT Compensation" "0,1"
bitfld.long 0x00 6.--7. "         DSOEMODE            ,Enables the OE mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--5. " DSTEMODE               ,Enables the TE mode values for DQS." "0,1,2,3"
bitfld.long 0x00 2.--3. "         DSPDRMODE           ,Enables the PDR mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " RDMBVT                 ,Read Data Mask BDL VT Compensation" "0,1"
bitfld.long 0x00 0. "         WDMBVT              ,Write Data Mask BDL VT Compensation" "0,1"
group.long 0x810++0x3
line.long 0x00 "DDRPHY_DX1GCR4,DATX8 n General Configuration Register 4"
bitfld.long 0x00 28. " DXREFPEN               ,Byte Lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         DXREFEEN            ,Byte Lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " DXREFSEN               ,Byte Lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 23. "         DXREFESELRANGE      ,External VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--22. 1. " DXREFESEL              ,Byte Lane External VREF Select"
bitfld.long 0x00 15. "        DXREFSSELRANGE      ,Single ended VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFSSEL              ,Byte Lane Single-End VREF Select"
bitfld.long 0x00 2.--5. "        DXREFIEN            ,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--1. " DXREFIMON              ,VRMON control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3"
group.long 0x814++0x3
line.long 0x00 "DDRPHY_DX1GCR5,DATX8 n General Configuration Register 5"
hexmask.long.byte 0x00 24.--30. 1. " DXREFISELR3            ,Byte Lane internal VREF Select for Rank 3"
hexmask.long.byte 0x00 16.--22. 1. "        DXREFISELR2         ,Byte Lane internal VREF Select for Rank 2"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFISELR1            ,Byte Lane internal VREF Select for Rank 1"
hexmask.long.byte 0x00 0.--6. 1. "        DXREFISELR0         ,Byte Lane internal VREF Select for Rank 0"
group.long 0x818++0x3
line.long 0x00 "DDRPHY_DX1GCR6,DATX8 n General Configuration Register 6"
bitfld.long 0x00 24.--29. " DXDQVREFR3             ,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DXDQVREFR2          ,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DXDQVREFR1             ,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DXDQVREFR0          ,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x81C++0x3
line.long 0x00 "DDRPHY_DX1GCR7,DATX8 n General Configuration Register 7"
bitfld.long 0x00 9. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 0.--8. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
group.long 0x820++0x3
line.long 0x00 "DDRPHY_DX1GCR8,DATX8 n General Configuration Register 8"
group.long 0x824++0x3
line.long 0x00 "DDRPHY_DX1GCR9,DATX8 n General Configuration Register 9"
group.long 0x828++0x3
line.long 0x00 "DDRPHY_DX1DQMAP0,DATX8 n DQ/DM Mapping Register 0"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 16.--19. "         DQ4MAP              ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12.--15. " DQ3MAP                 ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        DQ2MAP              ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DQ1MAP                 ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DQ0MAP              ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x82C++0x3
line.long 0x00 "DDRPHY_DX1DQMAP1,DATX8 n DQ/DM Mapping Register 1"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 12.--15. "         DMMAP               ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " DQ7MAP                 ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DQ6MAP              ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQ5MAP                 ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x840++0x3
line.long 0x00 "DDRPHY_DX1BDLR0,DATX8 n Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " DQ3WBD                 ,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2WBD              ,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1WBD                 ,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0WBD              ,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x844++0x3
line.long 0x00 "DDRPHY_DX1BDLR1,DATX8 n Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " DQ7WBD                 ,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6WBD              ,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5WBD                 ,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4WBD              ,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x848++0x3
line.long 0x00 "DDRPHY_DX1BDLR2,DATX8 n Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " DSNWBD                 ,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DSOEBD              ,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DSWBD                  ,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DMWBD               ,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x850++0x3
line.long 0x00 "DDRPHY_DX1BDLR3,DATX8 n Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " DQ3RBD                 ,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2RBD              ,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1RBD                 ,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0RBD              ,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x854++0x3
line.long 0x00 "DDRPHY_DX1BDLR4,DATX8 n Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " DQ7RBD                 ,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6RBD              ,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5RBD                 ,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4RBD              ,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x858++0x3
line.long 0x00 "DDRPHY_DX1BDLR5,DATX8 n Bit Delay Line Register 5"
bitfld.long 0x00 0.--5. " DMRBD                  ,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x860++0x3
line.long 0x00 "DDRPHY_DX1BDLR6,DATX8 n Bit Delay Line Register 6"
bitfld.long 0x00 16.--21. " TERBD                  ,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        PDRBD               ,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x864++0x3
line.long 0x00 "DDRPHY_DX1BDLR7,DATX8 n Bit Delay Line Register 7"
group.long 0x868++0x3
line.long 0x00 "DDRPHY_DX1BDLR8,DATX8 n Bit Delay Line Register 8"
group.long 0x86C++0x3
line.long 0x00 "DDRPHY_DX1BDLR9,DATX8 n Bit Delay Line Register 9"
group.long 0x880++0x3
line.long 0x00 "DDRPHY_DX1LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
hexmask.long.word 0x00 0.--8. 1. " WLD                    ,Write Leveling Delay"
group.long 0x884++0x3
line.long 0x00 "DDRPHY_DX1LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " WDQD                   ,Write Data Delay"
group.long 0x888++0x3
line.long 0x00 "DDRPHY_DX1LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
hexmask.long.word 0x00 0.--8. 1. " DQSGD                  ,Read DQS Gating Delay"
group.long 0x88C++0x3
line.long 0x00 "DDRPHY_DX1LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
hexmask.long.word 0x00 0.--8. 1. " RDQSD                  ,Read DQS Delay"
group.long 0x890++0x3
line.long 0x00 "DDRPHY_DX1LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
hexmask.long.word 0x00 0.--8. 1. " RDQSND                 ,Read DQSN Delay"
group.long 0x894++0x3
line.long 0x00 "DDRPHY_DX1LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
hexmask.long.word 0x00 0.--8. 1. " DQSGSD                 ,DQS Gating Status Delay"
group.long 0x8A0++0x3
line.long 0x00 "DDRPHY_DX1MDLR0,DATX8 n Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0x8A4++0x3
line.long 0x00 "DDRPHY_DX1MDLR1,DATX8 n Master Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " MDLD                   ,MDL Delay"
group.long 0x8C0++0x3
line.long 0x00 "DDRPHY_DX1GTR0,DATX8 n General Timing Register 0"
bitfld.long 0x00 24.--26. " WDQSL                  ,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         WLSL                ,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--4. " DGSL                   ,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x8D0++0x3
line.long 0x00 "DDRPHY_DX1RSR0,DATX8 n Rank Status Register 0"
hexmask.long.word 0x00 0.--15. 1. " QSGERR                 ,DQS Gate Training Error"
rgroup.long 0x8D4++0x3
line.long 0x00 "DDRPHY_DX1RSR1,DATX8 n Rank Status Register 1"
hexmask.long.word 0x00 0.--15. 1. " RDLVLERR               ,Read Leveling Error"
rgroup.long 0x8D8++0x3
line.long 0x00 "DDRPHY_DX1RSR2,DATX8 n Rank Status Register 2"
hexmask.long.word 0x00 0.--15. 1. " WLAWN                  ,Write Latency Adjustment (DQS off on some DQ lines) Warning"
rgroup.long 0x8DC++0x3
line.long 0x00 "DDRPHY_DX1RSR3,DATX8 n Rank Status Register 3"
hexmask.long.word 0x00 0.--15. 1. " WLAERR                 ,Write Leveling Adjustment Error"
rgroup.long 0x8E0++0x3
line.long 0x00 "DDRPHY_DX1GSR0,DATX8 n General Status Register 0"
bitfld.long 0x00 30. " WLDQ                   ,Write Leveling DQ Status" "0,1"
hexmask.long.word 0x00 17.--25. 1. "         GDQSPRD             ,Read DQS gating Period"
textline "                              "
bitfld.long 0x00 16. " DPLOCK                 ,DATX8 PLL Lock" "0,1"
hexmask.long.word 0x00 7.--15. 1. "         WLPRD               ,Write Leveling Period"
textline "                              "
bitfld.long 0x00 6. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 5. "         WLDONE              ,Write Leveling Done" "0,1"
textline "                              "
bitfld.long 0x00 4. " WLCAL                  ,Write Leveling Calibration" "0,1"
bitfld.long 0x00 3. "         GDQSCAL             ,Read DQS gating Calibration" "0,1"
textline "                              "
bitfld.long 0x00 2. " RDQSNCAL               ,Read DQS# Calibration" "0,1"
bitfld.long 0x00 1. "         RDQSCAL             ,Read DQS Calibration" "0,1"
textline "                              "
bitfld.long 0x00 0. " WDQCAL                 ,Write DQ Calibration" "0,1"
rgroup.long 0x8E4++0x3
line.long 0x00 "DDRPHY_DX1GSR1,DATX8 n General Status Register 1"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done" "0,1"
rgroup.long 0x8E8++0x3
line.long 0x00 "DDRPHY_DX1GSR2,DATX8 n General Status Register 2"
hexmask.long.word 0x00 23.--31. 1. " GSDQSPRD               ,Read DQS gating Status Period"
bitfld.long 0x00 22. "      GSDQSCAL            ,Read DQS Gating Status Calibration" "0,1"
textline "                              "
bitfld.long 0x00 20. " SRDERR                 ,Static Read Error" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "         DQS2DQERR           ,Write DQS2DQ Training Error"
textline "                              "
bitfld.long 0x00 8.--11. " ESTAT                  ,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        WEWN                ,Write Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 6. " WEERR                  ,Write Eye Centering Error" "0,1"
bitfld.long 0x00 5. "         REWN                ,Read Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 4. " REERR                  ,Read Eye Centering Error" "0,1"
bitfld.long 0x00 3. "         WDWN                ,Write Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 2. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 1. "         RDWN                ,Read Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 0. " RDERR                  ,Read Bit Deskew Error" "0,1"
rgroup.long 0x8EC++0x3
line.long 0x00 "DDRPHY_DX1GSR3,DATX8 n General Status Register 3"
bitfld.long 0x00 24.--26. " ESTAT                  ,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         DVWRN               ,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " DVERR                  ,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        HVWRN               ,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " HVERR                  ,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        SRDPC               ,Static Read Delay Pass Count" "0,1,2,3"
group.long 0x8F0++0x3
line.long 0x00 "DDRPHY_DX1GSR4,DATX8 n General Status Register 4"
group.long 0x8F4++0x3
line.long 0x00 "DDRPHY_DX1GSR5,DATX8 n General Status Register 5"
rgroup.long 0x8F8++0x3
line.long 0x00 "DDRPHY_DX1GSR6,DATX8 n General Status Register 6"
hexmask.long.byte 0x00 24.--31. 1. " DBDQ                   ,Capture DB DQ[7:0], bits [31:28] is for DQ[[7:4] for upper nibble, bits [27:24] is for DQ[3:0] for lower nibble."
group.long 0x900++0x3
line.long 0x00 "DDRPHY_DX2GCR0,DATX8 n General Configuration Register 0"
bitfld.long 0x00 31. " CALBYP                 ,Calibration Bypass" "0,1"
bitfld.long 0x00 30. "         MDLEN               ,Master Delay Line Enable" "0,1"
textline "                              "
bitfld.long 0x00 28.--29. " CODTSHFT               ,Configurable ODT(TE) Phase Shift" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DQSDCC              ,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " RDDLY                  ,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "        DQSNSEPDR           ,DQSNSE Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 12. " DQSSEPDR               ,DQSSE Power Down Receiver" "0,1"
bitfld.long 0x00 11. "         RTTOAL              ,RTT On Additive Latency" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " RTTOH                  ,RTT Output Hold" "0,1,2,3"
bitfld.long 0x00 7.--8. "         CPDRSHFT            ,Configurable PDR Phase Shift" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6. " DQSRPD                 ,DQSR Power Down" "0,1"
bitfld.long 0x00 5. "         DQSGPDR             ,DQSG Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 3. " DQSGODT                ,DQSG On-Die Termination" "0,1"
bitfld.long 0x00 2. "         DQSGOE              ,DQSG Output Enable" "0,1"
group.long 0x904++0x3
line.long 0x00 "DDRPHY_DX2GCR1,DATX8 n General Configuration Register 1"
hexmask.long.word 0x00 16.--31. 1. " DXPDRMODE              ,Enables the PDR mode for DQ[7:0]"
bitfld.long 0x00 14. "      QSNSEL              ,Select the delayed or non-delayed read data strobe #" "0,1"
textline "                              "
bitfld.long 0x00 13. " QSSEL                  ,Select the delayed or non-delayed read data strobe" "0,1"
bitfld.long 0x00 12. "         OEEN                ,Enables Read Data Strobe in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 11. " PDREN                  ,Enables PDR in a byte lane" "0,1"
bitfld.long 0x00 10. "         TEEN                ,Enables ODT/TE in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 9. " DSEN                   ,Enables Write Data strobe in a byte lane" "0,1"
bitfld.long 0x00 8. "         DMEN                ,Enables DM pin in a byte lane" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DQEN                   ,Enables DQ corresponding to each bit in a byte"
group.long 0x908++0x3
line.long 0x00 "DDRPHY_DX2GCR2,DATX8 n General Configuration Register 2"
hexmask.long.word 0x00 16.--31. 1. " DXOEMODE               ,Enables the OE mode values for DQ[7:0]"
hexmask.long.word 0x00 0.--15. 1. "      DXTEMODE            ,Enables the TE (ODT) mode values for DQ[7:0]"
group.long 0x90C++0x3
line.long 0x00 "DDRPHY_DX2GCR3,DATX8 n General Configuration Register 3"
bitfld.long 0x00 31. " OEBVT                  ,Output Enable BDL VT Compensation" "0,1"
bitfld.long 0x00 30. "         TEBVT               ,Termination Enable BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 29. " RDBVT                  ,Read Data BDL VT Compensation" "0,1"
bitfld.long 0x00 28. "         WDBVT               ,Write Data BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 27. " RGLVT                  ,Read DQS Gating LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 26. "         RDLVT               ,Read DQS LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDLVT                  ,Write DQ LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 24. "         WLLVT               ,Write Leveling LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 23. " RGSLVT                 ,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 22. "         PDRBVT              ,Power Down Receiver BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DSNOEMODE              ,Enables the OE mode for DQs" "0,1,2,3"
bitfld.long 0x00 18.--19. "         DSNTEMODE           ,Enables the TE mode for DQS" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--17. " DSNPDRMODE             ,Enables the PDR mode for DQS" "0,1,2,3"
bitfld.long 0x00 14.--15. "         DMOEMODE            ,Enables the OE mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DMTEMODE               ,Enables the TE mode values for DM." "0,1,2,3"
bitfld.long 0x00 10.--11. "         DMPDRMODE           ,Enables the PDR mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " WDSBVT                 ,Write Data Strobe BDL VT Compensation" "0,1"
bitfld.long 0x00 6.--7. "         DSOEMODE            ,Enables the OE mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--5. " DSTEMODE               ,Enables the TE mode values for DQS." "0,1,2,3"
bitfld.long 0x00 2.--3. "         DSPDRMODE           ,Enables the PDR mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " RDMBVT                 ,Read Data Mask BDL VT Compensation" "0,1"
bitfld.long 0x00 0. "         WDMBVT              ,Write Data Mask BDL VT Compensation" "0,1"
group.long 0x910++0x3
line.long 0x00 "DDRPHY_DX2GCR4,DATX8 n General Configuration Register 4"
bitfld.long 0x00 28. " DXREFPEN               ,Byte Lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         DXREFEEN            ,Byte Lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " DXREFSEN               ,Byte Lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 23. "         DXREFESELRANGE      ,External VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--22. 1. " DXREFESEL              ,Byte Lane External VREF Select"
bitfld.long 0x00 15. "        DXREFSSELRANGE      ,Single ended VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFSSEL              ,Byte Lane Single-End VREF Select"
bitfld.long 0x00 2.--5. "        DXREFIEN            ,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--1. " DXREFIMON              ,VRMON control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3"
group.long 0x914++0x3
line.long 0x00 "DDRPHY_DX2GCR5,DATX8 n General Configuration Register 5"
hexmask.long.byte 0x00 24.--30. 1. " DXREFISELR3            ,Byte Lane internal VREF Select for Rank 3"
hexmask.long.byte 0x00 16.--22. 1. "        DXREFISELR2         ,Byte Lane internal VREF Select for Rank 2"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFISELR1            ,Byte Lane internal VREF Select for Rank 1"
hexmask.long.byte 0x00 0.--6. 1. "        DXREFISELR0         ,Byte Lane internal VREF Select for Rank 0"
group.long 0x918++0x3
line.long 0x00 "DDRPHY_DX2GCR6,DATX8 n General Configuration Register 6"
bitfld.long 0x00 24.--29. " DXDQVREFR3             ,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DXDQVREFR2          ,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DXDQVREFR1             ,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DXDQVREFR0          ,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x91C++0x3
line.long 0x00 "DDRPHY_DX2GCR7,DATX8 n General Configuration Register 7"
bitfld.long 0x00 9. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 0.--8. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
group.long 0x920++0x3
line.long 0x00 "DDRPHY_DX2GCR8,DATX8 n General Configuration Register 8"
group.long 0x924++0x3
line.long 0x00 "DDRPHY_DX2GCR9,DATX8 n General Configuration Register 9"
group.long 0x928++0x3
line.long 0x00 "DDRPHY_DX2DQMAP0,DATX8 n DQ/DM Mapping Register 0"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 16.--19. "         DQ4MAP              ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12.--15. " DQ3MAP                 ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        DQ2MAP              ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DQ1MAP                 ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DQ0MAP              ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x92C++0x3
line.long 0x00 "DDRPHY_DX2DQMAP1,DATX8 n DQ/DM Mapping Register 1"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 12.--15. "         DMMAP               ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " DQ7MAP                 ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DQ6MAP              ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQ5MAP                 ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x940++0x3
line.long 0x00 "DDRPHY_DX2BDLR0,DATX8 n Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " DQ3WBD                 ,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2WBD              ,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1WBD                 ,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0WBD              ,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x944++0x3
line.long 0x00 "DDRPHY_DX2BDLR1,DATX8 n Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " DQ7WBD                 ,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6WBD              ,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5WBD                 ,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4WBD              ,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x948++0x3
line.long 0x00 "DDRPHY_DX2BDLR2,DATX8 n Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " DSNWBD                 ,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DSOEBD              ,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DSWBD                  ,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DMWBD               ,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x950++0x3
line.long 0x00 "DDRPHY_DX2BDLR3,DATX8 n Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " DQ3RBD                 ,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2RBD              ,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1RBD                 ,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0RBD              ,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x954++0x3
line.long 0x00 "DDRPHY_DX2BDLR4,DATX8 n Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " DQ7RBD                 ,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6RBD              ,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5RBD                 ,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4RBD              ,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x958++0x3
line.long 0x00 "DDRPHY_DX2BDLR5,DATX8 n Bit Delay Line Register 5"
bitfld.long 0x00 0.--5. " DMRBD                  ,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x960++0x3
line.long 0x00 "DDRPHY_DX2BDLR6,DATX8 n Bit Delay Line Register 6"
bitfld.long 0x00 16.--21. " TERBD                  ,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        PDRBD               ,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x964++0x3
line.long 0x00 "DDRPHY_DX2BDLR7,DATX8 n Bit Delay Line Register 7"
group.long 0x968++0x3
line.long 0x00 "DDRPHY_DX2BDLR8,DATX8 n Bit Delay Line Register 8"
group.long 0x96C++0x3
line.long 0x00 "DDRPHY_DX2BDLR9,DATX8 n Bit Delay Line Register 9"
group.long 0x980++0x3
line.long 0x00 "DDRPHY_DX2LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
hexmask.long.word 0x00 0.--8. 1. " WLD                    ,Write Leveling Delay"
group.long 0x984++0x3
line.long 0x00 "DDRPHY_DX2LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " WDQD                   ,Write Data Delay"
group.long 0x988++0x3
line.long 0x00 "DDRPHY_DX2LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
hexmask.long.word 0x00 0.--8. 1. " DQSGD                  ,Read DQS Gating Delay"
group.long 0x98C++0x3
line.long 0x00 "DDRPHY_DX2LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
hexmask.long.word 0x00 0.--8. 1. " RDQSD                  ,Read DQS Delay"
group.long 0x990++0x3
line.long 0x00 "DDRPHY_DX2LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
hexmask.long.word 0x00 0.--8. 1. " RDQSND                 ,Read DQSN Delay"
group.long 0x994++0x3
line.long 0x00 "DDRPHY_DX2LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
hexmask.long.word 0x00 0.--8. 1. " DQSGSD                 ,DQS Gating Status Delay"
group.long 0x9A0++0x3
line.long 0x00 "DDRPHY_DX2MDLR0,DATX8 n Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0x9A4++0x3
line.long 0x00 "DDRPHY_DX2MDLR1,DATX8 n Master Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " MDLD                   ,MDL Delay"
group.long 0x9C0++0x3
line.long 0x00 "DDRPHY_DX2GTR0,DATX8 n General Timing Register 0"
bitfld.long 0x00 24.--26. " WDQSL                  ,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         WLSL                ,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--4. " DGSL                   ,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x9D0++0x3
line.long 0x00 "DDRPHY_DX2RSR0,DATX8 n Rank Status Register 0"
hexmask.long.word 0x00 0.--15. 1. " QSGERR                 ,DQS Gate Training Error"
rgroup.long 0x9D4++0x3
line.long 0x00 "DDRPHY_DX2RSR1,DATX8 n Rank Status Register 1"
hexmask.long.word 0x00 0.--15. 1. " RDLVLERR               ,Read Leveling Error"
rgroup.long 0x9D8++0x3
line.long 0x00 "DDRPHY_DX2RSR2,DATX8 n Rank Status Register 2"
hexmask.long.word 0x00 0.--15. 1. " WLAWN                  ,Write Latency Adjustment (DQS off on some DQ lines) Warning"
rgroup.long 0x9DC++0x3
line.long 0x00 "DDRPHY_DX2RSR3,DATX8 n Rank Status Register 3"
hexmask.long.word 0x00 0.--15. 1. " WLAERR                 ,Write Leveling Adjustment Error"
rgroup.long 0x9E0++0x3
line.long 0x00 "DDRPHY_DX2GSR0,DATX8 n General Status Register 0"
bitfld.long 0x00 30. " WLDQ                   ,Write Leveling DQ Status" "0,1"
hexmask.long.word 0x00 17.--25. 1. "         GDQSPRD             ,Read DQS gating Period"
textline "                              "
bitfld.long 0x00 16. " DPLOCK                 ,DATX8 PLL Lock" "0,1"
hexmask.long.word 0x00 7.--15. 1. "         WLPRD               ,Write Leveling Period"
textline "                              "
bitfld.long 0x00 6. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 5. "         WLDONE              ,Write Leveling Done" "0,1"
textline "                              "
bitfld.long 0x00 4. " WLCAL                  ,Write Leveling Calibration" "0,1"
bitfld.long 0x00 3. "         GDQSCAL             ,Read DQS gating Calibration" "0,1"
textline "                              "
bitfld.long 0x00 2. " RDQSNCAL               ,Read DQS# Calibration" "0,1"
bitfld.long 0x00 1. "         RDQSCAL             ,Read DQS Calibration" "0,1"
textline "                              "
bitfld.long 0x00 0. " WDQCAL                 ,Write DQ Calibration" "0,1"
rgroup.long 0x9E4++0x3
line.long 0x00 "DDRPHY_DX2GSR1,DATX8 n General Status Register 1"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done" "0,1"
rgroup.long 0x9E8++0x3
line.long 0x00 "DDRPHY_DX2GSR2,DATX8 n General Status Register 2"
hexmask.long.word 0x00 23.--31. 1. " GSDQSPRD               ,Read DQS gating Status Period"
bitfld.long 0x00 22. "      GSDQSCAL            ,Read DQS Gating Status Calibration" "0,1"
textline "                              "
bitfld.long 0x00 20. " SRDERR                 ,Static Read Error" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "         DQS2DQERR           ,Write DQS2DQ Training Error"
textline "                              "
bitfld.long 0x00 8.--11. " ESTAT                  ,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        WEWN                ,Write Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 6. " WEERR                  ,Write Eye Centering Error" "0,1"
bitfld.long 0x00 5. "         REWN                ,Read Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 4. " REERR                  ,Read Eye Centering Error" "0,1"
bitfld.long 0x00 3. "         WDWN                ,Write Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 2. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 1. "         RDWN                ,Read Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 0. " RDERR                  ,Read Bit Deskew Error" "0,1"
rgroup.long 0x9EC++0x3
line.long 0x00 "DDRPHY_DX2GSR3,DATX8 n General Status Register 3"
bitfld.long 0x00 24.--26. " ESTAT                  ,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         DVWRN               ,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " DVERR                  ,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        HVWRN               ,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " HVERR                  ,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        SRDPC               ,Static Read Delay Pass Count" "0,1,2,3"
group.long 0x9F0++0x3
line.long 0x00 "DDRPHY_DX2GSR4,DATX8 n General Status Register 4"
group.long 0x9F4++0x3
line.long 0x00 "DDRPHY_DX2GSR5,DATX8 n General Status Register 5"
rgroup.long 0x9F8++0x3
line.long 0x00 "DDRPHY_DX2GSR6,DATX8 n General Status Register 6"
hexmask.long.byte 0x00 24.--31. 1. " DBDQ                   ,Capture DB DQ[7:0], bits [31:28] is for DQ[[7:4] for upper nibble, bits [27:24] is for DQ[3:0] for lower nibble."
group.long 0xA00++0x3
line.long 0x00 "DDRPHY_DX3GCR0,DATX8 n General Configuration Register 0"
bitfld.long 0x00 31. " CALBYP                 ,Calibration Bypass" "0,1"
bitfld.long 0x00 30. "         MDLEN               ,Master Delay Line Enable" "0,1"
textline "                              "
bitfld.long 0x00 28.--29. " CODTSHFT               ,Configurable ODT(TE) Phase Shift" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DQSDCC              ,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " RDDLY                  ,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "        DQSNSEPDR           ,DQSNSE Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 12. " DQSSEPDR               ,DQSSE Power Down Receiver" "0,1"
bitfld.long 0x00 11. "         RTTOAL              ,RTT On Additive Latency" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " RTTOH                  ,RTT Output Hold" "0,1,2,3"
bitfld.long 0x00 7.--8. "         CPDRSHFT            ,Configurable PDR Phase Shift" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6. " DQSRPD                 ,DQSR Power Down" "0,1"
bitfld.long 0x00 5. "         DQSGPDR             ,DQSG Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 3. " DQSGODT                ,DQSG On-Die Termination" "0,1"
bitfld.long 0x00 2. "         DQSGOE              ,DQSG Output Enable" "0,1"
group.long 0xA04++0x3
line.long 0x00 "DDRPHY_DX3GCR1,DATX8 n General Configuration Register 1"
hexmask.long.word 0x00 16.--31. 1. " DXPDRMODE              ,Enables the PDR mode for DQ[7:0]"
bitfld.long 0x00 14. "      QSNSEL              ,Select the delayed or non-delayed read data strobe #" "0,1"
textline "                              "
bitfld.long 0x00 13. " QSSEL                  ,Select the delayed or non-delayed read data strobe" "0,1"
bitfld.long 0x00 12. "         OEEN                ,Enables Read Data Strobe in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 11. " PDREN                  ,Enables PDR in a byte lane" "0,1"
bitfld.long 0x00 10. "         TEEN                ,Enables ODT/TE in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 9. " DSEN                   ,Enables Write Data strobe in a byte lane" "0,1"
bitfld.long 0x00 8. "         DMEN                ,Enables DM pin in a byte lane" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DQEN                   ,Enables DQ corresponding to each bit in a byte"
group.long 0xA08++0x3
line.long 0x00 "DDRPHY_DX3GCR2,DATX8 n General Configuration Register 2"
hexmask.long.word 0x00 16.--31. 1. " DXOEMODE               ,Enables the OE mode values for DQ[7:0]"
hexmask.long.word 0x00 0.--15. 1. "      DXTEMODE            ,Enables the TE (ODT) mode values for DQ[7:0]"
group.long 0xA0C++0x3
line.long 0x00 "DDRPHY_DX3GCR3,DATX8 n General Configuration Register 3"
bitfld.long 0x00 31. " OEBVT                  ,Output Enable BDL VT Compensation" "0,1"
bitfld.long 0x00 30. "         TEBVT               ,Termination Enable BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 29. " RDBVT                  ,Read Data BDL VT Compensation" "0,1"
bitfld.long 0x00 28. "         WDBVT               ,Write Data BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 27. " RGLVT                  ,Read DQS Gating LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 26. "         RDLVT               ,Read DQS LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDLVT                  ,Write DQ LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 24. "         WLLVT               ,Write Leveling LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 23. " RGSLVT                 ,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 22. "         PDRBVT              ,Power Down Receiver BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DSNOEMODE              ,Enables the OE mode for DQs" "0,1,2,3"
bitfld.long 0x00 18.--19. "         DSNTEMODE           ,Enables the TE mode for DQS" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--17. " DSNPDRMODE             ,Enables the PDR mode for DQS" "0,1,2,3"
bitfld.long 0x00 14.--15. "         DMOEMODE            ,Enables the OE mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DMTEMODE               ,Enables the TE mode values for DM." "0,1,2,3"
bitfld.long 0x00 10.--11. "         DMPDRMODE           ,Enables the PDR mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " WDSBVT                 ,Write Data Strobe BDL VT Compensation" "0,1"
bitfld.long 0x00 6.--7. "         DSOEMODE            ,Enables the OE mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--5. " DSTEMODE               ,Enables the TE mode values for DQS." "0,1,2,3"
bitfld.long 0x00 2.--3. "         DSPDRMODE           ,Enables the PDR mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " RDMBVT                 ,Read Data Mask BDL VT Compensation" "0,1"
bitfld.long 0x00 0. "         WDMBVT              ,Write Data Mask BDL VT Compensation" "0,1"
group.long 0xA10++0x3
line.long 0x00 "DDRPHY_DX3GCR4,DATX8 n General Configuration Register 4"
bitfld.long 0x00 28. " DXREFPEN               ,Byte Lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         DXREFEEN            ,Byte Lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " DXREFSEN               ,Byte Lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 23. "         DXREFESELRANGE      ,External VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--22. 1. " DXREFESEL              ,Byte Lane External VREF Select"
bitfld.long 0x00 15. "        DXREFSSELRANGE      ,Single ended VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFSSEL              ,Byte Lane Single-End VREF Select"
bitfld.long 0x00 2.--5. "        DXREFIEN            ,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--1. " DXREFIMON              ,VRMON control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3"
group.long 0xA14++0x3
line.long 0x00 "DDRPHY_DX3GCR5,DATX8 n General Configuration Register 5"
hexmask.long.byte 0x00 24.--30. 1. " DXREFISELR3            ,Byte Lane internal VREF Select for Rank 3"
hexmask.long.byte 0x00 16.--22. 1. "        DXREFISELR2         ,Byte Lane internal VREF Select for Rank 2"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFISELR1            ,Byte Lane internal VREF Select for Rank 1"
hexmask.long.byte 0x00 0.--6. 1. "        DXREFISELR0         ,Byte Lane internal VREF Select for Rank 0"
group.long 0xA18++0x3
line.long 0x00 "DDRPHY_DX3GCR6,DATX8 n General Configuration Register 6"
bitfld.long 0x00 24.--29. " DXDQVREFR3             ,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DXDQVREFR2          ,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DXDQVREFR1             ,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DXDQVREFR0          ,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA1C++0x3
line.long 0x00 "DDRPHY_DX3GCR7,DATX8 n General Configuration Register 7"
bitfld.long 0x00 9. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 0.--8. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
group.long 0xA20++0x3
line.long 0x00 "DDRPHY_DX3GCR8,DATX8 n General Configuration Register 8"
group.long 0xA24++0x3
line.long 0x00 "DDRPHY_DX3GCR9,DATX8 n General Configuration Register 9"
group.long 0xA28++0x3
line.long 0x00 "DDRPHY_DX3DQMAP0,DATX8 n DQ/DM Mapping Register 0"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 16.--19. "         DQ4MAP              ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12.--15. " DQ3MAP                 ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        DQ2MAP              ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DQ1MAP                 ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DQ0MAP              ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA2C++0x3
line.long 0x00 "DDRPHY_DX3DQMAP1,DATX8 n DQ/DM Mapping Register 1"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 12.--15. "         DMMAP               ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " DQ7MAP                 ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DQ6MAP              ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQ5MAP                 ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA40++0x3
line.long 0x00 "DDRPHY_DX3BDLR0,DATX8 n Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " DQ3WBD                 ,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2WBD              ,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1WBD                 ,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0WBD              ,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA44++0x3
line.long 0x00 "DDRPHY_DX3BDLR1,DATX8 n Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " DQ7WBD                 ,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6WBD              ,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5WBD                 ,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4WBD              ,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA48++0x3
line.long 0x00 "DDRPHY_DX3BDLR2,DATX8 n Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " DSNWBD                 ,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DSOEBD              ,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DSWBD                  ,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DMWBD               ,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA50++0x3
line.long 0x00 "DDRPHY_DX3BDLR3,DATX8 n Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " DQ3RBD                 ,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2RBD              ,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1RBD                 ,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0RBD              ,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA54++0x3
line.long 0x00 "DDRPHY_DX3BDLR4,DATX8 n Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " DQ7RBD                 ,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6RBD              ,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5RBD                 ,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4RBD              ,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA58++0x3
line.long 0x00 "DDRPHY_DX3BDLR5,DATX8 n Bit Delay Line Register 5"
bitfld.long 0x00 0.--5. " DMRBD                  ,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA60++0x3
line.long 0x00 "DDRPHY_DX3BDLR6,DATX8 n Bit Delay Line Register 6"
bitfld.long 0x00 16.--21. " TERBD                  ,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        PDRBD               ,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA64++0x3
line.long 0x00 "DDRPHY_DX3BDLR7,DATX8 n Bit Delay Line Register 7"
group.long 0xA68++0x3
line.long 0x00 "DDRPHY_DX3BDLR8,DATX8 n Bit Delay Line Register 8"
group.long 0xA6C++0x3
line.long 0x00 "DDRPHY_DX3BDLR9,DATX8 n Bit Delay Line Register 9"
group.long 0xA80++0x3
line.long 0x00 "DDRPHY_DX3LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
hexmask.long.word 0x00 0.--8. 1. " WLD                    ,Write Leveling Delay"
group.long 0xA84++0x3
line.long 0x00 "DDRPHY_DX3LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " WDQD                   ,Write Data Delay"
group.long 0xA88++0x3
line.long 0x00 "DDRPHY_DX3LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
hexmask.long.word 0x00 0.--8. 1. " DQSGD                  ,Read DQS Gating Delay"
group.long 0xA8C++0x3
line.long 0x00 "DDRPHY_DX3LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
hexmask.long.word 0x00 0.--8. 1. " RDQSD                  ,Read DQS Delay"
group.long 0xA90++0x3
line.long 0x00 "DDRPHY_DX3LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
hexmask.long.word 0x00 0.--8. 1. " RDQSND                 ,Read DQSN Delay"
group.long 0xA94++0x3
line.long 0x00 "DDRPHY_DX3LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
hexmask.long.word 0x00 0.--8. 1. " DQSGSD                 ,DQS Gating Status Delay"
group.long 0xAA0++0x3
line.long 0x00 "DDRPHY_DX3MDLR0,DATX8 n Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0xAA4++0x3
line.long 0x00 "DDRPHY_DX3MDLR1,DATX8 n Master Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " MDLD                   ,MDL Delay"
group.long 0xAC0++0x3
line.long 0x00 "DDRPHY_DX3GTR0,DATX8 n General Timing Register 0"
bitfld.long 0x00 24.--26. " WDQSL                  ,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         WLSL                ,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--4. " DGSL                   ,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xAD0++0x3
line.long 0x00 "DDRPHY_DX3RSR0,DATX8 n Rank Status Register 0"
hexmask.long.word 0x00 0.--15. 1. " QSGERR                 ,DQS Gate Training Error"
rgroup.long 0xAD4++0x3
line.long 0x00 "DDRPHY_DX3RSR1,DATX8 n Rank Status Register 1"
hexmask.long.word 0x00 0.--15. 1. " RDLVLERR               ,Read Leveling Error"
rgroup.long 0xAD8++0x3
line.long 0x00 "DDRPHY_DX3RSR2,DATX8 n Rank Status Register 2"
hexmask.long.word 0x00 0.--15. 1. " WLAWN                  ,Write Latency Adjustment (DQS off on some DQ lines) Warning"
rgroup.long 0xADC++0x3
line.long 0x00 "DDRPHY_DX3RSR3,DATX8 n Rank Status Register 3"
hexmask.long.word 0x00 0.--15. 1. " WLAERR                 ,Write Leveling Adjustment Error"
rgroup.long 0xAE0++0x3
line.long 0x00 "DDRPHY_DX3GSR0,DATX8 n General Status Register 0"
bitfld.long 0x00 30. " WLDQ                   ,Write Leveling DQ Status" "0,1"
hexmask.long.word 0x00 17.--25. 1. "         GDQSPRD             ,Read DQS gating Period"
textline "                              "
bitfld.long 0x00 16. " DPLOCK                 ,DATX8 PLL Lock" "0,1"
hexmask.long.word 0x00 7.--15. 1. "         WLPRD               ,Write Leveling Period"
textline "                              "
bitfld.long 0x00 6. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 5. "         WLDONE              ,Write Leveling Done" "0,1"
textline "                              "
bitfld.long 0x00 4. " WLCAL                  ,Write Leveling Calibration" "0,1"
bitfld.long 0x00 3. "         GDQSCAL             ,Read DQS gating Calibration" "0,1"
textline "                              "
bitfld.long 0x00 2. " RDQSNCAL               ,Read DQS# Calibration" "0,1"
bitfld.long 0x00 1. "         RDQSCAL             ,Read DQS Calibration" "0,1"
textline "                              "
bitfld.long 0x00 0. " WDQCAL                 ,Write DQ Calibration" "0,1"
rgroup.long 0xAE4++0x3
line.long 0x00 "DDRPHY_DX3GSR1,DATX8 n General Status Register 1"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done" "0,1"
rgroup.long 0xAE8++0x3
line.long 0x00 "DDRPHY_DX3GSR2,DATX8 n General Status Register 2"
hexmask.long.word 0x00 23.--31. 1. " GSDQSPRD               ,Read DQS gating Status Period"
bitfld.long 0x00 22. "      GSDQSCAL            ,Read DQS Gating Status Calibration" "0,1"
textline "                              "
bitfld.long 0x00 20. " SRDERR                 ,Static Read Error" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "         DQS2DQERR           ,Write DQS2DQ Training Error"
textline "                              "
bitfld.long 0x00 8.--11. " ESTAT                  ,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        WEWN                ,Write Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 6. " WEERR                  ,Write Eye Centering Error" "0,1"
bitfld.long 0x00 5. "         REWN                ,Read Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 4. " REERR                  ,Read Eye Centering Error" "0,1"
bitfld.long 0x00 3. "         WDWN                ,Write Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 2. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 1. "         RDWN                ,Read Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 0. " RDERR                  ,Read Bit Deskew Error" "0,1"
rgroup.long 0xAEC++0x3
line.long 0x00 "DDRPHY_DX3GSR3,DATX8 n General Status Register 3"
bitfld.long 0x00 24.--26. " ESTAT                  ,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         DVWRN               ,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " DVERR                  ,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        HVWRN               ,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " HVERR                  ,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        SRDPC               ,Static Read Delay Pass Count" "0,1,2,3"
group.long 0xAF0++0x3
line.long 0x00 "DDRPHY_DX3GSR4,DATX8 n General Status Register 4"
group.long 0xAF4++0x3
line.long 0x00 "DDRPHY_DX3GSR5,DATX8 n General Status Register 5"
rgroup.long 0xAF8++0x3
line.long 0x00 "DDRPHY_DX3GSR6,DATX8 n General Status Register 6"
hexmask.long.byte 0x00 24.--31. 1. " DBDQ                   ,Capture DB DQ[7:0], bits [31:28] is for DQ[[7:4] for upper nibble, bits [27:24] is for DQ[3:0] for lower nibble."
group.long 0xB00++0x3
line.long 0x00 "DDRPHY_DX4GCR0,DATX8 n General Configuration Register 0"
bitfld.long 0x00 31. " CALBYP                 ,Calibration Bypass" "0,1"
bitfld.long 0x00 30. "         MDLEN               ,Master Delay Line Enable" "0,1"
textline "                              "
bitfld.long 0x00 28.--29. " CODTSHFT               ,Configurable ODT(TE) Phase Shift" "0,1,2,3"
bitfld.long 0x00 24.--27. "         DQSDCC              ,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 20.--23. " RDDLY                  ,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "        DQSNSEPDR           ,DQSNSE Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 12. " DQSSEPDR               ,DQSSE Power Down Receiver" "0,1"
bitfld.long 0x00 11. "         RTTOAL              ,RTT On Additive Latency" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " RTTOH                  ,RTT Output Hold" "0,1,2,3"
bitfld.long 0x00 7.--8. "         CPDRSHFT            ,Configurable PDR Phase Shift" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6. " DQSRPD                 ,DQSR Power Down" "0,1"
bitfld.long 0x00 5. "         DQSGPDR             ,DQSG Power Down Receiver" "0,1"
textline "                              "
bitfld.long 0x00 3. " DQSGODT                ,DQSG On-Die Termination" "0,1"
bitfld.long 0x00 2. "         DQSGOE              ,DQSG Output Enable" "0,1"
group.long 0xB04++0x3
line.long 0x00 "DDRPHY_DX4GCR1,DATX8 n General Configuration Register 1"
hexmask.long.word 0x00 16.--31. 1. " DXPDRMODE              ,Enables the PDR mode for DQ[7:0]"
bitfld.long 0x00 14. "      QSNSEL              ,Select the delayed or non-delayed read data strobe #" "0,1"
textline "                              "
bitfld.long 0x00 13. " QSSEL                  ,Select the delayed or non-delayed read data strobe" "0,1"
bitfld.long 0x00 12. "         OEEN                ,Enables Read Data Strobe in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 11. " PDREN                  ,Enables PDR in a byte lane" "0,1"
bitfld.long 0x00 10. "         TEEN                ,Enables ODT/TE in a byte lane" "0,1"
textline "                              "
bitfld.long 0x00 9. " DSEN                   ,Enables Write Data strobe in a byte lane" "0,1"
bitfld.long 0x00 8. "         DMEN                ,Enables DM pin in a byte lane" "0,1"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " DQEN                   ,Enables DQ corresponding to each bit in a byte"
group.long 0xB08++0x3
line.long 0x00 "DDRPHY_DX4GCR2,DATX8 n General Configuration Register 2"
hexmask.long.word 0x00 16.--31. 1. " DXOEMODE               ,Enables the OE mode values for DQ[7:0]"
hexmask.long.word 0x00 0.--15. 1. "      DXTEMODE            ,Enables the TE (ODT) mode values for DQ[7:0]"
group.long 0xB0C++0x3
line.long 0x00 "DDRPHY_DX4GCR3,DATX8 n General Configuration Register 3"
bitfld.long 0x00 31. " OEBVT                  ,Output Enable BDL VT Compensation" "0,1"
bitfld.long 0x00 30. "         TEBVT               ,Termination Enable BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 29. " RDBVT                  ,Read Data BDL VT Compensation" "0,1"
bitfld.long 0x00 28. "         WDBVT               ,Write Data BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 27. " RGLVT                  ,Read DQS Gating LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 26. "         RDLVT               ,Read DQS LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 25. " WDLVT                  ,Write DQ LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 24. "         WLLVT               ,Write Leveling LCDL Delay VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 23. " RGSLVT                 ,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
bitfld.long 0x00 22. "         PDRBVT              ,Power Down Receiver BDL VT Compensation" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DSNOEMODE              ,Enables the OE mode for DQs" "0,1,2,3"
bitfld.long 0x00 18.--19. "         DSNTEMODE           ,Enables the TE mode for DQS" "0,1,2,3"
textline "                              "
bitfld.long 0x00 16.--17. " DSNPDRMODE             ,Enables the PDR mode for DQS" "0,1,2,3"
bitfld.long 0x00 14.--15. "         DMOEMODE            ,Enables the OE mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 12.--13. " DMTEMODE               ,Enables the TE mode values for DM." "0,1,2,3"
bitfld.long 0x00 10.--11. "         DMPDRMODE           ,Enables the PDR mode values for DM." "0,1,2,3"
textline "                              "
bitfld.long 0x00 8. " WDSBVT                 ,Write Data Strobe BDL VT Compensation" "0,1"
bitfld.long 0x00 6.--7. "         DSOEMODE            ,Enables the OE mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 4.--5. " DSTEMODE               ,Enables the TE mode values for DQS." "0,1,2,3"
bitfld.long 0x00 2.--3. "         DSPDRMODE           ,Enables the PDR mode values for DQS." "0,1,2,3"
textline "                              "
bitfld.long 0x00 1. " RDMBVT                 ,Read Data Mask BDL VT Compensation" "0,1"
bitfld.long 0x00 0. "         WDMBVT              ,Write Data Mask BDL VT Compensation" "0,1"
group.long 0xB10++0x3
line.long 0x00 "DDRPHY_DX4GCR4,DATX8 n General Configuration Register 4"
bitfld.long 0x00 28. " DXREFPEN               ,Byte Lane VREF Pad Enable" "0,1"
bitfld.long 0x00 26.--27. "         DXREFEEN            ,Byte Lane Internal VREF Enable" "0,1,2,3"
textline "                              "
bitfld.long 0x00 25. " DXREFSEN               ,Byte Lane Single-End VREF Enable" "0,1"
bitfld.long 0x00 23. "         DXREFESELRANGE      ,External VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 16.--22. 1. " DXREFESEL              ,Byte Lane External VREF Select"
bitfld.long 0x00 15. "        DXREFSSELRANGE      ,Single ended VREF generator REFSEL range select" "0,1"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFSSEL              ,Byte Lane Single-End VREF Select"
bitfld.long 0x00 2.--5. "        DXREFIEN            ,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--1. " DXREFIMON              ,VRMON control for DQ IO (Single Ended) buffers of a byte lane." "0,1,2,3"
group.long 0xB14++0x3
line.long 0x00 "DDRPHY_DX4GCR5,DATX8 n General Configuration Register 5"
hexmask.long.byte 0x00 24.--30. 1. " DXREFISELR3            ,Byte Lane internal VREF Select for Rank 3"
hexmask.long.byte 0x00 16.--22. 1. "        DXREFISELR2         ,Byte Lane internal VREF Select for Rank 2"
textline "                              "
hexmask.long.byte 0x00 8.--14. 1. " DXREFISELR1            ,Byte Lane internal VREF Select for Rank 1"
hexmask.long.byte 0x00 0.--6. 1. "        DXREFISELR0         ,Byte Lane internal VREF Select for Rank 0"
group.long 0xB18++0x3
line.long 0x00 "DDRPHY_DX4GCR6,DATX8 n General Configuration Register 6"
bitfld.long 0x00 24.--29. " DXDQVREFR3             ,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DXDQVREFR2          ,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DXDQVREFR1             ,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DXDQVREFR0          ,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB1C++0x3
line.long 0x00 "DDRPHY_DX4GCR7,DATX8 n General Configuration Register 7"
bitfld.long 0x00 9. " DCALTYPE               ,DDL Calibration Type" "0,1"
hexmask.long.word 0x00 0.--8. 1. "         DCALSVAL            ,DDL Calibration Starting Value"
group.long 0xB20++0x3
line.long 0x00 "DDRPHY_DX4GCR8,DATX8 n General Configuration Register 8"
group.long 0xB24++0x3
line.long 0x00 "DDRPHY_DX4GCR9,DATX8 n General Configuration Register 9"
group.long 0xB28++0x3
line.long 0x00 "DDRPHY_DX4DQMAP0,DATX8 n DQ/DM Mapping Register 0"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 16.--19. "         DQ4MAP              ,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12.--15. " DQ3MAP                 ,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        DQ2MAP              ,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 4.--7. " DQ1MAP                 ,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DQ0MAP              ,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB2C++0x3
line.long 0x00 "DDRPHY_DX4DQMAP1,DATX8 n DQ/DM Mapping Register 1"
bitfld.long 0x00 31. " MAPOK                  ,Checksum bit" "0,1"
bitfld.long 0x00 12.--15. "         DMMAP               ,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " DQ7MAP                 ,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        DQ6MAP              ,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQ5MAP                 ,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB40++0x3
line.long 0x00 "DDRPHY_DX4BDLR0,DATX8 n Bit Delay Line Register 0"
bitfld.long 0x00 24.--29. " DQ3WBD                 ,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2WBD              ,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1WBD                 ,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0WBD              ,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB44++0x3
line.long 0x00 "DDRPHY_DX4BDLR1,DATX8 n Bit Delay Line Register 1"
bitfld.long 0x00 24.--29. " DQ7WBD                 ,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6WBD              ,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5WBD                 ,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4WBD              ,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB48++0x3
line.long 0x00 "DDRPHY_DX4BDLR2,DATX8 n Bit Delay Line Register 2"
bitfld.long 0x00 24.--29. " DSNWBD                 ,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DSOEBD              ,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DSWBD                  ,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DMWBD               ,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB50++0x3
line.long 0x00 "DDRPHY_DX4BDLR3,DATX8 n Bit Delay Line Register 3"
bitfld.long 0x00 24.--29. " DQ3RBD                 ,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ2RBD              ,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ1RBD                 ,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ0RBD              ,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB54++0x3
line.long 0x00 "DDRPHY_DX4BDLR4,DATX8 n Bit Delay Line Register 4"
bitfld.long 0x00 24.--29. " DQ7RBD                 ,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        DQ6RBD              ,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " DQ5RBD                 ,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        DQ4RBD              ,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB58++0x3
line.long 0x00 "DDRPHY_DX4BDLR5,DATX8 n Bit Delay Line Register 5"
bitfld.long 0x00 0.--5. " DMRBD                  ,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB60++0x3
line.long 0x00 "DDRPHY_DX4BDLR6,DATX8 n Bit Delay Line Register 6"
bitfld.long 0x00 16.--21. " TERBD                  ,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        PDRBD               ,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB64++0x3
line.long 0x00 "DDRPHY_DX4BDLR7,DATX8 n Bit Delay Line Register 7"
group.long 0xB68++0x3
line.long 0x00 "DDRPHY_DX4BDLR8,DATX8 n Bit Delay Line Register 8"
group.long 0xB6C++0x3
line.long 0x00 "DDRPHY_DX4BDLR9,DATX8 n Bit Delay Line Register 9"
group.long 0xB80++0x3
line.long 0x00 "DDRPHY_DX4LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
hexmask.long.word 0x00 0.--8. 1. " WLD                    ,Write Leveling Delay"
group.long 0xB84++0x3
line.long 0x00 "DDRPHY_DX4LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " WDQD                   ,Write Data Delay"
group.long 0xB88++0x3
line.long 0x00 "DDRPHY_DX4LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
hexmask.long.word 0x00 0.--8. 1. " DQSGD                  ,Read DQS Gating Delay"
group.long 0xB8C++0x3
line.long 0x00 "DDRPHY_DX4LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
hexmask.long.word 0x00 0.--8. 1. " RDQSD                  ,Read DQS Delay"
group.long 0xB90++0x3
line.long 0x00 "DDRPHY_DX4LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
hexmask.long.word 0x00 0.--8. 1. " RDQSND                 ,Read DQSN Delay"
group.long 0xB94++0x3
line.long 0x00 "DDRPHY_DX4LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
hexmask.long.word 0x00 0.--8. 1. " DQSGSD                 ,DQS Gating Status Delay"
group.long 0xBA0++0x3
line.long 0x00 "DDRPHY_DX4MDLR0,DATX8 n Master Delay Line Register 0"
hexmask.long.word 0x00 16.--24. 1. " TPRD                   ,Target Period"
hexmask.long.word 0x00 0.--8. 1. "      IPRD                ,Initial Period"
group.long 0xBA4++0x3
line.long 0x00 "DDRPHY_DX4MDLR1,DATX8 n Master Delay Line Register 1"
hexmask.long.word 0x00 0.--8. 1. " MDLD                   ,MDL Delay"
group.long 0xBC0++0x3
line.long 0x00 "DDRPHY_DX4GTR0,DATX8 n General Timing Register 0"
bitfld.long 0x00 24.--26. " WDQSL                  ,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         WLSL                ,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--4. " DGSL                   ,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xBD0++0x3
line.long 0x00 "DDRPHY_DX4RSR0,DATX8 n Rank Status Register 0"
hexmask.long.word 0x00 0.--15. 1. " QSGERR                 ,DQS Gate Training Error"
rgroup.long 0xBD4++0x3
line.long 0x00 "DDRPHY_DX4RSR1,DATX8 n Rank Status Register 1"
hexmask.long.word 0x00 0.--15. 1. " RDLVLERR               ,Read Leveling Error"
rgroup.long 0xBD8++0x3
line.long 0x00 "DDRPHY_DX4RSR2,DATX8 n Rank Status Register 2"
hexmask.long.word 0x00 0.--15. 1. " WLAWN                  ,Write Latency Adjustment (DQS off on some DQ lines) Warning"
rgroup.long 0xBDC++0x3
line.long 0x00 "DDRPHY_DX4RSR3,DATX8 n Rank Status Register 3"
hexmask.long.word 0x00 0.--15. 1. " WLAERR                 ,Write Leveling Adjustment Error"
rgroup.long 0xBE0++0x3
line.long 0x00 "DDRPHY_DX4GSR0,DATX8 n General Status Register 0"
bitfld.long 0x00 30. " WLDQ                   ,Write Leveling DQ Status" "0,1"
hexmask.long.word 0x00 17.--25. 1. "         GDQSPRD             ,Read DQS gating Period"
textline "                              "
bitfld.long 0x00 16. " DPLOCK                 ,DATX8 PLL Lock" "0,1"
hexmask.long.word 0x00 7.--15. 1. "         WLPRD               ,Write Leveling Period"
textline "                              "
bitfld.long 0x00 6. " WLERR                  ,Write Leveling Error" "0,1"
bitfld.long 0x00 5. "         WLDONE              ,Write Leveling Done" "0,1"
textline "                              "
bitfld.long 0x00 4. " WLCAL                  ,Write Leveling Calibration" "0,1"
bitfld.long 0x00 3. "         GDQSCAL             ,Read DQS gating Calibration" "0,1"
textline "                              "
bitfld.long 0x00 2. " RDQSNCAL               ,Read DQS# Calibration" "0,1"
bitfld.long 0x00 1. "         RDQSCAL             ,Read DQS Calibration" "0,1"
textline "                              "
bitfld.long 0x00 0. " WDQCAL                 ,Write DQ Calibration" "0,1"
rgroup.long 0xBE4++0x3
line.long 0x00 "DDRPHY_DX4GSR1,DATX8 n General Status Register 1"
hexmask.long.tbyte 0x00 1.--24. 1. " DLTCODE                ,Delay Line Test Code"
bitfld.long 0x00 0. "    DLTDONE             ,Delay Line Test Done" "0,1"
rgroup.long 0xBE8++0x3
line.long 0x00 "DDRPHY_DX4GSR2,DATX8 n General Status Register 2"
hexmask.long.word 0x00 23.--31. 1. " GSDQSPRD               ,Read DQS gating Status Period"
bitfld.long 0x00 22. "      GSDQSCAL            ,Read DQS Gating Status Calibration" "0,1"
textline "                              "
bitfld.long 0x00 20. " SRDERR                 ,Static Read Error" "0,1"
hexmask.long.byte 0x00 12.--19. 1. "         DQS2DQERR           ,Write DQS2DQ Training Error"
textline "                              "
bitfld.long 0x00 8.--11. " ESTAT                  ,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        WEWN                ,Write Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 6. " WEERR                  ,Write Eye Centering Error" "0,1"
bitfld.long 0x00 5. "         REWN                ,Read Eye Centering Warning" "0,1"
textline "                              "
bitfld.long 0x00 4. " REERR                  ,Read Eye Centering Error" "0,1"
bitfld.long 0x00 3. "         WDWN                ,Write Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 2. " WDERR                  ,Write Bit Deskew Error" "0,1"
bitfld.long 0x00 1. "         RDWN                ,Read Bit Deskew Warning" "0,1"
textline "                              "
bitfld.long 0x00 0. " RDERR                  ,Read Bit Deskew Error" "0,1"
rgroup.long 0xBEC++0x3
line.long 0x00 "DDRPHY_DX4GSR3,DATX8 n General Status Register 3"
bitfld.long 0x00 24.--26. " ESTAT                  ,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         DVWRN               ,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 16.--19. " DVERR                  ,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "        HVWRN               ,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8.--11. " HVERR                  ,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        SRDPC               ,Static Read Delay Pass Count" "0,1,2,3"
group.long 0xBF0++0x3
line.long 0x00 "DDRPHY_DX4GSR4,DATX8 n General Status Register 4"
group.long 0xBF4++0x3
line.long 0x00 "DDRPHY_DX4GSR5,DATX8 n General Status Register 5"
rgroup.long 0xBF8++0x3
line.long 0x00 "DDRPHY_DX4GSR6,DATX8 n General Status Register 6"
hexmask.long.byte 0x00 24.--31. 1. " DBDQ                   ,Capture DB DQ[7:0], bits [31:28] is for DQ[[7:4] for upper nibble, bits [27:24] is for DQ[3:0] for lower nibble."
group.long 0x1434++0x3
line.long 0x00 "DDRPHY_DX4SL0IOCR,DATX4 Slice 0-1 I/O Configuration Register"
hgroup.long 0x1440++0x3
hide.long 0x00 "DDRPHY_DX8SL1OSC,DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register"
in
textline "                              "
group.long 0x1444++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0"
bitfld.long 0x00 31. " PLLBYP                 ,PLL Bypass" "0,1"
bitfld.long 0x00 30. "         PLLRST              ,PLL Reset" "0,1"
textline "                              "
bitfld.long 0x00 29. " PLLPD                  ,PLL Power Down" "0,1"
bitfld.long 0x00 28. "         RSTOPM              ,Reference Stop Mode" "0,1"
textline "                              "
bitfld.long 0x00 24.--27. " FRQSEL                 ,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RLOCKM              ,Relock Mode" "0,1"
textline "                              "
bitfld.long 0x00 17.--22. " CPPC                   ,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 13.--16. "        CPIC                ,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12. " GSHIFT                 ,Gear Shift" "0,1"
bitfld.long 0x00 8. "         ATOEN               ,Analog Test Enable (ATOEN)" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " ATC                    ,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DTC                 ,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1448++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
hexmask.long.word 0x00 6.--21. 1. " PLLPROG                ,Connects to the PLL PLL_PROG bus."
bitfld.long 0x00 5. "      BYPVREGCP           ,Bypass PLL vreg_cp" "0,1"
textline "                              "
bitfld.long 0x00 4. " BYPVREGDIG             ,Bypass PLL vreg_dig" "0,1"
bitfld.long 0x00 3. "         BYPVDD              ,PLL VDD voltage level control" "0,1"
textline "                              "
bitfld.long 0x00 2. " LOCKPS                 ,Lock Detector Phase Select" "0,1"
bitfld.long 0x00 1. "         LOCKCS              ,Lock Detector Counter Select" "0,1"
textline "                              "
bitfld.long 0x00 0. " LOCKDS                 ,Lock Detector Select" "0,1"
group.long 0x144C++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_31_0           ,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
group.long 0x1450++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_63_32          ,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
group.long 0x1454++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_95_64          ,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
group.long 0x1458++0x3
line.long 0x00 "DDRPHY_DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
hexmask.long.byte 0x00 0.--7. 1. " PLLCTRL_103_96         ,Connectes to bits[103:96] of the PLL generatl control bus PLL_CTRL"
group.long 0x145C++0x3
line.long 0x00 "DDRPHY_DX8SL1DQSCTL,DATX8 0-1 DQS Control Register"
bitfld.long 0x00 24. " RRRMODE                ,Read Path Rise-to-Rise Mode" "0,1"
bitfld.long 0x00 21. "         WRRMODE             ,Write Path Rise-to-Rise Mode" "0,1"
textline "                              "
bitfld.long 0x00 19.--20. " DQSGX                  ,DQS Gate Extension" "0,1,2,3"
bitfld.long 0x00 18. "         LPPLLPD             ,Low Power PLL Power Down" "0,1"
textline "                              "
bitfld.long 0x00 17. " LPIOPD                 ,Low Power I/O Power Down" "0,1"
bitfld.long 0x00 15. "         PDAMODE             ,Set PDA mode timing" "0,1"
textline "                              "
bitfld.long 0x00 14. " QSCNTEN                ,QS Counter Enable" "0,1"
bitfld.long 0x00 13. "         UDQIOM              ,Unused DQ I/O Mode" "0,1"
textline "                              "
bitfld.long 0x00 8.--9. " DXSR                   ,Data Slew Rate" "0,1,2,3"
bitfld.long 0x00 4.--7. "         DQSNRES             ,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQSRES                 ,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1460++0x3
line.long 0x00 "DDRPHY_DX8SL1TRNCTL,DATX8 0-1 Training Control Register"
group.long 0x1464++0x3
line.long 0x00 "DDRPHY_DX8SL1DDLCTL,DATX8 0-1 DDL Control Register"
bitfld.long 0x00 26. " DLYLDTM                ,Delay Load Timing" "0,1"
bitfld.long 0x00 25. "         DXDDLLDT            ,DX DDL Load Type" "0,1"
textline "                              "
bitfld.long 0x00 18.--22. " DXDDLLD                ,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 2.--17. 1. "        DXDDLBYP            ,DATX8 DDL Bypass"
textline "                              "
bitfld.long 0x00 0.--1. " DDLBYPMODE             ,Controls DDL Bypass Mode" "0,1,2,3"
group.long 0x1468++0x3
line.long 0x00 "DDRPHY_DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1"
bitfld.long 0x00 24. " DXCALCLK               ,DATX Calibration Clock Select" "0,1"
bitfld.long 0x00 23. "         DXRCLKMD            ,DATX8 Read Clock Mode" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DXDTOSEL               ,DATX8 Digital Test Output Select" "0,1,2,3"
bitfld.long 0x00 19. "         DXGSMD              ,Read DQS Gating Status Mode" "0,1"
textline "                              "
bitfld.long 0x00 18. " DXQSDBYP               ,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
bitfld.long 0x00 17. "         DXGDBYP             ,Read DQS Gate Delay Load Bypass Mode" "0,1"
textline "                              "
bitfld.long 0x00 16. " DXTMODE                ,DATX8 Test Mode" "0,1"
group.long 0x146C++0x3
line.long 0x00 "DDRPHY_DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2"
bitfld.long 0x00 23. " CRDEN                  ,Configurable Read Data Enable" "0,1"
bitfld.long 0x00 20.--22. "         POSOEX              ,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 18.--19. " PREOEX                 ,OE Extension during Pre-amble" "0,1,2,3"
bitfld.long 0x00 16. "         IOAG                ,I/O Assisted Gate Select" "0,1"
textline "                              "
bitfld.long 0x00 15. " IOLB                   ,I/O Loopback Select" "0,1"
bitfld.long 0x00 9.--12. "         LPWAKEUP_THRSH      ,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8. " RDBI                   ,Read Data Bus Inversion Enable" "0,1"
bitfld.long 0x00 7. "         WDBI                ,Write Data Bus Inversion Enable" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRFBYP                 ,PUB Read FIFO Bypass" "0,1"
bitfld.long 0x00 4.--5. "         RDMODE              ,DATX8 Receive FIFO Read Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3. " DISRST                 ,Disables the Read FIFO Reset" "0,1"
bitfld.long 0x00 1.--2. "         DQSGLB              ,Read DQS Gate I/O Loopback" "0,1,2,3"
group.long 0x1470++0x3
line.long 0x00 "DDRPHY_DX8SL1IOCR,DATX8 0-1 I/O Configuration Register"
bitfld.long 0x00 28.--30. " DXDACRANGE             ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25.--27. "         DXVREFIOM           ,IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 22.--24. " DXIOM                  ,DX IO Mode" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 11.--21. 1. "         DXTXM               ,DX IO Transmitter Mode"
textline "                              "
hexmask.long.word 0x00 0.--10. 1. " DXRXM                  ,DX IO Receiver Mode"
group.long 0x1474++0x3
line.long 0x00 "DDRPHY_DX4SL1IOCR,DATX4 Slice 0-1 I/O Configuration Register"
hgroup.long 0x1480++0x3
hide.long 0x00 "DDRPHY_DX8SL2OSC,DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register"
in
textline "                              "
group.long 0x1484++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0"
bitfld.long 0x00 31. " PLLBYP                 ,PLL Bypass" "0,1"
bitfld.long 0x00 30. "         PLLRST              ,PLL Reset" "0,1"
textline "                              "
bitfld.long 0x00 29. " PLLPD                  ,PLL Power Down" "0,1"
bitfld.long 0x00 28. "         RSTOPM              ,Reference Stop Mode" "0,1"
textline "                              "
bitfld.long 0x00 24.--27. " FRQSEL                 ,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RLOCKM              ,Relock Mode" "0,1"
textline "                              "
bitfld.long 0x00 17.--22. " CPPC                   ,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 13.--16. "        CPIC                ,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12. " GSHIFT                 ,Gear Shift" "0,1"
bitfld.long 0x00 8. "         ATOEN               ,Analog Test Enable (ATOEN)" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " ATC                    ,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DTC                 ,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1488++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
hexmask.long.word 0x00 6.--21. 1. " PLLPROG                ,Connects to the PLL PLL_PROG bus."
bitfld.long 0x00 5. "      BYPVREGCP           ,Bypass PLL vreg_cp" "0,1"
textline "                              "
bitfld.long 0x00 4. " BYPVREGDIG             ,Bypass PLL vreg_dig" "0,1"
bitfld.long 0x00 3. "         BYPVDD              ,PLL VDD voltage level control" "0,1"
textline "                              "
bitfld.long 0x00 2. " LOCKPS                 ,Lock Detector Phase Select" "0,1"
bitfld.long 0x00 1. "         LOCKCS              ,Lock Detector Counter Select" "0,1"
textline "                              "
bitfld.long 0x00 0. " LOCKDS                 ,Lock Detector Select" "0,1"
group.long 0x148C++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_31_0           ,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
group.long 0x1490++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_63_32          ,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
group.long 0x1494++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_95_64          ,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
group.long 0x1498++0x3
line.long 0x00 "DDRPHY_DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
hexmask.long.byte 0x00 0.--7. 1. " PLLCTRL_103_96         ,Connectes to bits[103:96] of the PLL generatl control bus PLL_CTRL"
group.long 0x149C++0x3
line.long 0x00 "DDRPHY_DX8SL2DQSCTL,DATX8 0-1 DQS Control Register"
bitfld.long 0x00 24. " RRRMODE                ,Read Path Rise-to-Rise Mode" "0,1"
bitfld.long 0x00 21. "         WRRMODE             ,Write Path Rise-to-Rise Mode" "0,1"
textline "                              "
bitfld.long 0x00 19.--20. " DQSGX                  ,DQS Gate Extension" "0,1,2,3"
bitfld.long 0x00 18. "         LPPLLPD             ,Low Power PLL Power Down" "0,1"
textline "                              "
bitfld.long 0x00 17. " LPIOPD                 ,Low Power I/O Power Down" "0,1"
bitfld.long 0x00 15. "         PDAMODE             ,Set PDA mode timing" "0,1"
textline "                              "
bitfld.long 0x00 14. " QSCNTEN                ,QS Counter Enable" "0,1"
bitfld.long 0x00 13. "         UDQIOM              ,Unused DQ I/O Mode" "0,1"
textline "                              "
bitfld.long 0x00 8.--9. " DXSR                   ,Data Slew Rate" "0,1,2,3"
bitfld.long 0x00 4.--7. "         DQSNRES             ,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQSRES                 ,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14A0++0x3
line.long 0x00 "DDRPHY_DX8SL2TRNCTL,DATX8 0-1 Training Control Register"
group.long 0x14A4++0x3
line.long 0x00 "DDRPHY_DX8SL2DDLCTL,DATX8 0-1 DDL Control Register"
bitfld.long 0x00 26. " DLYLDTM                ,Delay Load Timing" "0,1"
bitfld.long 0x00 25. "         DXDDLLDT            ,DX DDL Load Type" "0,1"
textline "                              "
bitfld.long 0x00 18.--22. " DXDDLLD                ,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 2.--17. 1. "        DXDDLBYP            ,DATX8 DDL Bypass"
textline "                              "
bitfld.long 0x00 0.--1. " DDLBYPMODE             ,Controls DDL Bypass Mode" "0,1,2,3"
group.long 0x14A8++0x3
line.long 0x00 "DDRPHY_DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1"
bitfld.long 0x00 24. " DXCALCLK               ,DATX Calibration Clock Select" "0,1"
bitfld.long 0x00 23. "         DXRCLKMD            ,DATX8 Read Clock Mode" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DXDTOSEL               ,DATX8 Digital Test Output Select" "0,1,2,3"
bitfld.long 0x00 19. "         DXGSMD              ,Read DQS Gating Status Mode" "0,1"
textline "                              "
bitfld.long 0x00 18. " DXQSDBYP               ,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
bitfld.long 0x00 17. "         DXGDBYP             ,Read DQS Gate Delay Load Bypass Mode" "0,1"
textline "                              "
bitfld.long 0x00 16. " DXTMODE                ,DATX8 Test Mode" "0,1"
group.long 0x14AC++0x3
line.long 0x00 "DDRPHY_DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2"
bitfld.long 0x00 23. " CRDEN                  ,Configurable Read Data Enable" "0,1"
bitfld.long 0x00 20.--22. "         POSOEX              ,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 18.--19. " PREOEX                 ,OE Extension during Pre-amble" "0,1,2,3"
bitfld.long 0x00 16. "         IOAG                ,I/O Assisted Gate Select" "0,1"
textline "                              "
bitfld.long 0x00 15. " IOLB                   ,I/O Loopback Select" "0,1"
bitfld.long 0x00 9.--12. "         LPWAKEUP_THRSH      ,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8. " RDBI                   ,Read Data Bus Inversion Enable" "0,1"
bitfld.long 0x00 7. "         WDBI                ,Write Data Bus Inversion Enable" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRFBYP                 ,PUB Read FIFO Bypass" "0,1"
bitfld.long 0x00 4.--5. "         RDMODE              ,DATX8 Receive FIFO Read Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3. " DISRST                 ,Disables the Read FIFO Reset" "0,1"
bitfld.long 0x00 1.--2. "         DQSGLB              ,Read DQS Gate I/O Loopback" "0,1,2,3"
group.long 0x14B0++0x3
line.long 0x00 "DDRPHY_DX8SL2IOCR,DATX8 0-1 I/O Configuration Register"
bitfld.long 0x00 28.--30. " DXDACRANGE             ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25.--27. "         DXVREFIOM           ,IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 22.--24. " DXIOM                  ,DX IO Mode" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 11.--21. 1. "         DXTXM               ,DX IO Transmitter Mode"
textline "                              "
hexmask.long.word 0x00 0.--10. 1. " DXRXM                  ,DX IO Receiver Mode"
group.long 0x14B4++0x3
line.long 0x00 "DDRPHY_DX4SL2IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x14F4++0x3
line.long 0x00 "DDRPHY_DX4SL3IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x1534++0x3
line.long 0x00 "DDRPHY_DX4SL4IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x1574++0x3
line.long 0x00 "DDRPHY_DX4SL5IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x15B4++0x3
line.long 0x00 "DDRPHY_DX4SL6IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x15F4++0x3
line.long 0x00 "DDRPHY_DX4SL7IOCR,DATX4 Slice 0-1 I/O Configuration Register"
group.long 0x1634++0x3
line.long 0x00 "DDRPHY_DX4SL8IOCR,DATX4 Slice 0-1 I/O Configuration Register"
wgroup.long 0x17C0++0x3
line.long 0x00 "DDRPHY_DX8SLBOSC,DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register"
bitfld.long 0x00 28.--29. " GATEDXRDCLK            ,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
bitfld.long 0x00 26.--27. "         GATEDXDDRCLK        ,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
textline "                              "
bitfld.long 0x00 24.--25. " GATEDXCTLCLK           ,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
bitfld.long 0x00 22.--23. "         CLKLEVEL            ,Selects the level to which clocks will be stalled when clock gating is enabled." "0,1,2,3"
textline "                              "
bitfld.long 0x00 21. " LBMODE                 ,Loopback Mode" "0,1"
bitfld.long 0x00 20. "         LBGSDQS             ,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
textline "                              "
bitfld.long 0x00 18.--19. " LBGDQS                 ,Loopback DQS Gating" "0,1,2,3"
bitfld.long 0x00 17. "         LBDQSS              ,Loopback DQS Shift" "0,1"
textline "                              "
bitfld.long 0x00 16. " PHYHRST                ,PHY High-Speed Reset" "0,1"
bitfld.long 0x00 15. "         PHYFRST             ,PHY FIFO Reset" "0,1"
textline "                              "
bitfld.long 0x00 14. " DLTST                  ,Delay Line Test Start" "0,1"
bitfld.long 0x00 13. "         DLTMODE             ,Delay Line Test Mode" "0,1"
textline "                              "
bitfld.long 0x00 9.--10. " OSCWDDL                ,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
bitfld.long 0x00 5.--6. "         OSCWDL              ,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
textline "                              "
bitfld.long 0x00 1.--4. " OSCDIV                 ,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        OSCEN               ,Oscillator Enable" "0,1"
wgroup.long 0x17C4++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR0,DAXT8 0-8 PLL Control Register 0"
bitfld.long 0x00 31. " PLLBYP                 ,PLL Bypass" "0,1"
bitfld.long 0x00 30. "         PLLRST              ,PLL Reset" "0,1"
textline "                              "
bitfld.long 0x00 29. " PLLPD                  ,PLL Power Down" "0,1"
bitfld.long 0x00 28. "         RSTOPM              ,Reference Stop Mode" "0,1"
textline "                              "
bitfld.long 0x00 24.--27. " FRQSEL                 ,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RLOCKM              ,Relock Mode" "0,1"
textline "                              "
bitfld.long 0x00 17.--22. " CPPC                   ,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 13.--16. "        CPIC                ,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 12. " GSHIFT                 ,Gear Shift" "0,1"
bitfld.long 0x00 8. "         ATOEN               ,Analog Test Enable (ATOEN)" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " ATC                    ,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DTC                 ,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long 0x17C8++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR1,DAXT8 0-8 PLL Control Register 1 (Type B PLL Only)"
hexmask.long.word 0x00 6.--21. 1. " PLLPROG                ,Connects to the PLL PLL_PROG bus."
bitfld.long 0x00 5. "      BYPVREGCP           ,Bypass PLL vreg_cp" "0,1"
textline "                              "
bitfld.long 0x00 4. " BYPVREGDIG             ,Bypass PLL vreg_dig" "0,1"
bitfld.long 0x00 3. "         BYPVDD              ,PLL VDD voltage level control" "0,1"
textline "                              "
bitfld.long 0x00 2. " LOCKPS                 ,Lock Detector Phase Select" "0,1"
bitfld.long 0x00 1. "         LOCKCS              ,Lock Detector Counter Select" "0,1"
textline "                              "
bitfld.long 0x00 0. " LOCKDS                 ,Lock Detector Select" "0,1"
wgroup.long 0x17CC++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR2,DAXT8 0-8 PLL Control Register 2 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_31_0           ,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
wgroup.long 0x17D0++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR3,DAXT8 0-8 PLL Control Register 3 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_63_32          ,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
wgroup.long 0x17D4++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR4,DAXT8 0-8 PLL Control Register 4 (Type B PLL Only)"
hexmask.long 0x00 0.--31. 1. " PLLCTRL_95_64          ,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
wgroup.long 0x17D8++0x3
line.long 0x00 "DDRPHY_DX8SLBPLLCR5,DAXT8 0-8 PLL Control Register 5 (Type B PLL Only)"
hexmask.long.byte 0x00 0.--7. 1. " PLLCTRL_103_96         ,Connectes to bits[103:96] of the PLL generatl control bus PLL_CTRL"
wgroup.long 0x17DC++0x3
line.long 0x00 "DDRPHY_DX8SLBDQSCTL,DATX8 0-8 DQS Control Register"
bitfld.long 0x00 24. " RRRMODE                ,Read Path Rise-to-Rise Mode" "0,1"
bitfld.long 0x00 21. "         WRRMODE             ,Write Path Rise-to-Rise Mode" "0,1"
textline "                              "
bitfld.long 0x00 19.--20. " DQSGX                  ,DQS Gate Extension" "0,1,2,3"
bitfld.long 0x00 18. "         LPPLLPD             ,Low Power PLL Power Down" "0,1"
textline "                              "
bitfld.long 0x00 17. " LPIOPD                 ,Low Power I/O Power Down" "0,1"
bitfld.long 0x00 15. "         PDAMODE             ,Set PDA mode timing" "0,1"
textline "                              "
bitfld.long 0x00 14. " QSCNTEN                ,QS Counter Enable" "0,1"
bitfld.long 0x00 13. "         UDQIOM              ,Unused DQ I/O Mode" "0,1"
textline "                              "
bitfld.long 0x00 8.--9. " DXSR                   ,Data Slew Rate" "0,1,2,3"
bitfld.long 0x00 4.--7. "         DQSNRES             ,DQS# Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 0.--3. " DQSRES                 ,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x17E0++0x3
line.long 0x00 "DDRPHY_DX8SLBTRNCTL,DATX8 0-8 Training Control Register"
wgroup.long 0x17E4++0x3
line.long 0x00 "DDRPHY_DX8SLBDDLCTL,DATX8 0-8 DDL Control Register"
bitfld.long 0x00 26. " DLYLDTM                ,Delay Load Timing" "0,1"
bitfld.long 0x00 25. "         DXDDLLDT            ,DX DDL Load Type" "0,1"
textline "                              "
bitfld.long 0x00 18.--22. " DXDDLLD                ,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 2.--17. 1. "        DXDDLBYP            ,DATX8 DDL Bypass"
textline "                              "
bitfld.long 0x00 0.--1. " DDLBYPMODE             ,Controls DDL Bypass Mode" "0,1,2,3"
wgroup.long 0x17E8++0x3
line.long 0x00 "DDRPHY_DX8SLBDXCTL1,DATX8 0-8 DX Control Register 1"
bitfld.long 0x00 24. " DXCALCLK               ,DATX Calibration Clock Select" "0,1"
bitfld.long 0x00 23. "         DXRCLKMD            ,DATX8 Read Clock Mode" "0,1"
textline "                              "
bitfld.long 0x00 20.--21. " DXDTOSEL               ,DATX8 Digital Test Output Select" "0,1,2,3"
bitfld.long 0x00 19. "         DXGSMD              ,Read DQS Gating Status Mode" "0,1"
textline "                              "
bitfld.long 0x00 18. " DXQSDBYP               ,Read DQS/DQS# Delay Load Bypass Mode" "0,1"
bitfld.long 0x00 17. "         DXGDBYP             ,Read DQS Gate Delay Load Bypass Mode" "0,1"
textline "                              "
bitfld.long 0x00 16. " DXTMODE                ,DATX8 Test Mode" "0,1"
wgroup.long 0x17EC++0x3
line.long 0x00 "DDRPHY_DX8SLBDXCTL2,DATX8 0-8 DX Control Register 2"
bitfld.long 0x00 23. " CRDEN                  ,Configurable Read Data Enable" "0,1"
bitfld.long 0x00 20.--22. "         POSOEX              ,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 18.--19. " PREOEX                 ,OE Extension during Pre-amble" "0,1,2,3"
bitfld.long 0x00 16. "         IOAG                ,I/O Assisted Gate Select" "0,1"
textline "                              "
bitfld.long 0x00 15. " IOLB                   ,I/O Loopback Select" "0,1"
bitfld.long 0x00 9.--12. "         LPWAKEUP_THRSH      ,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                              "
bitfld.long 0x00 8. " RDBI                   ,Read Data Bus Inversion Enable" "0,1"
bitfld.long 0x00 7. "         WDBI                ,Write Data Bus Inversion Enable" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRFBYP                 ,PUB Read FIFO Bypass" "0,1"
bitfld.long 0x00 4.--5. "         RDMODE              ,DATX8 Receive FIFO Read Mode" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3. " DISRST                 ,Disables the Read FIFO Reset" "0,1"
bitfld.long 0x00 1.--2. "         DQSGLB              ,Read DQS Gate I/O Loopback" "0,1,2,3"
wgroup.long 0x17F0++0x3
line.long 0x00 "DDRPHY_DX8SLBIOCR,DATX8 0-8 I/O Configuration Register"
bitfld.long 0x00 28.--30. " DXDACRANGE             ,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25.--27. "         DXVREFIOM           ,IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 22.--24. " DXIOM                  ,DX IO Mode" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 11.--21. 1. "         DXTXM               ,DX IO Transmitter Mode"
textline "                              "
hexmask.long.word 0x00 0.--10. 1. " DXRXM                  ,DX IO Receiver Mode"
group.long 0x17F4++0x3
line.long 0x00 "DDRPHY_DX4SLBIOCR,DATX4 0-8 I/O Configuration Register"
width 0x0B
tree.end
tree.end
tree "DDR_Subsystem_Wrapper_Logic"
tree "DDRSS0_SS_CFG"
base ad:0x298E000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "DDRSS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem."
hexmask.long.word 0x00 16.--31. 1. " MOD_ID             ,Module ID"
bitfld.long 0x00 11.--15. "      RTL_VER            ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " MAJ_REV            ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM             ,Custom" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " MIN_REV            ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "DDRSS_SS_CTL_REG,The Subsystem Control Register contains fields for control functions required for submodules in the subsystem."
bitfld.long 0x00 16. " X22_LPDDR4         ,Write 0x1 to enable x22 LPDDR4 mode: 16-bit data plus 6-bit ECC with LPDDR4" "0,1"
bitfld.long 0x00 0. "         CTL_ARST           ,DDR controller and DDR PHY requires reset sequencing through software.Write 0 to deassert resets to the controller and PHY during initialization procedure. Write 1 to assert the resets.NOTE:This bit must only be used for the reset deassertion sequence during power-up. It must not be used for reset assertion after power-up, since it only resets the DDR controller and PHY, and does not reset the MSMC2DDR bridge or other DDRSS submodules. The MSMC2DDR bridge and the DDR controller use a credit based scheme for the HIF interface. Resetting just the DDR controller and not resetting the MSMC2DDR bridge will cause credit counts in the bridge to go out of sync with respect to the DDR controller, potentially causing a hang." "0,1"
group.long 0x20++0x3
line.long 0x00 "DDRSS_V2H_CTL_REG,The MSMC2DDR Bridge Control register contains control functions required for the MSMC2DDR bridge."
bitfld.long 0x00 31. " RMW_EN             ,Enables the ability for the MSMC2DDR bridge to create RMW operations for the DDR controller for sub DDR bus-width quanta writes.That is if a write occurs and the byte enables do not cover an entire DDR bus-width quanta a RMW operation is requested. This must be set to 1 if ECC and/or DBI is enabled in the DDR controller." "0,1"
bitfld.long 0x00 12.--16. "         CRIT_THRESH        ,Critical threshold.The MSMC2DDR bridge will give back global credits on the VBUSM.C interface only if the available credits on the LPR/NPW queues in the DDR controller are greater than this value. It must be ensured that this value is less than the SCHED.lpr_num_entries+1 in the DDR controller. The reset values of this field and SCHED.lpr_num_entries are optimal however, they can be changed for better traffic shaping." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 5.--9. " SDRAM_IDX          ,SDRAM Index = log2(connected SDRAM size) - 16.The sdram_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        REGION_IDX         ,Region Index = log2(CBA region size) - 16.The region_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x24++0x3
line.long 0x00 "DDRSS_V2H_R1_MAT_REG,The Range 1 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 1 Match Register uses the associated Range 1 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches."
bitfld.long 0x00 31. " RANGE1_RANGEEN_A   ,The range1_rangeen_a enables the RouteId AND'd with range1_mask_a to match the range1_routeid_a" "0,1"
bitfld.long 0x00 28.--30. "         RANGE1_MASK_A      ,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " RANGE1_ROUTEID_A   ,The range1_routeid_a is the value that is compared to the RouteId arriving on the command interface"
bitfld.long 0x00 15. "      RANGE1_RANGEEN_B   ,The range1_rangeen_b enables the RouteId AND'd with range1_mask_b to match the range1_routeid_b" "0,1"
textline "                                        "
bitfld.long 0x00 12.--14. " RANGE1_MASK_B      ,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "         RANGE1_ROUTEID_B   ,The range1_routeid_b is the value that is compared to the RouteId arriving on the command interface"
group.long 0x28++0x3
line.long 0x00 "DDRSS_V2H_R2_MAT_REG,The Range 2 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 2 Match Register uses the associated Range 2 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches."
bitfld.long 0x00 31. " RANGE2_RANGEEN_A   ,The range2_rangeen_a enables the RouteId AND'd with range2_mask_a to match the range2_routeid_a" "0,1"
bitfld.long 0x00 28.--30. "         RANGE2_MASK_A      ,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " RANGE2_ROUTEID_A   ,The range2_routeid_a is the value that is compared to the RouteId arriving on the command interface"
bitfld.long 0x00 15. "      RANGE2_RANGEEN_B   ,The range2_rangeen_b enables the RouteId AND'd with range2_mask_b to match the range2_routeid_b" "0,1"
textline "                                        "
bitfld.long 0x00 12.--14. " RANGE2_MASK_B      ,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "         RANGE2_ROUTEID_B   ,The range2_routeid_b is the value that is compared to the RouteId arriving on the command interface"
group.long 0x2C++0x3
line.long 0x00 "DDRSS_V2H_R3_MAT_REG,The Range 3 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 3 Match Register uses the associated Range 3 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches."
bitfld.long 0x00 31. " RANGE3_RANGEEN_A   ,The range3_rangeen_a enables the RouteId AND'd with range3_mask_a to match the range3_routeid_a" "0,1"
bitfld.long 0x00 28.--30. "         RANGE3_MASK_A      ,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " RANGE3_ROUTEID_A   ,The range3_routeid_a is the value that is compared to the RouteId arriving on the command interface"
bitfld.long 0x00 15. "      RANGE3_RANGEEN_B   ,The range3_rangeen_b enables the RouteId AND'd with range3_mask_b to match the range3_routeid_b" "0,1"
textline "                                        "
bitfld.long 0x00 12.--14. " RANGE3_MASK_B      ,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "         RANGE3_ROUTEID_B   ,The range3_routeid_b is the value that is compared to the RouteId arriving on the command interface"
group.long 0x30++0x3
line.long 0x00 "DDRSS_V2H_LPT_DEF_PRI_MAP_REG,The LPT Default Priority Mapping Register is used for accesses arriving on the Low Priority Thread on the VBUSM.C interface. The lpt_primapX is defined {HPR,cos_level} where the HPR (High Priority Read) bit will force a high priority read and the cos_level is 1-3 where 0 is Low Priority Read/Normal Priority Write (LPR/NPW). The cos_level 1-3 will apply the latency for the associated Class Latency Register to the HIF using Variable Priority Read/Write (VPR/VPW)."
bitfld.long 0x00 28.--31. " LPT_PRIMAP0        ,The field contains the HPR and cos_level for the VBUSM.C priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        LPT_PRIMAP1        ,The field contains the HPR and cos_level for the VBUSM.C priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " LPT_PRIMAP2        ,The field contains the HPR and cos_level for the VBUSM.C priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        LPT_PRIMAP3        ,The field contains the HPR and cos_level for the VBUSM.C priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " LPT_PRIMAP4        ,The field contains the HPR and cos_level for the VBUSM.C priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        LPT_PRIMAP5        ,The field contains the HPR and cos_level for the VBUSM.C priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " LPT_PRIMAP6        ,The field contains the HPR and cos_level for the VBUSM.C priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        LPT_PRIMAP7        ,The field contains the HPR and cos_level for the VBUSM.C priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x3
line.long 0x00 "DDRSS_V2H_LPT_R1_PRI_MAP_REG,The LPT Range 1 Priority Mapping Register is used to map the inbound priority on the Low Priority Thread to the latency class when a RouteId match 1 occurs. This allows the CoS level to be changed from the LPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " LPT_RANGE1_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        LPT_RANGE1_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " LPT_RANGE1_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        LPT_RANGE1_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " LPT_RANGE1_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        LPT_RANGE1_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " LPT_RANGE1_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        LPT_RANGE1_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "DDRSS_V2H_LPT_R2_PRI_MAP_REG,The LPT Range 2 Priority Mapping Register is used to map the inbound priority on the Low Priority Thread to the latency class when a RouteId match 2 occurs. This allows the CoS level to be changed from the LPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " LPT_RANGE2_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        LPT_RANGE2_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " LPT_RANGE2_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        LPT_RANGE2_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " LPT_RANGE2_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        LPT_RANGE2_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " LPT_RANGE2_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        LPT_RANGE2_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x3
line.long 0x00 "DDRSS_V2H_LPT_R3_PRI_MAP_REG,The LPT Range 3 Priority Mapping Register is used to map the inbound priority on the Low Priority Thread to the latency class when a RouteId match 3 occurs. This allows the CoS level to be changed from the LPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " LPT_RANGE3_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        LPT_RANGE3_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " LPT_RANGE3_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        LPT_RANGE3_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " LPT_RANGE3_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        LPT_RANGE3_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " LPT_RANGE3_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        LPT_RANGE3_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x3
line.long 0x00 "DDRSS_V2H_C1_LAT_REG,The Class 1 Latency Register is used to control how long a command may stay in the memory controller before it is executed without regard to performance impact of the DDR. The user must be careful when using small values as the smaller the value are, the more DDR thrashing could occur reducing overall system throughput."
hexmask.long.word 0x00 0.--10. 1. " CLASS1_LATENCY     ,The field contains the latency given in ddrss_ctl_clk cycles when the resulting priority map matches this class number.A value of zero causes that class of service to be disabled."
group.long 0x44++0x3
line.long 0x00 "DDRSS_V2H_C2_LAT_REG,The Class 2 Latency Register is used to control how long a command may stay in the memory controller before it is executed without regard to performance impact of the DDR. The user must be careful when using small values as the smaller the value are, the more DDR thrashing could occur reducing overall system throughput."
hexmask.long.word 0x00 0.--10. 1. " CLASS2_LATENCY     ,The field contains the latency given in ddrss_ctl_clk cycles when the resulting priority map matches this class number.A value of zero causes that class of service to be disabled."
group.long 0x48++0x3
line.long 0x00 "DDRSS_V2H_C3_LAT_REG,The Class 3 Latency Register is used to control how long a command may stay in the memory controller before it is executed without regard to performance impact of the DDR. The user must be careful when using small values as the smaller the value are, the more DDR thrashing could occur reducing overall system throughput."
hexmask.long.word 0x00 0.--10. 1. " CLASS3_LATENCY     ,The field contains the latency given in ddrss_ctl_clk cycles when the resulting priority map matches this class number.A value of zero causes that class of service to be disabled."
group.long 0x4C++0x3
line.long 0x00 "DDRSS_V2H_HPT_DEF_PRI_MAP_REG,The HPT Default Priority Mapping Register is used for accesses arriving on the High Priority Thread on the VBUSM.C interface. The hpt_primapX is defined {HPR,cos_level} where the HPR (High Priority Read) bit will force a high priority read and the cos_level is 1-3 where 0 is Low Priority Read/Normal Priority Write (LPR/NPW). The cos_level 1-3 will apply the latency for the associated Class Latency Register to the HIF using Variable Priority Read/Write (VPR/VPW)."
bitfld.long 0x00 28.--31. " HPT_PRIMAP0        ,The field contains the HPR and cos_level for the VBUSM.C priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        HPT_PRIMAP1        ,The field contains the HPR and cos_level for the VBUSM.C priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " HPT_PRIMAP2        ,The field contains the HPR and cos_level for the VBUSM.C priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        HPT_PRIMAP3        ,The field contains the HPR and cos_level for the VBUSM.C priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " HPT_PRIMAP4        ,The field contains the HPR and cos_level for the VBUSM.C priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        HPT_PRIMAP5        ,The field contains the HPR and cos_level for the VBUSM.C priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " HPT_PRIMAP6        ,The field contains the HPR and cos_level for the VBUSM.C priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        HPT_PRIMAP7        ,The field contains the HPR and cos_level for the VBUSM.C priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x3
line.long 0x00 "DDRSS_V2H_HPT_R1_PRI_MAP_REG,The HPT Range 1 Priority Mapping Register is used to map the inbound priority on the High Priority Thread to the latency class when a RouteId match 1 occurs. This allows the CoS level to be changed from the HPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " HPT_RANGE1_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        HPT_RANGE1_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " HPT_RANGE1_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        HPT_RANGE1_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " HPT_RANGE1_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        HPT_RANGE1_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " HPT_RANGE1_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        HPT_RANGE1_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "DDRSS_V2H_HPT_R2_PRI_MAP_REG,The HPT Range 2 Priority Mapping Register is used to map the inbound priority on the High Priority Thread to the latency class when a RouteId match 2 occurs. This allows the CoS level to be changed from the HPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " HPT_RANGE2_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        HPT_RANGE2_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " HPT_RANGE2_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        HPT_RANGE2_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " HPT_RANGE2_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        HPT_RANGE2_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " HPT_RANGE2_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        HPT_RANGE2_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x3
line.long 0x00 "DDRSS_V2H_HPT_R3_PRI_MAP_REG,The HPT Range 3 Priority Mapping Register is used to map the inbound priority on the High Priority Thread to the latency class when a RouteId match 3 occurs. This allows the CoS level to be changed from the HPT Default Priority Mapping value."
bitfld.long 0x00 28.--31. " HPT_RANGE3_PRIMAP0 ,The field contains the HPR and cos_level for the VBUSM.C priority 0 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        HPT_RANGE3_PRIMAP1 ,The field contains the HPR and cos_level for the VBUSM.C priority 1 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 20.--23. " HPT_RANGE3_PRIMAP2 ,The field contains the HPR and cos_level for the VBUSM.C priority 2 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        HPT_RANGE3_PRIMAP3 ,The field contains the HPR and cos_level for the VBUSM.C priority 3 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 12.--15. " HPT_RANGE3_PRIMAP4 ,The field contains the HPR and cos_level for the VBUSM.C priority 4 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        HPT_RANGE3_PRIMAP5 ,The field contains the HPR and cos_level for the VBUSM.C priority 5 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                        "
bitfld.long 0x00 4.--7. " HPT_RANGE3_PRIMAP6 ,The field contains the HPR and cos_level for the VBUSM.C priority 6 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        HPT_RANGE3_PRIMAP7 ,The field contains the HPR and cos_level for the VBUSM.C priority 7 for range match 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x70++0x3
hide.long 0x00 "DDRSS_V2H_AERR_LOG1_REG,The Address Error Log 1 register displays the routeID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range. Writing a 0x1 will clear all fields. Writing any other value has no effect. The Address Error Log 2 register will also be cleared upon writing this register."
in
textline "                                        "
rgroup.long 0x74++0x3
line.long 0x00 "DDRSS_V2H_AERR_LOG2_REG,The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range. This register will be cleared upon writing the Address Error Log 1 register."
hexmask.long 0x00 0.--27. 1. " AERR_ADDR_MSB      ,Address[47:20] of the VBUSM.C command"
hgroup.long 0x78++0x3
hide.long 0x00 "DDRSS_V2H_OERR_LOG_REG,The Opcode Error Log register displays the routeID and opcode for the first VBUSM.C command that had an unsupported opcode. Writing a 0x1 will clear all fields. Writing any other value has no effect."
in
textline "                                        "
hgroup.long 0x80++0x3
hide.long 0x00 "DDRSS_V2H_1B_ERR_CNT_REG,MSMC2DDR Bridge 1-Bit EDC Error Count Register"
in
textline "                                        "
hgroup.long 0x84++0x3
hide.long 0x00 "DDRSS_V2H_1B_ERR_LOG1_REG,The 1-Bit EDC Error Log 1 register displays the routeID, error position, and lsb of the address for the first VBUSM.C write that incurred 1-bit EDC error. Writing a 0x1 will clear all fields. Writing any other value has no effect. The 1-Bit EDC Error Log 2 register will also be cleared upon writing this register."
in
textline "                                        "
rgroup.long 0x88++0x3
line.long 0x00 "DDRSS_V2H_1B_ERR_LOG2_REG,The 1-Bit EDC Error Log 2 registers displays the msb of the address for the first VBUSM.C write that incurred 1-bit EDC error. This register will be cleared upon writing the 1-Bit EDC Error Log 1 register."
hexmask.long 0x00 0.--31. 1. " ADDR_MSB_1B        ,Address[47:16] of the VBUSM.C write command"
hgroup.long 0x8C++0x3
hide.long 0x00 "DDRSS_V2H_2B_ERR_LOG1_REG,The 2-Bit EDC Error Log 1 register displays the routeID, error position, and address of the first VBUSM.C write that incurs 2-bit EDC error. Writing a 0x1 clear all fields. Writing any other value has no effect. The 2-Bit EDC Error Log 2 register will also be cleared upon writing this register."
in
textline "                                        "
rgroup.long 0x90++0x3
line.long 0x00 "DDRSS_V2H_2B_ERR_LOG2_REG,The 2-Bit EDC Error Log 1 register displays the address of the first VBUSM.C write that incurs 2-bit EDC error. This register will be cleared upon writing the 2-Bit EDC Error Log 1 register."
hexmask.long 0x00 0.--31. 1. " ADR_MSB_2B         ,Address[47:16] of the VBUSM.C write command"
group.long 0xA0++0x3
line.long 0x00 "DDRSS_V2H_INT_RAW_REG,MSMC2DDR Bridge Interrupt Raw Status Register"
bitfld.long 0x00 1. " AERR               ,Raw status of MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range.Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1"
bitfld.long 0x00 0. "         OERR               ,Raw status of MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode.Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1"
hgroup.long 0xA4++0x3
hide.long 0x00 "DDRSS_V2H_INT_STAT_REG,MSMC2DDR Bridge Interrupt Status Register"
in
textline "                                        "
group.long 0xA8++0x3
line.long 0x00 "DDRSS_V2H_INT_SET_REG,MSMC2DDR Bridge Interrupt Enable Set Register"
bitfld.long 0x00 1. " AERR_EN            ,Enable set for MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range.Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
bitfld.long 0x00 0. "         OERR_EN            ,Enable set for MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode.Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1"
hgroup.long 0xAC++0x3
hide.long 0x00 "DDRSS_V2H_INT_CLR_REG,MSMC2DDR Bridge Interrupt Enable Clear Register"
in
textline "                                        "
wgroup.long 0xB0++0x3
line.long 0x00 "DDRSS_V2H_EOI_REG,MSMC2DDR Bridge End of Interrupt Register"
bitfld.long 0x00 0.--1. " EOI                ,Software End Of Interrupt (EOI) control.Write 0 for MSMC2DDR bridge aerr/oerr interrupt. Write 1 for MSMC2DDR bridge 1-bit EDC interrupt. Write 2 for MSMC2DDR bridge 2-bit EDC interrupt. This field always reads 0 (no EOI memory)." "0,1,2,3"
group.long 0x100++0x3
line.long 0x00 "DDRSS_PERF_CNT_SEL_REG,The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register."
bitfld.long 0x00 24.--29. " CNT4_SEL           ,Statistic select for Performance Counter 4 register.0x0 = Counts Read or Write commands send to the DDR controller. 0x1 = Counts every Write command send to the DDR controller. 0x2 = Counts every Read command send to the DDR controller. 0x3 = Counts every RMW command send to the DDR controller. 0x4 = Counts every High-Priority Read command send to the DDR controller. 0x6 = Counts every read data beat transfer on the DFI interface coming from SDRAM. 0x7 = Counts every High Priority Read transaction that is scheduled when the High Priority Queue is in Critical state in the DDR controller. 0x8 = Counts every Low Priority Read transaction that is scheduled when the Low Priority Queue is in Critical state in the DDR controller. 0x9 = Counts every Write transaction that is scheduled when the Write Queue is in Critical state in the DDR controller. 0xA = Counts every Activate that is issued for commands going through CAM in the DDR controller. 0xB = Counts every Read or Write that is issued for commands going through CAM in the DDR controller. 0xC = Counts every Read Activate that is issued for commands going through CAM in the DDR controller. 0xD = Counts every Read that is issued for commands going through CAM in the DDR controller. 0xE = Counts every Write that is issued for commands going through CAM in the DDR controller. 0xF = Counts every Masked Write that is issued for commands going through CAM in the DDR controller. 0x10 = Counts every Precharge that is issued by the DDR controller. 0x11 = Counts every Precharge that is issued by the DDR controller for Read or Write commands. 0x12 = Counts every Precharge that is issued by the DDR controller due to requests other than Read or Write (for eg: Refresh, ZQ Calib, MRW, MRR, tRAS(max)). 0x13 = Counts every Read to Write and Write to Read bus-turn-around that happens in the DDR controller. 0x14 = Counts every Write Combine operation that happens in the DDR controller. 0x15 = Counts every Write-after-Read collision tkhat happens in the DDR controller. 0x16 = Counts every Read-after-Write collision that happens in the DDR controller. 0x17 = Counts every Write-after-Write collision that happens in the DDR controller. Is valid only when Write Combine is turned off. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every entry into PowerDown mode. 0x1A = Counts every entry into Deep-PowerDown mode. 0x1B = Counts every entry into Maximum Power Savings mode. 0x1C = Counts every cycle for which the DDR controller stays in Self-Refresh mode. 0x1D = Counts every Refresh command that is issued by the DDR controller. 0x1E = Counts every Load Mode operation (MRW or MRR) that is issued by the DDR controller. 0x1F = Counts every ZQ Calib Long command that is issued by the DDR controller. 0x20 = Counts every ZQ Calib Short command that is issued by the DDR controller. 0x21-0x2F = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        CNT3_SEL           ,Statistic select for Performance Counter 3 register.0x0 = Counts Read or Write commands send to the DDR controller. 0x1 = Counts every Write command send to the DDR controller. 0x2 = Counts every Read command send to the DDR controller. 0x3 = Counts every RMW command send to the DDR controller. 0x4 = Counts every High-Priority Read command send to the DDR controller. 0x6 = Counts every read data beat transfer on the DFI interface coming from SDRAM. 0x7 = Counts every High Priority Read transaction that is scheduled when the High Priority Queue is in Critical state in the DDR controller. 0x8 = Counts every Low Priority Read transaction that is scheduled when the Low Priority Queue is in Critical state in the DDR controller. 0x9 = Counts every Write transaction that is scheduled when the Write Queue is in Critical state in the DDR controller. 0xA = Counts every Activate that is issued for commands going through CAM in the DDR controller. 0xB = Counts every Read or Write that is issued for commands going through CAM in the DDR controller. 0xC = Counts every Read Activate that is issued for commands going through CAM in the DDR controller. 0xD = Counts every Read that is issued for commands going through CAM in the DDR controller. 0xE = Counts every Write that is issued for commands going through CAM in the DDR controller. 0xF = Counts every Masked Write that is issued for commands going through CAM in the DDR controller. 0x10 = Counts every Precharge that is issued by the DDR controller. 0x11 = Counts every Precharge that is issued by the DDR controller for Read or Write commands. 0x12 = Counts every Precharge that is issued by the DDR controller due to requests other than Read or Write (for eg: Refresh, ZQ Calib, MRW, MRR, tRAS(max)). 0x13 = Counts every Read to Write and Write to Read bus-turn-around that happens in the DDR controller. 0x14 = Counts every Write Combine operation that happens in the DDR controller. 0x15 = Counts every Write-after-Read collision tkhat happens in the DDR controller. 0x16 = Counts every Read-after-Write collision that happens in the DDR controller. 0x17 = Counts every Write-after-Write collision that happens in the DDR controller. Is valid only when Write Combine is turned off. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every entry into PowerDown mode. 0x1A = Counts every entry into Deep-PowerDown mode. 0x1B = Counts every entry into Maximum Power Savings mode. 0x1C = Counts every cycle for which the DDR controller stays in Self-Refresh mode. 0x1D = Counts every Refresh command that is issued by the DDR controller. 0x1E = Counts every Load Mode operation (MRW or MRR) that is issued by the DDR controller. 0x1F = Counts every ZQ Calib Long command that is issued by the DDR controller. 0x20 = Counts every ZQ Calib Short command that is issued by the DDR controller. 0x21-0x2F = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                        "
bitfld.long 0x00 8.--13. " CNT2_SEL           ,Statistic select for Performance Counter 2 register.0x0 = Counts Read or Write commands send to the DDR controller. 0x1 = Counts every Write command send to the DDR controller. 0x2 = Counts every Read command send to the DDR controller. 0x3 = Counts every RMW command send to the DDR controller. 0x4 = Counts every High-Priority Read command send to the DDR controller. 0x6 = Counts every read data beat transfer on the DFI interface coming from SDRAM. 0x7 = Counts every High Priority Read transaction that is scheduled when the High Priority Queue is in Critical state in the DDR controller. 0x8 = Counts every Low Priority Read transaction that is scheduled when the Low Priority Queue is in Critical state in the DDR controller. 0x9 = Counts every Write transaction that is scheduled when the Write Queue is in Critical state in the DDR controller. 0xA = Counts every Activate that is issued for commands going through CAM in the DDR controller. 0xB = Counts every Read or Write that is issued for commands going through CAM in the DDR controller. 0xC = Counts every Read Activate that is issued for commands going through CAM in the DDR controller. 0xD = Counts every Read that is issued for commands going through CAM in the DDR controller. 0xE = Counts every Write that is issued for commands going through CAM in the DDR controller. 0xF = Counts every Masked Write that is issued for commands going through CAM in the DDR controller. 0x10 = Counts every Precharge that is issued by the DDR controller. 0x11 = Counts every Precharge that is issued by the DDR controller for Read or Write commands. 0x12 = Counts every Precharge that is issued by the DDR controller due to requests other than Read or Write (for eg: Refresh, ZQ Calib, MRW, MRR, tRAS(max)). 0x13 = Counts every Read to Write and Write to Read bus-turn-around that happens in the DDR controller. 0x14 = Counts every Write Combine operation that happens in the DDR controller. 0x15 = Counts every Write-after-Read collision tkhat happens in the DDR controller. 0x16 = Counts every Read-after-Write collision that happens in the DDR controller. 0x17 = Counts every Write-after-Write collision that happens in the DDR controller. Is valid only when Write Combine is turned off. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every entry into PowerDown mode. 0x1A = Counts every entry into Deep-PowerDown mode. 0x1B = Counts every entry into Maximum Power Savings mode. 0x1C = Counts every cycle for which the DDR controller stays in Self-Refresh mode. 0x1D = Counts every Refresh command that is issued by the DDR controller. 0x1E = Counts every Load Mode operation (MRW or MRR) that is issued by the DDR controller. 0x1F = Counts every ZQ Calib Long command that is issued by the DDR controller. 0x20 = Counts every ZQ Calib Short command that is issued by the DDR controller. 0x21-0x2F = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        CNT1_SEL           ,Statistic select for Performance Counter 1 register.0x0 = Counts Read or Write commands send to the DDR controller. 0x1 = Counts every Write command send to the DDR controller. 0x2 = Counts every Read command send to the DDR controller. 0x3 = Counts every RMW command send to the DDR controller. 0x4 = Counts every High-Priority Read command send to the DDR controller. 0x6 = Counts every read data beat transfer on the DFI interface coming from SDRAM. 0x7 = Counts every High Priority Read transaction that is scheduled when the High Priority Queue is in Critical state in the DDR controller. 0x8 = Counts every Low Priority Read transaction that is scheduled when the Low Priority Queue is in Critical state in the DDR controller. 0x9 = Counts every Write transaction that is scheduled when the Write Queue is in Critical state in the DDR controller. 0xA = Counts every Activate that is issued for commands going through CAM in the DDR controller. 0xB = Counts every Read or Write that is issued for commands going through CAM in the DDR controller. 0xC = Counts every Read Activate that is issued for commands going through CAM in the DDR controller. 0xD = Counts every Read that is issued for commands going through CAM in the DDR controller. 0xE = Counts every Write that is issued for commands going through CAM in the DDR controller. 0xF = Counts every Masked Write that is issued for commands going through CAM in the DDR controller. 0x10 = Counts every Precharge that is issued by the DDR controller. 0x11 = Counts every Precharge that is issued by the DDR controller for Read or Write commands. 0x12 = Counts every Precharge that is issued by the DDR controller due to requests other than Read or Write (for eg: Refresh, ZQ Calib, MRW, MRR, tRAS(max)). 0x13 = Counts every Read to Write and Write to Read bus-turn-around that happens in the DDR controller. 0x14 = Counts every Write Combine operation that happens in the DDR controller. 0x15 = Counts every Write-after-Read collision tkhat happens in the DDR controller. 0x16 = Counts every Read-after-Write collision that happens in the DDR controller. 0x17 = Counts every Write-after-Write collision that happens in the DDR controller. Is valid only when Write Combine is turned off. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every entry into PowerDown mode. 0x1A = Counts every entry into Deep-PowerDown mode. 0x1B = Counts every entry into Maximum Power Savings mode. 0x1C = Counts every cycle for which the DDR controller stays in Self-Refresh mode. 0x1D = Counts every Refresh command that is issued by the DDR controller. 0x1E = Counts every Load Mode operation (MRW or MRR) that is issued by the DDR controller. 0x1F = Counts every ZQ Calib Long command that is issued by the DDR controller. 0x20 = Counts every ZQ Calib Short command that is issued by the DDR controller. 0x21-0x2F = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x104++0x3
line.long 0x00 "DDRSS_PERF_CNT1_REG,Performance Counter 1 Register"
hexmask.long 0x00 0.--31. 1. " CNT1               ,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
rgroup.long 0x108++0x3
line.long 0x00 "DDRSS_PERF_CNT2_REG,Performance Counter 2 Register"
hexmask.long 0x00 0.--31. 1. " CNT2               ,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
rgroup.long 0x10C++0x3
line.long 0x00 "DDRSS_PERF_CNT3_REG,Performance Counter 3 Register"
hexmask.long 0x00 0.--31. 1. " CNT3               ,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
rgroup.long 0x110++0x3
line.long 0x00 "DDRSS_PERF_CNT4_REG,Performance Counter 4 Register"
hexmask.long 0x00 0.--31. 1. " CNT4               ,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register."
hgroup.long 0x150++0x3
hide.long 0x00 "DDRSS_HIF_MRR_STAT_REG,The HIF MRR Status register is used in conjunction with the HIF MRR Lane Data registers for Multi Purpose Register (MPR) read for DDR4 and Mode Register Read (MRR) for LPDDR4. The HIF MRR Lane Data registers display the data sent by the SDRAM as a result of the MPR or MRR."
in
textline "                                        "
rgroup.long 0x154++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN0_DATA1_REG,The HIF MRR Lane 0 Data 1 register displays the data sent by the SDRAM on byte lane 0 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L0_B3         ,Data for byte lane 0 burst beat 3"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L0_B2         ,Data for byte lane 0 burst beat 2"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L0_B1         ,Data for byte lane 0 burst beat 1"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L0_B0         ,Data for byte lane 0 burst beat 0"
rgroup.long 0x158++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN0_DATA2_REG,The HIF MRR Lane 0 Data 2 register displays the data sent by the SDRAM on byte lane 0 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L0_B7         ,Data for byte lane 0 burst beat 7"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L0_B6         ,Data for byte lane 0 burst beat 6"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L0_B5         ,Data for byte lane 0 burst beat 5"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L0_B4         ,Data for byte lane 0 burst beat 4"
rgroup.long 0x15C++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN1_DATA1_REG,The HIF MRR Lane 1 Data 1 register displays the data sent by the SDRAM on byte lane 1 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L1_B3         ,Data for byte lane 1 burst beat 3"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L1_B2         ,Data for byte lane 1 burst beat 2"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L1_B1         ,Data for byte lane 1 burst beat 1"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L1_B0         ,Data for byte lane 1 burst beat 0"
rgroup.long 0x160++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN1_DATA2_REG,The HIF MRR Lane 1 Data 2 register displays the data sent by the SDRAM on byte lane 1 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L1_B7         ,Data for byte lane 1 burst beat 7"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L1_B6         ,Data for byte lane 1 burst beat 6"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L1_B5         ,Data for byte lane 1 burst beat 5"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L1_B4         ,Data for byte lane 1 burst beat 4"
rgroup.long 0x164++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN2_DATA1_REG,The HIF MRR Lane 2 Data 1 register displays the data sent by the SDRAM on byte lane 2 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L2_B3         ,Data for byte lane 2 burst beat 3"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L2_B2         ,Data for byte lane 2 burst beat 2"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L2_B1         ,Data for byte lane 2 burst beat 1"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L2_B0         ,Data for byte lane 2 burst beat 0"
rgroup.long 0x168++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN2_DATA2_REG,The HIF MRR Lane 2 Data 2 register displays the data sent by the SDRAM on byte lane 2 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L2_B7         ,Data for byte lane 2 burst beat 7"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L2_B6         ,Data for byte lane 2 burst beat 6"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L2_B5         ,Data for byte lane 2 burst beat 5"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L2_B4         ,Data for byte lane 2 burst beat 4"
rgroup.long 0x16C++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN3_DATA1_REG,The HIF MRR Lane 3 Data 1 register displays the data sent by the SDRAM on byte lane 3 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L3_B3         ,Data for byte lane 3 burst beat 3"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L3_B2         ,Data for byte lane 3 burst beat 2"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L3_B1         ,Data for byte lane 3 burst beat 1"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L3_B0         ,Data for byte lane 3 burst beat 0"
rgroup.long 0x170++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN3_DATA2_REG,The HIF MRR Lane 3 Data 2 register displays the data sent by the SDRAM on byte lane 3 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L3_B7         ,Data for byte lane 3 burst beat 7"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L3_B6         ,Data for byte lane 3 burst beat 6"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L3_B5         ,Data for byte lane 3 burst beat 5"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L3_B4         ,Data for byte lane 3 burst beat 4"
rgroup.long 0x174++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN4_DATA1_REG,The HIF MRR Lane 4 Data 1 register displays the data sent by the SDRAM on byte lane 4 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L4_B3         ,Data for byte lane 4 burst beat 3"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L4_B2         ,Data for byte lane 4 burst beat 2"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L4_B1         ,Data for byte lane 4 burst beat 1"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L4_B0         ,Data for byte lane 4 burst beat 0"
rgroup.long 0x178++0x3
line.long 0x00 "DDRSS_HIF_MRR_LN4_DATA2_REG,The HIF MRR Lane 4 Data 2 register displays the data sent by the SDRAM on byte lane 4 as a result of the MPR or MRR. The beat represents the position of the data in the SDRAM burst."
hexmask.long.byte 0x00 24.--31. 1. " DATA_L4_B7         ,Data for byte lane 4 burst beat 7"
hexmask.long.byte 0x00 16.--23. 1. "        DATA_L4_B6         ,Data for byte lane 4 burst beat 6"
textline "                                        "
hexmask.long.byte 0x00 8.--15. 1. " DATA_L4_B5         ,Data for byte lane 4 burst beat 5"
hexmask.long.byte 0x00 0.--7. 1. "        DATA_L4_B4         ,Data for byte lane 4 burst beat 4"
width 0x0B
tree.end
tree.end
tree "Clocking"
tree "MCU_PLL0_CFG"
base ad:0x40D00000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_PID,Peripheral release details."
bitfld.long 0x00 30.--31. " SCHEME           ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                  ,Business unit - Processors" "0,1,2,3"
textline "                                  "
hexmask.long.word 0x00 16.--27. 1. " FUNC             ,Module functional identifier - PLL MMR"
bitfld.long 0x00 11.--15. "      R_RTL               ,RTL revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 8.--10. " X_MAJOR          ,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM              ,Custom revision number - actual value determined by RTL" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 0.--5. " Y_MINOR          ,Minor revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x8++0x3
line.long 0x00 "MCU_PLL_MMR_CFG0,Indicates the configuration of this set of PLL control registers."
bitfld.long 0x00 30.--31. " PLL15_TYPE       ,Indicates PLL15 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 28.--29. "         PLL14_TYPE          ,Indicates PLL14 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 26.--27. " PLL13_TYPE       ,Indicates PLL13 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 24.--25. "         PLL12_TYPE          ,Indicates PLL12 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 22.--23. " PLL11_TYPE       ,Indicates PLL11 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 20.--21. "         PLL10_TYPE          ,Indicates PLL10 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 18.--19. " PLL9_TYPE        ,Indicates PLL9 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 16.--17. "         PLL8_TYPE           ,Indicates PLL8 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 14.--15. " PLL7_TYPE        ,Indicates PLL7 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         PLL6_TYPE           ,Indicates PLL6 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 10.--11. " PLL5_TYPE        ,Indicates PLL5 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PLL4_TYPE           ,Indicates PLL4 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 6.--7. " PLL3_TYPE        ,Indicates PLL3 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PLL2_TYPE           ,Indicates PLL2 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 2.--3. " PLL1_TYPE        ,Indicates PLL1 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PLL0_TYPE           ,Indicates PLL0 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
rgroup.long 0xC++0x3
line.long 0x00 "MCU_PLL_MMR_CFG1,Indicates the configuration of this set of PLL control registers."
bitfld.long 0x00 30.--31. " PLL_NUM15_HSDIV  ,Indicates the number of High Speed dividers used on PLL15" "0,1,2,3"
bitfld.long 0x00 28.--29. "         PLL_NUM14_HSDIV     ,Indicates the number of High Speed dividers used on PLL14" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 26.--27. " PLL_NUM13_HSDIV  ,Indicates the number of High Speed dividers used on PLL13" "0,1,2,3"
bitfld.long 0x00 24.--25. "         PLL_NUM12_HSDIV     ,Indicates the number of High Speed dividers used on PLL12" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 22.--23. " PLL_NUM11_HSDIV  ,Indicates the number of High Speed dividers used on PLL11" "0,1,2,3"
bitfld.long 0x00 20.--21. "         PLL_NUM10_HSDIV     ,Indicates the number of High Speed dividers used on PLL10" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 18.--19. " PLL_NUM9_HSDIV   ,Indicates the number of High Speed dividers used on PLL9" "0,1,2,3"
bitfld.long 0x00 16.--17. "         PLL_NUM8_HSDIV      ,Indicates the number of High Speed dividers used on PLL8" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 14.--15. " PLL_NUM7_HSDIV   ,Indicates the number of High Speed dividers used on PLL7" "0,1,2,3"
bitfld.long 0x00 12.--13. "         PLL_NUM6_HSDIV      ,Indicates the number of High Speed dividers used on PLL6" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 10.--11. " PLL_NUM5_HSDIV   ,Indicates the number of High Speed dividers used on PLL5" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PLL_NUM4_HSDIV      ,Indicates the number of High Speed dividers used on PLL4" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 6.--7. " PLL_NUM3_HSDIV   ,Indicates the number of High Speed dividers used on PLL3" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PLL_NUM2_HSDIV      ,Indicates the number of High Speed dividers used on PLL2" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 2.--3. " PLL_NUM1_HSDIV   ,Indicates the number of High Speed dividers used on PLL1" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PLL_NUM0_HSDIV      ,Indicates the number of High Speed dividers used on PLL0" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "MCU_PLL0_KICK0,Lower 32-bits of PLL0 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL0 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x14++0x3
line.long 0x00 "MCU_PLL0_KICK1,Upper 32-bits of PLL0 register write lock key This register must be written with the designated key value following a write to with its key value before PLL0 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x20++0x3
line.long 0x00 "MCU_PLL0_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.word 0x00 8.--18. 1. " M_INT_MULT       ,PLL feedback multiplier (M) integer part"
hexmask.long.byte 0x00 0.--6. 1. "      N_DIV               ,PLL Input clock divider (N)"
group.long 0x24++0x3
line.long 0x00 "MCU_PLL0_PLL_FREQ_CTRL1,PLL frequency programming values."
hexmask.long.tbyte 0x00 0.--17. 1. " M_FRAC_MULT      ,PLL feedback multiplier (M) fractional part"
group.long 0x28++0x3
line.long 0x00 "MCU_PLL0_PLL_CLKDIV,Divider values for the PLL output clocks."
bitfld.long 0x00 16.--20. " M3_DIV           ,CLKOUHIF output divider (M3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        M2_DIV              ,PLL DCO output divider (M2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 0.--3. " M1_DIV           ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x3
line.long 0x00 "MCU_PLL0_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x30++0x3
line.long 0x00 "MCU_PLL0_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                                  "
bitfld.long 0x00 27. " DC_CORRECTOR_EN  ,Must be set to 1 when CLKOUT > 1.4 GHz is required" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 23. " LPMODE           ,Low power mode enable" "0,1"
bitfld.long 0x00 22. "         RELAXED_LOCK        ,Enable relaxed lock mode" "0,1"
textline "                                  "
bitfld.long 0x00 21. " LOWCURRSTBY      ,IDLE/LOSSCLK relock control" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                                  "
bitfld.long 0x00 19. " RELOCK_RAMP_EN   ,Relock clock ramp enable" "0,1"
bitfld.long 0x00 18. "         CLKINPHIF_SEL       ,CLKOUTHIF clock source select" "0,1"
textline "                                  "
bitfld.long 0x00 17. " REGM4X_EN        ,Enable 4x REGM mode" "0,1"
bitfld.long 0x00 16. "         DRIFTGUARD_EN       ,Re-calibration enable" "0,1"
textline "                                  "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 12.--13. "         CLKRAMP_LEVEL       ,Controls the clock ramp sequence 0h - No ramping 1h - Bypass clock to Fout/8 to Fout/4 to Fout/2 to Fout 2h - Bypass clock to Fout/4 to Fout/2 to Fout/1.5 to Fout 3h - Reserved - no ramping" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 8.--10. " CLKRAMP_RATE     ,Controls the time spent on each ramp step 0h - 2 REFCLK periods 1h - 4 REFCLK periods 2h - 8 REFCLK periods 3h - 16 REFCLK periods 4h - 32 REFCLK periods 5h - 64 REFCLK periods 6h - 128 REFCLK periods 7h - 256 REFCLK periods" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                                  "
bitfld.long 0x00 4. " CLKDCOLDO_EN     ,CLKDCOLDO enable" "0,1"
bitfld.long 0x00 3. "         CLKOUT_EN           ,CLKOUT enable" "0,1"
textline "                                  "
bitfld.long 0x00 2. " CLKOUTX2_EN      ,CLKOUTX2 enable" "0,1"
bitfld.long 0x00 1. "         CLKOUTHIF_EN        ,CLKOUTHIF enable" "0,1"
textline "                                  "
bitfld.long 0x00 0. " CLKOUTBYPASS_EN  ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x34++0x3
line.long 0x00 "MCU_PLL0_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                                  "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                                  "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                                  "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                                  "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 11. "         M3CHANGE_ACK        ,M3 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 10. " M2CHANGE_ACK     ,M2 divider change done" "0,1"
bitfld.long 0x00 9. "         M1CHANGE_ACK        ,M1 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 7. " BYPASS_ACK       ,Bypass status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUTX2_EN_ACK     ,CLKOUTX2 enable status" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUTHIF_EN_ACK ,CLKOUTHIF enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x38++0x3
line.long 0x00 "MCU_PLL0_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                                  "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                                  "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                                  "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                                  "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x3C++0x3
line.long 0x00 "MCU_PLL0_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                                  "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCU_PLL0_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--25. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x44++0x3
line.long 0x00 "MCU_PLL0_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x120++0x3
line.long 0x00 "MCU_PLL0_HSDIV_CLKDIV,Divider values for the HSDIVIDER output clocks."
bitfld.long 0x00 24.--29. " HSDIV4           ,CLKOUT4 divider value (HSDIV4+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        HSDIV3              ,CLKOUT3 divider value (HSDIV3+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                  "
bitfld.long 0x00 8.--13. " HSDIV2           ,CLKOUT2 divider value (HSDIV2+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        HSDIV1              ,CLKOUT1 divider value (HSDIV1+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x124++0x3
line.long 0x00 "MCU_PLL0_HSDIV_CTRL,Controls the HSDIVIDER features and mode of operation."
bitfld.long 0x00 31. " TENABLDIV        ,Output divider load enable" "0,1"
bitfld.long 0x00 16.--20. "         SPAREIN             ,Test mode inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT4_EN       ,CLKOUT4 enable" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN          ,CLKOUT3 enable" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUT2_EN       ,CLKOUT2 enable" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN          ,CLKOUT1 enable" "0,1"
rgroup.long 0x128++0x3
line.long 0x00 "MCU_PLL0_HSDIV_STAT,Indicates the status of HSDIVIDER operation."
bitfld.long 0x00 16.--20. " SPAREOUT         ,Test outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "        LOCK                ,When set, indicates that all enabled output clocks are out of bypass" "0,1"
textline "                                  "
bitfld.long 0x00 11. " DIV4_CHANGE_ACK  ,CLKOUT4 divider change done" "0,1"
bitfld.long 0x00 10. "         DIV3_CHANGE_ACK     ,CLKOUT3 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 9. " DIV2_CHANGE_ACK  ,CLKOUT2 divider change done" "0,1"
bitfld.long 0x00 8. "         DIV1_CHANGE_ACK     ,CLKOUT1 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT4_EN_ACK   ,CLKOUT4 enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN_ACK      ,CLKOUT3 enable status" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUT2_EN_ACK   ,CLKOUT2 enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN_ACK      ,CLKOUT1 enable status" "0,1"
group.long 0x12C++0x3
line.long 0x00 "MCU_PLL0_HSDIV_PWR_CTRL,Controls HSDIVIDER power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                                  "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 20. "         ISO                 ,Output isolation control" "0,1"
textline "                                  "
bitfld.long 0x00 16. " ISO_CLR          ,ISO latch clear" "0,1"
bitfld.long 0x00 8. "         AIPOFF              ,Set to 1 to switch off VDDA logic to prevent leakage when VDD power is off and VDDA power is active" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ISO_PRE_Z        ,ISO latch preset (active low)" "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCU_PLL0_HSDIV_PWR_STAT,Indicates the HSDIVIDER power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                                  "
bitfld.long 0x00 14. " LDOPWDN          ,Internal LDO powerdown status" "0,1"
group.long 0x1010++0x3
line.long 0x00 "MCU_PLL1_KICK0,Lower 32-bits of PLL1 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL1 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x1014++0x3
line.long 0x00 "MCU_PLL1_KICK1,Upper 32-bits of PLL1 register write lock key This register must be written with the designated key value following a write to with its key value before PLL1 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x1020++0x3
line.long 0x00 "MCU_PLL1_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.word 0x00 8.--18. 1. " M_INT_MULT       ,PLL feedback multiplier (M) integer part"
hexmask.long.byte 0x00 0.--6. 1. "      N_DIV               ,PLL Input clock divider (N)"
group.long 0x1024++0x3
line.long 0x00 "MCU_PLL1_PLL_FREQ_CTRL1,PLL frequency programming values."
hexmask.long.tbyte 0x00 0.--17. 1. " M_FRAC_MULT      ,PLL feedback multiplier (M) fractional part"
group.long 0x1028++0x3
line.long 0x00 "MCU_PLL1_PLL_CLKDIV,Divider values for the PLL output clocks."
bitfld.long 0x00 16.--20. " M3_DIV           ,CLKOUHIF output divider (M3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        M2_DIV              ,PLL DCO output divider (M2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 0.--3. " M1_DIV           ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x102C++0x3
line.long 0x00 "MCU_PLL1_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x1030++0x3
line.long 0x00 "MCU_PLL1_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                                  "
bitfld.long 0x00 27. " DC_CORRECTOR_EN  ,Must be set to 1 when CLKOUT > 1.4 GHz is required" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 23. " LPMODE           ,Low power mode enable" "0,1"
bitfld.long 0x00 22. "         RELAXED_LOCK        ,Enable relaxed lock mode" "0,1"
textline "                                  "
bitfld.long 0x00 21. " LOWCURRSTBY      ,IDLE/LOSSCLK relock control" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                                  "
bitfld.long 0x00 19. " RELOCK_RAMP_EN   ,Relock clock ramp enable" "0,1"
bitfld.long 0x00 18. "         CLKINPHIF_SEL       ,CLKOUTHIF clock source select" "0,1"
textline "                                  "
bitfld.long 0x00 17. " REGM4X_EN        ,Enable 4x REGM mode" "0,1"
bitfld.long 0x00 16. "         DRIFTGUARD_EN       ,Re-calibration enable" "0,1"
textline "                                  "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 12.--13. "         CLKRAMP_LEVEL       ,Controls the clock ramp sequence 0h - No ramping 1h - Bypass clock to Fout/8 to Fout/4 to Fout/2 to Fout 2h - Bypass clock to Fout/4 to Fout/2 to Fout/1.5 to Fout 3h - Reserved - no ramping" "0,1,2,3"
textline "                                  "
bitfld.long 0x00 8.--10. " CLKRAMP_RATE     ,Controls the time spent on each ramp step 0h - 2 REFCLK periods 1h - 4 REFCLK periods 2h - 8 REFCLK periods 3h - 16 REFCLK periods 4h - 32 REFCLK periods 5h - 64 REFCLK periods 6h - 128 REFCLK periods 7h - 256 REFCLK periods" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                                  "
bitfld.long 0x00 4. " CLKDCOLDO_EN     ,CLKDCOLDO enable" "0,1"
bitfld.long 0x00 3. "         CLKOUT_EN           ,CLKOUT enable" "0,1"
textline "                                  "
bitfld.long 0x00 2. " CLKOUTX2_EN      ,CLKOUTX2 enable" "0,1"
bitfld.long 0x00 1. "         CLKOUTHIF_EN        ,CLKOUTHIF enable" "0,1"
textline "                                  "
bitfld.long 0x00 0. " CLKOUTBYPASS_EN  ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x1034++0x3
line.long 0x00 "MCU_PLL1_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                                  "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                                  "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                                  "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                                  "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 11. "         M3CHANGE_ACK        ,M3 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 10. " M2CHANGE_ACK     ,M2 divider change done" "0,1"
bitfld.long 0x00 9. "         M1CHANGE_ACK        ,M1 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 7. " BYPASS_ACK       ,Bypass status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUTX2_EN_ACK     ,CLKOUTX2 enable status" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUTHIF_EN_ACK ,CLKOUTHIF enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x1038++0x3
line.long 0x00 "MCU_PLL1_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                                  "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                                  "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                                  "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                                  "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x103C++0x3
line.long 0x00 "MCU_PLL1_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                                  "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x1040++0x3
line.long 0x00 "MCU_PLL1_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--25. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x1044++0x3
line.long 0x00 "MCU_PLL1_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x1120++0x3
line.long 0x00 "MCU_PLL1_HSDIV_CLKDIV,Divider values for the HSDIVIDER output clocks."
bitfld.long 0x00 24.--29. " HSDIV4           ,CLKOUT4 divider value (HSDIV4+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        HSDIV3              ,CLKOUT3 divider value (HSDIV3+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                  "
bitfld.long 0x00 8.--13. " HSDIV2           ,CLKOUT2 divider value (HSDIV2+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        HSDIV1              ,CLKOUT1 divider value (HSDIV1+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1124++0x3
line.long 0x00 "MCU_PLL1_HSDIV_CTRL,Controls the HSDIVIDER features and mode of operation."
bitfld.long 0x00 31. " TENABLDIV        ,Output divider load enable" "0,1"
bitfld.long 0x00 16.--20. "         SPAREIN             ,Test mode inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT4_EN       ,CLKOUT4 enable" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN          ,CLKOUT3 enable" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUT2_EN       ,CLKOUT2 enable" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN          ,CLKOUT1 enable" "0,1"
rgroup.long 0x1128++0x3
line.long 0x00 "MCU_PLL1_HSDIV_STAT,Indicates the status of HSDIVIDER operation."
bitfld.long 0x00 16.--20. " SPAREOUT         ,Test outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "        LOCK                ,When set, indicates that all enabled output clocks are out of bypass" "0,1"
textline "                                  "
bitfld.long 0x00 11. " DIV4_CHANGE_ACK  ,CLKOUT4 divider change done" "0,1"
bitfld.long 0x00 10. "         DIV3_CHANGE_ACK     ,CLKOUT3 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 9. " DIV2_CHANGE_ACK  ,CLKOUT2 divider change done" "0,1"
bitfld.long 0x00 8. "         DIV1_CHANGE_ACK     ,CLKOUT1 divider change done" "0,1"
textline "                                  "
bitfld.long 0x00 3. " CLKOUT4_EN_ACK   ,CLKOUT4 enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN_ACK      ,CLKOUT3 enable status" "0,1"
textline "                                  "
bitfld.long 0x00 1. " CLKOUT2_EN_ACK   ,CLKOUT2 enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN_ACK      ,CLKOUT1 enable status" "0,1"
group.long 0x112C++0x3
line.long 0x00 "MCU_PLL1_HSDIV_PWR_CTRL,Controls HSDIVIDER power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                                  "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 20. "         ISO                 ,Output isolation control" "0,1"
textline "                                  "
bitfld.long 0x00 16. " ISO_CLR          ,ISO latch clear" "0,1"
bitfld.long 0x00 8. "         AIPOFF              ,Set to 1 to switch off VDDA logic to prevent leakage when VDD power is off and VDDA power is active" "0,1"
textline "                                  "
bitfld.long 0x00 0. " ISO_PRE_Z        ,ISO latch preset (active low)" "0,1"
rgroup.long 0x1130++0x3
line.long 0x00 "MCU_PLL1_HSDIV_PWR_STAT,Indicates the HSDIVIDER power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                                  "
bitfld.long 0x00 14. " LDOPWDN          ,Internal LDO powerdown status" "0,1"
width 0x0B
tree.end
tree "PLL0_CFG"
base ad:0x680000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "PID,Peripheral release details."
bitfld.long 0x00 30.--31. " SCHEME           ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                  ,Business unit - Processors" "0,1,2,3"
textline "                              "
hexmask.long.word 0x00 16.--27. 1. " FUNC             ,Module functional identifier - PLL MMR"
bitfld.long 0x00 11.--15. "      R_RTL               ,RTL revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 8.--10. " X_MAJOR          ,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM              ,Custom revision number - actual value determined by RTL" "0,1,2,3"
textline "                              "
bitfld.long 0x00 0.--5. " Y_MINOR          ,Minor revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x8++0x3
line.long 0x00 "PLL_MMR_CFG0,Indicates the configuration of this set of PLL control registers."
bitfld.long 0x00 30.--31. " PLL15_TYPE       ,Indicates PLL15 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 28.--29. "         PLL14_TYPE          ,Indicates PLL14 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 26.--27. " PLL13_TYPE       ,Indicates PLL13 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 24.--25. "         PLL12_TYPE          ,Indicates PLL12 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22.--23. " PLL11_TYPE       ,Indicates PLL11 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 20.--21. "         PLL10_TYPE          ,Indicates PLL10 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 18.--19. " PLL9_TYPE        ,Indicates PLL9 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 16.--17. "         PLL8_TYPE           ,Indicates PLL8 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 14.--15. " PLL7_TYPE        ,Indicates PLL7 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         PLL6_TYPE           ,Indicates PLL6 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 10.--11. " PLL5_TYPE        ,Indicates PLL5 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PLL4_TYPE           ,Indicates PLL4 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6.--7. " PLL3_TYPE        ,Indicates PLL3 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PLL2_TYPE           ,Indicates PLL2 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--3. " PLL1_TYPE        ,Indicates PLL1 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PLL0_TYPE           ,Indicates PLL0 presence and type 0h - PLL is not present 1h - Standard ADPLLM is present 2h - Low-jitter ADPLLLJM is present 3h - Reserved" "0,1,2,3"
rgroup.long 0xC++0x3
line.long 0x00 "PLL_MMR_CFG1,Indicates the configuration of this set of PLL control registers."
bitfld.long 0x00 30.--31. " PLL_NUM15_HSDIV  ,Indicates the number of High Speed dividers used on PLL15" "0,1,2,3"
bitfld.long 0x00 28.--29. "         PLL_NUM14_HSDIV     ,Indicates the number of High Speed dividers used on PLL14" "0,1,2,3"
textline "                              "
bitfld.long 0x00 26.--27. " PLL_NUM13_HSDIV  ,Indicates the number of High Speed dividers used on PLL13" "0,1,2,3"
bitfld.long 0x00 24.--25. "         PLL_NUM12_HSDIV     ,Indicates the number of High Speed dividers used on PLL12" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22.--23. " PLL_NUM11_HSDIV  ,Indicates the number of High Speed dividers used on PLL11" "0,1,2,3"
bitfld.long 0x00 20.--21. "         PLL_NUM10_HSDIV     ,Indicates the number of High Speed dividers used on PLL10" "0,1,2,3"
textline "                              "
bitfld.long 0x00 18.--19. " PLL_NUM9_HSDIV   ,Indicates the number of High Speed dividers used on PLL9" "0,1,2,3"
bitfld.long 0x00 16.--17. "         PLL_NUM8_HSDIV      ,Indicates the number of High Speed dividers used on PLL8" "0,1,2,3"
textline "                              "
bitfld.long 0x00 14.--15. " PLL_NUM7_HSDIV   ,Indicates the number of High Speed dividers used on PLL7" "0,1,2,3"
bitfld.long 0x00 12.--13. "         PLL_NUM6_HSDIV      ,Indicates the number of High Speed dividers used on PLL6" "0,1,2,3"
textline "                              "
bitfld.long 0x00 10.--11. " PLL_NUM5_HSDIV   ,Indicates the number of High Speed dividers used on PLL5" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PLL_NUM4_HSDIV      ,Indicates the number of High Speed dividers used on PLL4" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6.--7. " PLL_NUM3_HSDIV   ,Indicates the number of High Speed dividers used on PLL3" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PLL_NUM2_HSDIV      ,Indicates the number of High Speed dividers used on PLL2" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2.--3. " PLL_NUM1_HSDIV   ,Indicates the number of High Speed dividers used on PLL1" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PLL_NUM0_HSDIV      ,Indicates the number of High Speed dividers used on PLL0" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "PLL0_KICK0,Lower 32-bits of PLL0 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL0 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x14++0x3
line.long 0x00 "PLL0_KICK1,Upper 32-bits of PLL0 register write lock key This register must be written with the designated key value following a write to with its key value before PLL0 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers"
group.long 0x20++0x3
line.long 0x00 "PLL0_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.byte 0x00 24.--31. 1. " SD_DIV           ,Sigma-Delta divider (SD)"
hexmask.long.word 0x00 8.--19. 1. "        M_INT_MULT          ,PLL feedback multiplier (M) integer part"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " N_DIV            ,PLL Input clock divider (N)"
group.long 0x24++0x3
line.long 0x00 "PLL0_PLL_FREQ_CTRL1,PLL frequency programming values."
bitfld.long 0x00 24.--26. " SEL_FREQ_DCO     ,DCO frequency range selector 2h - HS2 mode - DCOCLK is 750 to 1500 MHz 4h - HS1 mode - DCOCLK is 1250 to 2500 MHz" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         M_FRAC_MULT         ,PLL feedback multiplier (M) fractional part"
group.long 0x28++0x3
line.long 0x00 "PLL0_PLL_CLKDIV,Divider values for the PLL output clocks."
hexmask.long.byte 0x00 8.--14. 1. " M2_DIV           ,PLL DCO output divider (M2)"
bitfld.long 0x00 0.--3. "        M1_DIV              ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x3
line.long 0x00 "PLL0_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x30++0x3
line.long 0x00 "PLL0_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 26. " BW_DECRZ         ,Decreases loop bandwidth ranges" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22. " RELAXED_LOCK     ,Enable relaxed lock mode" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN     ,CLKOUTLDO enable" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN        ,CLKDCOLDO enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN        ,CLKOUT enable" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN     ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x34++0x3
line.long 0x00 "PLL0_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 10. "         M2CHANGE_ACK        ,M2 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " M1CHANGE_ACK     ,M1 divider change done" "0,1"
bitfld.long 0x00 7. "         BYPASS_ACK          ,Bypass status" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN_ACK ,CLKOUTLDO enable status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x38++0x3
line.long 0x00 "PLL0_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x3C++0x3
line.long 0x00 "PLL0_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x40++0x3
line.long 0x00 "PLL0_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--26. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x44++0x3
line.long 0x00 "PLL0_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x120++0x3
line.long 0x00 "PLL0_HSDIV_CLKDIV,Divider values for the HSDIVIDER output clocks."
bitfld.long 0x00 24.--29. " HSDIV4           ,CLKOUT4 divider value (HSDIV4+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        HSDIV3              ,CLKOUT3 divider value (HSDIV3+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " HSDIV2           ,CLKOUT2 divider value (HSDIV2+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        HSDIV1              ,CLKOUT1 divider value (HSDIV1+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x124++0x3
line.long 0x00 "PLL0_HSDIV_CTRL,Controls the HSDIVIDER features and mode of operation."
bitfld.long 0x00 31. " TENABLDIV        ,Output divider load enable" "0,1"
bitfld.long 0x00 16.--20. "         SPAREIN             ,Test mode inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 3. " CLKOUT4_EN       ,CLKOUT4 enable" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN          ,CLKOUT3 enable" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUT2_EN       ,CLKOUT2 enable" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN          ,CLKOUT1 enable" "0,1"
rgroup.long 0x128++0x3
line.long 0x00 "PLL0_HSDIV_STAT,Indicates the status of HSDIVIDER operation."
bitfld.long 0x00 16.--20. " SPAREOUT         ,Test outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "        LOCK                ,When set, indicates that all enabled output clocks are out of bypass" "0,1"
textline "                              "
bitfld.long 0x00 11. " DIV4_CHANGE_ACK  ,CLKOUT4 divider change done" "0,1"
bitfld.long 0x00 10. "         DIV3_CHANGE_ACK     ,CLKOUT3 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " DIV2_CHANGE_ACK  ,CLKOUT2 divider change done" "0,1"
bitfld.long 0x00 8. "         DIV1_CHANGE_ACK     ,CLKOUT1 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT4_EN_ACK   ,CLKOUT4 enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN_ACK      ,CLKOUT3 enable status" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUT2_EN_ACK   ,CLKOUT2 enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN_ACK      ,CLKOUT1 enable status" "0,1"
group.long 0x12C++0x3
line.long 0x00 "PLL0_HSDIV_PWR_CTRL,Controls HSDIVIDER power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 20. "         ISO                 ,Output isolation control" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISO latch clear" "0,1"
bitfld.long 0x00 8. "         AIPOFF              ,Set to 1 to switch off VDDA logic to prevent leakage when VDD power is off and VDDA power is active" "0,1"
textline "                              "
bitfld.long 0x00 0. " ISO_PRE_Z        ,ISO latch preset (active low)" "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "PLL0_HSDIV_PWR_STAT,Indicates the HSDIVIDER power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 14. " LDOPWDN          ,Internal LDO powerdown status" "0,1"
group.long 0x1010++0x3
line.long 0x00 "PLL1_KICK0,Lower 32-bits of PLL1 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL1 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x1014++0x3
line.long 0x00 "PLL1_KICK1,Upper 32-bits of PLL1 register write lock key This register must be written with the designated key value following a write to with its key value before PLL1 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers"
group.long 0x1020++0x3
line.long 0x00 "PLL1_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.byte 0x00 24.--31. 1. " SD_DIV           ,Sigma-Delta divider (SD)"
hexmask.long.word 0x00 8.--19. 1. "        M_INT_MULT          ,PLL feedback multiplier (M) integer part"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " N_DIV            ,PLL Input clock divider (N)"
group.long 0x1024++0x3
line.long 0x00 "PLL1_PLL_FREQ_CTRL1,PLL frequency programming values."
bitfld.long 0x00 24.--26. " SEL_FREQ_DCO     ,DCO frequency range selector 2h - HS2 mode - DCOCLK is 750 to 1500 MHz 4h - HS1 mode - DCOCLK is 1250 to 2500 MHz" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         M_FRAC_MULT         ,PLL feedback multiplier (M) fractional part"
group.long 0x1028++0x3
line.long 0x00 "PLL1_PLL_CLKDIV,Divider values for the PLL output clocks."
hexmask.long.byte 0x00 8.--14. 1. " M2_DIV           ,PLL DCO output divider (M2)"
bitfld.long 0x00 0.--3. "        M1_DIV              ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x102C++0x3
line.long 0x00 "PLL1_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x1030++0x3
line.long 0x00 "PLL1_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 26. " BW_DECRZ         ,Decreases loop bandwidth ranges" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22. " RELAXED_LOCK     ,Enable relaxed lock mode" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN     ,CLKOUTLDO enable" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN        ,CLKDCOLDO enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN        ,CLKOUT enable" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN     ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x1034++0x3
line.long 0x00 "PLL1_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 10. "         M2CHANGE_ACK        ,M2 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " M1CHANGE_ACK     ,M1 divider change done" "0,1"
bitfld.long 0x00 7. "         BYPASS_ACK          ,Bypass status" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN_ACK ,CLKOUTLDO enable status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x1038++0x3
line.long 0x00 "PLL1_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x103C++0x3
line.long 0x00 "PLL1_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x1040++0x3
line.long 0x00 "PLL1_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--26. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x1044++0x3
line.long 0x00 "PLL1_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x2010++0x3
line.long 0x00 "PLL2_KICK0,Lower 32-bits of PLL2 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL2 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x2014++0x3
line.long 0x00 "PLL2_KICK1,Upper 32-bits of PLL2 register write lock key This register must be written with the designated key value following a write to with its key value before PLL2 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers"
group.long 0x2020++0x3
line.long 0x00 "PLL2_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.byte 0x00 24.--31. 1. " SD_DIV           ,Sigma-Delta divider (SD)"
hexmask.long.word 0x00 8.--19. 1. "        M_INT_MULT          ,PLL feedback multiplier (M) integer part"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " N_DIV            ,PLL Input clock divider (N)"
group.long 0x2024++0x3
line.long 0x00 "PLL2_PLL_FREQ_CTRL1,PLL frequency programming values."
bitfld.long 0x00 24.--26. " SEL_FREQ_DCO     ,DCO frequency range selector 2h - HS2 mode - DCOCLK is 750 to 1500 MHz 4h - HS1 mode - DCOCLK is 1250 to 2500 MHz" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         M_FRAC_MULT         ,PLL feedback multiplier (M) fractional part"
group.long 0x2028++0x3
line.long 0x00 "PLL2_PLL_CLKDIV,Divider values for the PLL output clocks."
hexmask.long.byte 0x00 8.--14. 1. " M2_DIV           ,PLL DCO output divider (M2)"
bitfld.long 0x00 0.--3. "        M1_DIV              ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x202C++0x3
line.long 0x00 "PLL2_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x2030++0x3
line.long 0x00 "PLL2_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 26. " BW_DECRZ         ,Decreases loop bandwidth ranges" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22. " RELAXED_LOCK     ,Enable relaxed lock mode" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN     ,CLKOUTLDO enable" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN        ,CLKDCOLDO enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN        ,CLKOUT enable" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN     ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x2034++0x3
line.long 0x00 "PLL2_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 10. "         M2CHANGE_ACK        ,M2 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " M1CHANGE_ACK     ,M1 divider change done" "0,1"
bitfld.long 0x00 7. "         BYPASS_ACK          ,Bypass status" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN_ACK ,CLKOUTLDO enable status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x2038++0x3
line.long 0x00 "PLL2_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x203C++0x3
line.long 0x00 "PLL2_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x2040++0x3
line.long 0x00 "PLL2_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--26. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x2044++0x3
line.long 0x00 "PLL2_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x2120++0x3
line.long 0x00 "PLL2_HSDIV_CLKDIV,Divider values for the HSDIVIDER output clocks."
bitfld.long 0x00 24.--29. " HSDIV4           ,CLKOUT4 divider value (HSDIV4+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        HSDIV3              ,CLKOUT3 divider value (HSDIV3+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 8.--13. " HSDIV2           ,CLKOUT2 divider value (HSDIV2+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        HSDIV1              ,CLKOUT1 divider value (HSDIV1+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2124++0x3
line.long 0x00 "PLL2_HSDIV_CTRL,Controls the HSDIVIDER features and mode of operation."
bitfld.long 0x00 31. " TENABLDIV        ,Output divider load enable" "0,1"
bitfld.long 0x00 16.--20. "         SPAREIN             ,Test mode inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 3. " CLKOUT4_EN       ,CLKOUT4 enable" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN          ,CLKOUT3 enable" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUT2_EN       ,CLKOUT2 enable" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN          ,CLKOUT1 enable" "0,1"
rgroup.long 0x2128++0x3
line.long 0x00 "PLL2_HSDIV_STAT,Indicates the status of HSDIVIDER operation."
bitfld.long 0x00 16.--20. " SPAREOUT         ,Test outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "        LOCK                ,When set, indicates that all enabled output clocks are out of bypass" "0,1"
textline "                              "
bitfld.long 0x00 11. " DIV4_CHANGE_ACK  ,CLKOUT4 divider change done" "0,1"
bitfld.long 0x00 10. "         DIV3_CHANGE_ACK     ,CLKOUT3 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " DIV2_CHANGE_ACK  ,CLKOUT2 divider change done" "0,1"
bitfld.long 0x00 8. "         DIV1_CHANGE_ACK     ,CLKOUT1 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT4_EN_ACK   ,CLKOUT4 enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUT3_EN_ACK      ,CLKOUT3 enable status" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUT2_EN_ACK   ,CLKOUT2 enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUT1_EN_ACK      ,CLKOUT1 enable status" "0,1"
group.long 0x212C++0x3
line.long 0x00 "PLL2_HSDIV_PWR_CTRL,Controls HSDIVIDER power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 20. "         ISO                 ,Output isolation control" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISO latch clear" "0,1"
bitfld.long 0x00 8. "         AIPOFF              ,Set to 1 to switch off VDDA logic to prevent leakage when VDD power is off and VDDA power is active" "0,1"
textline "                              "
bitfld.long 0x00 0. " ISO_PRE_Z        ,ISO latch preset (active low)" "0,1"
rgroup.long 0x2130++0x3
line.long 0x00 "PLL2_HSDIV_PWR_STAT,Indicates the HSDIVIDER power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 14. " LDOPWDN          ,Internal LDO powerdown status" "0,1"
group.long 0x3010++0x3
line.long 0x00 "PLL3_KICK0,Lower 32-bits of PLL3 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL3 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x3014++0x3
line.long 0x00 "PLL3_KICK1,Upper 32-bits of PLL3 register write lock key This register must be written with the designated key value following a write to with its key value before PLL3 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers"
group.long 0x3020++0x3
line.long 0x00 "PLL3_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.byte 0x00 24.--31. 1. " SD_DIV           ,Sigma-Delta divider (SD)"
hexmask.long.word 0x00 8.--19. 1. "        M_INT_MULT          ,PLL feedback multiplier (M) integer part"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " N_DIV            ,PLL Input clock divider (N)"
group.long 0x3024++0x3
line.long 0x00 "PLL3_PLL_FREQ_CTRL1,PLL frequency programming values."
bitfld.long 0x00 24.--26. " SEL_FREQ_DCO     ,DCO frequency range selector 2h - HS2 mode - DCOCLK is 750 to 1500 MHz 4h - HS1 mode - DCOCLK is 1250 to 2500 MHz" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         M_FRAC_MULT         ,PLL feedback multiplier (M) fractional part"
group.long 0x3028++0x3
line.long 0x00 "PLL3_PLL_CLKDIV,Divider values for the PLL output clocks."
hexmask.long.byte 0x00 8.--14. 1. " M2_DIV           ,PLL DCO output divider (M2)"
bitfld.long 0x00 0.--3. "        M1_DIV              ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x302C++0x3
line.long 0x00 "PLL3_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x3030++0x3
line.long 0x00 "PLL3_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 26. " BW_DECRZ         ,Decreases loop bandwidth ranges" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22. " RELAXED_LOCK     ,Enable relaxed lock mode" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN     ,CLKOUTLDO enable" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN        ,CLKDCOLDO enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN        ,CLKOUT enable" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN     ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x3034++0x3
line.long 0x00 "PLL3_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 10. "         M2CHANGE_ACK        ,M2 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " M1CHANGE_ACK     ,M1 divider change done" "0,1"
bitfld.long 0x00 7. "         BYPASS_ACK          ,Bypass status" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN_ACK ,CLKOUTLDO enable status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x3038++0x3
line.long 0x00 "PLL3_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x303C++0x3
line.long 0x00 "PLL3_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x3040++0x3
line.long 0x00 "PLL3_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--26. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x3044++0x3
line.long 0x00 "PLL3_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x4010++0x3
line.long 0x00 "PLL4_KICK0,Lower 32-bits of PLL4 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL4 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x4014++0x3
line.long 0x00 "PLL4_KICK1,Upper 32-bits of PLL4 register write lock key This register must be written with the designated key value following a write to with its key value before PLL4 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers"
group.long 0x4020++0x3
line.long 0x00 "PLL4_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.byte 0x00 24.--31. 1. " SD_DIV           ,Sigma-Delta divider (SD)"
hexmask.long.word 0x00 8.--19. 1. "        M_INT_MULT          ,PLL feedback multiplier (M) integer part"
textline "                              "
hexmask.long.byte 0x00 0.--7. 1. " N_DIV            ,PLL Input clock divider (N)"
group.long 0x4024++0x3
line.long 0x00 "PLL4_PLL_FREQ_CTRL1,PLL frequency programming values."
bitfld.long 0x00 24.--26. " SEL_FREQ_DCO     ,DCO frequency range selector 2h - HS2 mode - DCOCLK is 750 to 1500 MHz 4h - HS1 mode - DCOCLK is 1250 to 2500 MHz" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         M_FRAC_MULT         ,PLL feedback multiplier (M) fractional part"
group.long 0x4028++0x3
line.long 0x00 "PLL4_PLL_CLKDIV,Divider values for the PLL output clocks."
hexmask.long.byte 0x00 8.--14. 1. " M2_DIV           ,PLL DCO output divider (M2)"
bitfld.long 0x00 0.--3. "        M1_DIV              ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x402C++0x3
line.long 0x00 "PLL4_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x4030++0x3
line.long 0x00 "PLL4_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 26. " BW_DECRZ         ,Decreases loop bandwidth ranges" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 22. " RELAXED_LOCK     ,Enable relaxed lock mode" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN     ,CLKOUTLDO enable" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN        ,CLKDCOLDO enable" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN        ,CLKOUT enable" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN     ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x4034++0x3
line.long 0x00 "PLL4_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 10. "         M2CHANGE_ACK        ,M2 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 9. " M1CHANGE_ACK     ,M1 divider change done" "0,1"
bitfld.long 0x00 7. "         BYPASS_ACK          ,Bypass status" "0,1"
textline "                              "
bitfld.long 0x00 5. " CLKOUTLDO_EN_ACK ,CLKOUTLDO enable status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x4038++0x3
line.long 0x00 "PLL4_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x403C++0x3
line.long 0x00 "PLL4_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x4040++0x3
line.long 0x00 "PLL4_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--26. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x4044++0x3
line.long 0x00 "PLL4_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x5010++0x3
line.long 0x00 "PLL5_KICK0,Lower 32-bits of PLL5 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL5 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x5014++0x3
line.long 0x00 "PLL5_KICK1,Upper 32-bits of PLL5 register write lock key This register must be written with the designated key value following a write to with its key value before PLL5 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers"
group.long 0x5020++0x3
line.long 0x00 "PLL5_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.word 0x00 8.--18. 1. " M_INT_MULT       ,PLL feedback multiplier (M) integer part"
hexmask.long.byte 0x00 0.--6. 1. "      N_DIV               ,PLL Input clock divider (N)"
group.long 0x5024++0x3
line.long 0x00 "PLL5_PLL_FREQ_CTRL1,PLL frequency programming values."
hexmask.long.tbyte 0x00 0.--17. 1. " M_FRAC_MULT      ,PLL feedback multiplier (M) fractional part"
group.long 0x5028++0x3
line.long 0x00 "PLL5_PLL_CLKDIV,Divider values for the PLL output clocks."
bitfld.long 0x00 16.--20. " M3_DIV           ,CLKOUHIF output divider (M3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        M2_DIV              ,PLL DCO output divider (M2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--3. " M1_DIV           ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x502C++0x3
line.long 0x00 "PLL5_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x5030++0x3
line.long 0x00 "PLL5_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 27. " DC_CORRECTOR_EN  ,Must be set to 1 when CLKOUT > 1.4 GHz is required" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 23. " LPMODE           ,Low power mode enable" "0,1"
bitfld.long 0x00 22. "         RELAXED_LOCK        ,Enable relaxed lock mode" "0,1"
textline "                              "
bitfld.long 0x00 21. " LOWCURRSTBY      ,IDLE/LOSSCLK relock control" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 19. " RELOCK_RAMP_EN   ,Relock clock ramp enable" "0,1"
bitfld.long 0x00 18. "         CLKINPHIF_SEL       ,CLKOUTHIF clock source select" "0,1"
textline "                              "
bitfld.long 0x00 17. " REGM4X_EN        ,Enable 4x REGM mode" "0,1"
bitfld.long 0x00 16. "         DRIFTGUARD_EN       ,Re-calibration enable" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 12.--13. "         CLKRAMP_LEVEL       ,Controls the clock ramp sequence 0h - No ramping 1h - Bypass clock to Fout/8 to Fout/4 to Fout/2 to Fout 2h - Bypass clock to Fout/4 to Fout/2 to Fout/1.5 to Fout 3h - Reserved - no ramping" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--10. " CLKRAMP_RATE     ,Controls the time spent on each ramp step 0h - 2 REFCLK periods 1h - 4 REFCLK periods 2h - 8 REFCLK periods 3h - 16 REFCLK periods 4h - 32 REFCLK periods 5h - 64 REFCLK periods 6h - 128 REFCLK periods 7h - 256 REFCLK periods" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 4. " CLKDCOLDO_EN     ,CLKDCOLDO enable" "0,1"
bitfld.long 0x00 3. "         CLKOUT_EN           ,CLKOUT enable" "0,1"
textline "                              "
bitfld.long 0x00 2. " CLKOUTX2_EN      ,CLKOUTX2 enable" "0,1"
bitfld.long 0x00 1. "         CLKOUTHIF_EN        ,CLKOUTHIF enable" "0,1"
textline "                              "
bitfld.long 0x00 0. " CLKOUTBYPASS_EN  ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x5034++0x3
line.long 0x00 "PLL5_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 11. "         M3CHANGE_ACK        ,M3 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 10. " M2CHANGE_ACK     ,M2 divider change done" "0,1"
bitfld.long 0x00 9. "         M1CHANGE_ACK        ,M1 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 7. " BYPASS_ACK       ,Bypass status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUTX2_EN_ACK     ,CLKOUTX2 enable status" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUTHIF_EN_ACK ,CLKOUTHIF enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x5038++0x3
line.long 0x00 "PLL5_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x503C++0x3
line.long 0x00 "PLL5_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x5040++0x3
line.long 0x00 "PLL5_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--25. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x5044++0x3
line.long 0x00 "PLL5_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x6010++0x3
line.long 0x00 "PLL6_KICK0,Lower 32-bits of PLL6 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL6 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x6014++0x3
line.long 0x00 "PLL6_KICK1,Upper 32-bits of PLL6 register write lock key This register must be written with the designated key value following a write to with its key value before PLL6 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers"
group.long 0x6020++0x3
line.long 0x00 "PLL6_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.word 0x00 8.--18. 1. " M_INT_MULT       ,PLL feedback multiplier (M) integer part"
hexmask.long.byte 0x00 0.--6. 1. "      N_DIV               ,PLL Input clock divider (N)"
group.long 0x6024++0x3
line.long 0x00 "PLL6_PLL_FREQ_CTRL1,PLL frequency programming values."
hexmask.long.tbyte 0x00 0.--17. 1. " M_FRAC_MULT      ,PLL feedback multiplier (M) fractional part"
group.long 0x6028++0x3
line.long 0x00 "PLL6_PLL_CLKDIV,Divider values for the PLL output clocks."
bitfld.long 0x00 16.--20. " M3_DIV           ,CLKOUHIF output divider (M3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        M2_DIV              ,PLL DCO output divider (M2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--3. " M1_DIV           ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x602C++0x3
line.long 0x00 "PLL6_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x6030++0x3
line.long 0x00 "PLL6_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 27. " DC_CORRECTOR_EN  ,Must be set to 1 when CLKOUT > 1.4 GHz is required" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 23. " LPMODE           ,Low power mode enable" "0,1"
bitfld.long 0x00 22. "         RELAXED_LOCK        ,Enable relaxed lock mode" "0,1"
textline "                              "
bitfld.long 0x00 21. " LOWCURRSTBY      ,IDLE/LOSSCLK relock control" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 19. " RELOCK_RAMP_EN   ,Relock clock ramp enable" "0,1"
bitfld.long 0x00 18. "         CLKINPHIF_SEL       ,CLKOUTHIF clock source select" "0,1"
textline "                              "
bitfld.long 0x00 17. " REGM4X_EN        ,Enable 4x REGM mode" "0,1"
bitfld.long 0x00 16. "         DRIFTGUARD_EN       ,Re-calibration enable" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 12.--13. "         CLKRAMP_LEVEL       ,Controls the clock ramp sequence 0h - No ramping 1h - Bypass clock to Fout/8 to Fout/4 to Fout/2 to Fout 2h - Bypass clock to Fout/4 to Fout/2 to Fout/1.5 to Fout 3h - Reserved - no ramping" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--10. " CLKRAMP_RATE     ,Controls the time spent on each ramp step 0h - 2 REFCLK periods 1h - 4 REFCLK periods 2h - 8 REFCLK periods 3h - 16 REFCLK periods 4h - 32 REFCLK periods 5h - 64 REFCLK periods 6h - 128 REFCLK periods 7h - 256 REFCLK periods" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 4. " CLKDCOLDO_EN     ,CLKDCOLDO enable" "0,1"
bitfld.long 0x00 3. "         CLKOUT_EN           ,CLKOUT enable" "0,1"
textline "                              "
bitfld.long 0x00 2. " CLKOUTX2_EN      ,CLKOUTX2 enable" "0,1"
bitfld.long 0x00 1. "         CLKOUTHIF_EN        ,CLKOUTHIF enable" "0,1"
textline "                              "
bitfld.long 0x00 0. " CLKOUTBYPASS_EN  ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x6034++0x3
line.long 0x00 "PLL6_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 11. "         M3CHANGE_ACK        ,M3 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 10. " M2CHANGE_ACK     ,M2 divider change done" "0,1"
bitfld.long 0x00 9. "         M1CHANGE_ACK        ,M1 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 7. " BYPASS_ACK       ,Bypass status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUTX2_EN_ACK     ,CLKOUTX2 enable status" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUTHIF_EN_ACK ,CLKOUTHIF enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x6038++0x3
line.long 0x00 "PLL6_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x603C++0x3
line.long 0x00 "PLL6_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x6040++0x3
line.long 0x00 "PLL6_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--25. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x6044++0x3
line.long 0x00 "PLL6_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
group.long 0x7010++0x3
line.long 0x00 "PLL7_KICK0,Lower 32-bits of PLL7 register write lock key This register must be written with the designated key value followed by a write to with its key value before PLL7 registers can be written."
hexmask.long 0x00 1.--31. 1. " KEY              ,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
bitfld.long 0x00 0. "  UNLOCKED            ,Unlock status." "0,1"
group.long 0x7014++0x3
line.long 0x00 "PLL7_KICK1,Upper 32-bits of PLL7 register write lock key This register must be written with the designated key value following a write to with its key value before PLL7 registers can be written."
hexmask.long 0x00 0.--31. 1. " KEY              ,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers"
group.long 0x7020++0x3
line.long 0x00 "PLL7_PLL_FREQ_CTRL0,PLL frequency programming values."
hexmask.long.word 0x00 8.--18. 1. " M_INT_MULT       ,PLL feedback multiplier (M) integer part"
hexmask.long.byte 0x00 0.--6. 1. "      N_DIV               ,PLL Input clock divider (N)"
group.long 0x7024++0x3
line.long 0x00 "PLL7_PLL_FREQ_CTRL1,PLL frequency programming values."
hexmask.long.tbyte 0x00 0.--17. 1. " M_FRAC_MULT      ,PLL feedback multiplier (M) fractional part"
group.long 0x7028++0x3
line.long 0x00 "PLL7_PLL_CLKDIV,Divider values for the PLL output clocks."
bitfld.long 0x00 16.--20. " M3_DIV           ,CLKOUHIF output divider (M3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        M2_DIV              ,PLL DCO output divider (M2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--3. " M1_DIV           ,PLL bypass output divider (M1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x702C++0x3
line.long 0x00 "PLL7_PLL_PROG,Drives the signals used to load the PLL frequency configuration values."
bitfld.long 0x00 8. " DIV_PROG         ,Output divider load enable" "0,1"
bitfld.long 0x00 0.--1. "         PROG_SM             ,PLL programming state 0h - Activation 1h - Programming IDLE state 2h - Load PLL loop values (PLL_FREQ_CTRL0, PLL_FREQ_CTRL1) 3h - Calibrate and lock" "0,1,2,3"
group.long 0x7030++0x3
line.long 0x00 "PLL7_PLL_CTRL,Controls the PLL features and mode of operation."
bitfld.long 0x00 31. " SSC_EN           ,Enable spread spectrum operation" "0,1"
bitfld.long 0x00 30. "         DOWNSPREAD          ,Spread spectrum clocking spread operation" "0,1"
textline "                              "
bitfld.long 0x00 27. " DC_CORRECTOR_EN  ,Must be set to 1 when CLKOUT > 1.4 GHz is required" "0,1"
bitfld.long 0x00 24.--25. "         BW_CONTROL          ,Loop bandwidth control 0h - BW = REFCLK/30 to REFCLK/70 1h - BW = REFCLK/60 to REFCLK/10 2h - BW = REFCLK/120 to REFCLK/280 3h - BW = REFCLK/240 to REFCLK/560" "0,1,2,3"
textline "                              "
bitfld.long 0x00 23. " LPMODE           ,Low power mode enable" "0,1"
bitfld.long 0x00 22. "         RELAXED_LOCK        ,Enable relaxed lock mode" "0,1"
textline "                              "
bitfld.long 0x00 21. " LOWCURRSTBY      ,IDLE/LOSSCLK relock control" "0,1"
bitfld.long 0x00 20. "         CYCLESLIP_EN        ,Enable recalibration on cycle slip between REFCLK and Feedback clock" "0,1"
textline "                              "
bitfld.long 0x00 19. " RELOCK_RAMP_EN   ,Relock clock ramp enable" "0,1"
bitfld.long 0x00 18. "         CLKINPHIF_SEL       ,CLKOUTHIF clock source select" "0,1"
textline "                              "
bitfld.long 0x00 17. " REGM4X_EN        ,Enable 4x REGM mode" "0,1"
bitfld.long 0x00 16. "         DRIFTGUARD_EN       ,Re-calibration enable" "0,1"
textline "                              "
bitfld.long 0x00 15. " ULOWCLK_EN       ,Bypass mode clock select" "0,1"
bitfld.long 0x00 12.--13. "         CLKRAMP_LEVEL       ,Controls the clock ramp sequence 0h - No ramping 1h - Bypass clock to Fout/8 to Fout/4 to Fout/2 to Fout 2h - Bypass clock to Fout/4 to Fout/2 to Fout/1.5 to Fout 3h - Reserved - no ramping" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--10. " CLKRAMP_RATE     ,Controls the time spent on each ramp step 0h - 2 REFCLK periods 1h - 4 REFCLK periods 2h - 8 REFCLK periods 3h - 16 REFCLK periods 4h - 32 REFCLK periods 5h - 64 REFCLK periods 6h - 128 REFCLK periods 7h - 256 REFCLK periods" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "         IDLE                ,Set PLL in idle mode" "0,1"
textline "                              "
bitfld.long 0x00 4. " CLKDCOLDO_EN     ,CLKDCOLDO enable" "0,1"
bitfld.long 0x00 3. "         CLKOUT_EN           ,CLKOUT enable" "0,1"
textline "                              "
bitfld.long 0x00 2. " CLKOUTX2_EN      ,CLKOUTX2 enable" "0,1"
bitfld.long 0x00 1. "         CLKOUTHIF_EN        ,CLKOUTHIF enable" "0,1"
textline "                              "
bitfld.long 0x00 0. " CLKOUTBYPASS_EN  ,CLKOUTBYPASS enable" "0,1"
rgroup.long 0x7034++0x3
line.long 0x00 "PLL7_PLL_STAT,Indicates the status of PLL operation."
bitfld.long 0x00 31. " SS_ACK           ,Spread spectrum clocking status" "0,1"
bitfld.long 0x00 27. "         RECAL               ,Internal recalibration required" "0,1"
textline "                              "
bitfld.long 0x00 26. " LOSSREF          ,Reference input loss indicator" "0,1"
bitfld.long 0x00 25. "         FREQLOCK            ,PLL is in frequency lock" "0,1"
textline "                              "
bitfld.long 0x00 24. " PHASELOCK        ,PLL is in phase lock" "0,1"
bitfld.long 0x00 23. "         HIGHJITTER          ,High jitter status" "0,1"
textline "                              "
bitfld.long 0x00 22. " LOCK2            ,ADPLL internal loop lock status" "0,1"
bitfld.long 0x00 20. "         TVALID              ,Valid phase lock indicator" "0,1"
textline "                              "
bitfld.long 0x00 15. " BYPASS_CLKTYPE   ,Bypass mode CLK source indicator" "0,1"
bitfld.long 0x00 11. "         M3CHANGE_ACK        ,M3 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 10. " M2CHANGE_ACK     ,M2 divider change done" "0,1"
bitfld.long 0x00 9. "         M1CHANGE_ACK        ,M1 divider change done" "0,1"
textline "                              "
bitfld.long 0x00 7. " BYPASS_ACK       ,Bypass status" "0,1"
bitfld.long 0x00 4. "         CLKDCOLDO_EN_ACK    ,CLKDCOLDO enable status" "0,1"
textline "                              "
bitfld.long 0x00 3. " CLKOUT_EN_ACK    ,CLKOUT enable status" "0,1"
bitfld.long 0x00 2. "         CLKOUTX2_EN_ACK     ,CLKOUTX2 enable status" "0,1"
textline "                              "
bitfld.long 0x00 1. " CLKOUTHIF_EN_ACK ,CLKOUTHIF enable status" "0,1"
bitfld.long 0x00 0. "         CLKOUTBYPASS_EN_ACK ,CLKOUTBYPASS enable status" "0,1"
group.long 0x7038++0x3
line.long 0x00 "PLL7_PLL_PWR_CTRL,Controls PLL power features."
bitfld.long 0x00 31. " PONIN            ,Weak power switch control" "0,1"
bitfld.long 0x00 30. "         PGOODIN             ,Strong power switch control" "0,1"
textline "                              "
bitfld.long 0x00 23. " RET              ,Retention mode control (digital)" "0,1"
bitfld.long 0x00 21. "         ISOSCAN             ,LDO domain testmode scan pin control" "0,1"
textline "                              "
bitfld.long 0x00 20. " ISORET           ,Output pin isolation control" "0,1"
bitfld.long 0x00 17. "         ISOSCAN_CLR         ,ISOSCAN latch clear" "0,1"
textline "                              "
bitfld.long 0x00 16. " ISO_CLR          ,ISORET latch clear" "0,1"
bitfld.long 0x00 8. "         OFFMODE             ,VDDA logic powerdown" "0,1"
textline "                              "
bitfld.long 0x00 1. " ISOSCAN_PRE_Z    ,ISOSCAN latch preset" "0,1"
bitfld.long 0x00 0. "         ISO_PRE_Z           ,ISORET latch preset" "0,1"
rgroup.long 0x703C++0x3
line.long 0x00 "PLL7_PLL_PWR_STAT,Indicates the PLL power state."
bitfld.long 0x00 31. " PONOUT           ,Weak power switch status" "0,1"
bitfld.long 0x00 30. "         PGOODOUT            ,Strong power switch status" "0,1"
textline "                              "
bitfld.long 0x00 15. " TICOPWDN         ,Core DCO power down status" "0,1"
bitfld.long 0x00 14. "         LDOPWDN             ,Internal LDO powerdown status" "0,1"
group.long 0x7040++0x3
line.long 0x00 "PLL7_PLL_SS_SPREAD,Defines the frequency spread when spread spectrum clocking is enabled."
bitfld.long 0x00 24.--25. " DELTA_MSTEP_INT  ,Spread spectrum spread control integer part" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "         DELTA_MSTEP_FRAC    ,Spread spectrum spread control fractional part"
group.long 0x7044++0x3
line.long 0x00 "PLL7_PLL_SS_MODFREQ,Defines the modulation frequency when spread spectrum clocking is enabled."
bitfld.long 0x00 8.--10. " MODFREQ_DIV_EXP  ,Spread spectrum modulation frequency REFCLK divider exponent" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--6. 1. "         MODFREQ_DIV_MANT    ,Spread spectrum modulation frequency REFCLK divider mantissa"
width 0x0B
tree.end
tree "PLLCTRL0"
base ad:0x410000
width 23.
rgroup.long 0x0++0x3
line.long 0x00 "PLLCTRL0_PID,register"
hexmask.long.word 0x00 16.--31. 1. " PID_MSB16    ,"
bitfld.long 0x00 11.--15. "  PID_MISC   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 8.--10. " PID_MAJOR    ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     PID_CUSTOM ," "0,1,2,3"
textline "                                "
bitfld.long 0x00 0.--5. " PID_MINOR    ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD0++0x3
line.long 0x00 "PLLCTRL0_SHIFTDIV,Shift divider register"
hexmask.long.byte 0x00 0.--7. 1. " DIV_VALUE    ,"
group.long 0xD4++0x3
line.long 0x00 "PLLCTRL0_CS0,Catscan control register"
bitfld.long 0x00 0. " CS_CLK_START ," "0,1"
group.long 0xD8++0x3
line.long 0x00 "PLLCTRL0_DFTFCNTR,DFT frequency counter register"
hexmask.long.word 0x00 16.--31. 1. " PLLREFCNT    ,"
hexmask.long.word 0x00 0.--15. 1. "  PLLCNT     ,"
group.long 0xDC++0x3
line.long 0x00 "PLLCTRL0_DFTFCNTRCNTL,DFT frequency counter control register"
bitfld.long 0x00 4.--7. " CLKMUX       ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "    STATUS     ," "0,1"
textline "                                "
bitfld.long 0x00 0. " START        ," "0,1"
rgroup.long 0xE0++0x3
line.long 0x00 "PLLCTRL0_FUSERR,Fusefarm error register"
bitfld.long 0x00 0.--4. " ERR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xE4++0x3
line.long 0x00 "PLLCTRL0_RSTYPE,Reset type status register"
bitfld.long 0x00 29. " EMU1         ," "0,1"
bitfld.long 0x00 28. "     EMU0       ," "0,1"
textline "                                "
hexmask.long.byte 0x00 8.--15. 1. " RSTREQ       ,"
bitfld.long 0x00 2. "    PLLCNTL    ," "0,1"
textline "                                "
bitfld.long 0x00 1. " RSTIN        ," "0,1"
bitfld.long 0x00 0. "     POR        ," "0,1"
group.long 0xE8++0x3
line.long 0x00 "PLLCTRL0_RSCTRL,Reset control register"
bitfld.long 0x00 16. " SWRST        ," "0,1"
hexmask.long.word 0x00 0.--15. 1. "     KEY        ,"
group.long 0xEC++0x3
line.long 0x00 "PLLCTRL0_RSCFG,Reset control register"
bitfld.long 0x00 29. " PLLCNTLBLOCK ," "0,1"
hexmask.long.byte 0x00 16.--23. 1. "     RSTBLOCK   ,"
textline "                                "
bitfld.long 0x00 13. " PLLCTRLSOFT  ," "0,1"
bitfld.long 0x00 12. "     RSTPITYPE  ," "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " RSTREQTYPE   ,"
group.long 0xF0++0x3
line.long 0x00 "PLLCTRL0_RSISO,Reset isolation control register"
hexmask.long.word 0x00 0.--15. 1. " SYSCLKISO    ,"
group.long 0x100++0x3
line.long 0x00 "PLLCTRL0_PLLCTL,PLL control register"
bitfld.long 0x00 9. " EXCLKSRC     ," "0,1"
bitfld.long 0x00 8. "     CLKMODE    ," "0,1"
textline "                                "
bitfld.long 0x00 7. " PLLSELB      ," "0,1"
bitfld.long 0x00 5. "     PLLENSRC   ," "0,1"
textline "                                "
bitfld.long 0x00 4. " PLLDIS       ," "0,1"
bitfld.long 0x00 3. "     PLLRST     ," "0,1"
textline "                                "
bitfld.long 0x00 1. " PLLPWRDN     ," "0,1"
bitfld.long 0x00 0. "     PLLEN      ," "0,1"
group.long 0x110++0x3
line.long 0x00 "PLLCTRL0_PLLM,PLL multiplier control register"
hexmask.long.byte 0x00 0.--7. 1. " _            ,"
group.long 0x118++0x3
line.long 0x00 "PLLCTRL0_PLLDIV1,PLL controller divider1 control register"
bitfld.long 0x00 15. " DN_EN        ," "0,1"
bitfld.long 0x00 14. "     HALF_RATIO ," "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " RATIO        ,"
group.long 0x11C++0x3
line.long 0x00 "PLLCTRL0_PLLDIV2,PLL controller divider2 control register"
bitfld.long 0x00 15. " DN_EN        ," "0,1"
bitfld.long 0x00 14. "     HALF_RATIO ," "0,1"
textline "                                "
hexmask.long.byte 0x00 0.--7. 1. " RATIO        ,"
group.long 0x12C++0x3
line.long 0x00 "PLLCTRL0_BPDIV,Bypass divider register"
bitfld.long 0x00 15. " BPDEN        ," "0,1"
hexmask.long.byte 0x00 0.--7. 1. "     RATIO      ,"
group.long 0x130++0x3
line.long 0x00 "PLLCTRL0_WAKEUP,Wakeup register"
hexmask.long.word 0x00 0.--15. 1. " WKEN         ,"
group.long 0x138++0x3
line.long 0x00 "PLLCTRL0_PLLCMD,PLL Controller command register"
bitfld.long 0x00 1. " OSCPWRDN     ," "0,1"
bitfld.long 0x00 0. "     GOSET      ," "0,1"
rgroup.long 0x13C++0x3
line.long 0x00 "PLLCTRL0_PLLSTAT,PLL Controller status register"
bitfld.long 0x00 2. " STABLE       ," "0,1"
bitfld.long 0x00 1. "     LOCK       ," "0,1"
textline "                                "
bitfld.long 0x00 0. " GOSET        ," "0,1"
group.long 0x140++0x3
line.long 0x00 "PLLCTRL0_ALNCTL,PLL Controller clock align control register"
hexmask.long.word 0x00 1.--15. 1. " ALN          ,"
bitfld.long 0x00 0. "  ALN1       ," "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "PLLCTRL0_DCHANGE,PLLDIV ratio change register"
hexmask.long.word 0x00 1.--15. 1. " SYS          ,"
bitfld.long 0x00 0. "  SYS1       ," "0,1"
rgroup.long 0x150++0x3
line.long 0x00 "PLLCTRL0_SYSTAT,Sysclk status register"
bitfld.long 0x00 1. " SYS2_ON      ," "0,1"
bitfld.long 0x00 0. "     SYS1_ON    ," "0,1"
width 0x0B
tree.end
tree "WKUP_PLLCTRL0"
base ad:0x42010000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "WKUP_PLLCTRL0_PID,register"
hexmask.long.word 0x00 16.--31. 1. " PID_MSB16    ,"
bitfld.long 0x00 11.--15. "  PID_MISC   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                     "
bitfld.long 0x00 8.--10. " PID_MAJOR    ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     PID_CUSTOM ," "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--5. " PID_MINOR    ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD0++0x3
line.long 0x00 "WKUP_PLLCTRL0_SHIFTDIV,Shift divider register"
hexmask.long.byte 0x00 0.--7. 1. " DIV_VALUE    ,"
group.long 0xD4++0x3
line.long 0x00 "WKUP_PLLCTRL0_CS0,Catscan control register"
bitfld.long 0x00 0. " CS_CLK_START ," "0,1"
group.long 0xD8++0x3
line.long 0x00 "WKUP_PLLCTRL0_DFTFCNTR,DFT frequency counter register"
hexmask.long.word 0x00 16.--31. 1. " PLLREFCNT    ,"
hexmask.long.word 0x00 0.--15. 1. "  PLLCNT     ,"
group.long 0xDC++0x3
line.long 0x00 "WKUP_PLLCTRL0_DFTFCNTRCNTL,DFT frequency counter control register"
bitfld.long 0x00 4.--7. " CLKMUX       ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "    STATUS     ," "0,1"
textline "                                     "
bitfld.long 0x00 0. " START        ," "0,1"
rgroup.long 0xE0++0x3
line.long 0x00 "WKUP_PLLCTRL0_FUSERR,Fusefarm error register"
bitfld.long 0x00 0.--4. " ERR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xE4++0x3
line.long 0x00 "WKUP_PLLCTRL0_RSTYPE,Reset type status register"
bitfld.long 0x00 29. " EMU1         ," "0,1"
bitfld.long 0x00 28. "     EMU0       ," "0,1"
textline "                                     "
hexmask.long.byte 0x00 8.--15. 1. " RSTREQ       ,"
bitfld.long 0x00 2. "    PLLCNTL    ," "0,1"
textline "                                     "
bitfld.long 0x00 1. " RSTIN        ," "0,1"
bitfld.long 0x00 0. "     POR        ," "0,1"
group.long 0xE8++0x3
line.long 0x00 "WKUP_PLLCTRL0_RSCTRL,Reset control register"
bitfld.long 0x00 16. " SWRST        ," "0,1"
hexmask.long.word 0x00 0.--15. 1. "     KEY        ,"
group.long 0xEC++0x3
line.long 0x00 "WKUP_PLLCTRL0_RSCFG,Reset control register"
bitfld.long 0x00 29. " PLLCNTLBLOCK ," "0,1"
hexmask.long.byte 0x00 16.--23. 1. "     RSTBLOCK   ,"
textline "                                     "
bitfld.long 0x00 13. " PLLCTRLSOFT  ," "0,1"
bitfld.long 0x00 12. "     RSTPITYPE  ," "0,1"
textline "                                     "
hexmask.long.byte 0x00 0.--7. 1. " RSTREQTYPE   ,"
group.long 0xF0++0x3
line.long 0x00 "WKUP_PLLCTRL0_RSISO,Reset isolation control register"
hexmask.long.word 0x00 0.--15. 1. " SYSCLKISO    ,"
group.long 0x100++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLCTL,PLL control register"
bitfld.long 0x00 9. " EXCLKSRC     ," "0,1"
bitfld.long 0x00 8. "     CLKMODE    ," "0,1"
textline "                                     "
bitfld.long 0x00 7. " PLLSELB      ," "0,1"
bitfld.long 0x00 5. "     PLLENSRC   ," "0,1"
textline "                                     "
bitfld.long 0x00 4. " PLLDIS       ," "0,1"
bitfld.long 0x00 3. "     PLLRST     ," "0,1"
textline "                                     "
bitfld.long 0x00 1. " PLLPWRDN     ," "0,1"
bitfld.long 0x00 0. "     PLLEN      ," "0,1"
group.long 0x110++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLM,PLL multiplier control register"
hexmask.long.byte 0x00 0.--7. 1. " _            ,"
group.long 0x118++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLDIV1,PLL controller divider1 control register"
bitfld.long 0x00 15. " DN_EN        ," "0,1"
bitfld.long 0x00 14. "     HALF_RATIO ," "0,1"
textline "                                     "
hexmask.long.byte 0x00 0.--7. 1. " RATIO        ,"
group.long 0x11C++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLDIV2,PLL controller divider2 control register"
bitfld.long 0x00 15. " DN_EN        ," "0,1"
bitfld.long 0x00 14. "     HALF_RATIO ," "0,1"
textline "                                     "
hexmask.long.byte 0x00 0.--7. 1. " RATIO        ,"
group.long 0x12C++0x3
line.long 0x00 "WKUP_PLLCTRL0_BPDIV,Bypass divider register"
bitfld.long 0x00 15. " BPDEN        ," "0,1"
hexmask.long.byte 0x00 0.--7. 1. "     RATIO      ,"
group.long 0x130++0x3
line.long 0x00 "WKUP_PLLCTRL0_WAKEUP,Wakeup register"
hexmask.long.word 0x00 0.--15. 1. " WKEN         ,"
group.long 0x138++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLCMD,PLL Controller command register"
bitfld.long 0x00 1. " OSCPWRDN     ," "0,1"
bitfld.long 0x00 0. "     GOSET      ," "0,1"
rgroup.long 0x13C++0x3
line.long 0x00 "WKUP_PLLCTRL0_PLLSTAT,PLL Controller status register"
bitfld.long 0x00 2. " STABLE       ," "0,1"
bitfld.long 0x00 1. "     LOCK       ," "0,1"
textline "                                     "
bitfld.long 0x00 0. " GOSET        ," "0,1"
group.long 0x140++0x3
line.long 0x00 "WKUP_PLLCTRL0_ALNCTL,PLL Controller clock align control register"
hexmask.long.word 0x00 1.--15. 1. " ALN          ,"
bitfld.long 0x00 0. "  ALN1       ," "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "WKUP_PLLCTRL0_DCHANGE,PLLDIV ratio change register"
hexmask.long.word 0x00 1.--15. 1. " SYS          ,"
bitfld.long 0x00 0. "  SYS1       ," "0,1"
rgroup.long 0x150++0x3
line.long 0x00 "WKUP_PLLCTRL0_SYSTAT,Sysclk status register"
bitfld.long 0x00 1. " SYS2_ON      ," "0,1"
bitfld.long 0x00 0. "     SYS1_ON    ," "0,1"
width 0x0B
tree.end
tree.end
tree "MCU_CPSW"
tree "MCU_CPSW0_NUSS"
base ad:0x46000000
width 38.
rgroup.long 0x0++0x3
line.long 0x00 "CPSW0_CPSW_NUSS_IDVER_REG,ID Version Register"
hexmask.long.word 0x00 16.--31. 1. " IDENT                                 ,Identification value"
bitfld.long 0x00 11.--15. "      RTL_VER                               ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " MAJOR_VER                             ,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER                             ,Minor version value"
group.long 0x4++0x3
line.long 0x00 "CPSW0_SYNCE_COUNT_REG,SyncE Count Register"
hexmask.long 0x00 0.--31. 1. " SYNCE_CNT                             ,Sync E Count Value"
group.long 0x8++0x3
line.long 0x00 "CPSW0_SYNCE_MUX_REG,SyncE Mux Register"
bitfld.long 0x00 0.--5. " SYNCE_SEL                             ,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "CPSW0_SGMII_MODE_REG,SyncE Mux Register"
bitfld.long 0x00 0. " SYNCE_SEL                             ,SGMII_MODE Input" "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "CPSW0_RGMII_STATUS_REG,RGMII Status Register"
bitfld.long 0x00 3. " FULLDUPLEX                            ,Rgmii full dulex: 0=Half-duplex, 1=Full-duplex" "0,1"
bitfld.long 0x00 1.--2. "         SPEED                                 ,Rgmii speed: 00=10Mbps, 01=100Mbps, 10=1000Mbps, 11=reserved" "0,1,2,3"
textline "                                               "
bitfld.long 0x00 0. " LINK                                  ,Rgmii link indicator: 0=Link is down, 1=Link is up" "0,1"
rgroup.long 0x1C++0x3
line.long 0x00 "CPSW0_SUBSSYSTEM_STATUS_REG,Subsystem Status Register"
bitfld.long 0x00 0. " EEE_CLKSTOP_ACK                       ,Energy Efficient Ethernet clockstop acknowledge from MCU_CPSW0_NUSS" "0,1"
rgroup.long 0x100++0x3
line.long 0x00 "CPSW0_SGMII_IDVER_REG,SGMII Identification and Version Register."
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT                              ,"
bitfld.long 0x00 11.--15. "      RTL_VER                               ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " MAJOR_VER                             ,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER                             ,Minor version value"
group.long 0x104++0x3
line.long 0x00 "CPSW0_SOFT_RESET_REG,Software Reset Register."
bitfld.long 0x00 1. " RT_SOFT_RESET                         ,Transmit and receive software reset" "0,1"
bitfld.long 0x00 0. "         SOFT_RESET                            ,Software reset" "0,1"
rgroup.long 0x114++0x3
line.long 0x00 "CPSW0_STATUS_REG,Status Register."
bitfld.long 0x00 5. " FIB_SIG_DETECT                        ,Fiber signal detect" "0,1"
bitfld.long 0x00 4. "         LOCK                                  ,Lock" "0,1"
textline "                                               "
bitfld.long 0x00 3. " MR_PAGE_RX                            ,Next page received" "0,1"
bitfld.long 0x00 2. "         MR_AN_COMPLETE                        ,Auto-negotiation complete" "0,1"
textline "                                               "
bitfld.long 0x00 1. " AN_ERROR                              ,Auto-negotiation error" "0,1"
bitfld.long 0x00 0. "         LINK                                  ,Link indicator" "0,1"
group.long 0x118++0x3
line.long 0x00 "CPSW0_MR_ADV_ABILITY_REG,Advertised Ability Register."
hexmask.long.word 0x00 0.--15. 1. " MR_ADV_ABILITY                        ,Advertised ability"
group.long 0x11C++0x3
line.long 0x00 "CPSW0_MR_NP_TX_REG,Transmit Next Page Register."
hexmask.long.word 0x00 0.--15. 1. " MR_NP_TX                              ,Next page transmit"
rgroup.long 0x120++0x3
line.long 0x00 "CPSW0_MR_LP_ADV_ABILITY_REG,Link Partner Advertised Ability."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_ADV_ABILITY                     ,Link partner advertised ability"
rgroup.long 0x124++0x3
line.long 0x00 "CPSW0_MR_LP_NP_RX_REG,Link Partner Receive Next Page Register."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_NP_RX                           ,Link Partner Next Page Received"
group.long 0x130++0x3
line.long 0x00 "CPSW0_TX_CFG_REG,"
hexmask.long 0x00 0.--31. 1. " TX_CFG                                ,Transmit configuration register output"
group.long 0x134++0x3
line.long 0x00 "CPSW0_RX_CFG_REG,"
hexmask.long 0x00 0.--31. 1. " RX_CFG                                ,Receive configuration register output"
group.long 0x138++0x3
line.long 0x00 "CPSW0_AUX_CFG_REG,"
hexmask.long 0x00 0.--31. 1. " AUX_CFG                               ,Auxiliary configuration register output"
group.long 0x140++0x3
line.long 0x00 "CPSW0_DIAG_CLEAR_REG,"
bitfld.long 0x00 0. " DIAG_CLEAR                            ,Diagnostics clear" "0,1"
group.long 0x144++0x3
line.long 0x00 "CPSW0_DIAG_CONTROL_REG,"
bitfld.long 0x00 4.--6. " DIAG_SM_SEL                           ,Diagnostic select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "         DIAG_EDGE_SEL                         ,Diagnostics hold signals edge select" "0,1,2,3"
rgroup.long 0x148++0x3
line.long 0x00 "CPSW0_DIAG_STATUS_REG,"
hexmask.long.word 0x00 0.--15. 1. " DIAG_STATUS                           ,Diagnostics status"
rgroup.long 0xF00++0x3
line.long 0x00 "CPSW0_MDIO_VERSION_REG,version_reg"
bitfld.long 0x00 30.--31. " SCHEME                                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                                    ,bu" "0,1,2,3"
textline "                                               "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                             ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL                                ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " REVMAJ                                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                ,Custom version" "0,1,2,3"
textline "                                               "
bitfld.long 0x00 0.--5. " REVMIN                                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x3
line.long 0x00 "CPSW0_MDIO_CONTROL_REG,"
bitfld.long 0x00 31. " IDLE                                  ,MDIO state machine idle" "0,1"
bitfld.long 0x00 30. "         ENABLE                                ,Enable" "0,1"
textline "                                               "
bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL                  ,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "        PREAMBLE                              ,Preamble disable" "0,1"
textline "                                               "
bitfld.long 0x00 19. " FAULT                                 ,Fault indicator" "0,1"
bitfld.long 0x00 18. "         FAULT_DETECT_ENABLE                   ,Fault detect enable" "0,1"
textline "                                               "
bitfld.long 0x00 17. " INT_TEST_ENABLE                       ,Interrupt test enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         CLKDIV                                ,Clock divider"
group.long 0xF08++0x3
line.long 0x00 "CPSW0_ALIVE_REG,MDIO PHY Acknowledge Status Register"
hexmask.long 0x00 0.--31. 1. " ALIVE                                 ,MDIO alive"
rgroup.long 0xF0C++0x3
line.long 0x00 "CPSW0_LINK_REG,"
hexmask.long 0x00 0.--31. 1. " LINK                                  ,MDIO link state"
group.long 0xF10++0x3
line.long 0x00 "CPSW0_LINK_INT_RAW_REG,"
bitfld.long 0x00 0.--1. " LINKINTRAW                            ,MDIO link change event raw value" "0,1,2,3"
group.long 0xF14++0x3
line.long 0x00 "CPSW0_LINK_INT_MASKED_REG,"
bitfld.long 0x00 0.--1. " LINKINTMASKED                         ,MDIO link change interrupt masked value" "0,1,2,3"
group.long 0xF18++0x3
line.long 0x00 "CPSW0_LINK_INT_MASK_SET_REG,"
bitfld.long 0x00 0. " LINKINTMASKSET                        ,MDIO link interrupt mask set" "0,1"
group.long 0xF1C++0x3
line.long 0x00 "CPSW0_LINK_INT_MASK_CLEAR_REG,"
bitfld.long 0x00 0. " LINKINTMASKCLR                        ,MDIO link interrupt mask clear" "0,1"
group.long 0xF20++0x3
line.long 0x00 "CPSW0_USER_INT_RAW_REG,"
bitfld.long 0x00 0.--1. " USERINTRAW                            ,User interrupt raw" "0,1,2,3"
group.long 0xF24++0x3
line.long 0x00 "CPSW0_USER_INT_MASKED_REG,"
bitfld.long 0x00 0.--1. " USERINTMASKED                         ,User interrupt masked" "0,1,2,3"
group.long 0xF28++0x3
line.long 0x00 "CPSW0_USER_INT_MASK_SET_REG,"
bitfld.long 0x00 0.--1. " USERINTMASKSET                        ,MDIO user interrupt mask set" "0,1,2,3"
group.long 0xF2C++0x3
line.long 0x00 "CPSW0_USER_INT_MASK_CLEAR_REG,"
bitfld.long 0x00 0.--1. " USERINTMASKCLR                        ,MDIO user interrupt mask clear" "0,1,2,3"
group.long 0xF30++0x3
line.long 0x00 "CPSW0_MANUAL_IF_REG,"
bitfld.long 0x00 2. " MDIO_MDCLK_O                          ,MDIO Clock Output" "0,1"
bitfld.long 0x00 1. "         MDIO_OE                               ,MDIO Output Enable" "0,1"
textline "                                               "
bitfld.long 0x00 0. " MDIO_PIN                              ,MDIO Pin" "0,1"
group.long 0xF34++0x3
line.long 0x00 "CPSW0_POLL_REG,"
bitfld.long 0x00 31. " MANUALMODE                            ,MDIO Manual Mode" "0,1"
bitfld.long 0x00 30. "         STATECHANGEMODE                       ,MDIO State Change Mode" "0,1"
textline "                                               "
hexmask.long.byte 0x00 0.--7. 1. " IPG                                   ,MDIO IPG"
group.long 0xF38++0x3
line.long 0x00 "CPSW0_POLL_EN_REG,"
hexmask.long 0x00 0.--31. 1. " POLL_EN                               ,MDIO Poll Enable"
group.long 0xF3C++0x3
line.long 0x00 "CPSW0_CLAUS45_REG,Clause 45 enable register."
hexmask.long 0x00 0.--31. 1. " CLAUSE45                              ,MDIO Clause 45"
group.long 0xF40++0x3
line.long 0x00 "CPSW0_USER_ADDR0_REG,"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR0                            ,MDIO USER Address 0"
group.long 0xF44++0x3
line.long 0x00 "CPSW0_USER_ADDR1_REG,"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR1                            ,MDIO USER Address 1"
group.long 0xF80++0x3
line.long 0x00 "CPSW0_USER_ACCESS_REG_k,user_access_reg Offset = F80h + (k * 8h); where k = 0h to 1h"
bitfld.long 0x00 31. " GO                                    ,Go" "0,1"
bitfld.long 0x00 30. "         WRITE                                 ,Write" "0,1"
textline "                                               "
bitfld.long 0x00 29. " ACK                                   ,Acknowledge" "0,1"
bitfld.long 0x00 21.--25. "         REGADR                                ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 16.--20. " PHYADR                                ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "        DATA                                  ,User data"
group.long 0xF84++0x3
line.long 0x00 "CPSW0_USER_PHY_SEL_REG_k,user_phy_sel_reg Offset = F84h + (k * 8h); where k = 0h to 1h"
bitfld.long 0x00 7. " LINKSEL                               ,Link status determination select" "0,1"
bitfld.long 0x00 6. "         LINKINT_ENABLE                        ,Link change interrupt enable" "0,1"
textline "                                               "
bitfld.long 0x00 0.--4. " PHYADR_MON                            ,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x1000++0x3
line.long 0x00 "CPSW0_REVISION,Revision Register"
bitfld.long 0x00 30.--31. " SCHEME                                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                                    ,BU" "0,1,2,3"
textline "                                               "
hexmask.long.word 0x00 16.--27. 1. " FUNCTION                              ,Module ID"
bitfld.long 0x00 11.--15. "      RTLVER                                ,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " MAJREV                                ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                ,Custom" "0,1,2,3"
textline "                                               "
bitfld.long 0x00 0.--5. " MINREV                                ,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1010++0x3
line.long 0x00 "CPSW0_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. " EOI_VECTOR                            ,End of Interrupt Vector"
rgroup.long 0x1014++0x3
line.long 0x00 "CPSW0_INTR_VECTOR_REG,Interrupt Vector Register"
hexmask.long 0x00 0.--31. 1. " INTR_VECTOR                           ,Interrupt Vector Register"
group.long 0x1100++0x3
line.long 0x00 "CPSW0_ENABLE_REG_EVNT_PULSE0_0,Enable Register 0"
bitfld.long 0x00 2. " ENABLE_EVNT_PULSE0_EN_STAT_LEVEL1     ,Enable Set for evnt_pulse0_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         ENABLE_EVNT_PULSE0_EN_STAT_LEVEL0     ,Enable Set for evnt_pulse0_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " ENABLE_EVNT_PULSE0_EN_EVNT_LEVEL0     ,Enable Set for evnt_pulse0_en_evnt_level0" "0,1"
group.long 0x1104++0x3
line.long 0x00 "CPSW0_ENABLE_REG_STAT_PULSE0_0,Enable Register 1"
bitfld.long 0x00 2. " ENABLE_STAT_PULSE0_EN_STAT_LEVEL1     ,Enable Set for stat_pulse0_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         ENABLE_STAT_PULSE0_EN_STAT_LEVEL0     ,Enable Set for stat_pulse0_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " ENABLE_STAT_PULSE0_EN_EVNT_LEVEL0     ,Enable Set for stat_pulse0_en_evnt_level0" "0,1"
group.long 0x1108++0x3
line.long 0x00 "CPSW0_ENABLE_REG_STAT_PULSE1_0,Enable Register 2"
bitfld.long 0x00 2. " ENABLE_STAT_PULSE1_EN_STAT_LEVEL1     ,Enable Set for stat_pulse1_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         ENABLE_STAT_PULSE1_EN_STAT_LEVEL0     ,Enable Set for stat_pulse1_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " ENABLE_STAT_PULSE1_EN_EVNT_LEVEL0     ,Enable Set for stat_pulse1_en_evnt_level0" "0,1"
hgroup.long 0x1300++0x3
hide.long 0x00 "CPSW0_ENABLE_CLR_REG_EVNT_PULSE0_0,Enable Clear Register 0"
in
textline "                                               "
hgroup.long 0x1304++0x3
hide.long 0x00 "CPSW0_ENABLE_CLR_REG_STAT_PULSE0_0,Enable Clear Register 1"
in
textline "                                               "
hgroup.long 0x1308++0x3
hide.long 0x00 "CPSW0_ENABLE_CLR_REG_STAT_PULSE1_0,Enable Clear Register 2"
in
textline "                                               "
rgroup.long 0x1500++0x3
line.long 0x00 "CPSW0_STATUS_REG_EVNT_PULSE0_0,Status Register 0"
bitfld.long 0x00 2. " STATUS_EVNT_PULSE0_STAT_LEVEL1        ,Status for evnt_pulse0_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         STATUS_EVNT_PULSE0_STAT_LEVEL0        ,Status for evnt_pulse0_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " STATUS_EVNT_PULSE0_EVNT_LEVEL0        ,Status for evnt_pulse0_en_evnt_level0" "0,1"
rgroup.long 0x1504++0x3
line.long 0x00 "CPSW0_STATUS_REG_STAT_PULSE0_0,Status Register 1"
bitfld.long 0x00 2. " STATUS_STAT_PULSE0_STAT_LEVEL1        ,Status for stat_pulse0_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         STATUS_STAT_PULSE0_STAT_LEVEL0        ,Status for stat_pulse0_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " STATUS_STAT_PULSE0_EVNT_LEVEL0        ,Status for stat_pulse0_en_evnt_level0" "0,1"
rgroup.long 0x1508++0x3
line.long 0x00 "CPSW0_STATUS_REG_STAT_PULSE1_0,Status Register 2"
bitfld.long 0x00 2. " STATUS_STAT_PULSE1_STAT_LEVEL1        ,Status for stat_pulse1_en_stat_level1" "0,1"
bitfld.long 0x00 1. "         STATUS_STAT_PULSE1_STAT_LEVEL0        ,Status for stat_pulse1_en_stat_level0" "0,1"
textline "                                               "
bitfld.long 0x00 0. " STATUS_STAT_PULSE1_EVNT_LEVEL0        ,Status for stat_pulse1_en_evnt_level0" "0,1"
rgroup.long 0x1A80++0x3
line.long 0x00 "CPSW0_INTR_VECTOR_REG_EVNT_PULSE0,Interrupt Vector for evnt_pulse0"
hexmask.long 0x00 0.--31. 1. " INTR_VECTOR_EVNT_PULSE0               ,Interrupt Vector"
rgroup.long 0x1A84++0x3
line.long 0x00 "CPSW0_INTR_VECTOR_REG_STAT_PULSE0,Interrupt Vector for stat_pulse0"
hexmask.long 0x00 0.--31. 1. " INTR_VECTOR_STAT_PULSE0               ,Interrupt Vector"
rgroup.long 0x1A88++0x3
line.long 0x00 "CPSW0_INTR_VECTOR_REG_STAT_PULSE1,Interrupt Vector for stat_pulse1"
hexmask.long 0x00 0.--31. 1. " INTR_VECTOR_STAT_PULSE1               ,Interrupt Vector"
rgroup.long 0x20000++0x3
line.long 0x00 "CPSW0_CPSW_ID_VER_REG,MCU_CPSW0_NUSS ID Version"
hexmask.long.word 0x00 16.--31. 1. " IDENT                                 ,Identification Value"
bitfld.long 0x00 11.--15. "      RTL_VER                               ,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " MAJOR_VER                             ,Major Version Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM_VER                            ,Custom Version Value" "0,1,2,3"
textline "                                               "
bitfld.long 0x00 0.--5. " MINOR_VER                             ,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20004++0x3
line.long 0x00 "CPSW0_CONTROL_REG,Control Register"
bitfld.long 0x00 1. " EEE_PHY_ONLY                          ,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the MCU_CPSW0_NUSS, 1=The low power indicate state does not gate the clock to the MCU_CPSW0_NUSS" "0,1"
bitfld.long 0x00 0. "         EEE_EN                                ,Energy Efficient Ethernet Enable: 0=EEE is disabled, 1=EEE is enabled" "0,1"
group.long 0x20010++0x3
line.long 0x00 "CPSW0_EM_CONTROL_REG,MCU_CPSW0_NUSS Emulation Control"
bitfld.long 0x00 1. " SOFT                                  ,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "         FREE                                  ,Emulation Free Bit" "0,1"
group.long 0x20014++0x3
line.long 0x00 "CPSW0_STAT_PORT_EN_REG,MCU_CPSW0_NUSS Statistics Port Enable"
bitfld.long 0x00 8. " P8_STAT_EN                            ,Port 8 Statistics Enable" "0,1"
bitfld.long 0x00 7. "         P7_STAT_EN                            ,Port 7 Statistics Enable" "0,1"
textline "                                               "
bitfld.long 0x00 6. " P6_STAT_EN                            ,Port 6 Statistics Enable" "0,1"
bitfld.long 0x00 5. "         P5_STAT_EN                            ,Port 5 Statistics Enable" "0,1"
textline "                                               "
bitfld.long 0x00 4. " P4_STAT_EN                            ,Port 4 Statistics Enable" "0,1"
bitfld.long 0x00 3. "         P3_STAT_EN                            ,Port 3 Statistics Enable" "0,1"
textline "                                               "
bitfld.long 0x00 2. " P2_STAT_EN                            ,Port 2 Statistics Enable" "0,1"
bitfld.long 0x00 1. "         P1_STAT_EN                            ,Port 1 Statistics Enable" "0,1"
textline "                                               "
bitfld.long 0x00 0. " P0_STAT_EN                            ,Port 0 Statistics Enable" "0,1"
group.long 0x20018++0x3
line.long 0x00 "CPSW0_PTYPE_REG,MCU_CPSW0_NUSS Transmit Priority Type"
bitfld.long 0x00 16. " P8_PTYPE_ESC                          ,Port 8 Priority Type Escalate" "0,1"
bitfld.long 0x00 15. "         P7_PTYPE_ESC                          ,Port 7 Priority Type Escalate" "0,1"
textline "                                               "
bitfld.long 0x00 14. " P6_PTYPE_ESC                          ,Port 6 Priority Type Escalate" "0,1"
bitfld.long 0x00 13. "         P5_PTYPE_ESC                          ,Port 5 Priority Type Escalate" "0,1"
textline "                                               "
bitfld.long 0x00 12. " P4_PTYPE_ESC                          ,Port 4 Priority Type Escalate" "0,1"
bitfld.long 0x00 11. "         P3_PTYPE_ESC                          ,Port 3 Priority Type Escalate" "0,1"
textline "                                               "
bitfld.long 0x00 10. " P2_PTYPE_ESC                          ,Port 2 Priority Type Escalate" "0,1"
bitfld.long 0x00 9. "         P1_PTYPE_ESC                          ,Port 1 Priority Type Escalate" "0,1"
textline "                                               "
bitfld.long 0x00 8. " P0_PTYPE_ESC                          ,Port 0 Priority Type Escalate" "0,1"
bitfld.long 0x00 0.--4. "         ESC_PRI_LD_VAL                        ,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2001C++0x3
line.long 0x00 "CPSW0_SOFT_IDLE_REG,MCU_CPSW0_NUSS Software Idle"
bitfld.long 0x00 0. " SOFT_IDLE                             ,Software Idle" "0,1"
group.long 0x20020++0x3
line.long 0x00 "CPSW0_THRU_RATE_REG,MCU_CPSW0_NUSS Thru Rate"
bitfld.long 0x00 12.--15. " SL_RX_THRU_RATE                       ,Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        P0_RX_THRU_RATE                       ,CPPI FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20024++0x3
line.long 0x00 "CPSW0_GAP_THRESH_REG,MCU_CPSW0_NUSS Transmit FIFO Short Gap Threshold"
bitfld.long 0x00 0.--4. " GAP_THRESH                            ,Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20028++0x3
line.long 0x00 "CPSW0_TX_START_WDS_REG,MCU_CPSW0_NUSS Transmit FIFO Start Words"
hexmask.long.word 0x00 0.--10. 1. " TX_START_WDS                          ,FIFO Packet Transmit Start Words"
group.long 0x2002C++0x3
line.long 0x00 "CPSW0_EEE_PRESCALE_REG,MCU_CPSW0_NUSS Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x00 0.--11. 1. " EEE_PRESCALE                          ,Energy Efficient Ethernet Pre-scale count load value"
group.long 0x20030++0x3
line.long 0x00 "CPSW0_TX_G_OFLOW_THRESH_SET_REG,MCU_CPSW0_NUSS PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20034++0x3
line.long 0x00 "CPSW0_TX_G_OFLOW_THRESH_CLR_REG,MCU_CPSW0_NUSS PFC Tx Global Out Flow Threshold Clear"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20038++0x3
line.long 0x00 "CPSW0_TX_G_BUF_THRESH_SET_L_REG,MCU_CPSW0_NUSS PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0x00 24.--31. 1. " PRI3                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x00 16.--23. 1. "        PRI2                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PRI1                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
hexmask.long.byte 0x00 0.--7. 1. "        PRI0                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
group.long 0x2003C++0x3
line.long 0x00 "CPSW0_TX_G_BUF_THRESH_SET_H_REG,MCU_CPSW0_NUSS PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x00 24.--31. 1. " PRI7                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x00 16.--23. 1. "        PRI6                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PRI5                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
hexmask.long.byte 0x00 0.--7. 1. "        PRI4                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20040++0x3
line.long 0x00 "CPSW0_TX_G_BUF_THRESH_CLR_L_REG,MCU_CPSW0_NUSS PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x00 24.--31. 1. " PRI3                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x00 16.--23. 1. "        PRI2                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PRI1                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
hexmask.long.byte 0x00 0.--7. 1. "        PRI0                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
group.long 0x20044++0x3
line.long 0x00 "CPSW0_TX_G_BUF_THRESH_CLR_H_REG,MCU_CPSW0_NUSS PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x00 24.--31. 1. " PRI7                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x00 16.--23. 1. "        PRI6                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PRI5                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
hexmask.long.byte 0x00 0.--7. 1. "        PRI4                                  ,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x3
line.long 0x00 "CPSW0_VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x00 16.--31. 1. " VLAN_LTYPE_OUTER                      ,Outer VLAN LType"
hexmask.long.word 0x00 0.--15. 1. "      VLAN_LTYPE_INNER                      ,Inner VLAN LType"
group.long 0x20054++0x3
line.long 0x00 "CPSW0_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x00 0.--7. 1. " EST_TS_DOMAIN                         ,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x3
line.long 0x00 "CPSW0_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI0_MAXLEN                        ,Transmit Priority 0 Maximum Length"
group.long 0x20104++0x3
line.long 0x00 "CPSW0_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI1_MAXLEN                        ,Transmit Priority 1 Maximum Length"
group.long 0x20108++0x3
line.long 0x00 "CPSW0_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI2_MAXLEN                        ,Transmit Priority 2 Maximum Length"
group.long 0x2010C++0x3
line.long 0x00 "CPSW0_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI3_MAXLEN                        ,Transmit Priority 3 Maximum Length"
group.long 0x20110++0x3
line.long 0x00 "CPSW0_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI4_MAXLEN                        ,Transmit Priority 4 Maximum Length"
group.long 0x20114++0x3
line.long 0x00 "CPSW0_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI5_MAXLEN                        ,Transmit Priority 5 Maximum Length"
group.long 0x20118++0x3
line.long 0x00 "CPSW0_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI6_MAXLEN                        ,Transmit Priority 6 Maximum Length"
group.long 0x2011C++0x3
line.long 0x00 "CPSW0_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. " TX_PRI7_MAXLEN                        ,Transmit Priority 7 Maximum Length"
group.long 0x21004++0x3
line.long 0x00 "CPSW0_P0_CONTROL_REG,CPPI Port 0 Control"
bitfld.long 0x00 18. " RX_REMAP_DSCP_V6                      ,Port 0 Remap DSCP_V6 Enable" "0,1"
bitfld.long 0x00 17. "         RX_REMAP_DSCP_V4                      ,Port 0 Remap DSCP_V4 Enable" "0,1"
textline "                                               "
bitfld.long 0x00 16. " RX_REMAP_VLAN                         ,Port 0 Remap VLAN Enable" "0,1"
bitfld.long 0x00 15. "         RX_ECC_ERR_EN                         ,Port 0 Receive ECC Error Enable" "0,1"
textline "                                               "
bitfld.long 0x00 14. " TX_ECC_ERR_EN                         ,Port 0 Transmit ECC Error Enable" "0,1"
bitfld.long 0x00 2. "         DSCP_IPV6_EN                          ,Port 0 IPv6 DSCP enable" "0,1"
textline "                                               "
bitfld.long 0x00 1. " DSCP_IPV4_EN                          ,Port 0 IPv4 DSCP enable" "0,1"
bitfld.long 0x00 0. "         RX_CHECKSUM_EN                        ,Port 0 Receive Checksum Enable" "0,1"
group.long 0x21008++0x3
line.long 0x00 "CPSW0_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset"
hexmask.long.word 0x00 0.--13. 1. " VALUE                                 ,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x3
line.long 0x00 "CPSW0_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count"
bitfld.long 0x00 8.--12. " TX_BLK_CNT                            ,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "        RX_BLK_CNT                            ,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x21014++0x3
line.long 0x00 "CPSW0_P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
bitfld.long 0x00 13.--15. " PORT_PRI                              ,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         PORT_CFI                              ,Port CFI bit" "0,1"
textline "                                               "
hexmask.long.word 0x00 0.--11. 1. " PORT_VID                              ,Port VLAN ID"
group.long 0x21018++0x3
line.long 0x00 "CPSW0_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x00 28.--30. " PRI7                                  ,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,Priority 6" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,Priority 4" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,Priority 2" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,Priority 0" "0,1,2,3,4,5,6,7"
group.long 0x2101C++0x3
line.long 0x00 "CPSW0_P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
hexmask.long.byte 0x00 16.--23. 1. " RX_FLOW_PRI                           ,Receive Priority Based Flow Control Enable (per priority)"
bitfld.long 0x00 8. "        RX_PTYPE                              ,Receive Priority Type" "0,1"
group.long 0x21020++0x3
line.long 0x00 "CPSW0_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x00 28.--30. " PRI7                                  ,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,Priority 6" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,Priority 4" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,Priority 2" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,Priority 0" "0,1,2,3,4,5,6,7"
group.long 0x21024++0x3
line.long 0x00 "CPSW0_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x00 0.--13. 1. " RX_MAXLEN                             ,Rx Maximum Frame Length"
group.long 0x21028++0x3
line.long 0x00 "CPSW0_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x3
line.long 0x00 "CPSW0_P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT                                 ,Port 0 EEE Idle to LPI counter load value"
group.long 0x21034++0x3
line.long 0x00 "CPSW0_P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT                                 ,Port 0 EEE LPI to wake counter load value"
rgroup.long 0x21038++0x3
line.long 0x00 "CPSW0_P0_EEE_STATUS_REG,Port 0 EEE status"
bitfld.long 0x00 6. " TX_FIFO_EMPTY                         ,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
bitfld.long 0x00 5. "         RX_FIFO_EMPTY                         ,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
textline "                                               "
bitfld.long 0x00 4. " TX_FIFO_HOLD                          ,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
bitfld.long 0x00 3. "         TX_WAKE                               ,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
textline "                                               "
bitfld.long 0x00 2. " TX_LPI                                ,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
bitfld.long 0x00 1. "         RX_LPI                                ,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
textline "                                               "
bitfld.long 0x00 0. " WAIT_IDLE2LPI                         ,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
group.long 0x2103C++0x3
line.long 0x00 "CPSW0_P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority 7 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority 6 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority 5 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority 4 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority 3 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority 2 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority 1 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority 0 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2104C++0x3
line.long 0x00 "CPSW0_P0_RX_GAP_REG,Port 0 Receive Gap Register"
hexmask.long.word 0x00 16.--25. 1. " RX_GAP_CNT                            ,Port 0 Receive Gap Count"
hexmask.long.byte 0x00 0.--7. 1. "      RX_GAP_EN                             ,Port 0 Receive Gap Enable"
rgroup.long 0x21050++0x3
line.long 0x00 "CPSW0_P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x00 0.--7. 1. " TX_PRI_ACTIVE                         ,Port 0 FIFO Status"
group.long 0x21120++0x3
line.long 0x00 "CPSW0_P0_RX_DSCP_MAP_REG_y,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N Offset = 00021120h + (y * 4h); where y = 0h to 7h"
bitfld.long 0x00 28.--30. " PRI7                                  ,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x21140++0x3
line.long 0x00 "CPSW0_P0_PRI_CIR_REG_y,CPPI Port 0 Rx Priority P Committed Information Rate Offset = 00021140h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. " PRI_CIR                               ,Priority N CIR"
group.long 0x21160++0x3
line.long 0x00 "CPSW0_P0_PRI_EIR_REG_y,CPPI Port 0 Rx Priority P Excess Information Rate Offset = 00021160h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. " PRI_EIR                               ,Priority N EIR"
group.long 0x21180++0x3
line.long 0x00 "CPSW0_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21184++0x3
line.long 0x00 "CPSW0_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21188++0x3
line.long 0x00 "CPSW0_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2118C++0x3
line.long 0x00 "CPSW0_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21190++0x3
line.long 0x00 "CPSW0_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21194++0x3
line.long 0x00 "CPSW0_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21198++0x3
line.long 0x00 "CPSW0_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2119C++0x3
line.long 0x00 "CPSW0_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x3
line.long 0x00 "CPSW0_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 24.--31. 1. " PORT4                                 ,Port 4 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 16.--23. 1. "        PORT3                                 ,Port 3 CPPI Info Word0 Source ID Value"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PORT2                                 ,Port 2 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 0.--7. 1. "        PORT1                                 ,Port 1 CPPI Info Word0 Source ID Value"
group.long 0x21304++0x3
line.long 0x00 "CPSW0_P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
hexmask.long.byte 0x00 24.--31. 1. " PORT8                                 ,Port 8 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 16.--23. 1. "        PORT7                                 ,Port 7 CPPI Info Word0 Source ID Value"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " PORT6                                 ,Port 6 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 0.--7. 1. "        PORT5                                 ,Port 5 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x3
line.long 0x00 "CPSW0_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority 7 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority 6 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority 5 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority 4 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority 3 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority 2 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority 1 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority 0 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x22000++0x3
line.long 0x00 "CPSW0_PN_RESERVED_REG,Reserved"
group.long 0x22004++0x3
line.long 0x00 "CPSW0_PN_CONTROL_REG,Enet Port N Control"
bitfld.long 0x00 17. " EST_PORT_EN                           ,EST Port Enable" "0,1"
bitfld.long 0x00 16. "         IET_PORT_EN                           ,IET Port Enable" "0,1"
textline "                                               "
bitfld.long 0x00 15. " RX_ECC_ERR_EN                         ,Port 0 Receive ECC Error Enable" "0,1"
bitfld.long 0x00 14. "         TX_ECC_ERR_EN                         ,Port 0 Transmit ECC Error Enable" "0,1"
textline "                                               "
bitfld.long 0x00 12. " TX_LPI_CLKSTOP_EN                     ,Transmit LPI clockstop enable" "0,1"
bitfld.long 0x00 2. "         DSCP_IPV6_EN                          ,IPv6 DSCP enable" "0,1"
textline "                                               "
bitfld.long 0x00 1. " DSCP_IPV4_EN                          ,IPv4 DSCP enable" "0,1"
group.long 0x22008++0x3
line.long 0x00 "CPSW0_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x00 8.--15. 1. " TX_MAX_BLKS                           ,Transmit FIFO maximum blocks"
hexmask.long.byte 0x00 0.--7. 1. "        RX_MAX_BLKS                           ,Receive FIFO maximum blocks"
rgroup.long 0x22010++0x3
line.long 0x00 "CPSW0_PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
bitfld.long 0x00 16.--21. " RX_BLK_CNT_P                          ,Receive Prempt Queue Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--12. "        TX_BLK_CNT                            ,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 0.--5. " RX_BLK_CNT_E                          ,Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x22014++0x3
line.long 0x00 "CPSW0_PN_PORT_VLAN_REG,Enet Port N VLAN"
bitfld.long 0x00 13.--15. " PORT_PRI                              ,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "         PORT_CFI                              ,Port CFI bit" "0,1"
textline "                                               "
hexmask.long.word 0x00 0.--11. 1. " PORT_VID                              ,Port VLAN ID"
group.long 0x22018++0x3
line.long 0x00 "CPSW0_PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x00 28.--30. " PRI7                                  ,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,Priority 6" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,Priority 4" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,Priority 2" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,Priority 0" "0,1,2,3,4,5,6,7"
group.long 0x2201C++0x3
line.long 0x00 "CPSW0_PN_PRI_CTL_REG,Enet Port N Priority Control"
hexmask.long.byte 0x00 24.--31. 1. " TX_FLOW_PRI                           ,Transmit Priority Based Flow Control Enable (per priority)"
hexmask.long.byte 0x00 16.--23. 1. "        RX_FLOW_PRI                           ,Receive Priority Based Flow Control Enable (per priority)"
textline "                                               "
bitfld.long 0x00 12.--15. " TX_HOST_BLKS_REM                      ,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x22020++0x3
line.long 0x00 "CPSW0_PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
bitfld.long 0x00 28.--30. " PRI7                                  ,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,Priority 6" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,Priority 4" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,Priority 2" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,Priority 0" "0,1,2,3,4,5,6,7"
group.long 0x22024++0x3
line.long 0x00 "CPSW0_PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x00 0.--13. 1. " RX_MAXLEN                             ,Rx Maximum Frame Length"
group.long 0x22028++0x3
line.long 0x00 "CPSW0_PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
bitfld.long 0x00 28.--31. " PRI7                                  ,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        PRI6                                  ,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 20.--23. " PRI5                                  ,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PRI4                                  ,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 12.--15. " PRI3                                  ,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        PRI2                                  ,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
bitfld.long 0x00 4.--7. " PRI1                                  ,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PRI0                                  ,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2202C++0x3
line.long 0x00 "CPSW0_PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
hexmask.long.word 0x00 0.--8. 1. " COUNT                                 ,Receive Flow Threshold in Words"
group.long 0x22030++0x3
line.long 0x00 "CPSW0_PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT                                 ,EEE Idle to LPI counter load value"
group.long 0x22034++0x3
line.long 0x00 "CPSW0_PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT                                 ,EEE LPI to wake counter load value"
rgroup.long 0x22038++0x3
line.long 0x00 "CPSW0_PN_EEE_STATUS_REG,Enet Port N EEE status"
bitfld.long 0x00 6. " TX_FIFO_EMPTY                         ,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
bitfld.long 0x00 5. "         RX_FIFO_EMPTY                         ,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
textline "                                               "
bitfld.long 0x00 4. " TX_FIFO_HOLD                          ,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
bitfld.long 0x00 3. "         TX_WAKE                               ,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
textline "                                               "
bitfld.long 0x00 2. " TX_LPI                                ,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
bitfld.long 0x00 1. "         RX_LPI                                ,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
textline "                                               "
bitfld.long 0x00 0. " WAIT_IDLE2LPI                         ,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
rgroup.long 0x22050++0x3
line.long 0x00 "CPSW0_PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
bitfld.long 0x00 18. " EST_BUFACT                            ,Transmit FIFO EST Buffer Active" "0,1"
bitfld.long 0x00 17. "         EST_ADD_ERR                           ,Transmit FIFO EST Address Error" "0,1"
textline "                                               "
bitfld.long 0x00 16. " EST_CNT_ERR                           ,Transmit FIFO EST Count Error" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         TX_E_MAC_ALLOW                        ,Transmit FIFO Express Queue Priority Allow"
textline "                                               "
hexmask.long.byte 0x00 0.--7. 1. " TX_PRI_ACTIVE                         ,Transmit FIFO Priority Active"
group.long 0x22060++0x3
line.long 0x00 "CPSW0_PN_EST_CONTROL_REG,Enet Port N EST"
hexmask.long.word 0x00 16.--25. 1. " EST_FILL_MARGIN                       ,Transmit FIFO EST Fill Margin"
bitfld.long 0x00 8. "      EST_FILL_EN                           ,Transmit FIFO EST Fill Enable" "0,1"
textline "                                               "
bitfld.long 0x00 5.--7. " EST_TS_PRI                            ,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "         EST_TS_ONEPRI                         ,Transmit FIFO EST TimeStamp One Priority" "0,1"
textline "                                               "
bitfld.long 0x00 3. " EST_TS_FIRST                          ,Transmit FIFO EST TimeStamp First Express Packet" "0,1"
bitfld.long 0x00 2. "         EST_TS_EN                             ,Transmit FIFO EST TimeStamp Enable" "0,1"
textline "                                               "
bitfld.long 0x00 1. " EST_BUFSEL                            ,Transmit FIFO EST Buffer Select" "0,1"
bitfld.long 0x00 0. "         EST_ONEBUF                            ,Transmit FIFO EST One Buffer" "0,1"
group.long 0x22120++0x3
line.long 0x00 "CPSW0_PN_RX_DSCP_MAP_REG_y,Enet Port N Receive IPV4/IPV6 DSCP Map M Offset = 00022120h + (y * 4h); where y = 0h to 7h"
bitfld.long 0x00 28.--30. " PRI7                                  ,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         PRI6                                  ,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 20.--22. " PRI5                                  ,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         PRI4                                  ,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 12.--14. " PRI3                                  ,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "         PRI2                                  ,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 4.--6. " PRI1                                  ,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI0                                  ,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x22140++0x3
line.long 0x00 "CPSW0_PN_PRI_CIR_REG_y,Enet Port N Rx Priority P Committed Information Rate Value Offset = 00022140h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. " PRI_CIR                               ,Priority N committed information rate"
group.long 0x22160++0x3
line.long 0x00 "CPSW0_PN_PRI_EIR_REG_y,Enet Port N Rx Priority P Excess Informatoin Rate Value Offset = 00022160h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. " PRI_EIR                               ,Priority N Excess Information Rate count"
group.long 0x22180++0x3
line.long 0x00 "CPSW0_PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22184++0x3
line.long 0x00 "CPSW0_PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22188++0x3
line.long 0x00 "CPSW0_PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2218C++0x3
line.long 0x00 "CPSW0_PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22190++0x3
line.long 0x00 "CPSW0_PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22194++0x3
line.long 0x00 "CPSW0_PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22198++0x3
line.long 0x00 "CPSW0_PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2219C++0x3
line.long 0x00 "CPSW0_PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x3
line.long 0x00 "CPSW0_PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. " PRI3                                  ,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI2                                  ,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI1                                  ,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI0                                  ,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22304++0x3
line.long 0x00 "CPSW0_PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x00 24.--28. " PRI7                                  ,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "        PRI6                                  ,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--12. " PRI5                                  ,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "        PRI4                                  ,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22308++0x3
line.long 0x00 "CPSW0_PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0                        ,Source Address Lower 8 bits"
hexmask.long.byte 0x00 0.--7. 1. "        MACSRCADDR_15_8                       ,Source Address bits 15:8"
group.long 0x2230C++0x3
line.long 0x00 "CPSW0_PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16                      ,Source Address bits 23:16"
hexmask.long.byte 0x00 16.--23. 1. "        MACSRCADDR_31_24                      ,Source Address bits 31:24"
textline "                                               "
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32                      ,Source Address bits 39:32"
hexmask.long.byte 0x00 0.--7. 1. "        MACSRCADDR_47_40                      ,Source Address bits 47:40"
group.long 0x22310++0x3
line.long 0x00 "CPSW0_PN_TS_CTL_REG,Enet Port N Time Sync Control"
hexmask.long.word 0x00 16.--31. 1. " TS_MSG_TYPE_EN                        ,Time Sync Message Type Enable"
bitfld.long 0x00 11. "      TS_TX_HOST_TS_EN                      ,Time Sync Transmit Host Time Stamp Enable" "0,1"
textline "                                               "
bitfld.long 0x00 10. " TS_TX_ANNEX_E_EN                      ,Time Synce Transmit Annex E Enable" "0,1"
bitfld.long 0x00 9. "         TS_RX_ANNEX_E_EN                      ,Time Synce Receive Annex E Enable" "0,1"
textline "                                               "
bitfld.long 0x00 8. " TS_LTYPE2_EN                          ,Time Sync LTYPE 2 enable transmit and receive" "0,1"
bitfld.long 0x00 7. "         TS_TX_ANNEX_D_EN                      ,Time Synce Transmit Annex D Enable" "0,1"
textline "                                               "
bitfld.long 0x00 6. " TS_TX_VLAN_LTYPE2_EN                  ,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x00 5. "         TS_TX_VLAN_LTYPE1_EN                  ,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
textline "                                               "
bitfld.long 0x00 4. " TS_TX_ANNEX_F_EN                      ,Time Synce Transmit Annex F Enable" "0,1"
bitfld.long 0x00 3. "         TS_RX_ANNEX_D_EN                      ,Time Synce Receive Annex D Enable" "0,1"
textline "                                               "
bitfld.long 0x00 2. " TS_RX_VLAN_LTYPE2_EN                  ,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x00 1. "         TS_RX_VLAN_LTYPE1_EN                  ,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
textline "                                               "
bitfld.long 0x00 0. " TS_RX_ANNEX_F_EN                      ,Time Synce Receive Annex F Enable" "0,1"
group.long 0x22314++0x3
line.long 0x00 "CPSW0_PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x00 16.--21. " TS_SEQ_ID_OFFSET                      ,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        TS_LTYPE1                             ,Time Sync LTYPE1"
group.long 0x22318++0x3
line.long 0x00 "CPSW0_PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x00 16.--31. 1. " TS_VLAN_LTYPE2                        ,Time Sync VLAN LTYPE2"
hexmask.long.word 0x00 0.--15. 1. "      TS_VLAN_LTYPE1                        ,Time Sync VLAN LTYPE1"
group.long 0x2231C++0x3
line.long 0x00 "CPSW0_PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x00 24. " TS_UNI_EN                             ,Time Sync Unicast Enable" "0,1"
bitfld.long 0x00 23. "         TS_TTL_NONZERO                        ,Time Sync Time to Live Non-zero Enable" "0,1"
textline "                                               "
bitfld.long 0x00 22. " TS_320                                ,Time Sync Destination IP Address 320 Enable" "0,1"
bitfld.long 0x00 21. "         TS_319                                ,Time Sync Destination IP Address 319 Enable" "0,1"
textline "                                               "
bitfld.long 0x00 20. " TS_132                                ,Time Sync Destination IP Address 132 Enable" "0,1"
bitfld.long 0x00 19. "         TS_131                                ,Time Sync Destination IP Address 131 Enable" "0,1"
textline "                                               "
bitfld.long 0x00 18. " TS_130                                ,Time Sync Destination IP Address 130 Enable" "0,1"
bitfld.long 0x00 17. "         TS_129                                ,Time Sync Destination IP Address 129 Enable" "0,1"
textline "                                               "
bitfld.long 0x00 16. " TS_107                                ,Time Sync Destination IP Address 107 Enable" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         TS_LTYPE2                             ,Time Sync LTYPE2"
group.long 0x22320++0x3
line.long 0x00 "CPSW0_PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
bitfld.long 0x00 16.--21. " TS_DOMAIN_OFFSET                      ,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        TS_MCAST_TYPE_EN                      ,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x3
line.long 0x00 "CPSW0_PN_MAC_CONTROL_REG,Enet Port N Mac Control"
bitfld.long 0x00 24. " RX_CMF_EN                             ,RX Copy MAC Control Frames Enable" "0,1"
bitfld.long 0x00 23. "         RX_CSF_EN                             ,RX Copy Short Frames Enable" "0,1"
textline "                                               "
bitfld.long 0x00 22. " RX_CEF_EN                             ,RX Copy Error Frames Enable" "0,1"
bitfld.long 0x00 21. "         TX_SHORT_GAP_LIM_EN                   ,Transmit Short Gap Limit Enable" "0,1"
textline "                                               "
bitfld.long 0x00 20. " EXT_TX_FLOW_EN                        ,External Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 19. "         EXT_RX_FLOW_EN                        ,External Receive Flow Control Enable" "0,1"
textline "                                               "
bitfld.long 0x00 18. " CTL_EN                                ,Control Enable" "0,1"
bitfld.long 0x00 17. "         GIG_FORCE                             ,Gigabit Mode Force" "0,1"
textline "                                               "
bitfld.long 0x00 16. " IFCTL_B                               ,Interface Control B" "0,1"
bitfld.long 0x00 15. "         IFCTL_A                               ,Interface Control A" "0,1"
textline "                                               "
bitfld.long 0x00 12. " CRC_TYPE                              ,Port CRC Type" "0,1"
bitfld.long 0x00 11. "         CMD_IDLE                              ,Command Idle" "0,1"
textline "                                               "
bitfld.long 0x00 10. " TX_SHORT_GAP_ENABLE                   ,Transmit Short Gap Enable" "0,1"
bitfld.long 0x00 7. "         GIG                                   ,Gigabit Mode" "0,1"
textline "                                               "
bitfld.long 0x00 6. " TX_PACE                               ,Transmit Pacing Enable" "0,1"
bitfld.long 0x00 5. "         GMII_EN                               ,GMII Enable" "0,1"
textline "                                               "
bitfld.long 0x00 4. " TX_FLOW_EN                            ,Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 3. "         RX_FLOW_EN                            ,Receive Flow Control Enable" "0,1"
textline "                                               "
bitfld.long 0x00 2. " MTEST                                 ,Manufacturing Test Mode" "0,1"
bitfld.long 0x00 1. "         LOOPBACK                              ,Loop Back Mode" "0,1"
textline "                                               "
bitfld.long 0x00 0. " FULLDUPLEX                            ,Full Duplex mode" "0,1"
rgroup.long 0x22334++0x3
line.long 0x00 "CPSW0_PN_MAC_STATUS_REG,Enet Port N Mac Status"
bitfld.long 0x00 31. " IDLE                                  ,cpxmac_sl IDLE" "0,1"
bitfld.long 0x00 30. "         E_IDLE                                ,cpxmac_sl IDLE" "0,1"
textline "                                               "
bitfld.long 0x00 29. " P_IDLE                                ,cpxmac_sl IDLE" "0,1"
bitfld.long 0x00 28. "         TX_IDLE                               ,cpxmac_sl IDLE" "0,1"
textline "                                               "
bitfld.long 0x00 27. " TORF                                  ,Top of receive FIFO flowCPSW0_CONTROL trigger occurred. This bit is write one to clear." "0,1"
bitfld.long 0x00 24.--26. "         TORF_PRI                              ,The lowest priority that caused top of receive FIFO flowCPSW0_CONTROL trigger since the last write to clear. This field is write 0x7 to clear." "0,1,2,3,4,5,6,7"
textline "                                               "
hexmask.long.byte 0x00 16.--23. 1. " TX_PFC_FLOW_ACT                       ,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
hexmask.long.byte 0x00 8.--15. 1. "        RX_PFC_FLOW_ACT                       ,Receive Priority Based Flow Control Active (priority 7 down to 0)"
textline "                                               "
bitfld.long 0x00 6. " EXT_RX_FLOW_EN                        ,External Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 5. "         EXT_TX_FLOW_EN                        ,External Receive Flow Control Enable" "0,1"
textline "                                               "
bitfld.long 0x00 4. " EXT_GIG                               ,External GIG mode" "0,1"
bitfld.long 0x00 3. "         EXT_FULLDUPLEX                        ,External Fullduplex" "0,1"
textline "                                               "
bitfld.long 0x00 1. " RX_FLOW_ACT                           ,Receive Flow Control Active" "0,1"
bitfld.long 0x00 0. "         TX_FLOW_ACT                           ,Transmit Flow Control Active" "0,1"
group.long 0x22338++0x3
line.long 0x00 "CPSW0_PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
bitfld.long 0x00 0. " SOFT_RESET                            ,Software reset" "0,1"
group.long 0x2233C++0x3
line.long 0x00 "CPSW0_PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
bitfld.long 0x00 26.--30. " PACEVAL                               ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 16.--25. 1. "        RNDNUM                                ,Backoff Random Number Generator"
textline "                                               "
bitfld.long 0x00 12.--15. " COLL_COUNT                            ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "        TX_BACKOFF                            ,Backoff Count"
group.long 0x22340++0x3
line.long 0x00 "CPSW0_PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
hexmask.long.word 0x00 0.--15. 1. " RX_PAUSETIMER                         ,RX Pause Timer Value"
group.long 0x22350++0x3
line.long 0x00 "CPSW0_PN_MAC_RXN_PAUSETIMER_REG_y,Enet Port N PFC Priority P Rx Pause Timer Offset = 00022350h + (y * 4h); where y = 0h to 7h"
hexmask.long.word 0x00 0.--15. 1. " RX_PAUSETIMER                         ,RX Pause Timer Value"
group.long 0x22370++0x3
line.long 0x00 "CPSW0_PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. " TX_PAUSETIMER                         ,TX Pause Timer Value"
group.long 0x22380++0x3
line.long 0x00 "CPSW0_PN_MAC_TXN_PAUSETIMER_REG_y,Enet Port N PFC Priority P Tx Pause Timer Offset = 00022380h + (y * 4h); where y = 0h to 7h"
hexmask.long.word 0x00 0.--15. 1. " TX_PAUSETIMER                         ,TX Pause Timer Value"
group.long 0x223A0++0x3
line.long 0x00 "CPSW0_PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
bitfld.long 0x00 1. " SOFT                                  ,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "         FREE                                  ,Emulation Free Bit" "0,1"
group.long 0x223A4++0x3
line.long 0x00 "CPSW0_PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x00 0.--15. 1. " TX_GAP                                ,Transmit Inter-Packet Gap"
group.long 0x32000++0x3
line.long 0x00 "CPSW0_FETCH_LOC_y,These are the RAM locations for one ethernet port Offset = 00032000h + (y * 4h); where y = 0h to 7Fh"
hexmask.long.tbyte 0x00 0.--21. 1. " LOC                                   ,RAM Location"
group.long 0x3A200++0x3
line.long 0x00 "CPSW0_RXGOODFRAMES,Total number of good frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good frames received"
group.long 0x3A204++0x3
line.long 0x00 "CPSW0_RXBROADCASTFRAMES,Total number of good broadcast frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good broadcast frames received"
group.long 0x3A208++0x3
line.long 0x00 "CPSW0_RXMULTICASTFRAMES,Total number of good multicast frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good multicast frames received"
group.long 0x3A20C++0x3
line.long 0x00 "CPSW0_RXPAUSEFRAMES,Total number of pause frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of pause frames received"
group.long 0x3A210++0x3
line.long 0x00 "CPSW0_RXCRCERRORS,Total number of CRC errors frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of CRC errors frames received"
group.long 0x3A214++0x3
line.long 0x00 "CPSW0_RXALIGNCODEERRORS,Total number of alignment/code errors received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of alignment/code errors received"
group.long 0x3A218++0x3
line.long 0x00 "CPSW0_RXOVERSIZEDFRAMES,Total number of oversized frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of oversized frames received"
group.long 0x3A21C++0x3
line.long 0x00 "CPSW0_RXJABBERFRAMES,Total number of jabber frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of jabber frames received"
group.long 0x3A220++0x3
line.long 0x00 "CPSW0_RXUNDERSIZEDFRAMES,Total number of undersized frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of undersized frames received"
group.long 0x3A224++0x3
line.long 0x00 "CPSW0_RXFRAGMENTS,Total number of fragmented frames received"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of fragmented frames received"
group.long 0x3A228++0x3
line.long 0x00 "CPSW0_ALE_DROP,Total number of frames dropped by the ALE"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames dropped by the ALE"
group.long 0x3A22C++0x3
line.long 0x00 "CPSW0_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of overrun frames dropped by the ALE"
group.long 0x3A230++0x3
line.long 0x00 "CPSW0_RXOCTETS,Total number of received bytes in good frames"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of received bytes in good frames"
group.long 0x3A234++0x3
line.long 0x00 "CPSW0_TXGOODFRAMES,Total number of good frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good frames transmitted"
group.long 0x3A238++0x3
line.long 0x00 "CPSW0_TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good broadcast frames transmitted"
group.long 0x3A23C++0x3
line.long 0x00 "CPSW0_TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of good multicast frames transmitted"
group.long 0x3A240++0x3
line.long 0x00 "CPSW0_TXPAUSEFRAMES,Total number of pause frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of pause frames transmitted"
group.long 0x3A244++0x3
line.long 0x00 "CPSW0_TXDEFERREDFRAMES,Total number of deferred frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of deferred frames transmitted"
group.long 0x3A248++0x3
line.long 0x00 "CPSW0_TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames experiencing a collision"
group.long 0x3A24C++0x3
line.long 0x00 "CPSW0_TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames experiencing a single collision"
group.long 0x3A250++0x3
line.long 0x00 "CPSW0_TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames experiencing multiple collisions"
group.long 0x3A254++0x3
line.long 0x00 "CPSW0_TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames abandoned due to excessive collisions"
group.long 0x3A258++0x3
line.long 0x00 "CPSW0_TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames abandoned due to a late collision"
group.long 0x3A25C++0x3
line.long 0x00 "CPSW0_RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of receive inter-packet gap errors (10G only)"
group.long 0x3A260++0x3
line.long 0x00 "CPSW0_TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of transmitted frames that experienced a carrier loss"
group.long 0x3A264++0x3
line.long 0x00 "CPSW0_TXOCTETS,Total number of bytes in all good frames transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of bytes in all good frames transmitted"
group.long 0x3A268++0x3
line.long 0x00 "CPSW0_OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of 64-byte frames received and transmitted"
group.long 0x3A26C++0x3
line.long 0x00 "CPSW0_OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames of size 65 to 127 bytes received and transmitted"
group.long 0x3A270++0x3
line.long 0x00 "CPSW0_OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames of size 128 to 255 bytes received and transmitted"
group.long 0x3A274++0x3
line.long 0x00 "CPSW0_OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames of size 256 to 511 bytes received and transmitted"
group.long 0x3A278++0x3
line.long 0x00 "CPSW0_OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames of size 512 to 1023 bytes received and transmitted"
group.long 0x3A27C++0x3
line.long 0x00 "CPSW0_OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
group.long 0x3A280++0x3
line.long 0x00 "CPSW0_NETOCTETS,Total number of bytes received and transmitted"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of bytes received and transmitted"
group.long 0x3A284++0x3
line.long 0x00 "CPSW0_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Receive Bottom of FIFO Drop"
group.long 0x3A288++0x3
line.long 0x00 "CPSW0_PORTMASK_DROP,Total number of dropped frames received due to portmask"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames received due to portmask"
group.long 0x3A28C++0x3
line.long 0x00 "CPSW0_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Receive Top of FIFO Drop"
group.long 0x3A290++0x3
line.long 0x00 "CPSW0_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to ALE Rate Limiting"
group.long 0x3A294++0x3
line.long 0x00 "CPSW0_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to ALE VID Ingress"
group.long 0x3A298++0x3
line.long 0x00 "CPSW0_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to DA=SA"
group.long 0x3A29C++0x3
line.long 0x00 "CPSW0_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to ALE Block Mode"
group.long 0x3A2A0++0x3
line.long 0x00 "CPSW0_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to ALE Secure Mode"
group.long 0x3A2A4++0x3
line.long 0x00 "CPSW0_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,Total number of dropped frames due to ALE Authentication"
group.long 0x3A2A8++0x3
line.long 0x00 "CPSW0_ALE_UNKN_UNI,ALE Receive Unknown Unicast"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Unicast"
group.long 0x3A2AC++0x3
line.long 0x00 "CPSW0_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Unicast Bytecount"
group.long 0x3A2B0++0x3
line.long 0x00 "CPSW0_ALE_UNKN_MLT,ALE Receive Unknown Multicast"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Multicast"
group.long 0x3A2B4++0x3
line.long 0x00 "CPSW0_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Multicast Bytecount"
group.long 0x3A2B8++0x3
line.long 0x00 "CPSW0_ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Broadcast"
group.long 0x3A2BC++0x3
line.long 0x00 "CPSW0_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Receive Unknown Broadcast Bytecount"
group.long 0x3A2C0++0x3
line.long 0x00 "CPSW0_ALE_POL_MATCH,ALE Policer Matched"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Policer Matched"
group.long 0x3A2C4++0x3
line.long 0x00 "CPSW0_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Policer Matched and Condition Red"
group.long 0x3A2C8++0x3
line.long 0x00 "CPSW0_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
hexmask.long 0x00 0.--31. 1. " COUNT                                 ,ALE Policer Matched and Condition Yellow"
group.long 0x3A37C++0x3
line.long 0x00 "CPSW0_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. " COUNT                                 ,Transmit Memory Protect CRC Error"
group.long 0x3A380++0x3
line.long 0x00 "CPSW0_ENET_PN_TX_PRI_REG_y,ENET Port n PRIORITY N Packet Count Offset = 0003A380h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--31. 1. " PN_TX_PRIN                            ,"
group.long 0x3A3A0++0x3
line.long 0x00 "CPSW0_ENET_PN_TX_PRI_BCNT_REG_y,ENET Port n PRIORITY N Packet Byte Count Offset = 0003A3A0h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--31. 1. " PN_TX_PRIN_BCNT                       ,ENET Port n PRIORITY N Packet Byte Count"
group.long 0x3A3C0++0x3
line.long 0x00 "CPSW0_ENET_PN_TX_PRI_DROP_REG_y,ENET Port n PRIORITY N Packet Drop Count Offset = 0003A3C0h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--31. 1. " PN_TX_PRIN_DROP                       ,ENET Port n PRIORITY N Packet Drop Count"
group.long 0x3A3E0++0x3
line.long 0x00 "CPSW0_ENET_PN_TX_PRI_DROP_BCNT_REG_y,ENET Port n PRIORITY N Packet Drop Byte Count Offset = 0003A3E0h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--31. 1. " PN_TX_PRIN_DROP_BCNT                  ,ENET Port n PRIORITY N Packet Drop Byte Count"
group.long 0x3D004++0x3
line.long 0x00 "CPSW0_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x00 28.--31. " TS_SYNC_SEL                           ,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "        HW8_TS_PUSH_EN                        ,Hardware push 8 enable" "0,1"
textline "                                               "
bitfld.long 0x00 14. " HW7_TS_PUSH_EN                        ,Hardware push 7 enable" "0,1"
bitfld.long 0x00 13. "         HW6_TS_PUSH_EN                        ,Hardware push 6 enable" "0,1"
textline "                                               "
bitfld.long 0x00 12. " HW5_TS_PUSH_EN                        ,Hardware push 5 enable" "0,1"
bitfld.long 0x00 11. "         HW4_TS_PUSH_EN                        ,Hardware push 4 enable" "0,1"
textline "                                               "
bitfld.long 0x00 10. " HW3_TS_PUSH_EN                        ,Hardware push 3 enable" "0,1"
bitfld.long 0x00 9. "         HW2_TS_PUSH_EN                        ,Hardware push 2 enable" "0,1"
textline "                                               "
bitfld.long 0x00 8. " HW1_TS_PUSH_EN                        ,Hardware push 1 enable" "0,1"
bitfld.long 0x00 7. "         TS_PPM_DIR                            ,Timestamp PPM Direction" "0,1"
textline "                                               "
bitfld.long 0x00 6. " TS_COMP_TOG                           ,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode, 1=TS_COMP is in toggle mode" "0,1"
bitfld.long 0x00 5. "         MODE                                  ,Timestamp mode" "0,1"
textline "                                               "
bitfld.long 0x00 4. " SEQUENCE_EN                           ,Sequence Enable" "0,1"
bitfld.long 0x00 3. "         TSTAMP_EN                             ,Host Receive Timestamp Enable" "0,1"
textline "                                               "
bitfld.long 0x00 2. " TS_COMP_POLARITY                      ,TS_COMP polarity" "0,1"
bitfld.long 0x00 1. "         INT_TEST                              ,Interrupt test" "0,1"
textline "                                               "
bitfld.long 0x00 0. " CPTS_EN                               ,Time sync enable" "0,1"
group.long 0x3D008++0x3
line.long 0x00 "CPSW0_RFTCLK_SEL_REG,Added RFTCLK_SEL Register Bit Field Description RFTCLK Select Register"
bitfld.long 0x00 0.--4. " RFTCLK_SEL                            ,Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h: Selects CPSWHSDIV_CLKOUT2 clock 1h: Selects MAINHSDIV_CLKOUT3 clock 2h: Selects MCU_CPTS0_RFT_CLK I/O pin 3h: Selects CPTS0_RFT_CLK I/O pin 4h: Selects MCU_EXT_REFCLK0 I/O pin 5h: Selects EXT_REFCLK1 I/O pin 6h: Selects PCIE0_TXI0_CLK clock 7h: Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x3D00C++0x3
line.long 0x00 "CPSW0_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x00 0. " TS_PUSH                               ,Time stamp event push" "0,1"
group.long 0x3D010++0x3
line.long 0x00 "CPSW0_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL                           ,Time stamp load low value"
wgroup.long 0x3D014++0x3
line.long 0x00 "CPSW0_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x00 0. " TS_LOAD_EN                            ,Time stamp load enable" "0,1"
group.long 0x3D018++0x3
line.long 0x00 "CPSW0_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_VAL                           ,Time stamp comparison low value"
group.long 0x3D01C++0x3
line.long 0x00 "CPSW0_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_LENGTH                        ,Time stamp comparison length"
group.long 0x3D020++0x3
line.long 0x00 "CPSW0_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x00 0. " TS_PEND_RAW                           ,TS_PEND_RAW int read (before enable)" "0,1"
rgroup.long 0x3D024++0x3
line.long 0x00 "CPSW0_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x00 0. " TS_PEND                               ,TS_PEND masked interrupt read (after enable)" "0,1"
group.long 0x3D028++0x3
line.long 0x00 "CPSW0_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x00 0. " TS_PEND_EN                            ,TS_PEND masked interrupt enable" "0,1"
group.long 0x3D02C++0x3
line.long 0x00 "CPSW0_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE                                 ,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
wgroup.long 0x3D030++0x3
line.long 0x00 "CPSW0_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x00 0. " EVENT_POP                             ,Event pop" "0,1"
rgroup.long 0x3D034++0x3
line.long 0x00 "CPSW0_EVENT_0_REG,Event 0 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP                            ,Time Stamp"
rgroup.long 0x3D038++0x3
line.long 0x00 "CPSW0_EVENT_1_REG,Event 1 Register"
bitfld.long 0x00 29. " PREMPT_QUEUE                          ,Prempt QUEUE" "0,1"
bitfld.long 0x00 24.--28. "         PORT_NUMBER                           ,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 20.--23. " EVENT_TYPE                            ,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        MESSAGE_TYPE                          ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                               "
hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID                           ,Sequence ID"
rgroup.long 0x3D03C++0x3
line.long 0x00 "CPSW0_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x00 0.--7. 1. " DOMAIN                                ,Domain"
rgroup.long 0x3D040++0x3
line.long 0x00 "CPSW0_EVENT_3_REG,Event 3 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP                            ,Time Stamp"
group.long 0x3D044++0x3
line.long 0x00 "CPSW0_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL                           ,Time stamp load high value"
group.long 0x3D048++0x3
line.long 0x00 "CPSW0_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_HIGH_VAL                      ,Time stamp comparison high value"
group.long 0x3D04C++0x3
line.long 0x00 "CPSW0_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x00 0.--2. " ADD_VAL                               ,Add Value" "0,1,2,3,4,5,6,7"
group.long 0x3D050++0x3
line.long 0x00 "CPSW0_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_PPM_LOW_VAL                        ,Time stamp PPM Low value"
group.long 0x3D054++0x3
line.long 0x00 "CPSW0_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x00 0.--9. 1. " TS_PPM_HIGH_VAL                       ,Time stamp PPM High value"
group.long 0x3D058++0x3
line.long 0x00 "CPSW0_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x00 0.--7. 1. " TS_NUDGE_VAL                          ,Time stamp Nudge value"
group.long 0x3D0E0++0x3
line.long 0x00 "CPSW0_COMP_LOW_REG_l,Time Stamp Generate Function Comparison Low Value Offset = 0003D0E0h + (l * 20h); where l = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " COMP_LOW                              ,Time Stamp Generate Function Comparison Low Value"
group.long 0x3D0E4++0x3
line.long 0x00 "CPSW0_COMP_HIGH_REG_l,Time Stamp Generate Function Comparison high Value Offset = 0003D0E4h + (l * 20h); where l = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " COMP_HIGH                             ,Time Stamp Generate Function Comparison High Value"
group.long 0x3D0E8++0x3
line.long 0x00 "CPSW0_CONTROL_REG_l,Time Stamp Generate Function Control Offset = 0003D0E8h + (l * 20h); where l = 0h to 1h"
bitfld.long 0x00 1. " POLARITY_INV                          ,Time Stamp Generate Function Polarity Invert" "0,1"
bitfld.long 0x00 0. "         PPM_DIR                               ,Time Stamp Generate Function PPM Direction" "0,1"
group.long 0x3D0EC++0x3
line.long 0x00 "CPSW0_LENGTH_REG_l,Time Stamp Generate Function Length Value Offset = 0003D0ECh + (l * 20h); where l = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " LENGTH                                ,Time Stamp Generate Function Length Value"
group.long 0x3D0F0++0x3
line.long 0x00 "CPSW0_PPM_LOW_REG_L,Time Stamp Generate Function PPM Low Value Offset = 0003D0F0h + (l * 20h); where l = 0h to 1h"
hexmask.long 0x00 0.--31. 1. " PPM_LOW                               ,Time Stamp Generate Function PPM Low Value"
group.long 0x3D0F4++0x3
line.long 0x00 "CPSW0_PPM_HIGH_REG_l,Time Stamp Generate Function PPM High Value Offset = 0003D0F4h + (l * 20h); where l = 0h to 1h"
hexmask.long.word 0x00 0.--9. 1. " PPM_HIGH                              ,Time Stamp Generate Function PPM High Value"
group.long 0x3D0F8++0x3
line.long 0x00 "CPSW0_NUDGE_REG_l,Time Stamp Generate Function Nudge Value Offset = 0003D0F8h + (l * 20h); where l = 0h to 1h"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE                                 ,Time Stamp Generate Function Nudge Value"
group.long 0x3D200++0x3
line.long 0x00 "CPSW0_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
hexmask.long 0x00 0.--31. 1. " COMP_LOW                              ,Time Stamp ESTF Generate Function Comparison Low Value"
group.long 0x3D204++0x3
line.long 0x00 "CPSW0_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
hexmask.long 0x00 0.--31. 1. " COMP_HIGH                             ,Time Stamp ESTF Generate Function Comparison High Value"
group.long 0x3D208++0x3
line.long 0x00 "CPSW0_TS_GENF_CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x00 1. " POLARITY_INV                          ,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
bitfld.long 0x00 0. "         PPM_DIR                               ,Time Stamp ESTF Generate Function PPM Direction" "0,1"
group.long 0x3D20C++0x3
line.long 0x00 "CPSW0_LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
hexmask.long 0x00 0.--31. 1. " LENGTH                                ,Time Stamp ESTF Generate Function Length Value"
group.long 0x3D210++0x3
line.long 0x00 "CPSW0_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
hexmask.long 0x00 0.--31. 1. " PPM_LOW                               ,Time Stamp ESTF Generate Function PPM Low Value"
group.long 0x3D214++0x3
line.long 0x00 "CPSW0_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x00 0.--9. 1. " PPM_HIGH                              ,Time Stamp ESTF Generate Function PPM High Value"
group.long 0x3D218++0x3
line.long 0x00 "CPSW0_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE                                 ,Time Stamp ESTF Generate Function Nudge Value"
rgroup.long 0x3E000++0x3
line.long 0x00 "CPSW0_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT                              ,Identification value"
bitfld.long 0x00 11.--15. "      RTL_VER                               ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                               "
bitfld.long 0x00 8.--10. " MAJOR_VER                             ,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER                             ,Minor version value"
rgroup.long 0x3E004++0x3
line.long 0x00 "CPSW0_ALE_STATUS_REG,Status"
hexmask.long.byte 0x00 8.--15. 1. " POLICERS_DIV_8                        ,The number of policing entries divided by 8"
hexmask.long.byte 0x00 0.--7. 1. "        ENTRIES_DIV_1024                      ,The number of ALE entries in the ALE table divided by 1024"
group.long 0x3E008++0x3
line.long 0x00 "CPSW0_ALE_CONTROL_REG,Control"
bitfld.long 0x00 31. " ENABLE                                ,Enable ALE" "0,1"
bitfld.long 0x00 30. "         CLEAR_TABLE                           ,Clear ALE Address table" "0,1"
textline "                                               "
bitfld.long 0x00 29. " AGE_OUT_NOW                           ,Age Out Address Table Now" "0,1"
bitfld.long 0x00 24. "         MIRROR_DP                             ,This field defines the port to which traffic destined will be duplicated to" "0,1"
textline "                                               "
bitfld.long 0x00 21.--23. " UPD_BW_CTL                            ,The upd_bw_ctrl field allows for up to 8 times the rate in which adds, updates, touches, writes, and aging updates can occur" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         MIRROR_TOP                            ,This field defines the destination port for the mirror traffic" "0,1"
textline "                                               "
bitfld.long 0x00 15. " REG_UPD_STATIC                        ,Reg Update Static" "0,1"
bitfld.long 0x00 13. "         UVLAN_NO_LEARN                        ,Unknown VLAN No Learn" "0,1"
textline "                                               "
bitfld.long 0x00 12. " MIRROR_MEN                            ,Mirror Match Entry Enable" "0,1"
bitfld.long 0x00 11. "         MIRROR_DEN                            ,Mirror Destination Port Enable" "0,1"
textline "                                               "
bitfld.long 0x00 10. " MIRROR_SEN                            ,Mirror Source Port Enable" "0,1"
bitfld.long 0x00 8. "         UNI_FLOOD_TO_HOST                     ,Enable Port 0 Unicast Flood" "0,1"
textline "                                               "
bitfld.long 0x00 7. " LEARN_NO_VID                          ,Learn No VID" "0,1"
bitfld.long 0x00 6. "         EN_VID0_MODE                          ,Enable VLAN ID = 0 Mode" "0,1"
textline "                                               "
bitfld.long 0x00 5. " ENABLE_OUI_DENY                       ,Enable OUI Deny Mode" "0,1"
bitfld.long 0x00 4. "         BYPASS                                ,ALE Bypass" "0,1"
textline "                                               "
bitfld.long 0x00 3. " RATE_LIMIT_TX                         ,Rate Limit Transmit Mode" "0,1"
bitfld.long 0x00 2. "         VLAN_AWARE                            ,ALE VLAN Aware" "0,1"
textline "                                               "
bitfld.long 0x00 1. " ENABLE_AUTH_MODE                      ,Enable MAC Authorization Mode" "0,1"
bitfld.long 0x00 0. "         ENABLE_RATE_LIMIT                     ,Enable Broadcast and Multicast Rate Limit" "0,1"
group.long 0x3E00C++0x3
line.long 0x00 "CPSW0_ALE_CONTROL2_REG,Control 2"
bitfld.long 0x00 31. " TRK_EN_DST                            ,Trunk Destination Enable" "0,1"
bitfld.long 0x00 30. "         TRK_EN_SRC                            ,Trunk Source Enable" "0,1"
textline "                                               "
bitfld.long 0x00 29. " TRK_EN_PRI                            ,Trunk Priority Enable" "0,1"
bitfld.long 0x00 27. "         TRK_EN_VLAN                           ,Trunk VLAN Enable" "0,1"
textline "                                               "
bitfld.long 0x00 25. " TRK_EN_SIP                            ,Trunk Source IP Address Enable" "0,1"
bitfld.long 0x00 24. "         TRK_EN_DIP                            ,Trunk Destination IP Address Enable" "0,1"
textline "                                               "
bitfld.long 0x00 16.--18. " TRK_BASE                              ,Trunk Base" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--5. "         MIRROR_MIDX                           ,Mirror Match Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E010++0x3
line.long 0x00 "CPSW0_PRESCALE_REG,Prescale"
hexmask.long.tbyte 0x00 0.--19. 1. " PRESCALE                              ,ALE Prescale Register"
group.long 0x3E014++0x3
line.long 0x00 "CPSW0_AGING_TIMER_REG,Aging Timer"
bitfld.long 0x00 31. " PRESCALE_1_DISABLE                    ,ALE Prescaler 1 Disable: When set, removes 1,000 from the auto aging multiplier." "0,1"
bitfld.long 0x00 30. "         PRESCALE_2_DISABLE                    ,ALE Prescaler 2 Disable: When set, removes 1,000 from the auto aging multiplier." "0,1"
textline "                                               "
hexmask.long.tbyte 0x00 0.--23. 1. " AGING_TIMER                           ,ALE Aging Timer: When non-zero, auto-aging is enabled."
group.long 0x3E020++0x3
line.long 0x00 "CPSW0_TABLE_CONTROL_REG,Table Control"
bitfld.long 0x00 31. " WRITE_RDZ                             ,Write Bit" "0,1"
bitfld.long 0x00 0.--5. "         ENTRY_POINTER                         ,Table Entry Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E034++0x3
line.long 0x00 "CPSW0_TABLE_WORD2_REG,Table Word 2"
hexmask.long.byte 0x00 0.--6. 1. " ENTRY_71_64                           ,Table Entry Bits 70:64"
group.long 0x3E038++0x3
line.long 0x00 "CPSW0_TABLE_WORD1_REG,Table Word 1"
hexmask.long 0x00 0.--31. 1. " ENTRY_63_32                           ,Table Entry Bits 63:32"
group.long 0x3E03C++0x3
line.long 0x00 "CPSW0_TABLE_WORD0_REG,Table Word 0"
hexmask.long 0x00 0.--31. 1. " ENTRY_31_0                            ,Table Entry Bits 31:0"
group.long 0x3E090++0x3
line.long 0x00 "CPSW0_UNKNOWN_VLAN_REG,Unknown VLAN Member List"
bitfld.long 0x00 0.--1. " LIST                                  ,Unknown VLAN Member List" "0,1,2,3"
group.long 0x3E094++0x3
line.long 0x00 "CPSW0_UNKNOWN_MCAST_FLOOD_REG,Unknown VLAN Multicast Flood Mask"
bitfld.long 0x00 0.--1. " MASK                                  ,Unknown VLAN Multicast Flood Mask" "0,1,2,3"
group.long 0x3E098++0x3
line.long 0x00 "CPSW0_UNKNOWN_REG_MCAST_FLOOD_REG,Unknown VLAN Multicast Flood Mask"
bitfld.long 0x00 0.--1. " MASK                                  ,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3"
group.long 0x3E09C++0x3
line.long 0x00 "CPSW0_FORCE_UNTAGGED_EGRESS_REG,Unknown VLAN Force Untagged Egress"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
rgroup.long 0x3E0C0++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX0_REG,VLAN Mask Mux 0 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0C4++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX1_REG,VLAN Mask Mux 1 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0C8++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX2_REG,VLAN Mask Mux 2 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0CC++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX3_REG,VLAN Mask Mux 3 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0D0++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX4_REG,VLAN Mask Mux 4 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0D4++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX5_REG,VLAN Mask Mux 5 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0D8++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX6_REG,VLAN Mask Mux 6 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0DC++0x3
line.long 0x00 "CPSW0_VLAN_MASK_MUX7_REG,VLAN Mask Mux 7 Select"
bitfld.long 0x00 0.--1. " MASK                                  ,Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E100++0x3
line.long 0x00 "CPSW0_POLICER_PORT_OUI_REG,Specifies the port, frame priority, and OUI address index as well as match enables for port, frame priority, and OUI address matching"
bitfld.long 0x00 31. " PORT_MEN                              ,Enabled port match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 30. "         TRUNK_ID                              ,When set indicates the port number is a trunk group" "0,1"
textline "                                               "
bitfld.long 0x00 25. " PORT_NUM                              ,If enabled, specifies the port address to match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 19. "         PRI_MEN                               ,Enabled frame priority match for the selected policing/classifier entry" "0,1"
textline "                                               "
bitfld.long 0x00 16.--18. " PRI_VAL                               ,If enabled, specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "         OUI_MEN                               ,Enabled frame OUI address match for the selected policing/classifier entry" "0,1"
textline "                                               "
bitfld.long 0x00 0.--5. " OUI_INDEX                             ,If enabled, specifies the ALE OUI address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E104++0x3
line.long 0x00 "CPSW0_POLICER_DA_SA_REG,Specifies the match enable/match index for the L2 destination and L2 source addresses"
bitfld.long 0x00 31. " DST_MEN                               ,Enabled frame L2 destination address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 16.--21. "         DST_INDEX                             ,If enabled, specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                               "
bitfld.long 0x00 15. " SRC_MEN                               ,Enabled frame L2 source address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 0.--5. "         SRC_INDEX                             ,If enabled, specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E108++0x3
line.long 0x00 "CPSW0_POLICER_VLAN_REG,Specifies the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x00 31. " OVLAN_MEN                             ,Enabled frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 16.--21. "         OVLAN_INDEX                           ,If enabled, specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                               "
bitfld.long 0x00 15. " IVLAN_MEN                             ,Enabled frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 0.--5. "         IVLAN_INDEX                           ,If enabled, specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E10C++0x3
line.long 0x00 "CPSW0_POLICER_ETHERTYPE_IPSA_REG,Specifies the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x00 31. " ETHERTYPE_MEN                         ,Enabled frame Ether Type match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 16.--21. "         ETHERTYPE_INDEX                       ,If enabled, specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                               "
bitfld.long 0x00 15. " IPSRC_MEN                             ,Enabled frame IP Source address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 0.--5. "         IPSRC_INDEX                           ,If enabled, specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E110++0x3
line.long 0x00 "CPSW0_POLICER_IPDA_REG,Specifies the match enable/match index for the IP Destination address"
bitfld.long 0x00 31. " IPDST_MEN                             ,Enabled frame IP Destination address match for the selected policing/classifier entry" "0,1"
bitfld.long 0x00 16.--21. "         IPDST_INDEX                           ,If enabled, specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E118++0x3
line.long 0x00 "CPSW0_POLICER_PIR_REG,Specifies the PIR idle increment value"
hexmask.long 0x00 0.--31. 1. " PRI_IDLE_INC_VAL                      ,The number added to the PIR counter every clock cycle. If 0, the PIR counter is disabled and packets will never be marked or processed as RED."
group.long 0x3E11C++0x3
line.long 0x00 "CPSW0_POLICER_CIR_REG,Specifies the CIR idle increment value"
hexmask.long 0x00 0.--31. 1. " CIR_IDLE_INC_VAL                      ,The number added to the CIR counter every clock cycle. If 0, the CIR counter is disabled."
group.long 0x3E120++0x3
line.long 0x00 "CPSW0_POLICER_TBL_CTL_REG,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x00 31. " WRITE_ENABLE                          ,Setting this bit will write the POLICER_CFG 0-7 to the pol_tbl_index selected policing/classifier entry" "0,1"
bitfld.long 0x00 0.--2. "         POL_TBL_INDEX                         ,This field specifies the policing/classifier entry to be read or written" "0,1,2,3,4,5,6,7"
group.long 0x3E124++0x3
line.long 0x00 "CPSW0_POLICER_CTL_REG,The Control Enables color marking as well as internal ALE packet dropping"
bitfld.long 0x00 31. " POL_EN                                ,Enables the policing to color the packets. This also enables red or yellow drop capabilities." "0,1"
bitfld.long 0x00 29. "         RED_DROP_EN                           ,Red Drop Enable" "0,1"
textline "                                               "
bitfld.long 0x00 28. " YELLOW_DROP_EN                        ,Yellow Drop Enable" "0,1"
bitfld.long 0x00 24.--26. "         YELLOW_THRESH                         ,Yellow Drop Threshold" "0,1,2,3,4,5,6,7"
textline "                                               "
bitfld.long 0x00 22.--23. " POL_MATCH_MODE                        ,Policing Match Mode determines what happens to packets that fail to hit any policing/classifier entry" "0,1,2,3"
group.long 0x3E128++0x3
line.long 0x00 "CPSW0_POLICER_TEST_CTL_REG,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x00 31. " POL_CLR                               ,Policer Clear - This bit clears all the policer/classifier hit bits (policer_hit, policer_hit_red, and policer_hit_yellow bits for all policer/classifiers)" "0,1"
bitfld.long 0x00 30. "         POL_CLR_RED                           ,Policer Clear RED - This bit clears all policer/classifier RED hit bits (policer_hit_red for all policer/classifiers)" "0,1"
textline "                                               "
bitfld.long 0x00 29. " POL_CLR_YELLOW                        ,Policer Clear YELLOW - This bit clears all policer/classifier YELLOW hit bits (policer_hit_yellow for all policer/classifiers)" "0,1"
bitfld.long 0x00 28. "         POL_CLR_SELECTED                      ,Policer Clear Selected - This bit clears the selected policer/classifier policer_hit, policer_hit_red, and policer_hit_yellow bits" "0,1"
textline "                                               "
bitfld.long 0x00 0.--2. " POL_TEST_ENTRY                        ,Policer Test Entry Pointer - This field selects the policer/classifier entry that will have hit bits read or written" "0,1,2,3,4,5,6,7"
rgroup.long 0x3E12C++0x3
line.long 0x00 "CPSW0_POLICER_HIT_STATUS_REG,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x00 31. " POL_HIT                               ,This indicates that the selected policing/classifier via the pol_test_index field has been hit by a packet seen on any port that matches the policing/classifier entry match." "0,1"
bitfld.long 0x00 30. "         POL_HIT_RED                           ,This indicates that the selected policing/classifier via the pol_test_index field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match." "0,1"
textline "                                               "
bitfld.long 0x00 29. " POL_HIT_YELLOW                        ,This indicates that the selected policing/classifier via the pol_test_index field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match." "0,1"
group.long 0x3E134++0x3
line.long 0x00 "CPSW0_THREAD_DEF_REG,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched"
bitfld.long 0x00 15. " ENABLE                                ,This field is the read or written enable for the Default Thread ID. When set, the switch will use the def_thread_val for the default thread ID if no classifier is matched. If clear, the switch will generate its own thread ID based on port and priority if there is no classifier match." "0,1"
bitfld.long 0x00 0.--5. "         VALUE                                 ,This field is the read or written default thread ID value that is used for host traffic." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E138++0x3
line.long 0x00 "CPSW0_THREAD_CTL_REG,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
bitfld.long 0x00 0.--2. " ENTRY_PTR                             ,Policer Thread Entry Pointer." "0,1,2,3,4,5,6,7"
group.long 0x3E13C++0x3
line.long 0x00 "CPSW0_THREAD_VAL_REG,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x00 15. " ENABLE                                ,This field is the read or written enable for the Thread ID. When set, the switch will use the thread_val for the particular classifier match. If clear, the switch will generate its own thread ID based on port and priority." "0,1"
bitfld.long 0x00 0.--5. "         VALUE                                 ,This field is the read or written thread ID value that is used to map a classifier hit to thread ID for host traffic." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xEE040++0x3
line.long 0x00 "CPSW0_PORT_CONTROL_REG_y,Port N Control Offset = 0003E040h + (y * 4h); where y = 0h to 1h"
hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT                           ,Broadcast Packet Rate Limit"
hexmask.long.byte 0x00 16.--23. 1. "        MCAST_LIMIT                           ,Multicast Packet Rate Limit"
textline "                                               "
bitfld.long 0x00 15. " DROP_DBL_VLAN                         ,DROP Double VLAN" "0,1"
bitfld.long 0x00 14. "         DROP_DUAL_VLAN                        ,DROP Dual VLAN" "0,1"
textline "                                               "
bitfld.long 0x00 13. " MAC_ONLY_CAF                          ,MAC Only Copy All Frames" "0,1"
bitfld.long 0x00 12. "         DISABLE_AUTH_MODE                     ,Disable MAC Authorization Mode" "0,1"
textline "                                               "
bitfld.long 0x00 11. " MAC_ONLY                              ,MAC Only Mode" "0,1"
bitfld.long 0x00 10. "         TRUNK_EN                              ,Trunk Enable" "0,1"
textline "                                               "
bitfld.long 0x00 8.--9. " TRUNK_NUMBER                          ,Trunk Number" "0,1,2,3"
bitfld.long 0x00 7. "         MIRROR_SP                             ,Mirror Source Port Enable" "0,1"
textline "                                               "
bitfld.long 0x00 5. " NO_SA_UPDATE                          ,No Source Address Update" "0,1"
bitfld.long 0x00 4. "         NO_LEARN                              ,No Learn Mode" "0,1"
textline "                                               "
bitfld.long 0x00 3. " VID_INGRESS_CHECK                     ,VLAN ID Ingress Check" "0,1"
bitfld.long 0x00 2. "         DROP_UNTAGGED                         ,Drop Untagged Packets" "0,1"
textline "                                               "
bitfld.long 0x00 0.--1. " PORT_STATE                            ,Port State" "0,1,2,3"
width 0x0B
tree.end
tree "MCU_CPSW0_ECC"
base ad:0x40709000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "CPSW0_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME              ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                  ,bu" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID           ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL              ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " REVMAJ              ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM              ,Custom version" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " REVMIN              ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "CPSW0_VECTOR,ECC Vector Register"
in
textline "                                    "
rgroup.long 0xC++0x3
line.long 0x00 "CPSW0_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS            ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "CPSW0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR              ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "CPSW0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 19. " RAMECC19_PEND       ,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "     RAMECC18_PEND       ,Interrupt Pending Status for ramecc18_pend" "0,1"
textline "                                    "
bitfld.long 0x00 17. " RAMECC17_PEND       ,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "     RAMECC16_PEND       ,Interrupt Pending Status for ramecc16_pend" "0,1"
textline "                                    "
bitfld.long 0x00 15. " RAMECC15_PEND       ,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "     RAMECC14_PEND       ,Interrupt Pending Status for ramecc14_pend" "0,1"
textline "                                    "
bitfld.long 0x00 13. " RAMECC13_PEND       ,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "     RAMECC12_PEND       ,Interrupt Pending Status for ramecc12_pend" "0,1"
textline "                                    "
bitfld.long 0x00 11. " RAMECC11_PEND       ,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "     RAMECC10_PEND       ,Interrupt Pending Status for ramecc10_pend" "0,1"
textline "                                    "
bitfld.long 0x00 9. " RAMECC9_PEND        ,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "     RAMECC8_PEND        ,Interrupt Pending Status for ramecc8_pend" "0,1"
textline "                                    "
bitfld.long 0x00 7. " RAMECC7_PEND        ,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "     RAMECC6_PEND        ,Interrupt Pending Status for ramecc6_pend" "0,1"
textline "                                    "
bitfld.long 0x00 5. " RAMECC5_PEND        ,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "     RAMECC4_PEND        ,Interrupt Pending Status for ramecc4_pend" "0,1"
textline "                                    "
bitfld.long 0x00 3. " RAMECC3_PEND        ,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "     RAMECC2_PEND        ,Interrupt Pending Status for ramecc2_pend" "0,1"
textline "                                    "
bitfld.long 0x00 1. " RAMECC1_PEND        ,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "     RAMECC0_PEND        ,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "CPSW0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. " RAMECC19_ENABLE_SET ,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "     RAMECC18_ENABLE_SET ,Interrupt Enable Set Register for ramecc18_pend" "0,1"
textline "                                    "
bitfld.long 0x00 17. " RAMECC17_ENABLE_SET ,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "     RAMECC16_ENABLE_SET ,Interrupt Enable Set Register for ramecc16_pend" "0,1"
textline "                                    "
bitfld.long 0x00 15. " RAMECC15_ENABLE_SET ,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "     RAMECC14_ENABLE_SET ,Interrupt Enable Set Register for ramecc14_pend" "0,1"
textline "                                    "
bitfld.long 0x00 13. " RAMECC13_ENABLE_SET ,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "     RAMECC12_ENABLE_SET ,Interrupt Enable Set Register for ramecc12_pend" "0,1"
textline "                                    "
bitfld.long 0x00 11. " RAMECC11_ENABLE_SET ,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "     RAMECC10_ENABLE_SET ,Interrupt Enable Set Register for ramecc10_pend" "0,1"
textline "                                    "
bitfld.long 0x00 9. " RAMECC9_ENABLE_SET  ,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "     RAMECC8_ENABLE_SET  ,Interrupt Enable Set Register for ramecc8_pend" "0,1"
textline "                                    "
bitfld.long 0x00 7. " RAMECC7_ENABLE_SET  ,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "     RAMECC6_ENABLE_SET  ,Interrupt Enable Set Register for ramecc6_pend" "0,1"
textline "                                    "
bitfld.long 0x00 5. " RAMECC5_ENABLE_SET  ,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "     RAMECC4_ENABLE_SET  ,Interrupt Enable Set Register for ramecc4_pend" "0,1"
textline "                                    "
bitfld.long 0x00 3. " RAMECC3_ENABLE_SET  ,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "     RAMECC2_ENABLE_SET  ,Interrupt Enable Set Register for ramecc2_pend" "0,1"
textline "                                    "
bitfld.long 0x00 1. " RAMECC1_ENABLE_SET  ,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "     RAMECC0_ENABLE_SET  ,Interrupt Enable Set Register for ramecc0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "CPSW0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x13C++0x3
line.long 0x00 "CPSW0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR              ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "CPSW0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 19. " RAMECC19_PEND       ,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "     RAMECC18_PEND       ,Interrupt Pending Status for ramecc18_pend" "0,1"
textline "                                    "
bitfld.long 0x00 17. " RAMECC17_PEND       ,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "     RAMECC16_PEND       ,Interrupt Pending Status for ramecc16_pend" "0,1"
textline "                                    "
bitfld.long 0x00 15. " RAMECC15_PEND       ,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "     RAMECC14_PEND       ,Interrupt Pending Status for ramecc14_pend" "0,1"
textline "                                    "
bitfld.long 0x00 13. " RAMECC13_PEND       ,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "     RAMECC12_PEND       ,Interrupt Pending Status for ramecc12_pend" "0,1"
textline "                                    "
bitfld.long 0x00 11. " RAMECC11_PEND       ,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "     RAMECC10_PEND       ,Interrupt Pending Status for ramecc10_pend" "0,1"
textline "                                    "
bitfld.long 0x00 9. " RAMECC9_PEND        ,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "     RAMECC8_PEND        ,Interrupt Pending Status for ramecc8_pend" "0,1"
textline "                                    "
bitfld.long 0x00 7. " RAMECC7_PEND        ,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "     RAMECC6_PEND        ,Interrupt Pending Status for ramecc6_pend" "0,1"
textline "                                    "
bitfld.long 0x00 5. " RAMECC5_PEND        ,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "     RAMECC4_PEND        ,Interrupt Pending Status for ramecc4_pend" "0,1"
textline "                                    "
bitfld.long 0x00 3. " RAMECC3_PEND        ,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "     RAMECC2_PEND        ,Interrupt Pending Status for ramecc2_pend" "0,1"
textline "                                    "
bitfld.long 0x00 1. " RAMECC1_PEND        ,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "     RAMECC0_PEND        ,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "CPSW0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. " RAMECC19_ENABLE_SET ,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "     RAMECC18_ENABLE_SET ,Interrupt Enable Set Register for ramecc18_pend" "0,1"
textline "                                    "
bitfld.long 0x00 17. " RAMECC17_ENABLE_SET ,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "     RAMECC16_ENABLE_SET ,Interrupt Enable Set Register for ramecc16_pend" "0,1"
textline "                                    "
bitfld.long 0x00 15. " RAMECC15_ENABLE_SET ,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "     RAMECC14_ENABLE_SET ,Interrupt Enable Set Register for ramecc14_pend" "0,1"
textline "                                    "
bitfld.long 0x00 13. " RAMECC13_ENABLE_SET ,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "     RAMECC12_ENABLE_SET ,Interrupt Enable Set Register for ramecc12_pend" "0,1"
textline "                                    "
bitfld.long 0x00 11. " RAMECC11_ENABLE_SET ,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "     RAMECC10_ENABLE_SET ,Interrupt Enable Set Register for ramecc10_pend" "0,1"
textline "                                    "
bitfld.long 0x00 9. " RAMECC9_ENABLE_SET  ,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "     RAMECC8_ENABLE_SET  ,Interrupt Enable Set Register for ramecc8_pend" "0,1"
textline "                                    "
bitfld.long 0x00 7. " RAMECC7_ENABLE_SET  ,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "     RAMECC6_ENABLE_SET  ,Interrupt Enable Set Register for ramecc6_pend" "0,1"
textline "                                    "
bitfld.long 0x00 5. " RAMECC5_ENABLE_SET  ,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "     RAMECC4_ENABLE_SET  ,Interrupt Enable Set Register for ramecc4_pend" "0,1"
textline "                                    "
bitfld.long 0x00 3. " RAMECC3_ENABLE_SET  ,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "     RAMECC2_ENABLE_SET  ,Interrupt Enable Set Register for ramecc2_pend" "0,1"
textline "                                    "
bitfld.long 0x00 1. " RAMECC1_ENABLE_SET  ,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "     RAMECC0_ENABLE_SET  ,Interrupt Enable Set Register for ramecc0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "CPSW0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x200++0x3
line.long 0x00 "CPSW0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT             ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY              ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "CPSW0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                    "
group.long 0x208++0x3
line.long 0x00 "CPSW0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT             ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY              ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "CPSW0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT             ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY              ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "CPU0_ECC_AGGR_CFG_REGS"
base ad:0x40080000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                                         ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                                            ,bu" "0,1,2,3"
textline "                              "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                                      ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                                        ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 8.--10. " REVMAJ                                         ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                                        ,Custom version" "0,1,2,3"
textline "                              "
bitfld.long 0x00 0.--5. " REVMIN                                         ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "VECTOR,ECC Vector Register"
in
textline "                              "
rgroup.long 0xC++0x3
line.long 0x00 "STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                                       ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                                         ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 31. " CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND       ,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND          ,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND          ,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU0_VBUSM2AXI_EDC_PEND                       ,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU0_KS_VIM_RAMECC_PEND                        ,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM0_BANK1_PEND                             ,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM0_BANK0_PEND                              ,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM0_BANK1_PEND                             ,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM0_BANK0_PEND                              ,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM0_BANK1_PEND                              ,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM0_BANK0_PEND                               ,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU0_DDATA_RAM7_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU0_DDATA_RAM6_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU0_DDATA_RAM5_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU0_DDATA_RAM4_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU0_DDATA_RAM3_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU0_DDATA_RAM2_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU0_DDATA_RAM1_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU0_DDATA_RAM0_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU0_DDIRTY_RAM_PEND                          ,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU0_DTAG_RAM3_PEND                            ,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU0_DTAG_RAM2_PEND                           ,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU0_DTAG_RAM1_PEND                            ,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU0_DTAG_RAM0_PEND                           ,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU0_IDATA_BANK3_PEND                          ,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU0_IDATA_BANK2_PEND                         ,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU0_IDATA_BANK1_PEND                          ,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU0_IDATA_BANK0_PEND                         ,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU0_ITAG_RAM3_PEND                            ,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU0_ITAG_RAM2_PEND                           ,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_ITAG_RAM1_PEND                            ,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_ITAG_RAM0_PEND                           ,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x44++0x3
line.long 0x00 "SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x00 3. " CPU0_EDC_CTRL_PEND                             ,Interrupt Pending Status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "     SCRP_EDC_PEND                                 ,Interrupt Pending Status for scrp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_AHB2VBUSP_EDC_PEND                        ,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND       ,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. " CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU0_VBUSM2AXI_EDC_ENABLE_SET                 ,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU0_KS_VIM_RAMECC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM0_BANK1_ENABLE_SET                       ,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM0_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM0_BANK1_ENABLE_SET                       ,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM0_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM0_BANK1_ENABLE_SET                        ,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM0_BANK0_ENABLE_SET                         ,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU0_DDATA_RAM7_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU0_DDATA_RAM6_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU0_DDATA_RAM5_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU0_DDATA_RAM4_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU0_DDATA_RAM3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU0_DDATA_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU0_DDATA_RAM1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU0_DDATA_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU0_DDIRTY_RAM_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU0_DTAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU0_DTAG_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU0_DTAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU0_DTAG_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU0_IDATA_BANK3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU0_IDATA_BANK2_ENABLE_SET                   ,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU0_IDATA_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU0_IDATA_BANK0_ENABLE_SET                   ,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU0_ITAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU0_ITAG_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_ITAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_ITAG_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x84++0x3
line.long 0x00 "SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x00 3. " CPU0_EDC_CTRL_ENABLE_SET                       ,Interrupt Enable Set Register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "     SCRP_EDC_ENABLE_SET                           ,Interrupt Enable Set Register for scrp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_AHB2VBUSP_EDC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                              "
hgroup.long 0xC4++0x3
hide.long 0x00 "SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
in
textline "                              "
group.long 0x13C++0x3
line.long 0x00 "DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                                         ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 31. " CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND       ,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND          ,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND          ,Interrupt Pending Status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU0_VBUSM2AXI_EDC_PEND                       ,Interrupt Pending Status for cpu0_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU0_KS_VIM_RAMECC_PEND                        ,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM0_BANK1_PEND                             ,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM0_BANK0_PEND                              ,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM0_BANK1_PEND                             ,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM0_BANK0_PEND                              ,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM0_BANK1_PEND                              ,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM0_BANK0_PEND                               ,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU0_DDATA_RAM7_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU0_DDATA_RAM6_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU0_DDATA_RAM5_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU0_DDATA_RAM4_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU0_DDATA_RAM3_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU0_DDATA_RAM2_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU0_DDATA_RAM1_PEND                          ,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU0_DDATA_RAM0_PEND                           ,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU0_DDIRTY_RAM_PEND                          ,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU0_DTAG_RAM3_PEND                            ,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU0_DTAG_RAM2_PEND                           ,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU0_DTAG_RAM1_PEND                            ,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU0_DTAG_RAM0_PEND                           ,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU0_IDATA_BANK3_PEND                          ,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU0_IDATA_BANK2_PEND                         ,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU0_IDATA_BANK1_PEND                          ,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU0_IDATA_BANK0_PEND                         ,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU0_ITAG_RAM3_PEND                            ,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU0_ITAG_RAM2_PEND                           ,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_ITAG_RAM1_PEND                            ,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_ITAG_RAM0_PEND                           ,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x144++0x3
line.long 0x00 "DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x00 3. " CPU0_EDC_CTRL_PEND                             ,Interrupt Pending Status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "     SCRP_EDC_PEND                                 ,Interrupt Pending Status for scrp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_AHB2VBUSP_EDC_PEND                        ,Interrupt Pending Status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND       ,Interrupt Pending Status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. " CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU0_VBUSM2AXI_EDC_ENABLE_SET                 ,Interrupt Enable Set Register for cpu0_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU0_KS_VIM_RAMECC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM0_BANK1_ENABLE_SET                       ,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM0_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM0_BANK1_ENABLE_SET                       ,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM0_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM0_BANK1_ENABLE_SET                        ,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM0_BANK0_ENABLE_SET                         ,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU0_DDATA_RAM7_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU0_DDATA_RAM6_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU0_DDATA_RAM5_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU0_DDATA_RAM4_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU0_DDATA_RAM3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU0_DDATA_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU0_DDATA_RAM1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU0_DDATA_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU0_DDIRTY_RAM_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU0_DTAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU0_DTAG_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU0_DTAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU0_DTAG_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU0_IDATA_BANK3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU0_IDATA_BANK2_ENABLE_SET                   ,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU0_IDATA_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU0_IDATA_BANK0_ENABLE_SET                   ,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU0_ITAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU0_ITAG_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_ITAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_ITAG_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x184++0x3
line.long 0x00 "DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x00 3. " CPU0_EDC_CTRL_ENABLE_SET                       ,Interrupt Enable Set Register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "     SCRP_EDC_ENABLE_SET                           ,Interrupt Enable Set Register for scrp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU0_AHB2VBUSP_EDC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x00 0. "     CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                              "
hgroup.long 0x1C4++0x3
hide.long 0x00 "DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
in
textline "                              "
group.long 0x200++0x3
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                                        ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                                        ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                              "
group.long 0x208++0x3
line.long 0x00 "AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                                        ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                                        ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                                        ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                                        ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "CPU1_ECC_AGGR_CFG_REGS"
base ad:0x400C0000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                                         ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                                         ,bu" "0,1,2,3"
textline "                              "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                                      ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                                     ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 8.--10. " REVMAJ                                         ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                                     ,Custom version" "0,1,2,3"
textline "                              "
bitfld.long 0x00 0.--5. " REVMIN                                         ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "VECTOR,ECC Vector Register"
in
textline "                              "
rgroup.long 0xC++0x3
line.long 0x00 "STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                                       ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                                         ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 31. " CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND       ,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND       ,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND          ,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU1_VBUSM2AXI_EDC_PEND                    ,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU1_KS_VIM_RAMECC_PEND                        ,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM1_BANK1_PEND                          ,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM1_BANK0_PEND                              ,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM1_BANK1_PEND                          ,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM1_BANK0_PEND                              ,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM1_BANK1_PEND                           ,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM1_BANK0_PEND                               ,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU1_DDATA_RAM7_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU1_DDATA_RAM6_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU1_DDATA_RAM5_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU1_DDATA_RAM4_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU1_DDATA_RAM3_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU1_DDATA_RAM2_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU1_DDATA_RAM1_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU1_DDATA_RAM0_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU1_DDIRTY_RAM_PEND                       ,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU1_DTAG_RAM3_PEND                            ,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU1_DTAG_RAM2_PEND                        ,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU1_DTAG_RAM1_PEND                            ,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU1_DTAG_RAM0_PEND                        ,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU1_IDATA_BANK3_PEND                          ,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU1_IDATA_BANK2_PEND                      ,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU1_IDATA_BANK1_PEND                          ,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU1_IDATA_BANK0_PEND                      ,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU1_ITAG_RAM3_PEND                            ,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU1_ITAG_RAM2_PEND                        ,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU1_ITAG_RAM1_PEND                            ,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU1_ITAG_RAM0_PEND                        ,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x44++0x3
line.long 0x00 "SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x00 2. " CPU1_EDC_CTRL_PEND                             ,Interrupt Pending Status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "     CPU1_AHB2VBUSP_EDC_PEND                    ,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 0. " CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND        ,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. " CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU1_VBUSM2AXI_EDC_ENABLE_SET              ,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU1_KS_VIM_RAMECC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM1_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM1_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM1_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM1_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM1_BANK1_ENABLE_SET                     ,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM1_BANK0_ENABLE_SET                         ,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU1_DDATA_RAM7_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU1_DDATA_RAM6_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU1_DDATA_RAM5_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU1_DDATA_RAM4_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU1_DDATA_RAM3_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU1_DDATA_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU1_DDATA_RAM1_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU1_DDATA_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU1_DDIRTY_RAM_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU1_DTAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU1_DTAG_RAM2_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU1_DTAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU1_DTAG_RAM0_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU1_IDATA_BANK3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU1_IDATA_BANK2_ENABLE_SET                ,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU1_IDATA_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU1_IDATA_BANK0_ENABLE_SET                ,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU1_ITAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU1_ITAG_RAM2_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU1_ITAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU1_ITAG_RAM0_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x84++0x3
line.long 0x00 "SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x00 2. " CPU1_EDC_CTRL_ENABLE_SET                       ,Interrupt Enable Set Register for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "     CPU1_AHB2VBUSP_EDC_ENABLE_SET              ,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 0. " CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET  ,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                              "
hgroup.long 0xC4++0x3
hide.long 0x00 "SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
in
textline "                              "
group.long 0x13C++0x3
line.long 0x00 "DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                                         ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 31. " CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND       ,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND       ,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND          ,Interrupt Pending Status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU1_VBUSM2AXI_EDC_PEND                    ,Interrupt Pending Status for cpu1_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU1_KS_VIM_RAMECC_PEND                        ,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM1_BANK1_PEND                          ,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM1_BANK0_PEND                              ,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM1_BANK1_PEND                          ,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM1_BANK0_PEND                              ,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM1_BANK1_PEND                           ,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM1_BANK0_PEND                               ,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU1_DDATA_RAM7_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU1_DDATA_RAM6_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU1_DDATA_RAM5_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU1_DDATA_RAM4_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU1_DDATA_RAM3_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU1_DDATA_RAM2_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU1_DDATA_RAM1_PEND                       ,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU1_DDATA_RAM0_PEND                           ,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU1_DDIRTY_RAM_PEND                       ,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU1_DTAG_RAM3_PEND                            ,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU1_DTAG_RAM2_PEND                        ,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU1_DTAG_RAM1_PEND                            ,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU1_DTAG_RAM0_PEND                        ,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU1_IDATA_BANK3_PEND                          ,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU1_IDATA_BANK2_PEND                      ,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU1_IDATA_BANK1_PEND                          ,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU1_IDATA_BANK0_PEND                      ,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU1_ITAG_RAM3_PEND                            ,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU1_ITAG_RAM2_PEND                        ,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU1_ITAG_RAM1_PEND                            ,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU1_ITAG_RAM0_PEND                        ,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x144++0x3
line.long 0x00 "DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x00 2. " CPU1_EDC_CTRL_PEND                             ,Interrupt Pending Status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "     CPU1_AHB2VBUSP_EDC_PEND                    ,Interrupt Pending Status for cpu1_ahb2vbusp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 0. " CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND        ,Interrupt Pending Status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. " CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "     CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET ,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 29. " CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET    ,Interrupt Enable Set Register for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "     CPU1_VBUSM2AXI_EDC_ENABLE_SET              ,Interrupt Enable Set Register for cpu1_vbusm2axi_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 27. " CPU1_KS_VIM_RAMECC_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "     B1TCM1_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 25. " B1TCM1_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "     B0TCM1_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 23. " B0TCM1_BANK0_ENABLE_SET                        ,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "     ATCM1_BANK1_ENABLE_SET                     ,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
textline "                              "
bitfld.long 0x00 21. " ATCM1_BANK0_ENABLE_SET                         ,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "     CPU1_DDATA_RAM7_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
textline "                              "
bitfld.long 0x00 19. " CPU1_DDATA_RAM6_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "     CPU1_DDATA_RAM5_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
textline "                              "
bitfld.long 0x00 17. " CPU1_DDATA_RAM4_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "     CPU1_DDATA_RAM3_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
textline "                              "
bitfld.long 0x00 15. " CPU1_DDATA_RAM2_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "     CPU1_DDATA_RAM1_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
textline "                              "
bitfld.long 0x00 13. " CPU1_DDATA_RAM0_ENABLE_SET                     ,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "     CPU1_DDIRTY_RAM_ENABLE_SET                 ,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
textline "                              "
bitfld.long 0x00 11. " CPU1_DTAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "     CPU1_DTAG_RAM2_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 9. " CPU1_DTAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "     CPU1_DTAG_RAM0_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
textline "                              "
bitfld.long 0x00 7. " CPU1_IDATA_BANK3_ENABLE_SET                    ,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "     CPU1_IDATA_BANK2_ENABLE_SET                ,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
textline "                              "
bitfld.long 0x00 5. " CPU1_IDATA_BANK1_ENABLE_SET                    ,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "     CPU1_IDATA_BANK0_ENABLE_SET                ,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
textline "                              "
bitfld.long 0x00 3. " CPU1_ITAG_RAM3_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "     CPU1_ITAG_RAM2_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
textline "                              "
bitfld.long 0x00 1. " CPU1_ITAG_RAM1_ENABLE_SET                      ,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "     CPU1_ITAG_RAM0_ENABLE_SET                  ,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x184++0x3
line.long 0x00 "DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x00 2. " CPU1_EDC_CTRL_ENABLE_SET                       ,Interrupt Enable Set Register for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "     CPU1_AHB2VBUSP_EDC_ENABLE_SET              ,Interrupt Enable Set Register for cpu1_ahb2vbusp_edc_pend" "0,1"
textline "                              "
bitfld.long 0x00 0. " CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET  ,Interrupt Enable Set Register for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                              "
hgroup.long 0x1C4++0x3
hide.long 0x00 "DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
in
textline "                              "
group.long 0x200++0x3
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                                        ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                                     ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                              "
group.long 0x208++0x3
line.long 0x00 "AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                                        ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                                     ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                                        ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                                     ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "DCC"
tree "DCC0"
base ad:0x800000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC1"
base ad:0x804000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC2"
base ad:0x808000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC3"
base ad:0x80C000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC4"
base ad:0x810000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC5"
base ad:0x814000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC6"
base ad:0x818000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "DCC7"
base ad:0x81C000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_DCC0"
base ad:0x40100000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_DCC1"
base ad:0x40110000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "MCU_DCC2"
base ad:0x40120000
width 15.
group.long 0x0++0x3
line.long 0x00 "DCCGCTRL,DCC Global Control Register"
bitfld.long 0x00 12.--15. " DONEENA    ,The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      SINGLESHOT ,The SINGLESHOT bit enables/disables repetitive operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 4.--7. " ERRENA     ,The ERRENA bit enables/disables the error signal." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      DCCENA     ,The DCCENA bit starts and stops the operation of the DCC." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x4++0x3
line.long 0x00 "DCCREV,DCC Revision ID"
bitfld.long 0x00 30.--31. " SCHEME     ,User, privilege, and debug mode (read):" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "       FUNC       ,Reflects software-compatability. If there is no level a software compatability, a unique func number is assigned for compatible modules, the same number is maintained."
textline "                        "
bitfld.long 0x00 11.--15. " RTL        ,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "      MAJOR      ,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module." "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 6.--7. " CUSTOM     ,Indicates a special version of the module. May not be supported by standard software." "0,1,2,3"
bitfld.long 0x00 0.--5. "       MINOR      ,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DCCCNTSEED0,Count0 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,This field contains the seed value that gets loaded into Counter0 (clock source 0)."
group.long 0xC++0x3
line.long 0x00 "DCCVALIDSEED0,Valid0 Seed Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALIDSEED0 ,This field contains the seed value that gets loaded into the valid duration counter for clock source 0."
group.long 0x10++0x3
line.long 0x00 "DCCCNTSEED1,Count1 Seed Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED1 ,This field contains the seed value that gets loaded into Counter1 (clock source 1)."
group.long 0x14++0x3
line.long 0x00 "DCCSTAT,DCC Status Register"
bitfld.long 0x00 1. " DONEFLG    ,Indicates when single-shot mode is complete without error. Writing a 1h to this bit clears the flag." "0,1"
bitfld.long 0x00 0. "       ERRFLG     ,Indicates whether or not an error has occurred. Writing a 1h to this bit clears the flag." "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "DCCCNT0,Count0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0     ,This field contains the current value of Counter0."
rgroup.long 0x1C++0x3
line.long 0x00 "DCCVALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0     ,This field contains the current value of valid Counter0."
rgroup.long 0x20++0x3
line.long 0x00 "DCCCNT1,Count1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1     ,This field contains the current value of Counter1."
group.long 0x24++0x3
line.long 0x00 "DCCCLKSRC1,Clock Source Selection Register 1"
hexmask.long.word 0x00 16.--31. 1. " RES0       ,Reserved field."
bitfld.long 0x00 12.--15. "    KEY        ,This field enables or disables clock source selection." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
hexmask.long.byte 0x00 4.--11. 1. " RES1       ,Reserved field."
bitfld.long 0x00 0.--3. "      CLKSRC     ,This field specifies the clock source for COUNT1, when the KEY field enables this feature." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x3
line.long 0x00 "DCCCLKSRC0,Clock Source Selection Register 0"
bitfld.long 0x00 0.--3. " CLKSRC0    ,This field specifies the clock source for COUNT0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree.end
tree "DSS0_COMMON"
tree "DSS0_COMMON1"
base ad:0x4A01000
width 34.
wgroup.long 0x0++0x3
line.long 0x00 "DSS0_COMMON1_DISPC_IRQ_EOI,End Of Interrupt number"
bitfld.long 0x00 0. " EOI                        ,Software End Of Interrupt [EOI] control if pulse interrupts are used. Write 1 to acknowledge interrupt 0h = Write-0 : No action 1h = Write-1 : End-of-Interrupt" "0,1"
group.long 0x4++0x3
line.long 0x00 "DSS0_COMMON1_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status"
bitfld.long 0x00 4.--5. " VID_IRQ                    ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events. Bit [5] is for VIDL1 pipeline. Bit [4] is for VID pipeline. 0h = Write-0 : No action, Read-0 : No event pending 1h = Write-1 : Set event, Read-1 : IRQ event pending" "0,1,2,3"
bitfld.long 0x00 0.--1. "  VP_IRQ           ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events. Bit [1] is for VP2. Bit [0] is for VP1. 0h = Write-0 : No action, Read-0 : No event pending 1h = Write-1 : Set event, Read-1 : IRQ event pending" "0,1,2,3"
hgroup.long 0x8++0x3
hide.long 0x00 "DSS0_COMMON1_DISPC_IRQSTATUS,Interrupt status. Enabled status, isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared, i.e. even if not enabled"
in
textline "                                           "
group.long 0xC++0x3
line.long 0x00 "DSS0_COMMON1_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register"
bitfld.long 0x00 4.--5. " SET_VID_IRQ                ,VID IRQ Bit [5] is for VIDL1 pipeline. Bit [4] is for VID pipeline. 0h = Write-0 : No action, Read-0 : Interrupt Disabled 1h = Write-1 : Enable interrupt, Read-1 : Interrupt Enabled" "0,1,2,3"
bitfld.long 0x00 0.--1. "  SET_VP_IRQ       ,VP IRQ Bit [1] is for VP2. Bit [0] is for VP1. 0h = Write-0 : No action, Read-0 : Interrupt Disabled 1h = Write-1 : Enable interrupt, Read-1 : Interrupt Enabled" "0,1,2,3"
hgroup.long 0x10++0x3
hide.long 0x00 "DSS0_COMMON1_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable"
in
textline "                                           "
group.long 0x14++0x3
line.long 0x00 "DSS0_COMMON1_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 2. " SAFETYREGION_EN            ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 1. "  VIDENDWINDOW_EN  ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 0. " VIDBUFFERUNDERFLOW_EN      ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
group.long 0x18++0x3
line.long 0x00 "DSS0_COMMON1_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 2. " SAFETYREGION_EN            ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 1. "  VIDENDWINDOW_EN  ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 0. " VIDBUFFERUNDERFLOW_EN      ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
hgroup.long 0x24++0x3
hide.long 0x00 "DSS0_COMMON1_VID_IRQSTATUS_0,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field"
in
textline "                                           "
hgroup.long 0x28++0x3
hide.long 0x00 "DSS0_COMMON1_VID_IRQSTATUS_1,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field"
in
textline "                                           "
group.long 0x34++0x3
line.long 0x00 "DSS0_COMMON1_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 12. " DUMMY_EN                   ,Dummy IRQ for future use 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 11. "  VPSYNC_EN        ,Go bit clear event 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 10. " SECURITYVIOLATION_EN       ,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 6.--9. "  SAFETYREGION_EN  ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                           "
bitfld.long 0x00 5. " ACBIASCOUNTSTATUS_EN       ,AC BIAS transition counter has decremented to zero 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 4. "  VPSYNCLOST_EN    ,Synchronization Lost for Video Port 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 3. " VPPROGRAMMEDLINENUMBER_EN  ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 2. "  VPVSYNC_ODD_EN   ,VSYNC for odd field from interlace mode only 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 1. " VPVSYNC_EN                 ,Vertical Synchronization for VP 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 0. "  VPFRAMEDONE_EN   ,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
group.long 0x38++0x3
line.long 0x00 "DSS0_COMMON1_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 12. " DUMMY_EN                   ,Dummy IRQ for future use 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 11. "  VPSYNC_EN        ,Go bit clear event 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 10. " SECURITYVIOLATION_EN       ,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 6.--9. "  SAFETYREGION_EN  ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                           "
bitfld.long 0x00 5. " ACBIASCOUNTSTATUS_EN       ,AC BIAS transition counter has decremented to zero 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 4. "  VPSYNCLOST_EN    ,Synchronization Lost for Video Port 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 3. " VPPROGRAMMEDLINENUMBER_EN  ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 2. "  VPVSYNC_ODD_EN   ,VSYNC for odd field from interlace mode only 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                           "
bitfld.long 0x00 1. " VPVSYNC_EN                 ,Vertical Synchronization for VP 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 0. "  VPFRAMEDONE_EN   ,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
hgroup.long 0x40++0x3
hide.long 0x00 "DSS0_COMMON1_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit"
in
textline "                                           "
hgroup.long 0x44++0x3
hide.long 0x00 "DSS0_COMMON1_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit"
in
textline "                                           "
group.long 0x54++0x3
line.long 0x00 "DSS0_COMMON1_DISPC_SECURE,Security bit settings for different DISPC sub-modules"
bitfld.long 0x00 15.--16. " OVR_SECURE                 ,Secure bit for OVR Bit [16] is for OVR2. Bit [15] is for OVR1. 0h = Secure bit is reset 1h = Secure bit is set" "0,1,2,3"
bitfld.long 0x00 4.--5. "  VID_SECURE       ,Secure bit for VID Bit [5] is for VIDL1 pipeline. Bit [4] is for VID pipeline. 0h = Secure bit is reset 1h = Secure bit is set" "0,1,2,3"
textline "                                           "
bitfld.long 0x00 0.--1. " VP_SECURE                  ,Secure bit for VP Bit [1] is for VP2. Bit [0] is for VP1. 0h = Secure bit is reset 1h = Secure bit is set" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "DSS0_COMMON"
base ad:0x4A00000
width 42.
rgroup.long 0x4++0x3
line.long 0x00 "DSS0_COMMON_DSS_REVISION,This register contains the K3_DSS revision number"
hexmask.long.word 0x00 16.--31. 1. " MODID                      ,Module ID Field"
bitfld.long 0x00 11.--15. "      REVRTL               ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                   "
bitfld.long 0x00 8.--10. " REVMAJOR                   ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM               ,Custom" "0,1,2,3"
textline "                                                   "
bitfld.long 0x00 0.--5. " REVMIN                     ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "DSS0_COMMON_DSS_SYSCONFIG,This register controls various parameters related to software reset and IP idle"
bitfld.long 0x00 5. " WARMRESET                  ,Warm reset. Setting this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During read, it always returns 0. The warm reset keeps the configuration registers unchanged" "0,1"
bitfld.long 0x00 3.--4. "         IDLEMODE             ,Deprecated" "0,1,2,3"
textline "                                                   "
bitfld.long 0x00 1. " SOFTRESET                  ,Software reset. Setting this bit to 1 triggers a module reset. The bit is automatically reset by the hardware. During read, it always returns 0" "0,1"
bitfld.long 0x00 0. "         AUTOCLKGATING        ,Internal clock gating strategy 0h = Clocks are free-running 1h = Automatic clock gating strategy is applied, clocks are gated based on module activity" "0,1"
rgroup.long 0x20++0x3
line.long 0x00 "DSS0_COMMON_DSS_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information"
bitfld.long 0x00 9. " DISPC_IDLE_STATUS          ,Idle status of DISPC 0h = DISPC is not in Idle 1h = DISPC is in Idle" "0,1"
bitfld.long 0x00 5. "         OLDI_RESETDONE       ,Reset status of OLDI 0h = Internal module reset is on-going 1h = Reset completed" "0,1"
textline "                                                   "
bitfld.long 0x00 1.--2. " DISPC_VP_RESETDONE         ,Reset status of VP pixel clock domain But [2] is for VP2. Bit [1] is for VP1 0h = Internal module reset is on-going 1h = Reset completed" "0,1,2,3"
bitfld.long 0x00 0. "         DISPC_FUNC_RESETDONE ,Reset status of DISPC Functional clock domain 0h = Internal module reset is on-going 1h = Reset completed" "0,1"
wgroup.long 0x24++0x3
line.long 0x00 "DSS0_COMMON_DISPC_IRQ_EOI,End-Of-Interrupt register, to be used if pulse interrupts are used"
bitfld.long 0x00 0. " EOI                        ,Write 1 to acknowledge a pulse IRQ 0h = Write-0 : No action 1h = Write-1 : End-of-Interrupt" "0,1"
group.long 0x28++0x3
line.long 0x00 "DSS0_COMMON_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status"
bitfld.long 0x00 4.--5. " VID_IRQ                    ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events. Bit [5] is for VIDL1 pipeline. Bit [4] is for VID pipeline. 0h = Write-0 : No action, Read-0 : No event pending 1h = Write-1 : Set event, Read-1 : IRQ event pending" "0,1,2,3"
bitfld.long 0x00 0.--1. "         VP_IRQ               ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events. Bit [1] is for VP2. Bit [0] is for VP1. 0h = Write-0 : No action, Read-0 : No event pending 1h = Write-1 : Set event, Read-1 : IRQ event pending" "0,1,2,3"
hgroup.long 0x2C++0x3
hide.long 0x00 "DSS0_COMMON_DISPC_IRQSTATUS,Interrupt status. Enabled status, isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared, i.e. even if not enabled"
in
textline "                                                   "
group.long 0x30++0x3
line.long 0x00 "DSS0_COMMON_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register"
bitfld.long 0x00 4.--5. " SET_VID_IRQ                ,VID IRQ Bit [5] is for VIDL1 pipeline. Bit [4] is for VID pipeline. 0h = Write-0 : No action, Read-0 : Interrupt Disabled 1h = Write-1 : Enable interrupt, Read-1 : Interrupt Enabled" "0,1,2,3"
bitfld.long 0x00 0.--1. "         SET_VP_IRQ           ,VP IRQ Bit [1] is for VP2. Bit [0] is for VP1. 0h = Write-0 : No action, Read-0 : Interrupt Disabled 1h = Write-1 : Enable interrupt, Read-1 : Interrupt Enabled" "0,1,2,3"
hgroup.long 0x40++0x3
hide.long 0x00 "DSS0_COMMON_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable"
in
textline "                                                   "
group.long 0x44++0x3
line.long 0x00 "DSS0_COMMON_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 2. " SAFETYREGION_EN            ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 1. "         VIDENDWINDOW_EN      ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 0. " VIDBUFFERUNDERFLOW_EN      ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
group.long 0x48++0x3
line.long 0x00 "DSS0_COMMON_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 2. " SAFETYREGION_EN            ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 1. "         VIDENDWINDOW_EN      ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 0. " VIDBUFFERUNDERFLOW_EN      ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
hgroup.long 0x58++0x3
hide.long 0x00 "DSS0_COMMON_VID_IRQSTATUS_0,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field"
in
textline "                                                   "
hgroup.long 0x5C++0x3
hide.long 0x00 "DSS0_COMMON_VID_IRQSTATUS_1,This register groups all the status of the VIDL_0 internal events that generate an interrupt. Write 1 to a clear a bit field"
in
textline "                                                   "
group.long 0x70++0x3
line.long 0x00 "DSS0_COMMON_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 12. " DUMMY_EN                   ,Dummy IRQ for future use 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 11. "         VPSYNC_EN            ,Go bit clear event 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 10. " SECURITYVIOLATION_EN       ,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 6.--9. "         SAFETYREGION_EN      ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                   "
bitfld.long 0x00 5. " ACBIASCOUNTSTATUS_EN       ,AC BIAS transition counter has decremented to zero 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 4. "         VPSYNCLOST_EN        ,Synchronization Lost for Video Port 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 3. " VPPROGRAMMEDLINENUMBER_EN  ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 2. "         VPVSYNC_ODD_EN       ,VSYNC for odd field from interlace mode only 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 1. " VPVSYNC_EN                 ,Vertical Synchronization for VP 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 0. "         VPFRAMEDONE_EN       ,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
group.long 0x74++0x3
line.long 0x00 "DSS0_COMMON_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt, on an event-by-event basis"
bitfld.long 0x00 12. " DUMMY_EN                   ,Dummy IRQ for future use 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 11. "         VPSYNC_EN            ,Go bit clear event 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 10. " SECURITYVIOLATION_EN       ,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 6.--9. "         SAFETYREGION_EN      ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                   "
bitfld.long 0x00 5. " ACBIASCOUNTSTATUS_EN       ,AC BIAS transition counter has decremented to zero 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 4. "         VPSYNCLOST_EN        ,Synchronization Lost for Video Port 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 3. " VPPROGRAMMEDLINENUMBER_EN  ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 2. "         VPVSYNC_ODD_EN       ,VSYNC for odd field from interlace mode only 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
textline "                                                   "
bitfld.long 0x00 1. " VPVSYNC_EN                 ,Vertical Synchronization for VP 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
bitfld.long 0x00 0. "         VPFRAMEDONE_EN       ,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent 0h = Event is masked 1h = Event generates an interrupt when it occurs" "0,1"
hgroup.long 0x7C++0x3
hide.long 0x00 "DSS0_COMMON_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit"
in
textline "                                                   "
hgroup.long 0x80++0x3
hide.long 0x00 "DSS0_COMMON_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit"
in
textline "                                                   "
group.long 0x90++0x3
line.long 0x00 "DSS0_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register"
bitfld.long 0x00 6. " MFLAG_START                ,MFLAG_START for DMA master port 0h = When the DMA buffer is empty at the beginning of the frame, the MFLAG of each pipe is kept at 0 until PRELOAD is reached, then based on MFLAG_CTRL, MFLAG is generated and internal logic is arbitrating between pipeline requests 1h = Even at the beginning of the frame when the DMA buffer is empty, MFLAG_CTRL is used to determine how MFLAG dedicated to each pipe signal shall be driven" "0,1"
bitfld.long 0x00 0.--1. "         MFLAG_CTRL           ,MFLAG_CTRL for DMA master port 0h = MFLAG mechanism is disabled: MFLAG out band signal is set to 0 1h = MFLAG mechanism is enabled: MFLAG out band signal is always set to 1 2h = MFLAG mechanism is enabled and MFLAG out band signal is dynamically set to 0 or 1 depending on the MFLAG rules" "0,1,2,3"
group.long 0x94++0x3
line.long 0x00 "DSS0_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE,DISPC global output enable register. The ENABLE or GO bit for a particular output port is set when either the corresponding bit in this register is set or the corresponding bit within the sub-module is set. This register allows enabling multiple outputs synchronously [simultaneously], which is not possible if the ENABLE/GO bits are present only within the sub-module"
bitfld.long 0x00 16.--17. " VP_GO                      ,Global GO Command for the VP output(s). It is used to synchronize the pipelines associated with the VP output. wr: immediate Bit [17] is for VP2. Bit [16] is for VP1. 0h = The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the VP output using the user values. The hardware resets the bit when the update is completed 1h = The user has finished to program the shadow registers of the pipeline(s) associated with the VP output and the hardware can update the internal registers at the VFP start period" "0,1,2,3"
bitfld.long 0x00 0.--1. "         VP_ENABLE            ,Global VP Enable. Bit [1] is for VP2. Bit [0] is for VP1. 0h = VP port is disabled 1h = VP port is enabled" "0,1,2,3"
group.long 0x98++0x3
line.long 0x00 "DSS0_COMMON_DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipelines for DMA"
bitfld.long 0x00 31. " BUFFERFILLING              ,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold. 0h = Each DMA buffer is re-filled when it reaches LOW threshold. 1h = All DMA buffers are re-filled up to high threshold when at least one of them reaches the LOW threshold. Only active DMA buffers shall be considered and when reaching the end of the frame the DMA buffer goes to empty condition so no need to fill it again." "0,1"
bitfld.long 0x00 3.--5. "         VIDL1_BUFFER         ,VIDL1 DMA buffer allocation to one of the pipelines. 0h = DMA buffer allocated to the VID pipeline. 1h = DMA buffer allocated to the VIDL1 pipeline." "0,1,2,3,4,5,6,7"
textline "                                                   "
bitfld.long 0x00 0.--2. " VID_BUFFER                 ,VID DMA buffer allocation to one of the pipelines 0h = DMA buffer allocated to the VID pipeline. 1h = DMA buffer allocated to the VIDL1 pipeline." "0,1,2,3,4,5,6,7"
group.long 0x9C++0x3
line.long 0x00 "DSS0_COMMON_DSS_CBA_CFG,This register contains CBA specific config bits in DSS"
bitfld.long 0x00 3.--5. " PRI_HI                     ,The value sent out on the PRI_HI bus from DSS to CBA Indicates the priority level for high-priority [MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         PRI_LO               ,The value sent out on the PRI_LO bus from DSS to CBA Indicates the priority level for normal [non-MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7"
group.long 0xA0++0x3
line.long 0x00 "DSS0_COMMON_DISPC_DBG_CONTROL,DISPC debug status control register"
hexmask.long.byte 0x00 1.--8. 1. " DBGMUXSEL                  ,Mux select for the debug status 00h = 8 values to select any 4bytes, order from LSB 4bytes to MSB 4bytes, at a time from the 32byte VID debug bus 08h = 8 values to select any 4bytes, order from LSB 4bytes to MSB 4bytes, at a time from the 32byte VIDL1 debug bus 11h = Select OVR1 debug bus, 4bytes 12h = Select OVR2 debug bus, 4bytes 13h = Select VP1 debug bus, 8bytes 15h = Select VP2 debug bus, 8bytes 17h = Select MISC debug bus, 4bytes"
bitfld.long 0x00 0. "        DBGEN                ,Enable debug ports 0h = Disable 1h = Enable" "0,1"
rgroup.long 0xA4++0x3
line.long 0x00 "DSS0_COMMON_DISPC_DBG_STATUS,DISPC debug status register"
hexmask.long 0x00 0.--31. 1. " DBGOUT                     ,Debug status"
group.long 0xA8++0x3
line.long 0x00 "DSS0_COMMON_DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level"
bitfld.long 0x00 18.--19. " VP                         ,Clock gating control for VP. Bit [19] is for VP2. Bit [18] is for VP1. 0h = Clock-Gating is enabled 1h = Clock-gating is disabled. Clocks are free running" "0,1,2,3"
bitfld.long 0x00 14.--15. "         OVR                  ,Clock gating control for OVR. Bit [15] is for OVR2. Bit [14] is for OVR1. 0h = Clock-Gating is enabled 1h = Clock-gating is disabled. Clocks are free running" "0,1,2,3"
textline "                                                   "
bitfld.long 0x00 3.--4. " VID                        ,Clock gating control for VID. Bit [4] is for VIDL1. Bit [3] is for VID. 0h = Clock-Gating is enabled 1h = Clock-gating is disabled. Clocks are free running" "0,1,2,3"
bitfld.long 0x00 0. "         DMA                  ,Clock gating control for DMA. 0h = Clock-Gating is enabled 1h = Clock-gating is disabled. Clocks are free running" "0,1"
group.long 0xAC++0x3
line.long 0x00 "DSS0_COMMON_DISPC_SECURE_DISABLE,Disable security settings throughout DSS IP. COMMON_1.DISPC_SECURE bits are honoured only if COMMON. =0"
bitfld.long 0x00 0. " SECURE_DISABLE             ,Secure disable bit 0h = Secure bits, in COMMON1_DISPC_SECURE register, are active. 1h = Secure bits, in COMMON1_DISPC_SECURE register, are not active and IP will behave as non-secure." "0,1"
width 0x0B
tree.end
tree "DSS0_OVR"
tree "DSS0_OVR1"
base ad:0x4A07000
width 27.
group.long 0x0++0x3
line.long 0x00 "DSS0_OVR_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register"
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency Color Key Selection 0h = Destination transparency color key selected 1h = Source transparency color key selected" "0,1"
bitfld.long 0x00 10. "         TCKLCDENABLE ,Transparency Color Key Enable 0h = Disable the transparency color key for the LCD 1h = Enable the transparency color key for the LCD" "0,1"
textline "                                    "
bitfld.long 0x00 1. " COLORBAREN      ,Enable the Color-Bar 0h = Disabled 1h = Enabled" "0,1"
group.long 0x8++0x3
line.long 0x00 "DSS0_OVR_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register"
hexmask.long 0x00 0.--31. 1. " DEFAULTCOLOR    ,32-bit LSB of ARGB background color"
group.long 0xC++0x3
line.long 0x00 "DSS0_OVR_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " DEFAULTCOLOR    ,16-bit MSB of ARGB background color"
group.long 0x10++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register"
hexmask.long 0x00 0.--31. 1. " TRANSCOLORKEY   ,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format"
group.long 0x14++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register"
bitfld.long 0x00 0.--3. " TRANSCOLORKEY   ,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register"
hexmask.long 0x00 0.--31. 1. " TRANSCOLORKEY   ,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format"
group.long 0x1C++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register"
bitfld.long 0x00 0.--3. " TRANSCOLORKEY   ,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x3
line.long 0x00 "DSS0_OVR_ATTRIBUTES_0,The register configures the attributes of layer-0, ZORDER= 0, of the Overlay manager. Shadow register"
hexmask.long.word 0x00 19.--30. 1. " POSY            ,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0"
hexmask.long.word 0x00 6.--17. 1. "      POSX         ,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0"
textline "                                    "
bitfld.long 0x00 1.--4. " CHANNELIN       ,Input channel connected to Layer 0h = VID is connected to the layer 1h = VIDL-1 is connected to the layer Others = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        ENABLE       ,Layer Enable" "0,1"
group.long 0x24++0x3
line.long 0x00 "DSS0_OVR_ATTRIBUTES_1,The register configures the attributes of layer-1, ZORDER= 1, of the Overlay manager. Shadow register"
hexmask.long.word 0x00 19.--30. 1. " POSY            ,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0"
hexmask.long.word 0x00 6.--17. 1. "      POSX         ,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0"
textline "                                    "
bitfld.long 0x00 1.--4. " CHANNELIN       ,Input channel connected to Layer 0h = VID is connected to the layer 1h = VIDL-1 is connected to the layer Others = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        ENABLE       ,Layer Enable" "0,1"
width 0x0B
tree.end
tree "DSS0_OVR2"
base ad:0x4A08000
width 27.
group.long 0x0++0x3
line.long 0x00 "DSS0_OVR_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register"
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency Color Key Selection 0h = Destination transparency color key selected 1h = Source transparency color key selected" "0,1"
bitfld.long 0x00 10. "         TCKLCDENABLE ,Transparency Color Key Enable 0h = Disable the transparency color key for the LCD 1h = Enable the transparency color key for the LCD" "0,1"
textline "                                    "
bitfld.long 0x00 1. " COLORBAREN      ,Enable the Color-Bar 0h = Disabled 1h = Enabled" "0,1"
group.long 0x8++0x3
line.long 0x00 "DSS0_OVR_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register"
hexmask.long 0x00 0.--31. 1. " DEFAULTCOLOR    ,32-bit LSB of ARGB background color"
group.long 0xC++0x3
line.long 0x00 "DSS0_OVR_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " DEFAULTCOLOR    ,16-bit MSB of ARGB background color"
group.long 0x10++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register"
hexmask.long 0x00 0.--31. 1. " TRANSCOLORKEY   ,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format"
group.long 0x14++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register"
bitfld.long 0x00 0.--3. " TRANSCOLORKEY   ,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register"
hexmask.long 0x00 0.--31. 1. " TRANSCOLORKEY   ,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format"
group.long 0x1C++0x3
line.long 0x00 "DSS0_OVR_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register"
bitfld.long 0x00 0.--3. " TRANSCOLORKEY   ,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x3
line.long 0x00 "DSS0_OVR_ATTRIBUTES_0,The register configures the attributes of layer-0, ZORDER= 0, of the Overlay manager. Shadow register"
hexmask.long.word 0x00 19.--30. 1. " POSY            ,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0"
hexmask.long.word 0x00 6.--17. 1. "      POSX         ,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0"
textline "                                    "
bitfld.long 0x00 1.--4. " CHANNELIN       ,Input channel connected to Layer 0h = VID is connected to the layer 1h = VIDL-1 is connected to the layer Others = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        ENABLE       ,Layer Enable" "0,1"
group.long 0x24++0x3
line.long 0x00 "DSS0_OVR_ATTRIBUTES_1,The register configures the attributes of layer-1, ZORDER= 1, of the Overlay manager. Shadow register"
hexmask.long.word 0x00 19.--30. 1. " POSY            ,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0"
hexmask.long.word 0x00 6.--17. 1. "      POSX         ,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0"
textline "                                    "
bitfld.long 0x00 1.--4. " CHANNELIN       ,Input channel connected to Layer 0h = VID is connected to the layer 1h = VIDL-1 is connected to the layer Others = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        ENABLE       ,Layer Enable" "0,1"
width 0x0B
tree.end
tree.end
tree "DSS_VID"
tree "DSS0_VIDL1"
base ad:0x4A02000
width 32.
group.long 0x20++0x3
line.long 0x00 "DSS0_VID_ATTRIBUTES,The register configures the VID_ATTRIBUTES of the video window. Shadow register"
bitfld.long 0x00 31. " LUMAKEYENABLE    ,Enable Luma Key transparency matching 0h = Luma Key operation is disabled 1h = Luma Key operation is enabled" "0,1"
bitfld.long 0x00 30. "         GAMMAINVERSION  ,Inverse Gamma support [using the CLUT table] 0h = Gamma inversion is disabled 1h = Gamma inversion is enabled" "0,1"
textline "                                         "
bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data 0h = Non premultiplyalpha data color component 1h = Premultiplyalpha data color component" "0,1"
bitfld.long 0x00 24. "         SELFREFRESH     ,Enables the self refresh of the video window, from its own DMA buffer only 0h = The video pipeline accesses the interconnect to fetch data from the system memory 1h = The video pipeline does not need any more to fetch data from memory. Only the DMA buffer associated with the video1 is used. It takes effect after the frame has been loaded in the DMA buffer" "0,1"
textline "                                         "
bitfld.long 0x00 23. " ARBITRATION      ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal priority pipelines sending requests, the round-robin applies between the normal priority pipelines 0h = The video pipeline is one of the normal priority pipelines 1h = The video pipeline is one of the high priority pipelines" "0,1"
bitfld.long 0x00 21. "         VERTICALTAPS    ,This register field is functional only for VID pipeline. It is not functional for VIDL1 pipeline. Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap 0h = 3 taps are used for the vertical filtering logic. The 2 other taps are not used. The associated bit-fields for the 2 other taps coefficients do not need to be initialized 1h = 5 taps are used for the vertical filtering logic" "0,1"
textline "                                         "
bitfld.long 0x00 19. " BUFPRELOAD       ,Video Preload Value 0h = H/W prefetches pixels up to the 1h = H/W prefetches pixels up to high threshold value" "0,1"
bitfld.long 0x00 17. "         SELFREFRESHAUTO ,Automatic self refresh mode 0h = The transition from SELFREFRESH disabled to enabled is controlled SW 1h = The transition from SELFREFRESH disabled to enabled is controlled only by HW" "0,1"
textline "                                         "
bitfld.long 0x00 12. " FLIP             ,Describes the frame buffer flip operation 0h = No Flip 1h = Frame Buffer is flipped" "0,1"
bitfld.long 0x00 11. "         FULLRANGE       ,Color Space Conversion full range setting 0h = Limited Range Selected 1h = Full Range Selected" "0,1"
textline "                                         "
bitfld.long 0x00 10. " NIBBLEMODE       ,Video Nibble mode [only for 1-, 2-, and 4-bpp]0h = Nibble Mode Disabled 1h = Nibble Mode Enabled" "0,1"
bitfld.long 0x00 9. "         COLORCONVENABLE ,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format 0h = Color Space Conversion Disabled 1h = Color Space Conversion Enabled" "0,1"
textline "                                         "
bitfld.long 0x00 7.--8. " RESIZEENABLE     ,This register field is functional only for VID pipeline. It is not functional for VIDL1 pipeline. Video Resize Enable 0h = Disable both horizontal and vertical resizing 1h = Enable horizontal resizing 2h = Enable vertical resizing 3h = Enable both horizontal and vertical resizing" "0,1,2,3"
bitfld.long 0x00 1.--6. "         FORMAT          ,Video Format. It defines the pixel format when fetching the video frame buffer. (Alpha-X) denotes that Alpha can be disabled and can be replaced with global alpha value. 00h = ARGB16-4444 01h = ABGR16-4444 02h = RGBA16-4444 03h = RGB16-565 04h = BGR16-565 05h = ARGB16-1555 06h = ABGR16-1555 07h = ARGB32-8888 08h = ABGR32-8888 09h = RGBA32-8888 0Ah = BGRA32-8888 0Bh = RGB24-888 0Ch = BGR24-888 0Eh = ARGB32-2101010 0Fh = ABGR32-2101010 10h = ARGB64-16161616 11h = RGBA64-16161616 12h = BITMAP1 13h = BITMAP2 14h = BITMAP4 15h = BITMAP8 16h = RGB565A8 17h = BGR565A8 20h = ARGB16-4444 (Alpha-X) 21h = ABGR16-4444 (Alpha-X) 22h = RGBA16-4444 (Alpha-X) 25h = ARGB16-1555 (Alpha-X) 26h = ABGR16-1555 (Alpha-X) 27h = ARGB32-8888 (Alpha-X) 28h = ABGR32-8888 (Alpha-X) 29h = RGBA32-8888 (Alpha-X) 2Ah = BGRA32-8888 (Alpha-X) 2Eh = ARGB32-2101010 (Alpha-X) 2Fh = ABGR32-2101010 (Alpha-X) 30h = ARGB64-16161616 (Alpha-X) 31h = RGBA64-16161616 (Alpha-X) 3Dh = YUV420-NV12 (planar) 3Eh = YUV422-YUV2 (packed) 3Fh = YUV422-UYVY (packed)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                         "
bitfld.long 0x00 0. " ENABLE           ,Video pipeline Enable 0h = Video Pipe Disabled 1h = Video Pipe Enabled" "0,1"
group.long 0x24++0x3
line.long 0x00 "DSS0_VID_ATTRIBUTES2,The register configures the of the video window. Shadow register"
bitfld.long 0x00 26.--30. " TAGS             ,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "        YUV_ALIGN       ,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data 0h = lsb aligned - unused msb 1h = msb aligned - unused lsb" "0,1"
textline "                                         "
bitfld.long 0x00 9. " YUV_MODE         ,Mode of packing for YUV data [only for 10b/12b formats] 0h = YUV 10-bit formats have the same component packing order as 8-bit formats except that the packing is done across a multiple 32-bit word with 2 MSB in each 32-bit word not used. YUV 12-bit formats have the same component packing order as 8-bit formats except that the packing is done across a multiple 64-bit word with 4 MSB in each 64-bit word not used 1h = YUV 10-bit/12-bit unpacked formats have the same component packing order as 8-bit formats except that each component is stored in a 16-bit container - with MSB or LSB bits within the 16-bit container not used depending on the MSB/LSB alignment" "0,1"
bitfld.long 0x00 7.--8. "         YUV_SIZE        ,Size of YUV data 8b/10b/12b 0h = 8b per component-default 1h = 10b per component 2h = 12b per component" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 4.--6. " VC1_RANGE_CBCR   ,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1.--3. "         VC1_RANGE_Y     ,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 0. " VC1ENABLE        ,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats 0h = VC1 range mapping disabled 1h = VC1 range mapping enabled" "0,1"
group.long 0x28++0x3
line.long 0x00 "DSS0_VID_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV, this is the BA. In case of two plane YUV, this is the BA_Y. In case of two plane RGB565-A8, this is the BA_Alpha. BA__0 & BA__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address. Base address of the video buffer [Aligned on pixel DSS0_VID_SIZE boundary except for the following. In case of RGB24 packed format, 4-pixel alignment is required. In case of YUV422, 2-pixel alignment is required. In case of YUV420, byte alignment is required]"
group.long 0x2C++0x3
line.long 0x00 "DSS0_VID_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV, this is the BA. In case of two plane YUV, this is the BA_Y. In case of two plane RGB565-A8, this is the BA_Alpha. BA__0 & BA__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address. Base address of the video buffer [Aligned on pixel DSS0_VID_SIZE boundary except for the following. In case of RGB24 packed format, 4-pixel alignment is required. In case of YUV422, 2-pixel alignment is required. In case of YUV420, byte alignment is required]"
group.long 0x30++0x3
line.long 0x00 "DSS0_VID_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8, for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA_UV__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address aligned on 16-bit boundary. Base address of the UV video buffer used only in case of YUV420-NV12."
group.long 0x34++0x3
line.long 0x00 "DSS0_VID_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8, for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA_UV__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address aligned on 16-bit boundary. Base address of the UV video buffer used only in case of YUV420-NV12."
rgroup.long 0x38++0x3
line.long 0x00 "DSS0_VID_BUF_SIZE_STATUS,The register returns the Video buffer for the video pipeline"
hexmask.long.word 0x00 0.--15. 1. " BUFSIZE          ,Video DMA buffer Size in number of 128-bits"
group.long 0x3C++0x3
line.long 0x00 "DSS0_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register"
hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold. Number of 128-bits defining the threshold value"
hexmask.long.word 0x00 0.--15. 1. "      BUFLOWTHRESHOLD ,DMA buffer Low Threshold. Number of 128-bits defining the threshold value"
group.long 0x40++0x3
line.long 0x00 "DSS0_VID_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C01              ,C01 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C00             ,C00 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x44++0x3
line.long 0x00 "DSS0_VID_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C10              ,C10 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C02             ,C02 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x48++0x3
line.long 0x00 "DSS0_VID_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C12              ,C12 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C11             ,C11 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x4C++0x3
line.long 0x00 "DSS0_VID_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C21              ,C21 coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C20             ,C20 coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x50++0x3
line.long 0x00 "DSS0_VID_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 0.--10. 1. " C22              ,C22 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x54++0x3
line.long 0x00 "DSS0_VID_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " PREOFFSET2       ,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET1      ,Row1 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x58++0x3
line.long 0x00 "DSS0_VID_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET1      ,Row-1 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET3      ,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x1FC++0x3
line.long 0x00 "DSS0_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register"
hexmask.long.byte 0x00 0.--7. 1. " GLOBALALPHA      ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque"
group.long 0x208++0x3
line.long 0x00 "DSS0_VID_MFLAG_THRESHOLD,Register"
hexmask.long.word 0x00 16.--31. 1. " HT_MFLAG         ,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "      LT_MFLAG        ,MFlag Low Threshold"
group.long 0x20C++0x3
line.long 0x00 "DSS0_VID_PICTURE_SIZE,The register configures the of the video picture associated with the video layer before up/down-scaling. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " MEMSIZEY         ,Number of lines of the video picture. Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one]. When predecimation is set, the value represents the size of the image after predecimation, but the max size of the unpredecimated image size in memory is still bounded to 2exp[11]."
hexmask.long.word 0x00 0.--11. 1. "      MEMSIZEX        ,Number of pixels of the video picture. Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit [program to value minus one]. When predecimation is set, the value represents the size of the image after predecimation, but the max size of the unpredecimated image size in memory is still bounded to 2exp[11]."
group.long 0x210++0x3
line.long 0x00 "DSS0_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register"
hexmask.long.byte 0x00 0.--7. 1. " PIXELINC         ,Number of bytes to increment between two pixels. Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels for YUV420. Max supported value is 128."
group.long 0x218++0x3
line.long 0x00 "DSS0_VID_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register"
hexmask.long.word 0x00 0.--11. 1. " PRELOAD          ,DMA buffer preload value. Number of 128-bit words defining the preload value."
group.long 0x21C++0x3
line.long 0x00 "DSS0_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register"
hexmask.long 0x00 0.--31. 1. " ROWINC           ,Number of bytes to increment at the end of the row. Encoded signed value [from -2-1 to 2] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1- [n+1]*bpp means decrement of n pixels."
group.long 0x220++0x3
line.long 0x00 "DSS0_VID_SIZE,The register configures the of the video window. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " SIZEY            ,Number of lines of the video window. Encoded value [from 1 to 4096] to specify the number of lines of the video window [program size-1]."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Number of pixels of the video window. Encoded value [from 1 to 4096] to specify the number of pixels of the video window [program size-1]."
group.long 0x22C++0x3
line.long 0x00 "DSS0_VID_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register."
hexmask.long.word 0x00 0.--15. 1. " BA_EXT           ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x230++0x3
line.long 0x00 "DSS0_VID_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_EXT           ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x234++0x3
line.long 0x00 "DSS0_VID_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_UV_EXT        ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x238++0x3
line.long 0x00 "DSS0_VID_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_UV_EXT        ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x23C++0x3
line.long 0x00 "DSS0_VID_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET3      ,Row-3 post-offset. Encoded signed value [from -4096 to 4095]."
hexmask.long.word 0x00 3.--15. 1. "      POSTOFFSET2     ,Row-2 post-offset. Encoded signed value [from -4096 to 4095]."
group.long 0x248++0x3
line.long 0x00 "DSS0_VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register"
hexmask.long 0x00 0.--31. 1. " ROWINC           ,Number of bytes to increment at the end of the row. Encoded signed value [from -2-1 to 2] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1-[n+1]*bpp means decrement of n pixels."
wgroup.long 0x260++0x3
line.long 0x00 "DSS0_VID_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x264++0x3
line.long 0x00 "DSS0_VID_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x268++0x3
line.long 0x00 "DSS0_VID_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x26C++0x3
line.long 0x00 "DSS0_VID_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x270++0x3
line.long 0x00 "DSS0_VID_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x274++0x3
line.long 0x00 "DSS0_VID_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x278++0x3
line.long 0x00 "DSS0_VID_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x27C++0x3
line.long 0x00 "DSS0_VID_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x280++0x3
line.long 0x00 "DSS0_VID_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x284++0x3
line.long 0x00 "DSS0_VID_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x288++0x3
line.long 0x00 "DSS0_VID_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x28C++0x3
line.long 0x00 "DSS0_VID_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x290++0x3
line.long 0x00 "DSS0_VID_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x294++0x3
line.long 0x00 "DSS0_VID_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x298++0x3
line.long 0x00 "DSS0_VID_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x29C++0x3
line.long 0x00 "DSS0_VID_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
group.long 0x2A0++0x3
line.long 0x00 "DSS0_VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP        ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR not enabled -OR- terminal count reached -OR- compare == no match"
textline "                                         "
bitfld.long 0x00 2. " SEEDSELECT       ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module. 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                         "
bitfld.long 0x00 0. " ENABLE           ,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1"
rgroup.long 0x2A4++0x3
line.long 0x00 "DSS0_VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE        ,The register configures the reference signature of the safety sub-region. Shadow register"
group.long 0x2A8++0x3
line.long 0x00 "DSS0_VID_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY             ,Y position of the safety sub-region. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0"
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0"
group.long 0x2AC++0x3
line.long 0x00 "DSS0_VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE        ,The register configures the reference signature of the safety sub-region. Shadow register"
group.long 0x2B0++0x3
line.long 0x00 "DSS0_VID_SAFETY_SIZE,The register configures the of the safety sub-region. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " SIZEY            ,Height of the safety sub-region. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0"
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0"
group.long 0x2B4++0x3
line.long 0x00 "DSS0_VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register"
hexmask.long 0x00 0.--31. 1. " SEED             ,The register configures the seed [initial value] of the MISR. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register"
group.long 0x2B8++0x3
line.long 0x00 "DSS0_VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " LUMAKEYMAX       ,12b luma_key_max value"
hexmask.long.word 0x00 0.--11. 1. "      LUMAKEYMIN      ,12b luma_key_min value"
width 0x0B
tree.end
tree "DSS0_VID"
base ad:0x4A06000
width 32.
group.long 0x0++0x3
line.long 0x00 "DSS0_VID_ACCUH_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. VIDx_ACCU__0 & VIDx_ACCU__1 for ping-pong mechanism with external trigger, based on the field polarity. This register is used for ARGB and Y in YUV420/YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " HORIZONTALACCU   ,Horizontal initialization accu signed value"
group.long 0x4++0x3
line.long 0x00 "DSS0_VID_ACCUH_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. VIDx_ACCU__0 & VIDx_ACCU__1 for ping-pong mechanism with external trigger, based on the field polarity. This register is used for ARGB and Y in YUV420/YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " HORIZONTALACCU   ,Horizontal initialization accu signed value"
group.long 0x8++0x3
line.long 0x00 "DSS0_VID_ACCUH2_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. VID n_ACCU2__0 & VID n_ACCU2__1 for ping-pong mechanism with external trigger, based on the field polarity. This register is used for U/V components in YUV420/YUV422. It is not used when the input format is any RGB format. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " HORIZONTALACCU   ,Horizontal initialization accu signed value"
group.long 0xC++0x3
line.long 0x00 "DSS0_VID_ACCUH2_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. VID n_ACCU2__0 & VID n_ACCU2__1 for ping-pong mechanism with external trigger, based on the field polarity. This register is used for U/V components in YUV420/YUV422. It is not used when the input format is any RGB format. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " HORIZONTALACCU   ,Horizontal initialization accu signed value"
group.long 0x10++0x3
line.long 0x00 "DSS0_VID_ACCUV_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. VIDx_ACCU__0 & VIDx_ACCU__1 for ping-pong mechanism with external trigger, based on the field polarity. It is used for ARGB and Y in YUV420/YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " VERTICALACCU     ,Vertical initialization accu signed value"
group.long 0x14++0x3
line.long 0x00 "DSS0_VID_ACCUV_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. VIDx_ACCU__0 & VIDx_ACCU__1 for ping-pong mechanism with external trigger, based on the field polarity. It is used for ARGB and Y in YUV420/YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " VERTICALACCU     ,Vertical initialization accu signed value"
group.long 0x18++0x3
line.long 0x00 "DSS0_VID_ACCUV2_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger, based on the field polarity. It is used for U/V components for YUV420. It is not used when the input format is any RGB format or YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " VERTICALACCU     ,Vertical initialization accu signed value"
group.long 0x1C++0x3
line.long 0x00 "DSS0_VID_ACCUV2_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger, based on the field polarity. It is used for U/V components for YUV420. It is not used when the input format is any RGB format or YUV422. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " VERTICALACCU     ,Vertical initialization accu signed value"
group.long 0x20++0x3
line.long 0x00 "DSS0_VID_ATTRIBUTES,The register configures the VID_ATTRIBUTES of the video window. Shadow register"
bitfld.long 0x00 31. " LUMAKEYENABLE    ,Enable Luma Key transparency matching 0h = Luma Key operation is disabled 1h = Luma Key operation is enabled" "0,1"
bitfld.long 0x00 30. "         GAMMAINVERSION  ,Inverse Gamma support [using the CLUT table] 0h = Gamma inversion is disabled 1h = Gamma inversion is enabled" "0,1"
textline "                                         "
bitfld.long 0x00 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data 0h = Non premultiplyalpha data color component 1h = Premultiplyalpha data color component" "0,1"
bitfld.long 0x00 24. "         SELFREFRESH     ,Enables the self refresh of the video window, from its own DMA buffer only 0h = The video pipeline accesses the interconnect to fetch data from the system memory 1h = The video pipeline does not need any more to fetch data from memory. Only the DMA buffer associated with the video1 is used. It takes effect after the frame has been loaded in the DMA buffer" "0,1"
textline "                                         "
bitfld.long 0x00 23. " ARBITRATION      ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal priority pipelines sending requests, the round-robin applies between the normal priority pipelines 0h = The video pipeline is one of the normal priority pipelines 1h = The video pipeline is one of the high priority pipelines" "0,1"
bitfld.long 0x00 21. "         VERTICALTAPS    ,This register field is functional only for VID pipeline. It is not functional for VIDL1 pipeline. Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap 0h = 3 taps are used for the vertical filtering logic. The 2 other taps are not used. The associated bit-fields for the 2 other taps coefficients do not need to be initialized 1h = 5 taps are used for the vertical filtering logic" "0,1"
textline "                                         "
bitfld.long 0x00 19. " BUFPRELOAD       ,Video Preload Value 0h = H/W prefetches pixels up to the 1h = H/W prefetches pixels up to high threshold value" "0,1"
bitfld.long 0x00 17. "         SELFREFRESHAUTO ,Automatic self refresh mode 0h = The transition from SELFREFRESH disabled to enabled is controlled SW 1h = The transition from SELFREFRESH disabled to enabled is controlled only by HW" "0,1"
textline "                                         "
bitfld.long 0x00 12. " FLIP             ,Describes the frame buffer flip operation 0h = No Flip 1h = Frame Buffer is flipped" "0,1"
bitfld.long 0x00 11. "         FULLRANGE       ,Color Space Conversion full range setting 0h = Limited Range Selected 1h = Full Range Selected" "0,1"
textline "                                         "
bitfld.long 0x00 10. " NIBBLEMODE       ,Video Nibble mode [only for 1-, 2-, and 4-bpp]0h = Nibble Mode Disabled 1h = Nibble Mode Enabled" "0,1"
bitfld.long 0x00 9. "         COLORCONVENABLE ,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format 0h = Color Space Conversion Disabled 1h = Color Space Conversion Enabled" "0,1"
textline "                                         "
bitfld.long 0x00 7.--8. " RESIZEENABLE     ,This register field is functional only for VID pipeline. It is not functional for VIDL1 pipeline. Video Resize Enable 0h = Disable both horizontal and vertical resizing 1h = Enable horizontal resizing 2h = Enable vertical resizing 3h = Enable both horizontal and vertical resizing" "0,1,2,3"
bitfld.long 0x00 1.--6. "         FORMAT          ,Video Format. It defines the pixel format when fetching the video frame buffer. (Alpha-X) denotes that Alpha can be disabled and can be replaced with global alpha value. 00h = ARGB16-4444 01h = ABGR16-4444 02h = RGBA16-4444 03h = RGB16-565 04h = BGR16-565 05h = ARGB16-1555 06h = ABGR16-1555 07h = ARGB32-8888 08h = ABGR32-8888 09h = RGBA32-8888 0Ah = BGRA32-8888 0Bh = RGB24-888 0Ch = BGR24-888 0Eh = ARGB32-2101010 0Fh = ABGR32-2101010 10h = ARGB64-16161616 11h = RGBA64-16161616 12h = BITMAP1 13h = BITMAP2 14h = BITMAP4 15h = BITMAP8 16h = RGB565A8 17h = BGR565A8 20h = ARGB16-4444 (Alpha-X) 21h = ABGR16-4444 (Alpha-X) 22h = RGBA16-4444 (Alpha-X) 25h = ARGB16-1555 (Alpha-X) 26h = ABGR16-1555 (Alpha-X) 27h = ARGB32-8888 (Alpha-X) 28h = ABGR32-8888 (Alpha-X) 29h = RGBA32-8888 (Alpha-X) 2Ah = BGRA32-8888 (Alpha-X) 2Eh = ARGB32-2101010 (Alpha-X) 2Fh = ABGR32-2101010 (Alpha-X) 30h = ARGB64-16161616 (Alpha-X) 31h = RGBA64-16161616 (Alpha-X) 3Dh = YUV420-NV12 (planar) 3Eh = YUV422-YUV2 (packed) 3Fh = YUV422-UYVY (packed)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                         "
bitfld.long 0x00 0. " ENABLE           ,Video pipeline Enable 0h = Video Pipe Disabled 1h = Video Pipe Enabled" "0,1"
group.long 0x24++0x3
line.long 0x00 "DSS0_VID_ATTRIBUTES2,The register configures the of the video window. Shadow register"
bitfld.long 0x00 26.--30. " TAGS             ,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "        YUV_ALIGN       ,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data 0h = lsb aligned - unused msb 1h = msb aligned - unused lsb" "0,1"
textline "                                         "
bitfld.long 0x00 9. " YUV_MODE         ,Mode of packing for YUV data [only for 10b/12b formats] 0h = YUV 10-bit formats have the same component packing order as 8-bit formats except that the packing is done across a multiple 32-bit word with 2 MSB in each 32-bit word not used. YUV 12-bit formats have the same component packing order as 8-bit formats except that the packing is done across a multiple 64-bit word with 4 MSB in each 64-bit word not used 1h = YUV 10-bit/12-bit unpacked formats have the same component packing order as 8-bit formats except that each component is stored in a 16-bit container - with MSB or LSB bits within the 16-bit container not used depending on the MSB/LSB alignment" "0,1"
bitfld.long 0x00 7.--8. "         YUV_SIZE        ,Size of YUV data 8b/10b/12b 0h = 8b per component-default 1h = 10b per component 2h = 12b per component" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 4.--6. " VC1_RANGE_CBCR   ,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1.--3. "         VC1_RANGE_Y     ,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
textline "                                         "
bitfld.long 0x00 0. " VC1ENABLE        ,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats 0h = VC1 range mapping disabled 1h = VC1 range mapping enabled" "0,1"
group.long 0x28++0x3
line.long 0x00 "DSS0_VID_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV, this is the BA. In case of two plane YUV, this is the BA_Y. In case of two plane RGB565-A8, this is the BA_Alpha. BA__0 & BA__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address. Base address of the video buffer [Aligned on pixel DSS0_VID_SIZE boundary except for the following. In case of RGB24 packed format, 4-pixel alignment is required. In case of YUV422, 2-pixel alignment is required. In case of YUV420, byte alignment is required]"
group.long 0x2C++0x3
line.long 0x00 "DSS0_VID_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV, this is the BA. In case of two plane YUV, this is the BA_Y. In case of two plane RGB565-A8, this is the BA_Alpha. BA__0 & BA__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address. Base address of the video buffer [Aligned on pixel DSS0_VID_SIZE boundary except for the following. In case of RGB24 packed format, 4-pixel alignment is required. In case of YUV422, 2-pixel alignment is required. In case of YUV420, byte alignment is required]"
group.long 0x30++0x3
line.long 0x00 "DSS0_VID_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8, for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA_UV__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address aligned on 16-bit boundary. Base address of the UV video buffer used only in case of YUV420-NV12."
group.long 0x34++0x3
line.long 0x00 "DSS0_VID_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8, for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA_UV__0 is used. Shadow register"
hexmask.long 0x00 0.--31. 1. " BA               ,Video base address aligned on 16-bit boundary. Base address of the UV video buffer used only in case of YUV420-NV12."
rgroup.long 0x38++0x3
line.long 0x00 "DSS0_VID_BUF_SIZE_STATUS,The register returns the Video buffer for the video pipeline"
hexmask.long.word 0x00 0.--15. 1. " BUFSIZE          ,Video DMA buffer Size in number of 128-bits"
group.long 0x3C++0x3
line.long 0x00 "DSS0_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register"
hexmask.long.word 0x00 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer High Threshold. Number of 128-bits defining the threshold value"
hexmask.long.word 0x00 0.--15. 1. "      BUFLOWTHRESHOLD ,DMA buffer Low Threshold. Number of 128-bits defining the threshold value"
group.long 0x40++0x3
line.long 0x00 "DSS0_VID_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C01              ,C01 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C00             ,C00 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x44++0x3
line.long 0x00 "DSS0_VID_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C10              ,C10 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C02             ,C02 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x48++0x3
line.long 0x00 "DSS0_VID_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C12              ,C12 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C11             ,C11 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x4C++0x3
line.long 0x00 "DSS0_VID_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C21              ,C21 coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C20             ,C20 coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x50++0x3
line.long 0x00 "DSS0_VID_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 0.--10. 1. " C22              ,C22 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x54++0x3
line.long 0x00 "DSS0_VID_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " PREOFFSET2       ,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET1      ,Row1 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x58++0x3
line.long 0x00 "DSS0_VID_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET1      ,Row-1 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET3      ,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x5C++0x3
line.long 0x00 "DSS0_VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " FIRHINC          ,Horizontal increment of the up/down-sampling filter. The value 0 is invalid"
group.long 0x60++0x3
line.long 0x00 "DSS0_VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for U/V components for YUV 422 and 420 input formats. It is not used if input format is any RGB format. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " FIRHINC          ,Horizontal increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid"
group.long 0x64++0x3
line.long 0x00 "DSS0_VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register"
hexmask.long.tbyte 0x00 0.--23. 1. " FIRVINC          ,Vertical increment of the up/down-sampling filter. The value 0 is invalid"
group.long 0x68++0x3
line.long 0x00 "DSS0_VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for U/V components for YUV420 input format. It is not used when the input format is any RGB format or YUV422 format. Shadow register."
hexmask.long.tbyte 0x00 0.--23. 1. " FIRVINC          ,Vertical increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid"
group.long 0x6C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
group.long 0x70++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1"
group.long 0x74++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2"
group.long 0x78++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3"
group.long 0x7C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4"
group.long 0x80++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5"
group.long 0x84++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6"
group.long 0x88++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7"
group.long 0x8C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8"
group.long 0x90++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
group.long 0x94++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1"
group.long 0x98++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2"
group.long 0x9C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3"
group.long 0xA0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4"
group.long 0xA4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5"
group.long 0xA8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6"
group.long 0xAC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7"
group.long 0xB0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRHC0           ,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8"
group.long 0xB4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
group.long 0xB8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1"
group.long 0xBC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2"
group.long 0xC0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3"
group.long 0xC4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4"
group.long 0xC8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5"
group.long 0xCC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6"
group.long 0xD0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7"
group.long 0xD4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8"
group.long 0xD8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9"
group.long 0xDC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10"
group.long 0xE0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11"
group.long 0xE4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12"
group.long 0xE8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13"
group.long 0xEC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14"
group.long 0xF0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15"
group.long 0xF4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
group.long 0xF8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1"
group.long 0xFC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2"
group.long 0x100++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3"
group.long 0x104++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4"
group.long 0x108++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5"
group.long 0x10C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6"
group.long 0x110++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7"
group.long 0x114++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8"
group.long 0x118++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9"
group.long 0x11C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10"
group.long 0x120++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11"
group.long 0x124++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12"
group.long 0x128++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13"
group.long 0x12C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14"
group.long 0x130++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRHC2           ,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15"
hexmask.long.word 0x00 10.--19. 1. "      FIRHC1          ,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15"
group.long 0x134++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
group.long 0x138++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1"
group.long 0x13C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2"
group.long 0x140++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3"
group.long 0x144++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4"
group.long 0x148++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5"
group.long 0x14C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6"
group.long 0x150++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7"
group.long 0x154++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8"
group.long 0x158++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
group.long 0x15C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1"
group.long 0x160++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2"
group.long 0x164++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3"
group.long 0x168++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4"
group.long 0x16C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5"
group.long 0x170++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6"
group.long 0x174++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7"
group.long 0x178++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 0.--9. 1. " FIRVC0           ,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8"
group.long 0x17C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
group.long 0x180++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 1"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 1"
group.long 0x184++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 2"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 2"
group.long 0x188++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 3"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 3"
group.long 0x18C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 4"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 4"
group.long 0x190++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 5"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 5"
group.long 0x194++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 6"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 6"
group.long 0x198++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 7"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 7"
group.long 0x19C++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 8"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 8"
group.long 0x1A0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 9"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 9"
group.long 0x1A4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 10"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 10"
group.long 0x1A8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 11"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 11"
group.long 0x1AC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 12"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 12"
group.long 0x1B0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 13"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 13"
group.long 0x1B4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 14"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 14"
group.long 0x1B8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 15"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 15"
group.long 0x1BC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
group.long 0x1C0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 1"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 1"
group.long 0x1C4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 2"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 2"
group.long 0x1C8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 3"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 3"
group.long 0x1CC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 4"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 4"
group.long 0x1D0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 5"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 5"
group.long 0x1D4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 6"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 6"
group.long 0x1D8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 7"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 7"
group.long 0x1DC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 8"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 8"
group.long 0x1E0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 9"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 9"
group.long 0x1E4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 10"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 10"
group.long 0x1E8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 11"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 11"
group.long 0x1EC++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 12"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 12"
group.long 0x1F0++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 13"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 13"
group.long 0x1F4++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 14"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 14"
group.long 0x1F8++0x3
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. When the register is not used by the HW, any value can be used for the bit-fields. Shadow register"
hexmask.long.word 0x00 20.--29. 1. " FIRVC2           ,Signed coefficient C2 for the vertical up/down-scaling with the phase 15"
hexmask.long.word 0x00 10.--19. 1. "      FIRVC1          ,Signed coefficient C1 for the vertical up/down-scaling with the phase 15"
group.long 0x1FC++0x3
line.long 0x00 "DSS0_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register"
hexmask.long.byte 0x00 0.--7. 1. " GLOBALALPHA      ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque"
group.long 0x208++0x3
line.long 0x00 "DSS0_VID_MFLAG_THRESHOLD,Register"
hexmask.long.word 0x00 16.--31. 1. " HT_MFLAG         ,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "      LT_MFLAG        ,MFlag Low Threshold"
group.long 0x20C++0x3
line.long 0x00 "DSS0_VID_PICTURE_SIZE,The register configures the of the video picture associated with the video layer before up/down-scaling. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " MEMSIZEY         ,Number of lines of the video picture. Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one]. When predecimation is set, the value represents the size of the image after predecimation, but the max size of the unpredecimated image size in memory is still bounded to 2exp[11]."
hexmask.long.word 0x00 0.--11. 1. "      MEMSIZEX        ,Number of pixels of the video picture. Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit [program to value minus one]. When predecimation is set, the value represents the size of the image after predecimation, but the max size of the unpredecimated image size in memory is still bounded to 2exp[11]."
group.long 0x210++0x3
line.long 0x00 "DSS0_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register"
hexmask.long.byte 0x00 0.--7. 1. " PIXELINC         ,Number of bytes to increment between two pixels. Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels for YUV420. Max supported value is 128."
group.long 0x218++0x3
line.long 0x00 "DSS0_VID_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register"
hexmask.long.word 0x00 0.--11. 1. " PRELOAD          ,DMA buffer preload value. Number of 128-bit words defining the preload value."
group.long 0x21C++0x3
line.long 0x00 "DSS0_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register"
hexmask.long 0x00 0.--31. 1. " ROWINC           ,Number of bytes to increment at the end of the row. Encoded signed value [from -2-1 to 2] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1- [n+1]*bpp means decrement of n pixels."
group.long 0x220++0x3
line.long 0x00 "DSS0_VID_SIZE,The register configures the of the video window. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " SIZEY            ,Number of lines of the video window. Encoded value [from 1 to 4096] to specify the number of lines of the video window [program size-1]."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Number of pixels of the video window. Encoded value [from 1 to 4096] to specify the number of pixels of the video window [program size-1]."
group.long 0x22C++0x3
line.long 0x00 "DSS0_VID_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register."
hexmask.long.word 0x00 0.--15. 1. " BA_EXT           ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x230++0x3
line.long 0x00 "DSS0_VID_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_EXT           ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x234++0x3
line.long 0x00 "DSS0_VID_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_UV_EXT        ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x238++0x3
line.long 0x00 "DSS0_VID_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger, based on the field polarity. Shadow register"
hexmask.long.word 0x00 0.--15. 1. " BA_UV_EXT        ,Video base address extension [16 bits]. Addr extension to make the address space 48b wide."
group.long 0x23C++0x3
line.long 0x00 "DSS0_VID_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET3      ,Row-3 post-offset. Encoded signed value [from -4096 to 4095]."
hexmask.long.word 0x00 3.--15. 1. "      POSTOFFSET2     ,Row-2 post-offset. Encoded signed value [from -4096 to 4095]."
group.long 0x248++0x3
line.long 0x00 "DSS0_VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register"
hexmask.long 0x00 0.--31. 1. " ROWINC           ,Number of bytes to increment at the end of the row. Encoded signed value [from -2-1 to 2] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1-[n+1]*bpp means decrement of n pixels."
wgroup.long 0x260++0x3
line.long 0x00 "DSS0_VID_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x264++0x3
line.long 0x00 "DSS0_VID_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x268++0x3
line.long 0x00 "DSS0_VID_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x26C++0x3
line.long 0x00 "DSS0_VID_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x270++0x3
line.long 0x00 "DSS0_VID_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x274++0x3
line.long 0x00 "DSS0_VID_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x278++0x3
line.long 0x00 "DSS0_VID_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x27C++0x3
line.long 0x00 "DSS0_VID_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x280++0x3
line.long 0x00 "DSS0_VID_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x284++0x3
line.long 0x00 "DSS0_VID_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x288++0x3
line.long 0x00 "DSS0_VID_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x28C++0x3
line.long 0x00 "DSS0_VID_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x290++0x3
line.long 0x00 "DSS0_VID_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x294++0x3
line.long 0x00 "DSS0_VID_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x298++0x3
line.long 0x00 "DSS0_VID_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
wgroup.long 0x29C++0x3
line.long 0x00 "DSS0_VID_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats"
hexmask.long.byte 0x00 24.--31. 1. " INDEX            ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored."
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R-value to store at the location in the table defined by the bit-field INDEX."
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G          ,8-bit G-value to store at the location in the table defined by the bit-field INDEX."
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B-value to store at the location in the table defined by the bit-field INDEX."
group.long 0x2A0++0x3
line.long 0x00 "DSS0_VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP        ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR not enabled -OR- terminal count reached -OR- compare == no match"
textline "                                         "
bitfld.long 0x00 2. " SEEDSELECT       ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module. 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                         "
bitfld.long 0x00 0. " ENABLE           ,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1"
rgroup.long 0x2A4++0x3
line.long 0x00 "DSS0_VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE        ,The register configures the reference signature of the safety sub-region. Shadow register"
group.long 0x2A8++0x3
line.long 0x00 "DSS0_VID_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY             ,Y position of the safety sub-region. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0"
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0"
group.long 0x2AC++0x3
line.long 0x00 "DSS0_VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE        ,The register configures the reference signature of the safety sub-region. Shadow register"
group.long 0x2B0++0x3
line.long 0x00 "DSS0_VID_SAFETY_SIZE,The register configures the of the safety sub-region. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " SIZEY            ,Height of the safety sub-region. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0"
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0"
group.long 0x2B4++0x3
line.long 0x00 "DSS0_VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register"
hexmask.long 0x00 0.--31. 1. " SEED             ,The register configures the seed [initial value] of the MISR. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register"
group.long 0x2B8++0x3
line.long 0x00 "DSS0_VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " LUMAKEYMAX       ,12b luma_key_max value"
hexmask.long.word 0x00 0.--11. 1. "      LUMAKEYMIN      ,12b luma_key_min value"
width 0x0B
tree.end
tree.end
tree "DSS0_VP"
tree "DSS0_VP1"
base ad:0x4A0A000
width 33.
group.long 0x0++0x3
line.long 0x00 "DSS0_VP_CONFIG,The register configures the Display Controller module for the VP output. Shadow register."
bitfld.long 0x00 26. " COLORCONVPOS                   ,Determines the position of the COLORCONV module 0h = CSC block is after GAMMA correction 1h = CSC block is before GAMMA correction" "0,1"
bitfld.long 0x00 25. "         FULLRANGE       ,Color Space Conversion full range setting 0h = Limited range selected. 1h = Full range selected." "0,1"
textline "                                          "
bitfld.long 0x00 24. " COLORCONVENABLE                ,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CSC_COEF* registers 0h = Disable Color Space Conversion RGB to YUV 1h = Enable Color Space Conversion RGB to YUV" "0,1"
bitfld.long 0x00 23. "         FIDFIRST        ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used 0h = First field is even. 1h = Odd field is first." "0,1"
textline "                                          "
bitfld.long 0x00 22. " OUTPUTMODEENABLE               ,Selects between progressive and interlace mode for the VP output 0h = Progressive mode selected. 1h = Interlace mode selected." "0,1"
bitfld.long 0x00 21. "         BT1120ENABLE    ,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output 0h = BT-1120 is disabled. 1h = BT-1120 is enabled." "0,1"
textline "                                          "
bitfld.long 0x00 20. " BT656ENABLE                    ,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output 0h = BT-656 is disabled. 1h = BT-656 is enabled." "0,1"
bitfld.long 0x00 16. "         BUFFERHANDSHAKE ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 15. " CPR                            ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 8. "         EXTERNALSYNCEN  ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 7. " VSYNCGATED                     ,VSYNC Gated Enabled [VP output]. Shadow bit-field 0h = VSYNC Gated Disabled 1h = VSYNC Gated Enabled" "0,1"
bitfld.long 0x00 6. "         HSYNCGATED      ,HSYNC Gated Enabled [VP output]. Shadow bit-field 0h = HSYNC Gated Disabled 1h = HSYNC Gated Enabled" "0,1"
textline "                                          "
bitfld.long 0x00 5. " PIXELCLOCKGATED                ,Pixel Clock Gated Enabled [VP output]. Shadow bit-field 0h = Pixel Clock Gated Disabled 1h = Pixel Clock Gated Enabled" "0,1"
bitfld.long 0x00 4. "         PIXELDATAGATED  ,Pixel Data Gated Enabled [VP output]. Shadow bit-field 0h = Pixel Data Gated Disabled 1h = Pixel Data Gated Enabled" "0,1"
textline "                                          "
bitfld.long 0x00 3. " HDMIMODE                       ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 2. "         GAMMAENABLE     ,Enable the gamma Shadow bit-field 0h = Gamma disabled 1h = Gamma enabled" "0,1"
textline "                                          "
bitfld.long 0x00 1. " DATAENABLEGATED                ,DE Gated Enable Shadow bit-field 0h = DE signal is not gated 1h = DE signal is gated." "0,1"
bitfld.long 0x00 0. "         PIXELGATED      ,Pixel Gated Enable. Shadow bit-field 0h = Pixel clock always toggles - only in TFT mode 1h = Pixel clock only toggles when there is valid data to display - only in TFT mode" "0,1"
group.long 0x4++0x3
line.long 0x00 "DSS0_VP_CONTROL,The register configures the Display Controller module for the VP output"
bitfld.long 0x00 30.--31. " SPATIALTEMPORALDITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the VP output. Shadow bit-field. 0h = Spatial only 1h = Spatial and temporal over 2 frames 2h = Spatial and temporal over 4 frames 3h = Reserved" "0,1,2,3"
bitfld.long 0x00 25.--26. "         TDMUNUSEDBITS   ,State of unused bits [TDM mode only] for the VP output. Shadow bit-field. 0h = low level 1h = high level 2h = unchanged from previous state 3h = reserved" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT                 ,Cycle format [TDM mode only] for the VP output. Shadow bit-field. 0h = 1 cycle for 1 pixel 1h = 2 cycles for 1 pixel 2h = 3 cycles for 1 pixel 3h = 3 cycles for 2 pixels" "0,1,2,3"
bitfld.long 0x00 21.--22. "         TDMPARALLELMODE ,Output Interface width [TDM mode only] for the VP output. Shadow bit-field. 0h = 8-bit parallel output interface selected 1h = 9-bit parallel output interface selected 2h = 12-bit parallel output interface selected 3h = 16-bit parallel output interface selected" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 20. " TDMENABLE                      ,Enable the multiple cycle format for the VP output. Shadow bit-field. 0h = TDM disabled 1h = TDM enabled" "0,1"
bitfld.long 0x00 14.--16. "         HT              ,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 11. " STALLMODE                      ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 8.--10. "         DATALINES       ,Width of the data bus on VP output. Shadow bit-field. 0h = 12-bit output aligned on the LSB of the pixel data interface 1h = 16-bit output aligned on the LSB of the pixel data interface 2h = 18-bit output aligned on the LSB of the pixel data interface 3h = 24-bit output aligned on the LSB of the pixel data interface 4h = 30-bit output aligned on the LSB of the pixel data interface 5h = 36-bit output aligned on the LSB of the pixel data interface" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 7. " STDITHERENABLE                 ,Spatial Temporal dithering enable for the VP output. Shadow bit-field. 0h = Spatial/Temporal dithering logic disabled 1h = Spatial/Temporal dithering logic enabled" "0,1"
bitfld.long 0x00 6. "         DPIENABLE       ,Enable the DPI output. wr:immediate 0h = DPI output disabled 1h = DPI output enabled" "0,1"
textline "                                          "
bitfld.long 0x00 5. " GOBIT                          ,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate 0h = The hardware has finished the synchronization 1h = Software has requested for synchronization after register updates and the hardware has not finished the synchronization" "0,1"
bitfld.long 0x00 4. "         M8B             ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 3. " STN                            ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 2. "         MONOCOLOR       ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 1. " VPPROGLINENUMBERMODULO         ,Enable the modulo of the line number interrupt generation 0h = Disable modulo 1h = Enable Modulo" "0,1"
bitfld.long 0x00 0. "         ENABLE          ,Enable the video port output. wr:immediate 0h = LCD output disabled-at the end of the frame when the bit is reset 1h = LCD output enabled" "0,1"
group.long 0x8++0x3
line.long 0x00 "DSS0_VP_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C01                            ,C01 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C00             ,C00 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0xC++0x3
line.long 0x00 "DSS0_VP_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C10                            ,C10 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C02             ,C02 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x10++0x3
line.long 0x00 "DSS0_VP_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C12                            ,C12 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C11             ,C11 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x14++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_0,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits. Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_1,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_2,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits. Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44++0x3
line.long 0x00 "DSS0_VP_LINE_NUMBER,The register indicates the panel display line number for the interrupt and the DMA request. Shadow register"
hexmask.long.word 0x00 0.--11. 1. " LINENUMBER                     ,LCD panel line number programming. LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs."
group.long 0x4C++0x3
line.long 0x00 "DSS0_VP_POL_FREQ,The register configures the signal configuration. Shadow register"
bitfld.long 0x00 18. " ALIGN                          ,Defines the alignment between HSYNC and VSYNC assertion 0h = VSYNC and HSYNC are not aligned 1h = VSYNC and HSYNC assertions are aligned." "0,1"
bitfld.long 0x00 17. "         ONOFF           ,HSYNC/VSYNC Pixel clock Control On/Off 0h = HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 1h = HSYNC and VSYNC are driven according to bit 16" "0,1"
textline "                                          "
bitfld.long 0x00 16. " RF                             ,Program HSYNC/VSYNC Rise or Fall 0h = HSYNC and VSYNC are driven on falling edge of pixel clock -if bit 17 set to 1 1h = HSYNC and VSYNC are driven on rising edge of pixel clock -if bit 17 set to 1" "0,1"
bitfld.long 0x00 15. "         IEO             ,Invert output enable 0h = DE is active high 1h = DE is active low" "0,1"
textline "                                          "
bitfld.long 0x00 14. " IPC                            ,Invert pixel clock 0h = Data is driven on the LCD data lines on the rising-edge of the pixel clock 1h = Data is driven on the LCD data lines on the falling-edge of the pixel clock" "0,1"
bitfld.long 0x00 13. "         IHS             ,Invert HSYNC 0h = Hsync pin is active high and inactive low 1h = Hsync pin is active low and inactive high" "0,1"
textline "                                          "
bitfld.long 0x00 12. " IVS                            ,Invert VSYNC 0h = Vsync pin is active high and inactive low 1h = Vsync pin is active low and inactive high" "0,1"
bitfld.long 0x00 8.--11. "         ACBI            ,AC Bias Pin transitions per interrupt. Value [from 0 to 15] used to specify the number of AC Bias pin transitions." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " ACB                            ,AC Bias Pin Frequency. Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display."
group.long 0x50++0x3
line.long 0x00 "DSS0_VP_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line."
hexmask.long.word 0x00 16.--27. 1. " LPP                            ,Lines per panel. Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]."
bitfld.long 0x00 14.--15. "      DELTA_LPP       ,Indicates the delta size value of the odd field compared to the even field 0h = Same size 1h = Odd size is even size plus 1 2h = Odd size is even size minus 1" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 0.--11. 1. " PPL                            ,Pixels per line. Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode, any value is valid. In non-STALL mode, only values multiple of 8 pixels are valid."
group.long 0x54++0x3
line.long 0x00 "DSS0_VP_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register"
hexmask.long.word 0x00 20.--31. 1. " HBP                            ,Horizontal Back Porch. Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one]. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field."
hexmask.long.word 0x00 8.--19. 1. "      HFP             ,Horizontal front porch. Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one]. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " HSW                            ,Horizontal synchronization pulse width. Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one]. When in BT mode, this field corresponds to the LSB 8-bits of the 12-bit horizontal blanking. [BT_HBLANK[11:0] = {VSW[3:0], HSW[7:0]}]"
group.long 0x58++0x3
line.long 0x00 "DSS0_VP_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register"
hexmask.long.word 0x00 20.--31. 1. " VBP                            ,Vertical back porch. Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. When in BT and in progressive mode, this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display."
hexmask.long.word 0x00 8.--19. 1. "      VFP             ,Vertical front porch. Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. When in BT and in progressive mode, this field corresponds to the Vertical frame blanking No 2."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " VSW                            ,Vertical synchronization pulse width. Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses. Frame clock uses as VSYNC signal in active mode. When in BT mode, the LSB 4-bits of this field [VSW[3:0]] corresponds to the MSB 4-bits of the 12-bit horizontal blanking. [BT_HBLANK = {VSW[3:0], HSW[7:0]}]"
group.long 0x5C++0x3
line.long 0x00 "DSS0_VP_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C21                            ,C21 coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C20             ,C20 coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x60++0x3
line.long 0x00 "DSS0_VP_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 0.--10. 1. " C22                            ,C22 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x64++0x3
line.long 0x00 "DSS0_VP_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " PREOFFSET2                     ,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET1      ,Row1 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x68++0x3
line.long 0x00 "DSS0_VP_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET1                    ,Row-1 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET3      ,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x6C++0x3
line.long 0x00 "DSS0_VP_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET3                    ,Row-3 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      POSTOFFSET2     ,Row-2 post-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x70++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region" "0,1"
group.long 0x74++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field." "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
group.long 0x78++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field." "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
group.long 0x7C++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
rgroup.long 0x90++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x94++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x98++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x9C++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xB0++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xB4++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xB8++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xBC++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xD0++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xD4++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xD8++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xDC++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xF0++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xF4++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xF8++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xFC++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0x110++0x3
line.long 0x00 "DSS0_VP_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register."
hexmask.long 0x00 0.--31. 1. " SEED                           ,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register."
wgroup.long 0x120++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_0,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x124++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_1,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x128++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_2,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x12C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_3,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x130++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_4,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x134++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_5,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x138++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_6,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x13C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_7,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x140++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_8,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x144++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_9,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x148++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_10,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x14C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_11,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x150++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_12,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x154++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_13,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x158++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_14,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x15C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_15,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
group.long 0x160++0x3
line.long 0x00 "DSS0_VP_DSS_OLDI_CFG,This register configures the OLDI[N:0] modules connected to the DSS"
bitfld.long 0x00 13. " TPATCFG                        ,Test pattern Config" "0,1"
bitfld.long 0x00 12. "         SOFTRST         ,SoftWare Reset. By default, OLDI is kept under reset 0h = Software Reset is asserted - OLDI is under reset 1h = Software Reset is deasserted" "0,1"
textline "                                          "
bitfld.long 0x00 11. " DUALMODESYNC                   ,DualMode Sync 0h = Dual Mode operation is disabled 1h = Dual Mode Operation is enabled" "0,1"
bitfld.long 0x00 10. "         LBDATA          ,LoopBack Data" "0,1"
textline "                                          "
bitfld.long 0x00 9. " LBEN                           ,LoopBack Enable 0h = disabled 1h = enabled" "0,1"
bitfld.long 0x00 8. "         MSB             ,DSS bit-depth [for 18b LVDS only] 0h = Input from DSS is 18b. Use RGB data[17:0] as 18b RGB. 1h = Input from DSS is 24b. Use 6 msbs each of RGB data R[7:2], G[7:2] and B[7:2]." "0,1"
textline "                                          "
bitfld.long 0x00 7. " DEPOL                          ,Polarity of the DE signal 0h = DE is active-high 1h = DE is active-low" "0,1"
bitfld.long 0x00 6. "         MASTERSLAVE     ,Master selection in Dual mode only [typically tied off in the SoC] 0h = Master in Dual mode operation 1h = Slave in Dual mode operation" "0,1"
textline "                                          "
bitfld.long 0x00 5. " MODE                           ,Single mode or duplicate mode 0h = Single mode selected -independent operation 1h = Duplicate mode selected -synchronized operation" "0,1"
bitfld.long 0x00 4. "         SRC             ,Source Channel 0h = Video-0 is the source (DSS VP1) 1h = Video-1 is the source (DSS VP2)" "0,1"
textline "                                          "
bitfld.long 0x00 1.--3. " MAP                            ,Configuration of OLDI mapping. Also indicates dual mode. 0h = Single-link 18-bit 1h = Single-link 24-bit JEIDA 2h = Single-link 24-bit 4h = Dual-link 18-bit 5h = Dual-link 24-bit JEIDA 6h = Dual-link 24-bit" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         ENABLE          ,OLDI Enable 0h = Disabled 1h = Enabled" "0,1"
rgroup.long 0x164++0x3
line.long 0x00 "DSS0_VP_DSS_OLDI_STATUS,This register captures the PID from the OLDI[N:0] modules connected to the DSS. Reads 0x0 if no OLDI is connected"
hexmask.long.word 0x00 16.--31. 1. " MODID                          ,Module ID Field"
bitfld.long 0x00 11.--15. "      REVRTL          ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " REVMAJOR                       ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM          ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " REVMIN                         ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x168++0x3
line.long 0x00 "DSS0_VP_DSS_OLDI_LB,This register captures the Loopback data from OLDI"
hexmask.long.word 0x00 0.--9. 1. " LBRDATA                        ,Returned Data from Loopback"
width 0x0B
tree.end
tree "DSS0_VP2"
base ad:0x4A0B000
width 33.
group.long 0x0++0x3
line.long 0x00 "DSS0_VP_CONFIG,The register configures the Display Controller module for the VP output. Shadow register."
bitfld.long 0x00 26. " COLORCONVPOS                   ,Determines the position of the COLORCONV module 0h = CSC block is after GAMMA correction 1h = CSC block is before GAMMA correction" "0,1"
bitfld.long 0x00 25. "         FULLRANGE       ,Color Space Conversion full range setting 0h = Limited range selected. 1h = Full range selected." "0,1"
textline "                                          "
bitfld.long 0x00 24. " COLORCONVENABLE                ,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CSC_COEF* registers 0h = Disable Color Space Conversion RGB to YUV 1h = Enable Color Space Conversion RGB to YUV" "0,1"
bitfld.long 0x00 23. "         FIDFIRST        ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used 0h = First field is even. 1h = Odd field is first." "0,1"
textline "                                          "
bitfld.long 0x00 22. " OUTPUTMODEENABLE               ,Selects between progressive and interlace mode for the VP output 0h = Progressive mode selected. 1h = Interlace mode selected." "0,1"
bitfld.long 0x00 21. "         BT1120ENABLE    ,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output 0h = BT-1120 is disabled. 1h = BT-1120 is enabled." "0,1"
textline "                                          "
bitfld.long 0x00 20. " BT656ENABLE                    ,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output 0h = BT-656 is disabled. 1h = BT-656 is enabled." "0,1"
bitfld.long 0x00 16. "         BUFFERHANDSHAKE ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 15. " CPR                            ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 8. "         EXTERNALSYNCEN  ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 7. " VSYNCGATED                     ,VSYNC Gated Enabled [VP output]. Shadow bit-field 0h = VSYNC Gated Disabled 1h = VSYNC Gated Enabled" "0,1"
bitfld.long 0x00 6. "         HSYNCGATED      ,HSYNC Gated Enabled [VP output]. Shadow bit-field 0h = HSYNC Gated Disabled 1h = HSYNC Gated Enabled" "0,1"
textline "                                          "
bitfld.long 0x00 5. " PIXELCLOCKGATED                ,Pixel Clock Gated Enabled [VP output]. Shadow bit-field 0h = Pixel Clock Gated Disabled 1h = Pixel Clock Gated Enabled" "0,1"
bitfld.long 0x00 4. "         PIXELDATAGATED  ,Pixel Data Gated Enabled [VP output]. Shadow bit-field 0h = Pixel Data Gated Disabled 1h = Pixel Data Gated Enabled" "0,1"
textline "                                          "
bitfld.long 0x00 3. " HDMIMODE                       ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 2. "         GAMMAENABLE     ,Enable the gamma Shadow bit-field 0h = Gamma disabled 1h = Gamma enabled" "0,1"
textline "                                          "
bitfld.long 0x00 1. " DATAENABLEGATED                ,DE Gated Enable Shadow bit-field 0h = DE signal is not gated 1h = DE signal is gated." "0,1"
bitfld.long 0x00 0. "         PIXELGATED      ,Pixel Gated Enable. Shadow bit-field 0h = Pixel clock always toggles - only in TFT mode 1h = Pixel clock only toggles when there is valid data to display - only in TFT mode" "0,1"
group.long 0x4++0x3
line.long 0x00 "DSS0_VP_CONTROL,The register configures the Display Controller module for the VP output"
bitfld.long 0x00 30.--31. " SPATIALTEMPORALDITHERINGFRAMES ,Spatial/Temporal dithering number of frames for the VP output. Shadow bit-field. 0h = Spatial only 1h = Spatial and temporal over 2 frames 2h = Spatial and temporal over 4 frames 3h = Reserved" "0,1,2,3"
bitfld.long 0x00 25.--26. "         TDMUNUSEDBITS   ,State of unused bits [TDM mode only] for the VP output. Shadow bit-field. 0h = low level 1h = high level 2h = unchanged from previous state 3h = reserved" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT                 ,Cycle format [TDM mode only] for the VP output. Shadow bit-field. 0h = 1 cycle for 1 pixel 1h = 2 cycles for 1 pixel 2h = 3 cycles for 1 pixel 3h = 3 cycles for 2 pixels" "0,1,2,3"
bitfld.long 0x00 21.--22. "         TDMPARALLELMODE ,Output Interface width [TDM mode only] for the VP output. Shadow bit-field. 0h = 8-bit parallel output interface selected 1h = 9-bit parallel output interface selected 2h = 12-bit parallel output interface selected 3h = 16-bit parallel output interface selected" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 20. " TDMENABLE                      ,Enable the multiple cycle format for the VP output. Shadow bit-field. 0h = TDM disabled 1h = TDM enabled" "0,1"
bitfld.long 0x00 14.--16. "         HT              ,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 11. " STALLMODE                      ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 8.--10. "         DATALINES       ,Width of the data bus on VP output. Shadow bit-field. 0h = 12-bit output aligned on the LSB of the pixel data interface 1h = 16-bit output aligned on the LSB of the pixel data interface 2h = 18-bit output aligned on the LSB of the pixel data interface 3h = 24-bit output aligned on the LSB of the pixel data interface 4h = 30-bit output aligned on the LSB of the pixel data interface 5h = 36-bit output aligned on the LSB of the pixel data interface" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 7. " STDITHERENABLE                 ,Spatial Temporal dithering enable for the VP output. Shadow bit-field. 0h = Spatial/Temporal dithering logic disabled 1h = Spatial/Temporal dithering logic enabled" "0,1"
bitfld.long 0x00 6. "         DPIENABLE       ,Enable the DPI output. wr:immediate 0h = DPI output disabled 1h = DPI output enabled" "0,1"
textline "                                          "
bitfld.long 0x00 5. " GOBIT                          ,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate 0h = The hardware has finished the synchronization 1h = Software has requested for synchronization after register updates and the hardware has not finished the synchronization" "0,1"
bitfld.long 0x00 4. "         M8B             ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 3. " STN                            ,Deprecated. Always write 0" "0,1"
bitfld.long 0x00 2. "         MONOCOLOR       ,Deprecated. Always write 0" "0,1"
textline "                                          "
bitfld.long 0x00 1. " VPPROGLINENUMBERMODULO         ,Enable the modulo of the line number interrupt generation 0h = Disable modulo 1h = Enable Modulo" "0,1"
bitfld.long 0x00 0. "         ENABLE          ,Enable the video port output. wr:immediate 0h = LCD output disabled-at the end of the frame when the bit is reset 1h = LCD output enabled" "0,1"
group.long 0x8++0x3
line.long 0x00 "DSS0_VP_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C01                            ,C01 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C00             ,C00 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0xC++0x3
line.long 0x00 "DSS0_VP_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C10                            ,C10 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C02             ,C02 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x10++0x3
line.long 0x00 "DSS0_VP_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C12                            ,C12 Coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C11             ,C11 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x14++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_0,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits. Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_1,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x3
line.long 0x00 "DSS0_VP_DATA_CYCLE_2,The register configures the output data format over up to 3 cycles. Shadow register"
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2             ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "        NBBITSPIXEL2    ,Number of bits. Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1             ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "        NBBITSPIXEL1    ,Number of bits. Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44++0x3
line.long 0x00 "DSS0_VP_LINE_NUMBER,The register indicates the panel display line number for the interrupt and the DMA request. Shadow register"
hexmask.long.word 0x00 0.--11. 1. " LINENUMBER                     ,LCD panel line number programming. LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs."
group.long 0x4C++0x3
line.long 0x00 "DSS0_VP_POL_FREQ,The register configures the signal configuration. Shadow register"
bitfld.long 0x00 18. " ALIGN                          ,Defines the alignment between HSYNC and VSYNC assertion 0h = VSYNC and HSYNC are not aligned 1h = VSYNC and HSYNC assertions are aligned." "0,1"
bitfld.long 0x00 17. "         ONOFF           ,HSYNC/VSYNC Pixel clock Control On/Off 0h = HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 1h = HSYNC and VSYNC are driven according to bit 16" "0,1"
textline "                                          "
bitfld.long 0x00 16. " RF                             ,Program HSYNC/VSYNC Rise or Fall 0h = HSYNC and VSYNC are driven on falling edge of pixel clock -if bit 17 set to 1 1h = HSYNC and VSYNC are driven on rising edge of pixel clock -if bit 17 set to 1" "0,1"
bitfld.long 0x00 15. "         IEO             ,Invert output enable 0h = DE is active high 1h = DE is active low" "0,1"
textline "                                          "
bitfld.long 0x00 14. " IPC                            ,Invert pixel clock 0h = Data is driven on the LCD data lines on the rising-edge of the pixel clock 1h = Data is driven on the LCD data lines on the falling-edge of the pixel clock" "0,1"
bitfld.long 0x00 13. "         IHS             ,Invert HSYNC 0h = Hsync pin is active high and inactive low 1h = Hsync pin is active low and inactive high" "0,1"
textline "                                          "
bitfld.long 0x00 12. " IVS                            ,Invert VSYNC 0h = Vsync pin is active high and inactive low 1h = Vsync pin is active low and inactive high" "0,1"
bitfld.long 0x00 8.--11. "         ACBI            ,AC Bias Pin transitions per interrupt. Value [from 0 to 15] used to specify the number of AC Bias pin transitions." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " ACB                            ,AC Bias Pin Frequency. Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display."
group.long 0x50++0x3
line.long 0x00 "DSS0_VP_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line."
hexmask.long.word 0x00 16.--27. 1. " LPP                            ,Lines per panel. Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]."
bitfld.long 0x00 14.--15. "      DELTA_LPP       ,Indicates the delta size value of the odd field compared to the even field 0h = Same size 1h = Odd size is even size plus 1 2h = Odd size is even size minus 1" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 0.--11. 1. " PPL                            ,Pixels per line. Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode, any value is valid. In non-STALL mode, only values multiple of 8 pixels are valid."
group.long 0x54++0x3
line.long 0x00 "DSS0_VP_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register"
hexmask.long.word 0x00 20.--31. 1. " HBP                            ,Horizontal Back Porch. Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one]. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field."
hexmask.long.word 0x00 8.--19. 1. "      HFP             ,Horizontal front porch. Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one]. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " HSW                            ,Horizontal synchronization pulse width. Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one]. When in BT mode, this field corresponds to the LSB 8-bits of the 12-bit horizontal blanking. [BT_HBLANK[11:0] = {VSW[3:0], HSW[7:0]}]"
group.long 0x58++0x3
line.long 0x00 "DSS0_VP_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register"
hexmask.long.word 0x00 20.--31. 1. " VBP                            ,Vertical back porch. Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. When in BT and in progressive mode, this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display."
hexmask.long.word 0x00 8.--19. 1. "      VFP             ,Vertical front porch. Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. When in BT and in progressive mode, this field corresponds to the Vertical frame blanking No 2."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " VSW                            ,Vertical synchronization pulse width. Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses. Frame clock uses as VSYNC signal in active mode. When in BT mode, the LSB 4-bits of this field [VSW[3:0]] corresponds to the MSB 4-bits of the 12-bit horizontal blanking. [BT_HBLANK = {VSW[3:0], HSW[7:0]}]"
group.long 0x5C++0x3
line.long 0x00 "DSS0_VP_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 16.--26. 1. " C21                            ,C21 coefficient. Encoded signed value [from -1024 to 1023]"
hexmask.long.word 0x00 0.--10. 1. "      C20             ,C20 coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x60++0x3
line.long 0x00 "DSS0_VP_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 0.--10. 1. " C22                            ,C22 Coefficient. Encoded signed value [from -1024 to 1023]"
group.long 0x64++0x3
line.long 0x00 "DSS0_VP_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " PREOFFSET2                     ,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET1      ,Row1 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x68++0x3
line.long 0x00 "DSS0_VP_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET1                    ,Row-1 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      PREOFFSET3      ,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x6C++0x3
line.long 0x00 "DSS0_VP_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register"
hexmask.long.word 0x00 19.--31. 1. " POSTOFFSET3                    ,Row-3 post-offset. Encoded signed value [from -4096 to 4095]"
hexmask.long.word 0x00 3.--15. 1. "      POSTOFFSET2     ,Row-2 post-offset. Encoded signed value [from -4096 to 4095]"
group.long 0x70++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region" "0,1"
group.long 0x74++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field." "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
group.long 0x78++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field." "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
group.long 0x7C++0x3
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register"
bitfld.long 0x00 11.--12. " FRAMESKIP                      ,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays].0h = No frames are skipped 1h = Even Frames are skipped starting from second frame after ENABLE 2h = Odd Frames are skipped starting from first frame after ENABLE 3h = Reserved" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "         THRESHOLD       ,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1], a freeze frame detection will occur."
textline "                                          "
bitfld.long 0x00 2. " SEEDSELECT                     ,Initial seed selection control. 0h = Initial seed is always 0xFFFF_FFFF 1h = Initial seed is defined by SAFETY_LFSR_SEED.SEED register field" "0,1"
bitfld.long 0x00 1. "         CAPTUREMODE     ,Mode of operation of the safety check module 0h = Frame freeze detect enabled 1h = Data correctness check enabled" "0,1"
textline "                                          "
bitfld.long 0x00 0. " ENABLE                         ,Safety check Enable for the region." "0,1"
rgroup.long 0x90++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x94++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x98++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
rgroup.long 0x9C++0x3
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xB0++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xB4++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xB8++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xBC++0x3
line.long 0x00 "DSS0_VP_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register"
hexmask.long.word 0x00 16.--27. 1. " POSY                           ,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0."
hexmask.long.word 0x00 0.--11. 1. "      POSX            ,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0."
group.long 0xD0++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xD4++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xD8++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xDC++0x3
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register"
hexmask.long 0x00 0.--31. 1. " SIGNATURE                      ,The register configures the reference signature of the safety sub-region n. Shadow register."
group.long 0xF0++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xF4++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xF8++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0xFC++0x3
line.long 0x00 "DSS0_VP_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register."
hexmask.long.word 0x00 16.--27. 1. " SIZEY                          ,Height of the safety sub-region n. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0."
hexmask.long.word 0x00 0.--11. 1. "      SIZEX           ,Width of the safety sub-region n. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0."
group.long 0x110++0x3
line.long 0x00 "DSS0_VP_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register."
hexmask.long 0x00 0.--31. 1. " SEED                           ,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value. Otherwise, the MISR is initialized with 0xFFFF_FFFF. Shadow register."
wgroup.long 0x120++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_0,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x124++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_1,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x128++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_2,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x12C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_3,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x130++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_4,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x134++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_5,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x138++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_6,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x13C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_7,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x140++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_8,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x144++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_9,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x148++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_10,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x14C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_11,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x150++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_12,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x154++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_13,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x158++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_14,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
wgroup.long 0x15C++0x3
line.long 0x00 "DSS0_VP_GAMMA_TABLE_15,The register configures the gamma table on VP output."
hexmask.long.byte 0x00 24.--31. 1. " INDEX                          ,Defines the location in the table where the bit-fields VALUE_{R,G,B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "        VALUE_R         ,8-bit R value to be stored in the gamma table"
textline "                                          "
hexmask.long.byte 0x00 8.--15. 1. " VALUE_G                        ,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "        VALUE_B         ,8-bit B value to be stored in the gamma table"
width 0x0B
tree.end
tree.end
tree "ECAP"
tree "ECAP0_CTL_STS"
base ad:0x3100000
width 20.
group.long 0x0++0x3
line.long 0x00 "ECAP_TSCNT,Time Stamp Counter Register."
hexmask.long 0x00 0.--31. 1. " TSCNT      ,Active 32 bit-counter register that is used as the capture time-base"
group.long 0x4++0x3
line.long 0x00 "ECAP_CNTPHS,Counter Phase Control Register."
hexmask.long 0x00 0.--31. 1. " CNTPHS     ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded into"
group.long 0x8++0x3
line.long 0x00 "ECAP_CAP1,Capture-1 Register."
hexmask.long 0x00 0.--31. 1. " CAP1       ,This register can be loaded (written) by the following."
group.long 0xC++0x3
line.long 0x00 "ECAP_CAP2,Capture-2 Register."
hexmask.long 0x00 0.--31. 1. " CAP2       ,This register can be loaded (written) by the following."
group.long 0x10++0x3
line.long 0x00 "ECAP_CAP3,Capture-3 Register."
hexmask.long 0x00 0.--31. 1. " CAP3       ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User SW updates the PWM period value through this register. In this mode, CAP3 shadows CAP1."
group.long 0x14++0x3
line.long 0x00 "ECAP_CAP4,Capture-4 Register."
hexmask.long 0x00 0.--31. 1. " CAP4       ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User SW updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2."
group.long 0x28++0x3
line.long 0x00 "ECAP_ECCTL,ECAP Control Register."
bitfld.long 0x00 27.--31. " FILTER     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        APWMPOL     ,APWM output polarity select. This is applicable only in APWM operating mode 0h = Output is active high (Compare value defines high time) 1h = Output is active low (Compare value defines low time)" "0,1"
textline "                             "
bitfld.long 0x00 25. " CAP_APWM   ,CAP/APWM operating mode select 0h = ECAP module operates in capture mode. This mode forces the following configuration. 1. Inhibits TSCNT resets via TSCNT = PRD event. 2. Inhibits shadow loads on ECAP_CAP1 and ECAP_CAP2 registers. 3. Permits user to enable ECAP_CAP1- ECAP_CAP4 register load. (d) ECAP input / APWM output pin operates as a capture input." "0,1"
bitfld.long 0x00 24. "         SWSYNC      ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the TSCNT = PRD event. Note: Selection TSCNT = PRD is meaningful only in APWM mode. However, you can choose it in CAP mode if you find doing so useful." "0,1"
textline "                             "
bitfld.long 0x00 22.--23. " SYNCO_SEL  ,SyncOut Select" "0,1,2,3"
bitfld.long 0x00 21. "         SYNCI_EN    ," "0,1"
textline "                             "
bitfld.long 0x00 20. " TSCNTSTP   ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0h = TSCNT stopped 1h = TSCNT free-running" "0,1"
bitfld.long 0x00 19. "         REARM_RESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0h = Has no effect (reading always returns a 0) 1h = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1"
textline "                             "
bitfld.long 0x00 17.--18. " STOPVALUE  ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0h = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 1h = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 2h = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 3h = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3"
bitfld.long 0x00 16. "         CONT_ONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0h = Operate in continuous mode 1h = Operate in one-shot mode" "0,1"
textline "                             "
bitfld.long 0x00 14.--15. " FREE_SOFT  ,Emulation Control" "0,1,2,3"
bitfld.long 0x00 9.--13. "         EVTFLTPS    ,Event Filter prescale select:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 8. " CAPLDEN    ,Enable Loading of" "0,1"
bitfld.long 0x00 7. "         CTRRST4     ,Counter Reset on Capture Event 4" "0,1"
textline "                             "
bitfld.long 0x00 6. " CAP4POL    ,Capture Event 4 Polarity select" "0,1"
bitfld.long 0x00 5. "         CTRRST3     ,Counter Reset on Capture Event 3" "0,1"
textline "                             "
bitfld.long 0x00 4. " CAP3POL    ,Capture Event 3 Polarity select" "0,1"
bitfld.long 0x00 3. "         CTRRST2     ,Counter Reset on Capture Event 2" "0,1"
textline "                             "
bitfld.long 0x00 2. " CAP2POL    ,Capture Event 2 Polarity select" "0,1"
bitfld.long 0x00 1. "         CTRRST1     ,Counter Reset on Capture Event 1" "0,1"
textline "                             "
bitfld.long 0x00 0. " CAP1POL    ,Capture Event 1 Polarity select" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ECAP_ECEINT_EN_FLG,ECAP Interrupt Enable and Flag Register."
bitfld.long 0x00 23. " CMPEQ_FLG  ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0h = Indicates no event occurred 1h = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1"
bitfld.long 0x00 22. "         PRDEQ_FLG   ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0h = Indicates no event occurred 1h = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1"
textline "                             "
bitfld.long 0x00 21. " CNTOVF_FLG ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0h = Indicates no event occurred. 1h = Indicates the counter (TSCNT) has made the transition from FFFF FFFFh to 0000 0000h" "0,1"
bitfld.long 0x00 20. "         CEVT4_FLG   ,Capture Event 4 Status Flag. This flag is only active in CAP mode. 0h = Indicates no event occurred 1h = Indicates the fourth event occurred at ECAPn pin" "0,1"
textline "                             "
bitfld.long 0x00 19. " CEVT3_FLG  ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0h = Indicates no event occurred. 1h = Indicates the third event occurred at ECAPn pin." "0,1"
bitfld.long 0x00 18. "         CEVT2_FLG   ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0h = Indicates no event occurred. 1h = Indicates the second event occurred at ECAPn pin." "0,1"
textline "                             "
bitfld.long 0x00 17. " CEVT1_FLG  ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0h = Indicates no event occurred. 1h = Indicates the first event occurred at ECAPn pin." "0,1"
bitfld.long 0x00 16. "         INT_FLG     ,Global Interrupt Status Flag 0h = Indicates no interrupt generated. 1h = Indicates that an interrupt was generated." "0,1"
textline "                             "
bitfld.long 0x00 7. " CMPEQ_EN   ,Counter Equal Compare Interrupt Enable. 0h = Disable Compare Equal as an Interrupt source. 1h = Enable Compare Equal as an Interrupt source." "0,1"
bitfld.long 0x00 6. "         PRDEQ_EN    ,Counter Equal Period Interrupt Enable. 0h = Disable Period Equal as an Interrupt source. 1h = Enable Period Equal as an Interrupt source." "0,1"
textline "                             "
bitfld.long 0x00 5. " CNTOVF_EN  ,Counter Overflow Interrupt Enable. 0h = Disable counter Overflow as an Interrupt source. 1h = Enable counter Overflow as an Interrupt source." "0,1"
bitfld.long 0x00 4. "         CEVT4_EN    ,Capture Event 4 Interrupt Enable. 0h = Disable Capture Event 4 as an Interrupt source. 1h = Enable Capture Event 4 as an Interrupt source." "0,1"
textline "                             "
bitfld.long 0x00 3. " CEVT3_EN   ,Capture Event 3 Interrupt Enable. 0h = Disable Capture Event 3 as an Interrupt source. 1h = Enable Capture Event 3 as an Interrupt source." "0,1"
bitfld.long 0x00 2. "         CEVT2_EN    ,Capture Event 2 Interrupt Enable. 0h = Disable Capture Event 2 as an Interrupt source. 1h = Enable Capture Event 2 as an Interrupt source." "0,1"
textline "                             "
bitfld.long 0x00 1. " CEVT1_EN   ,Capture Event 1 Interrupt Enable . 0h = Disable Capture Event 1 as an Interrupt source. 1h = Enable Capture Event 1 as an Interrupt source." "0,1"
hgroup.long 0x30++0x3
hide.long 0x00 "ECAP_ECINT_CLR_FRC,ECAP Interrupt Clear and Forcing Register."
in
textline "                             "
rgroup.long 0x5C++0x3
line.long 0x00 "ECAP_PID,ECAP Revision ID."
hexmask.long 0x00 0.--31. 1. " REVISION   ,TI internal data. Identifies revision of peripheral."
width 0x0B
tree.end
tree.end
tree "ELM"
tree "ELM0"
base ad:0x5380000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "ELM_REVISION,This register contains the IP revision code. (A write to or reset of this register has no effect.)"
hexmask.long 0x00 0.--31. 1. " REVISION           ,TI internal data. Identifies revision of peripheral."
group.long 0x10++0x3
line.long 0x00 "ELM_SYSCONFIG,This register controls ELM local power management and software reset."
bitfld.long 0x00 8. " CLOCKACTIVITYOCP   ,ELM_FICLK activity when module is in IDLE mode 0h (R/W) = ELM_FICLK can be switched off. 1h (R/W) = ELM_FICLK is maintained." "OCP_OFF,OCP_ON"
bitfld.long 0x00 3.--4. "      SIDLEMODE       ,Slave interface power management (clock stop req/ack control) 0h (R/W) = Force-idle. A clock stop request is acknowledged unconditionally and immediately 1h (R/W) = No-idle. A clock stop request is never acknowledged. 2h (R/W) = Smart-idle. The acknowledgment to a clock stop request is given based on the internal activity. 3h (R/W) = Reserved do not use" "FORCE_IDLE,NO_IDLE,SMART_IDLE,RESERVED"
textline "                                    "
bitfld.long 0x00 1. " SOFTRESET          ,Module software reset 0h (R/W) = Normal mode 1h (R/W) = Start soft reset sequence." "NORMAL,RESET"
bitfld.long 0x00 0. "       AUTOGATING      ,Internal ELM_FICLK gating strategy 0h (R/W) = ELM_FICLK is free-running. 1h (R/W) = Automatic internal ELM_FICLK gating strategy is applied based on the Interconnect interface activity." "OCP_FREE,OCP_GATING"
rgroup.long 0x14++0x3
line.long 0x00 "ELM_SYSSTATUS,Internal reset monitoring Undefined since: From hardware perspective, the reset state is 0. From software user perspective, when the accessible module is 1."
bitfld.long 0x00 0. " RESETDONE          ,Internal reset monitoring 0h (R) = Reset is ongoing. 1h (R) = Reset is done (completed)." "RST_ONGOING,RST_DONE"
hgroup.long 0x18++0x3
hide.long 0x00 "ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error-location processes."
in
textline "                                    "
group.long 0x1C++0x3
line.long 0x00 "ELM_IRQENABLE,Interrupt enable."
bitfld.long 0x00 8. " PAGE_MASK          ,Page interrupt mask bit" "0,1"
bitfld.long 0x00 7. "            LOCATION_MASK_7 ,Error-location interrupt mask bit for syndrome polynomial 7" "0,1"
textline "                                    "
bitfld.long 0x00 6. " LOCATION_MASK_6    ,Error-location interrupt mask bit for syndrome polynomial 6" "0,1"
bitfld.long 0x00 5. "            LOCATION_MASK_5 ,Error-location interrupt mask bit for syndrome polynomial 5" "0,1"
textline "                                    "
bitfld.long 0x00 4. " LOCATION_MASK_4    ,Error-location interrupt mask bit for syndrome polynomial 4" "0,1"
bitfld.long 0x00 3. "            LOCATION_MASK_3 ,Error-location interrupt mask bit for syndrome polynomial 3" "0,1"
textline "                                    "
bitfld.long 0x00 2. " LOCATION_MASK_2    ,Error-location interrupt mask bit for syndrome polynomial 2" "0,1"
bitfld.long 0x00 1. "            LOCATION_MASK_1 ,Error-location interrupt mask bit for syndrome polynomial 1" "0,1"
textline "                                    "
bitfld.long 0x00 0. " LOCATION_MASK_0    ,Error-location interrupt mask bit for syndrome polynomial 0" "0,1"
group.long 0x20++0x3
line.long 0x00 "ELM_LOCATION_CONFIG,ECC algorithm parameters."
hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE           ,Maximum size of the buffers for which the error-location engine is used, in number of nibbles (4-bit entities)"
bitfld.long 0x00 0.--1. "         ECC_BCH_LEVEL   ,Error correction level" "0,1,2,3"
group.long 0x80++0x3
line.long 0x00 "ELM_PAGE_CTRL,Page definition."
bitfld.long 0x00 7. " SECTOR_7           ,Set to 1 if syndrome polynomial 7 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
bitfld.long 0x00 6. "            SECTOR_6        ,Set to 1 if syndrome polynomial 6 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
textline "                                    "
bitfld.long 0x00 5. " SECTOR_5           ,Set to 1 if syndrome polynomial 5 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
bitfld.long 0x00 4. "            SECTOR_4        ,Set to 1 if syndrome polynomial 4 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
textline "                                    "
bitfld.long 0x00 3. " SECTOR_3           ,Set to 1 if syndrome polynomial 3 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
bitfld.long 0x00 2. "            SECTOR_2        ,Set to 1 if syndrome polynomial 2 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
textline "                                    "
bitfld.long 0x00 1. " SECTOR_1           ,Set to 1 if syndrome polynomial 1 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
bitfld.long 0x00 0. "            SECTOR_0        ,Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode." "0,1"
group.long 0x400++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i,Input syndrome polynomial bits 0 to 31. Offset = 400h + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_0         ,Syndrome bits 0 to 31"
group.long 0x404++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_1_i,Input syndrome polynomial bits 32 to 63. Offset = 404h + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_1         ,Syndrome bits 32 to 63"
group.long 0x408++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_2_i,Input syndrome polynomial bits 64 to 95. Offset = 408h + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_2         ,Syndrome bits 64 to 95"
group.long 0x40C++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_3_i,Input syndrome polynomial bits 96 to 127. Offset = 40Ch + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_3         ,Syndrome bits 96 to 127"
group.long 0x410++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_4_i,Input syndrome polynomial bits 128 to 159. Offset = 410h + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_4         ,Syndrome bits 128 to 159"
group.long 0x414++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_5_i,Input syndrome polynomial bits 160 to 191. Offset = 414h + (i * 40h), where: i = 0 to 7"
hexmask.long 0x00 0.--31. 1. " SYNDROME_5         ,Syndrome bits 160 to 191"
group.long 0x418++0x3
line.long 0x00 "ELM_SYNDROME_FRAGMENT_6_i,Input syndrome polynomial bits 192 to 207. Offset = 418h + (i * 40h), where: i = 0 to 7"
bitfld.long 0x00 16. " SYNDROME_VALID     ,Syndrome valid bit" "0,1"
hexmask.long.word 0x00 0.--15. 1. "            SYNDROME_6      ,Syndrome bits 192 to 207"
rgroup.long 0x800++0x3
line.long 0x00 "ELM_LOCATION_STATUS_i,Exit status for the syndrome polynomial processing. Offset = 800h + (i * 100h), where: i = 0 to 7"
bitfld.long 0x00 8. " ECC_CORRECTABLE    ,Error-location process exit status" "0,1"
bitfld.long 0x00 0.--4. "            ECC_NB_ERRORS   ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x880++0x3
line.long 0x00 "ELM_ERROR_LOCATION_0_i,Error-location register 0. Offset = 880h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x884++0x3
line.long 0x00 "ELM_ERROR_LOCATION_1_i,Error-location register 1. Offset = 884h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x888++0x3
line.long 0x00 "ELM_ERROR_LOCATION_2_i,Error-location register 2. Offset = 888h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x88C++0x3
line.long 0x00 "ELM_ERROR_LOCATION_3_i,Error-location register 3. Offset = 88Ch + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x890++0x3
line.long 0x00 "ELM_ERROR_LOCATION_4_i,Error-location register 4. Offset = 890h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x894++0x3
line.long 0x00 "ELM_ERROR_LOCATION_5_i,Error-location register 5. Offset = 894h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x898++0x3
line.long 0x00 "ELM_ERROR_LOCATION_6_i,Error-location register 6. Offset = 898h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x89C++0x3
line.long 0x00 "ELM_ERROR_LOCATION_7_i,Error-location register 7. Offset = 89Ch + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8A0++0x3
line.long 0x00 "ELM_ERROR_LOCATION_8_i,Error-location register 8. Offset = 8A0h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8A4++0x3
line.long 0x00 "ELM_ERROR_LOCATION_9_i,Error-location register 9. Offset = 8A4h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8A8++0x3
line.long 0x00 "ELM_ERROR_LOCATION_10_i,Error-location register 10. Offset = 8A8h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8AC++0x3
line.long 0x00 "ELM_ERROR_LOCATION_11_i,Error-location register 11. Offset = 8ACh + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8B0++0x3
line.long 0x00 "ELM_ERROR_LOCATION_12_i,Error-location register 12. Offset = 8B0h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8B4++0x3
line.long 0x00 "ELM_ERROR_LOCATION_13_i,Error-location register 13. Offset = 8B4h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8B8++0x3
line.long 0x00 "ELM_ERROR_LOCATION_14_i,Error-location register 14. Offset = 8B8h + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
rgroup.long 0x8BC++0x3
line.long 0x00 "ELM_ERROR_LOCATION_15_i,Error-location register 15. Offset = 8BCh + (i * 100h), where: i = 0 to 7"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address"
width 0x0B
tree.end
tree.end
tree "EPWM"
tree "EHRPWM0_EPWM"
base ad:0x3000000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree "EHRPWM1_EPWM"
base ad:0x3010000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree "EHRPWM2_EPWM"
base ad:0x3020000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree "EHRPWM3_EPWM"
base ad:0x3030000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree "EHRPWM4_EPWM"
base ad:0x3040000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree "EHRPWM5_EPWM"
base ad:0x3050000
width 15.
group.word 0x0++0x1
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. " FREE_SOFT ," "0,1,2,3"
bitfld.word 0x00 13. "     PHSDIR    ," "0,1"
textline "                    "
bitfld.word 0x00 10.--12. " CLKDIV    ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "     HSPCLKDIV ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 6. " SWFSYNC   ," "0,1"
bitfld.word 0x00 4.--5. "     SYNCOSEL  ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 3. " PRDLD     ," "0,1"
bitfld.word 0x00 2. "     PHSEN     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " CTRMODE   ," "0,1,2,3"
hgroup.word 0x2++0x1
hide.word 0x00 "EPWM_TBSTS,"
in
textline "                    "
group.word 0x4++0x1
line.word 0x00 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH    ,"
group.word 0x6++0x1
line.word 0x00 "EPWM_TBPHS,"
hexmask.word 0x00 0.--15. 1. " TBPHS     ,"
group.word 0x8++0x1
line.word 0x00 "EPWM_TBCNT,"
hexmask.word 0x00 0.--15. 1. " TBCNT     ,"
group.word 0xA++0x1
line.word 0x00 "EPWM_TBPRD,"
hexmask.word 0x00 0.--15. 1. " TBPRD     ,"
group.word 0xE++0x1
line.word 0x00 "EPWM_CMPCTL,"
bitfld.word 0x00 9. " SHDWBFULL ," "0,1"
bitfld.word 0x00 8. "     SHDWAFULL ," "0,1"
textline "                    "
bitfld.word 0x00 6. " SHDWBMODE ," "0,1"
bitfld.word 0x00 4. "     SHDWAMODE ," "0,1"
textline "                    "
bitfld.word 0x00 2.--3. " LOADBMODE ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     LOADAMODE ," "0,1,2,3"
group.word 0x10++0x1
line.word 0x00 "HRPWM_CMPAHR,"
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR    ,"
group.word 0x12++0x1
line.word 0x00 "EPWM_CMPA,"
hexmask.word 0x00 0.--15. 1. " CMPA      ,"
group.word 0x14++0x1
line.word 0x00 "EPWM_CMPB,"
hexmask.word 0x00 0.--15. 1. " CMPB      ,"
group.word 0x16++0x1
line.word 0x00 "EPWM_AQCTLA,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x18++0x1
line.word 0x00 "EPWM_AQCTLB,"
bitfld.word 0x00 10.--11. " CBD       ," "0,1,2,3"
bitfld.word 0x00 8.--9. "     CBU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 6.--7. " CAD       ," "0,1,2,3"
bitfld.word 0x00 4.--5. "     CAU       ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " PRD       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     ZRO       ," "0,1,2,3"
group.word 0x1A++0x1
line.word 0x00 "EPWM_AQSFRC,"
bitfld.word 0x00 6.--7. " RLDCSF    ," "0,1,2,3"
bitfld.word 0x00 5. "     OTSFB     ," "0,1"
textline "                    "
bitfld.word 0x00 3.--4. " ACTSFB    ," "0,1,2,3"
bitfld.word 0x00 2. "     OTSFA     ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " ACTSFA    ," "0,1,2,3"
group.word 0x1C++0x1
line.word 0x00 "EPWM_AQCSFRC,"
bitfld.word 0x00 2.--3. " CSFB      ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     CSFA      ," "0,1,2,3"
group.word 0x1E++0x1
line.word 0x00 "EPWM_DBCTL,"
bitfld.word 0x00 4.--5. " IN_MODE   ," "0,1,2,3"
bitfld.word 0x00 2.--3. "     POLSEL    ," "0,1,2,3"
textline "                    "
bitfld.word 0x00 0.--1. " OUT_MODE  ," "0,1,2,3"
group.word 0x20++0x1
line.word 0x00 "EPWM_DBRED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x22++0x1
line.word 0x00 "EPWM_DBFED,"
hexmask.word 0x00 0.--9. 1. " DEL       ,"
group.word 0x24++0x1
line.word 0x00 "EPWM_TZSEL,"
bitfld.word 0x00 13. " OSHT6     ," "0,1"
bitfld.word 0x00 12. "     OSHT5     ," "0,1"
textline "                    "
bitfld.word 0x00 11. " OSHT4     ," "0,1"
bitfld.word 0x00 10. "     OSHT3     ," "0,1"
textline "                    "
bitfld.word 0x00 9. " OSHT2     ," "0,1"
bitfld.word 0x00 8. "     OSHT1     ," "0,1"
textline "                    "
bitfld.word 0x00 5. " CBC5      ," "0,1"
bitfld.word 0x00 4. "     CBC4      ," "0,1"
textline "                    "
bitfld.word 0x00 3. " CBC3      ," "0,1"
bitfld.word 0x00 2. "     CBC2      ," "0,1"
textline "                    "
bitfld.word 0x00 1. " CBC1      ," "0,1"
bitfld.word 0x00 0. "     CBC0      ," "0,1"
group.word 0x28++0x1
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. " TZB       ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     TZA       ," "0,1,2,3"
group.word 0x2A++0x1
line.word 0x00 "EPWM_TZEINT,"
bitfld.word 0x00 2. " OST       ,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1"
bitfld.word 0x00 1. "     CBC       ,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation. 1h = Enable interrupt generation" "0,1"
rgroup.word 0x2C++0x1
line.word 0x00 "EPWM_TZFLG,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x2E++0x1
line.word 0x00 "EPWM_TZCLR,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x30++0x1
line.word 0x00 "EPWM_TZFRC,"
bitfld.word 0x00 2. " OST       ," "0,1"
bitfld.word 0x00 1. "     CBC       ," "0,1"
group.word 0x32++0x1
line.word 0x00 "EPWM_ETSEL,"
bitfld.word 0x00 15. " SOCB      ,Enable SOCB pulse when set to 1." "0,1"
bitfld.word 0x00 12.--14. "     SOCBSEL   ,EPWMxSOCB Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 11. " SOCA      ,Enable SOCA pulse when set to 1." "0,1"
bitfld.word 0x00 8.--10. "     SOCASEL   ,EPWMxSOCA Selection Options: 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event). 2h: Enable event time-base counter equal to period (PRD_eq event). 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is incrementing (CMPA_eq_UC event). 5h: Enable event time-base counter equal to CMPA when the timer is decrementing (CMPA_eq_DC event). 6h: Enable event time-base counter equal to CMPB when the timer is incrementing (CMPB_eq_UC event). 7h: Enable event time-base counter equal to CMPB when the timer is decrementing (CMPB_eq_DC event)." "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 3. " INTEN     ," "0,1"
bitfld.word 0x00 0.--2. "     INTSEL    ," "0,1,2,3,4,5,6,7"
group.word 0x34++0x1
line.word 0x00 "EPWM_ETPS,"
bitfld.word 0x00 14.--15. " SOCBCNT   ,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 event" "0,1,2,3"
bitfld.word 0x00 12.--13. "     SOCBPRD   ,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCBCNT = 1 (1st event) 2h: Generate pulse on SOCBCNT = 2 (2nd event) 3h: Generate pulse on SOCBCNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 10.--11. " SOCACNT   ,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred: 0h: No events 1h: 1 events 2h: 2 events 3h: 3 events" "0,1,2,3"
bitfld.word 0x00 8.--9. "     SOCAPRD   ,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated: 0h: Disable counter 1h: Generate pulse on SOCACNT = 1 (1st event) 2h: Generate pulse on SOCACNT = 2 (2nd event) 3h: Generate pulse on SOCACNT = 3 (3rd event)" "0,1,2,3"
textline "                    "
bitfld.word 0x00 2.--3. " INTCNT    ," "0,1,2,3"
bitfld.word 0x00 0.--1. "     INTPRD    ," "0,1,2,3"
rgroup.word 0x36++0x1
line.word 0x00 "EPWM_ETFLG,"
bitfld.word 0x00 3. " SOCB      ,Latched SOCB Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB. Note: Unlike the INT flag bit, the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1"
bitfld.word 0x00 2. "     SOCA      ,Latched SOCA Flag Bit Status: 0h: Indicates no event occurred. 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA. Note: Unlike the INT flag bit, the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x38++0x1
line.word 0x00 "EPWM_ETCLR,"
bitfld.word 0x00 3. " SOCB      ,SOCB Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit." "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Flag Clear Bit: 0h: Writing a 0 has no effect. Always reads back a 0. 1h: Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit." "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3A++0x1
line.word 0x00 "EPWM_ETFRC,"
bitfld.word 0x00 3. " SOCB      ,SOCB Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCB and set the" "0,1"
bitfld.word 0x00 2. "     SOCA      ,SOCA Force Bit: 0h: Writing 0 to this bit will be ignored. Always reads back a 0. 1h: Writing 1 will generate a pulse on EPWMxSOCA and set the" "0,1"
textline "                    "
bitfld.word 0x00 0. " INT       ," "0,1"
group.word 0x3C++0x1
line.word 0x00 "EPWM_PCCTL,"
bitfld.word 0x00 8.--10. " CHPDUTY   ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 5.--7. "     CHPFREQ   ," "0,1,2,3,4,5,6,7"
textline "                    "
bitfld.word 0x00 1.--4. " OSHTWTH   ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. "    CHPEN     ," "0,1"
group.word 0x40++0x1
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension, otherwise this location is reserved."
bitfld.word 0x00 3. " PULSESEL  ," "0,1"
bitfld.word 0x00 2. "     DELBUSSEL ," "0,1"
textline "                    "
bitfld.word 0x00 0.--1. " DELMODE   ,Edge Mode Bits. Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic." "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "EQEP"
tree "EQEP0_REG"
base ad:0x3200000
width 20.
group.long 0x0++0x3
line.long 0x00 "EQEP_QPOSCNT,"
hexmask.long 0x00 0.--31. 1. " QPOSCNT   ,This 32 bit position counter register counts up/down on every EQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point."
group.long 0x4++0x3
line.long 0x00 "EQEP_QPOSINIT,"
hexmask.long 0x00 0.--31. 1. " QPOSINIT  ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software."
group.long 0x8++0x3
line.long 0x00 "EQEP_QPOSMAX,"
hexmask.long 0x00 0.--31. 1. " QPOSMAX   ,This register contains the maximum position counter value."
group.long 0xC++0x3
line.long 0x00 "EQEP_QPOSCMP,"
hexmask.long 0x00 0.--31. 1. " QPOSCMP   ,The position-compare value in this register is compared with the position counter ("
rgroup.long 0x10++0x3
line.long 0x00 "EQEP_QPOSILAT,"
hexmask.long 0x00 0.--31. 1. " QPOSILAT  ,The position-counter value is latched into this register on an index event as defined by the"
rgroup.long 0x14++0x3
line.long 0x00 "EQEP_QPOSSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSSLAT  ,The position-counter value is latched into this register on strobe event as defined by the"
rgroup.long 0x18++0x3
line.long 0x00 "EQEP_QPOSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSLAT   ,The position-counter value is latched into this register on unit time out event."
group.long 0x1C++0x3
line.long 0x00 "EQEP_QUTMR,"
hexmask.long 0x00 0.--31. 1. " QUTMR     ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated."
group.long 0x20++0x3
line.long 0x00 "EQEP_QUPRD,"
hexmask.long 0x00 0.--31. 1. " QUPRD     ,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt."
group.long 0x24++0x3
line.long 0x00 "EQEP_QWD_TMR_PRD,"
hexmask.long.word 0x00 16.--31. 1. " QWDPRD    ,This field contains the time-out count for the EQEP peripheral watch dog timer. When the watch dog timer value matches with the watch dog period value, status flag is set to indicate the stall."
hexmask.long.word 0x00 0.--15. 1. "      QWDTMR   ,This field acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion."
group.long 0x28++0x3
line.long 0x00 "EQEP_QDEC_QEP_CTL,"
bitfld.long 0x00 30.--31. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. EQEP_QPOSCNT behavior, x refers to the Position counter. EQEP_QWD_TMR_PRD behavior, x refers to the Watchdog counter. EQEP_QUTMR behavior, x refers to the Unit timer. EQEP_QCTMR behavior, x refers to the Capture timer. 0h = x stops immediately. For 1h = For QCTMR behavior, x continues to count until the next unit period event. 2h = x is unaffected by emulation suspend. 3h = x is unaffected by emulation suspend." "0,1,2,3"
bitfld.long 0x00 28.--29. "         PCRM     ,Position counter reset mode 0h = Position counter reset on an index event 1h = Position counter reset on the maximum position 2h = Position counter resets once on the first index event 3h = Position counter reset on a unit time event" "0,1,2,3"
textline "                             "
bitfld.long 0x00 26.--27. " SEI       ,Strobe event initialization of position counter 0h = Does nothing (action disabled) 1h = Does nothing (action disabled) 2h = Initializes the position counter on rising edge of the QEPS signal 3h = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3"
bitfld.long 0x00 24.--25. "         IEI      ,Index event initialization of position counter 0h = Do nothing (action disabled) 1h = Do nothing (action disabled) 2h = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 3h = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 23. " SWI       ,Software initialization of position counter 0h = Do nothing (action disabled) 1h = Initialize position counter, this bit is cleared automatically" "0,1"
bitfld.long 0x00 22. "         SEL      ,Strobe event latch of position counter 0h = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 1h = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1"
textline "                             "
bitfld.long 0x00 20.--21. " IEL       ,Index event latch of position counter (software index marker) 0h = Reserved 1h = Latches position counter on rising edge of the index signal 2h = Latches position counter on falling edge of the index signal 3h = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to theEQEP_QPOSILAT register and the direction flag is latched in the EQEP_QEPSTS[QDLF] bit. This mode is useful for software index marking." "0,1,2,3"
bitfld.long 0x00 19. "         QPEN     ,Quadrature position counter enable/software reset 0h = Reset the EQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 1h = EQEP position counter is enabled" "0,1"
textline "                             "
bitfld.long 0x00 18. " QCLM      ,EQEP capture latch mode 0h = Latch on position counter read by CPU. Capture timer and capture period values are latched into EQEP_QCTMRLAT and EQEP_QCPRDLAT registers when CPU reads the EQEP_QPOSCNT register. 1h = Latch on unit time out. Position counter, capture timer and capture period values are latched intoEQEP_QPOSLAT, EQEP_QCTMRLAT and EQEP_QCPRDLAT registers on unit time out." "0,1"
bitfld.long 0x00 17. "         UTE      ,EQEP unit timer enable 0h = Disable EQEP unit timer 1h = Enable unit timer" "0,1"
textline "                             "
bitfld.long 0x00 16. " WDE       ,EQEP watchdog enable 0h = Disable the EQEP watchdog timer 1h = Enable the EQEP watchdog timer" "0,1"
bitfld.long 0x00 14.--15. "         QSRC     ,Position-counter source selection. 0h = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 1h = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 2h = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 3h = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 13. " SOEN      ,Sync output-enable 0h = Disable position-compare sync output 1h = Enable position-compare sync output" "0,1"
bitfld.long 0x00 12. "         SPSEL    ,Sync output pin selection 0h = Index pin is used for sync output 1h = Strobe pin is used for sync output" "0,1"
textline "                             "
bitfld.long 0x00 11. " XCR       ,External clock rate 0h = 2x resolution: Count the rising/falling edge 1h = 1x resolution: Count the rising edge only" "0,1"
bitfld.long 0x00 10. "         SWAP     ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0h = Quadrature-clock inputs are not swapped 1h = Quadrature-clock inputs are swapped" "0,1"
textline "                             "
bitfld.long 0x00 9. " IGATE     ,Index pulse gating option 0h = Disable gating of Index pulse 1h = Gate the index pin with strobe" "0,1"
bitfld.long 0x00 8. "         QAP      ,QEPA input polarity 0h = No effect 1h = Negates QEPA input" "0,1"
textline "                             "
bitfld.long 0x00 7. " QBP       ,QEPB input polarity 0h = No effect 1h = Negates QEPB input" "0,1"
bitfld.long 0x00 6. "         QIP      ,QEPI input polarity 0h = No effect 1h = Negates QEPI input" "0,1"
textline "                             "
bitfld.long 0x00 5. " QSP       ,QEPS input polarity 0h = No effect 1h = Negates QEPS input" "0,1"
group.long 0x2C++0x3
line.long 0x00 "EQEP_QCAP_QPOS_CTL,"
bitfld.long 0x00 31. " PCSHDW    ,Position-compare shadow enable 0h = Shadow disabled, load Immediate 1h = Shadow enabled" "0,1"
bitfld.long 0x00 30. "         PCLOAD   ,Position-compare shadow load mode 0h = Load on QPOSCNT = 0 1h = Load when QPOSCNT = QPOSCMP" "0,1"
textline "                             "
bitfld.long 0x00 29. " PCPOL     ,Polarity of sync output 0h = Active HIGH pulse output 1h = Active LOW pulse output" "0,1"
bitfld.long 0x00 28. "         PCE      ,Position-compare enable/disable 0h = Disable position compare unit 1h = Enable position compare unit" "0,1"
textline "                             "
hexmask.long.word 0x00 16.--27. 1. " PCSPW     ,Select-position-compare sync output pulse width ... 0h = 1 ? 4 ? EQEP_FICLK cycles 1h = 2 ? 4 ? EQEP_FICLK cycles 2h = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles FFFh = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles"
bitfld.long 0x00 15. "      CEN      ,Enable EQEP capture 0h = EQEP capture unit is disabled 1h = EQEP capture unit is enabled" "0,1"
textline "                             "
bitfld.long 0x00 4.--6. " CCPS      ,EQEP capture timer clock prescaler 0h = CAPCLK = EQEP_FICLK/1 1h = CAPCLK = EQEP_FICLK/2 2h = CAPCLK = EQEP_FICLK/4 3h = CAPCLK = EQEP_FICLK/8 4h = CAPCLK = EQEP_FICLK/16 5h = CAPCLK = EQEP_FICLK/32 6h = CAPCLK = EQEP_FICLK/64 7h = CAPCLK = EQEP_FICLK/128" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         UPPS     ,Unit position event prescaler 0h = UPEVNT = QCLK/1 1h = UPEVNT = QCLK/2 2h = UPEVNT = QCLK/4 3h = UPEVNT = QCLK/8 4h = UPEVNT = QCLK/16 5h = UPEVNT = QCLK/32 6h = UPEVNT = QCLK/64 7h = UPEVNT = QCLK/128 8h = UPEVNT = QCLK/256 9h = UPEVNT = QCLK/512 Ah = UPEVNT = QCLK/1024 Bh = UPEVNT = QCLK/2048 Ch = Reserved Dh = Reserved Eh = Reserved Fh = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x3
line.long 0x00 "EQEP_QINT_EN_FLG,"
bitfld.long 0x00 27. " UTOI_FLG  ,Unit time out interrupt flag 0h = No interrupt generated 1h = Set by EQEP unit timer period match" "0,1"
bitfld.long 0x00 26. "         IELI_FLG ,Index event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching the" "0,1"
textline "                             "
bitfld.long 0x00 25. " SELI_FLG  ,Strobe event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching theEQEP_QPOSSLAT" "0,1"
bitfld.long 0x00 24. "         PCMI_FLG ,EQEP compare match event interrupt flag 0h = No interrupt generated 1h = This bit is set on position-compare match" "0,1"
textline "                             "
bitfld.long 0x00 23. " PCRI_FLG  ,Position-compare ready interrupt flag 0h = No interrupt generated 1h = This bit is set after transferring the shadow register value to the active position compare register." "0,1"
bitfld.long 0x00 22. "         PCOI_FLG ,Position counter overflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter overflow." "0,1"
textline "                             "
bitfld.long 0x00 21. " PCUI_FLG  ,Position counter underflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter underflow." "0,1"
bitfld.long 0x00 20. "         WTOI_FLG ,Watchdog timeout interrupt flag 0h = No interrupt generated 1h = Set by watch dog timeout" "0,1"
textline "                             "
bitfld.long 0x00 19. " QDCI_FLG  ,Quadrature direction change interrupt flag 0h = No interrupt generated 1h = This bit is set during change of direction" "0,1"
bitfld.long 0x00 18. "         QPEI_FLG ,Quadrature phase error interrupt flag 0h = No interrupt generated 1h = Set on simultaneous transition of QEPA and QEPB" "0,1"
textline "                             "
bitfld.long 0x00 17. " PCEI_FLG  ,Position counter error interrupt flag 0h = No interrupt generated 1h = Position counter error" "0,1"
bitfld.long 0x00 16. "         INT_FLG  ,Global interrupt status flag 0h = No interrupt generated 1h = Interrupt was generated" "0,1"
textline "                             "
bitfld.long 0x00 11. " UTOI_EN   ,Unit time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 10. "         IELI_EN  ,Index event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 9. " SELI_EN   ,Strobe event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 8. "         PCMI_EN  ,Position-compare match interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 7. " PCRI_EN   ,Position-compare ready interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 6. "         PCOI_EN  ,Position counter overflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 5. " PCUI_EN   ,Position counter underflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 4. "         WTOI_EN  ,Watchdog time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 3. " QDCI_EN   ,Quadrature direction change interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 2. "         QPEI_EN  ,Quadrature phase error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 1. " PCEI_EN   ,Position counter error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
hgroup.long 0x34++0x3
hide.long 0x00 "EQEP_QINT_CLR_FRC,"
in
textline "                             "
hgroup.long 0x38++0x3
hide.long 0x00 "EQEP_QEP_STS_CT,"
in
textline "                             "
group.long 0x3C++0x3
line.long 0x00 "EQEP_QC_PRD_TLAT,"
hexmask.long.word 0x00 16.--31. 1. " QCTMRLAT  ,The EQEP capture timer value can be latched into this register on two events:"
hexmask.long.word 0x00 0.--15. 1. "      QCPRD    ,This register holds the period count value between the last successive EQEP position events."
group.word 0x40++0x1
line.word 0x00 "EQEP_QCPRDLAT,"
hexmask.word 0x00 0.--15. 1. "     QCPRDLAT  ,The EQEP capture period value can be latched into this register on two events:"
rgroup.long 0x5C++0x3
line.long 0x00 "EQEP_REVID,"
hexmask.long 0x00 0.--31. 1. " REVISION  ,IP Revision"
width 0x0B
tree.end
tree "EQEP1_REG"
base ad:0x3210000
width 20.
group.long 0x0++0x3
line.long 0x00 "EQEP_QPOSCNT,"
hexmask.long 0x00 0.--31. 1. " QPOSCNT   ,This 32 bit position counter register counts up/down on every EQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point."
group.long 0x4++0x3
line.long 0x00 "EQEP_QPOSINIT,"
hexmask.long 0x00 0.--31. 1. " QPOSINIT  ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software."
group.long 0x8++0x3
line.long 0x00 "EQEP_QPOSMAX,"
hexmask.long 0x00 0.--31. 1. " QPOSMAX   ,This register contains the maximum position counter value."
group.long 0xC++0x3
line.long 0x00 "EQEP_QPOSCMP,"
hexmask.long 0x00 0.--31. 1. " QPOSCMP   ,The position-compare value in this register is compared with the position counter ("
rgroup.long 0x10++0x3
line.long 0x00 "EQEP_QPOSILAT,"
hexmask.long 0x00 0.--31. 1. " QPOSILAT  ,The position-counter value is latched into this register on an index event as defined by the"
rgroup.long 0x14++0x3
line.long 0x00 "EQEP_QPOSSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSSLAT  ,The position-counter value is latched into this register on strobe event as defined by the"
rgroup.long 0x18++0x3
line.long 0x00 "EQEP_QPOSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSLAT   ,The position-counter value is latched into this register on unit time out event."
group.long 0x1C++0x3
line.long 0x00 "EQEP_QUTMR,"
hexmask.long 0x00 0.--31. 1. " QUTMR     ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated."
group.long 0x20++0x3
line.long 0x00 "EQEP_QUPRD,"
hexmask.long 0x00 0.--31. 1. " QUPRD     ,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt."
group.long 0x24++0x3
line.long 0x00 "EQEP_QWD_TMR_PRD,"
hexmask.long.word 0x00 16.--31. 1. " QWDPRD    ,This field contains the time-out count for the EQEP peripheral watch dog timer. When the watch dog timer value matches with the watch dog period value, status flag is set to indicate the stall."
hexmask.long.word 0x00 0.--15. 1. "      QWDTMR   ,This field acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion."
group.long 0x28++0x3
line.long 0x00 "EQEP_QDEC_QEP_CTL,"
bitfld.long 0x00 30.--31. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. EQEP_QPOSCNT behavior, x refers to the Position counter. EQEP_QWD_TMR_PRD behavior, x refers to the Watchdog counter. EQEP_QUTMR behavior, x refers to the Unit timer. EQEP_QCTMR behavior, x refers to the Capture timer. 0h = x stops immediately. For 1h = For QCTMR behavior, x continues to count until the next unit period event. 2h = x is unaffected by emulation suspend. 3h = x is unaffected by emulation suspend." "0,1,2,3"
bitfld.long 0x00 28.--29. "         PCRM     ,Position counter reset mode 0h = Position counter reset on an index event 1h = Position counter reset on the maximum position 2h = Position counter resets once on the first index event 3h = Position counter reset on a unit time event" "0,1,2,3"
textline "                             "
bitfld.long 0x00 26.--27. " SEI       ,Strobe event initialization of position counter 0h = Does nothing (action disabled) 1h = Does nothing (action disabled) 2h = Initializes the position counter on rising edge of the QEPS signal 3h = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3"
bitfld.long 0x00 24.--25. "         IEI      ,Index event initialization of position counter 0h = Do nothing (action disabled) 1h = Do nothing (action disabled) 2h = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 3h = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 23. " SWI       ,Software initialization of position counter 0h = Do nothing (action disabled) 1h = Initialize position counter, this bit is cleared automatically" "0,1"
bitfld.long 0x00 22. "         SEL      ,Strobe event latch of position counter 0h = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 1h = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1"
textline "                             "
bitfld.long 0x00 20.--21. " IEL       ,Index event latch of position counter (software index marker) 0h = Reserved 1h = Latches position counter on rising edge of the index signal 2h = Latches position counter on falling edge of the index signal 3h = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to theEQEP_QPOSILAT register and the direction flag is latched in the EQEP_QEPSTS[QDLF] bit. This mode is useful for software index marking." "0,1,2,3"
bitfld.long 0x00 19. "         QPEN     ,Quadrature position counter enable/software reset 0h = Reset the EQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 1h = EQEP position counter is enabled" "0,1"
textline "                             "
bitfld.long 0x00 18. " QCLM      ,EQEP capture latch mode 0h = Latch on position counter read by CPU. Capture timer and capture period values are latched into EQEP_QCTMRLAT and EQEP_QCPRDLAT registers when CPU reads the EQEP_QPOSCNT register. 1h = Latch on unit time out. Position counter, capture timer and capture period values are latched intoEQEP_QPOSLAT, EQEP_QCTMRLAT and EQEP_QCPRDLAT registers on unit time out." "0,1"
bitfld.long 0x00 17. "         UTE      ,EQEP unit timer enable 0h = Disable EQEP unit timer 1h = Enable unit timer" "0,1"
textline "                             "
bitfld.long 0x00 16. " WDE       ,EQEP watchdog enable 0h = Disable the EQEP watchdog timer 1h = Enable the EQEP watchdog timer" "0,1"
bitfld.long 0x00 14.--15. "         QSRC     ,Position-counter source selection. 0h = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 1h = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 2h = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 3h = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 13. " SOEN      ,Sync output-enable 0h = Disable position-compare sync output 1h = Enable position-compare sync output" "0,1"
bitfld.long 0x00 12. "         SPSEL    ,Sync output pin selection 0h = Index pin is used for sync output 1h = Strobe pin is used for sync output" "0,1"
textline "                             "
bitfld.long 0x00 11. " XCR       ,External clock rate 0h = 2x resolution: Count the rising/falling edge 1h = 1x resolution: Count the rising edge only" "0,1"
bitfld.long 0x00 10. "         SWAP     ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0h = Quadrature-clock inputs are not swapped 1h = Quadrature-clock inputs are swapped" "0,1"
textline "                             "
bitfld.long 0x00 9. " IGATE     ,Index pulse gating option 0h = Disable gating of Index pulse 1h = Gate the index pin with strobe" "0,1"
bitfld.long 0x00 8. "         QAP      ,QEPA input polarity 0h = No effect 1h = Negates QEPA input" "0,1"
textline "                             "
bitfld.long 0x00 7. " QBP       ,QEPB input polarity 0h = No effect 1h = Negates QEPB input" "0,1"
bitfld.long 0x00 6. "         QIP      ,QEPI input polarity 0h = No effect 1h = Negates QEPI input" "0,1"
textline "                             "
bitfld.long 0x00 5. " QSP       ,QEPS input polarity 0h = No effect 1h = Negates QEPS input" "0,1"
group.long 0x2C++0x3
line.long 0x00 "EQEP_QCAP_QPOS_CTL,"
bitfld.long 0x00 31. " PCSHDW    ,Position-compare shadow enable 0h = Shadow disabled, load Immediate 1h = Shadow enabled" "0,1"
bitfld.long 0x00 30. "         PCLOAD   ,Position-compare shadow load mode 0h = Load on QPOSCNT = 0 1h = Load when QPOSCNT = QPOSCMP" "0,1"
textline "                             "
bitfld.long 0x00 29. " PCPOL     ,Polarity of sync output 0h = Active HIGH pulse output 1h = Active LOW pulse output" "0,1"
bitfld.long 0x00 28. "         PCE      ,Position-compare enable/disable 0h = Disable position compare unit 1h = Enable position compare unit" "0,1"
textline "                             "
hexmask.long.word 0x00 16.--27. 1. " PCSPW     ,Select-position-compare sync output pulse width ... 0h = 1 ? 4 ? EQEP_FICLK cycles 1h = 2 ? 4 ? EQEP_FICLK cycles 2h = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles FFFh = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles"
bitfld.long 0x00 15. "      CEN      ,Enable EQEP capture 0h = EQEP capture unit is disabled 1h = EQEP capture unit is enabled" "0,1"
textline "                             "
bitfld.long 0x00 4.--6. " CCPS      ,EQEP capture timer clock prescaler 0h = CAPCLK = EQEP_FICLK/1 1h = CAPCLK = EQEP_FICLK/2 2h = CAPCLK = EQEP_FICLK/4 3h = CAPCLK = EQEP_FICLK/8 4h = CAPCLK = EQEP_FICLK/16 5h = CAPCLK = EQEP_FICLK/32 6h = CAPCLK = EQEP_FICLK/64 7h = CAPCLK = EQEP_FICLK/128" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         UPPS     ,Unit position event prescaler 0h = UPEVNT = QCLK/1 1h = UPEVNT = QCLK/2 2h = UPEVNT = QCLK/4 3h = UPEVNT = QCLK/8 4h = UPEVNT = QCLK/16 5h = UPEVNT = QCLK/32 6h = UPEVNT = QCLK/64 7h = UPEVNT = QCLK/128 8h = UPEVNT = QCLK/256 9h = UPEVNT = QCLK/512 Ah = UPEVNT = QCLK/1024 Bh = UPEVNT = QCLK/2048 Ch = Reserved Dh = Reserved Eh = Reserved Fh = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x3
line.long 0x00 "EQEP_QINT_EN_FLG,"
bitfld.long 0x00 27. " UTOI_FLG  ,Unit time out interrupt flag 0h = No interrupt generated 1h = Set by EQEP unit timer period match" "0,1"
bitfld.long 0x00 26. "         IELI_FLG ,Index event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching the" "0,1"
textline "                             "
bitfld.long 0x00 25. " SELI_FLG  ,Strobe event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching theEQEP_QPOSSLAT" "0,1"
bitfld.long 0x00 24. "         PCMI_FLG ,EQEP compare match event interrupt flag 0h = No interrupt generated 1h = This bit is set on position-compare match" "0,1"
textline "                             "
bitfld.long 0x00 23. " PCRI_FLG  ,Position-compare ready interrupt flag 0h = No interrupt generated 1h = This bit is set after transferring the shadow register value to the active position compare register." "0,1"
bitfld.long 0x00 22. "         PCOI_FLG ,Position counter overflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter overflow." "0,1"
textline "                             "
bitfld.long 0x00 21. " PCUI_FLG  ,Position counter underflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter underflow." "0,1"
bitfld.long 0x00 20. "         WTOI_FLG ,Watchdog timeout interrupt flag 0h = No interrupt generated 1h = Set by watch dog timeout" "0,1"
textline "                             "
bitfld.long 0x00 19. " QDCI_FLG  ,Quadrature direction change interrupt flag 0h = No interrupt generated 1h = This bit is set during change of direction" "0,1"
bitfld.long 0x00 18. "         QPEI_FLG ,Quadrature phase error interrupt flag 0h = No interrupt generated 1h = Set on simultaneous transition of QEPA and QEPB" "0,1"
textline "                             "
bitfld.long 0x00 17. " PCEI_FLG  ,Position counter error interrupt flag 0h = No interrupt generated 1h = Position counter error" "0,1"
bitfld.long 0x00 16. "         INT_FLG  ,Global interrupt status flag 0h = No interrupt generated 1h = Interrupt was generated" "0,1"
textline "                             "
bitfld.long 0x00 11. " UTOI_EN   ,Unit time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 10. "         IELI_EN  ,Index event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 9. " SELI_EN   ,Strobe event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 8. "         PCMI_EN  ,Position-compare match interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 7. " PCRI_EN   ,Position-compare ready interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 6. "         PCOI_EN  ,Position counter overflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 5. " PCUI_EN   ,Position counter underflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 4. "         WTOI_EN  ,Watchdog time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 3. " QDCI_EN   ,Quadrature direction change interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 2. "         QPEI_EN  ,Quadrature phase error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 1. " PCEI_EN   ,Position counter error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
hgroup.long 0x34++0x3
hide.long 0x00 "EQEP_QINT_CLR_FRC,"
in
textline "                             "
hgroup.long 0x38++0x3
hide.long 0x00 "EQEP_QEP_STS_CT,"
in
textline "                             "
group.long 0x3C++0x3
line.long 0x00 "EQEP_QC_PRD_TLAT,"
hexmask.long.word 0x00 16.--31. 1. " QCTMRLAT  ,The EQEP capture timer value can be latched into this register on two events:"
hexmask.long.word 0x00 0.--15. 1. "      QCPRD    ,This register holds the period count value between the last successive EQEP position events."
group.word 0x40++0x1
line.word 0x00 "EQEP_QCPRDLAT,"
hexmask.word 0x00 0.--15. 1. "     QCPRDLAT  ,The EQEP capture period value can be latched into this register on two events:"
rgroup.long 0x5C++0x3
line.long 0x00 "EQEP_REVID,"
hexmask.long 0x00 0.--31. 1. " REVISION  ,IP Revision"
width 0x0B
tree.end
tree "EQEP2_REG"
base ad:0x3220000
width 20.
group.long 0x0++0x3
line.long 0x00 "EQEP_QPOSCNT,"
hexmask.long 0x00 0.--31. 1. " QPOSCNT   ,This 32 bit position counter register counts up/down on every EQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point."
group.long 0x4++0x3
line.long 0x00 "EQEP_QPOSINIT,"
hexmask.long 0x00 0.--31. 1. " QPOSINIT  ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software."
group.long 0x8++0x3
line.long 0x00 "EQEP_QPOSMAX,"
hexmask.long 0x00 0.--31. 1. " QPOSMAX   ,This register contains the maximum position counter value."
group.long 0xC++0x3
line.long 0x00 "EQEP_QPOSCMP,"
hexmask.long 0x00 0.--31. 1. " QPOSCMP   ,The position-compare value in this register is compared with the position counter ("
rgroup.long 0x10++0x3
line.long 0x00 "EQEP_QPOSILAT,"
hexmask.long 0x00 0.--31. 1. " QPOSILAT  ,The position-counter value is latched into this register on an index event as defined by the"
rgroup.long 0x14++0x3
line.long 0x00 "EQEP_QPOSSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSSLAT  ,The position-counter value is latched into this register on strobe event as defined by the"
rgroup.long 0x18++0x3
line.long 0x00 "EQEP_QPOSLAT,"
hexmask.long 0x00 0.--31. 1. " QPOSLAT   ,The position-counter value is latched into this register on unit time out event."
group.long 0x1C++0x3
line.long 0x00 "EQEP_QUTMR,"
hexmask.long 0x00 0.--31. 1. " QUTMR     ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated."
group.long 0x20++0x3
line.long 0x00 "EQEP_QUPRD,"
hexmask.long 0x00 0.--31. 1. " QUPRD     ,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt."
group.long 0x24++0x3
line.long 0x00 "EQEP_QWD_TMR_PRD,"
hexmask.long.word 0x00 16.--31. 1. " QWDPRD    ,This field contains the time-out count for the EQEP peripheral watch dog timer. When the watch dog timer value matches with the watch dog period value, status flag is set to indicate the stall."
hexmask.long.word 0x00 0.--15. 1. "      QWDTMR   ,This field acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion."
group.long 0x28++0x3
line.long 0x00 "EQEP_QDEC_QEP_CTL,"
bitfld.long 0x00 30.--31. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. EQEP_QPOSCNT behavior, x refers to the Position counter. EQEP_QWD_TMR_PRD behavior, x refers to the Watchdog counter. EQEP_QUTMR behavior, x refers to the Unit timer. EQEP_QCTMR behavior, x refers to the Capture timer. 0h = x stops immediately. For 1h = For QCTMR behavior, x continues to count until the next unit period event. 2h = x is unaffected by emulation suspend. 3h = x is unaffected by emulation suspend." "0,1,2,3"
bitfld.long 0x00 28.--29. "         PCRM     ,Position counter reset mode 0h = Position counter reset on an index event 1h = Position counter reset on the maximum position 2h = Position counter resets once on the first index event 3h = Position counter reset on a unit time event" "0,1,2,3"
textline "                             "
bitfld.long 0x00 26.--27. " SEI       ,Strobe event initialization of position counter 0h = Does nothing (action disabled) 1h = Does nothing (action disabled) 2h = Initializes the position counter on rising edge of the QEPS signal 3h = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3"
bitfld.long 0x00 24.--25. "         IEI      ,Index event initialization of position counter 0h = Do nothing (action disabled) 1h = Do nothing (action disabled) 2h = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 3h = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 23. " SWI       ,Software initialization of position counter 0h = Do nothing (action disabled) 1h = Initialize position counter, this bit is cleared automatically" "0,1"
bitfld.long 0x00 22. "         SEL      ,Strobe event latch of position counter 0h = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 1h = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1"
textline "                             "
bitfld.long 0x00 20.--21. " IEL       ,Index event latch of position counter (software index marker) 0h = Reserved 1h = Latches position counter on rising edge of the index signal 2h = Latches position counter on falling edge of the index signal 3h = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to theEQEP_QPOSILAT register and the direction flag is latched in the EQEP_QEPSTS[QDLF] bit. This mode is useful for software index marking." "0,1,2,3"
bitfld.long 0x00 19. "         QPEN     ,Quadrature position counter enable/software reset 0h = Reset the EQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 1h = EQEP position counter is enabled" "0,1"
textline "                             "
bitfld.long 0x00 18. " QCLM      ,EQEP capture latch mode 0h = Latch on position counter read by CPU. Capture timer and capture period values are latched into EQEP_QCTMRLAT and EQEP_QCPRDLAT registers when CPU reads the EQEP_QPOSCNT register. 1h = Latch on unit time out. Position counter, capture timer and capture period values are latched intoEQEP_QPOSLAT, EQEP_QCTMRLAT and EQEP_QCPRDLAT registers on unit time out." "0,1"
bitfld.long 0x00 17. "         UTE      ,EQEP unit timer enable 0h = Disable EQEP unit timer 1h = Enable unit timer" "0,1"
textline "                             "
bitfld.long 0x00 16. " WDE       ,EQEP watchdog enable 0h = Disable the EQEP watchdog timer 1h = Enable the EQEP watchdog timer" "0,1"
bitfld.long 0x00 14.--15. "         QSRC     ,Position-counter source selection. 0h = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 1h = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 2h = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 3h = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3"
textline "                             "
bitfld.long 0x00 13. " SOEN      ,Sync output-enable 0h = Disable position-compare sync output 1h = Enable position-compare sync output" "0,1"
bitfld.long 0x00 12. "         SPSEL    ,Sync output pin selection 0h = Index pin is used for sync output 1h = Strobe pin is used for sync output" "0,1"
textline "                             "
bitfld.long 0x00 11. " XCR       ,External clock rate 0h = 2x resolution: Count the rising/falling edge 1h = 1x resolution: Count the rising edge only" "0,1"
bitfld.long 0x00 10. "         SWAP     ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0h = Quadrature-clock inputs are not swapped 1h = Quadrature-clock inputs are swapped" "0,1"
textline "                             "
bitfld.long 0x00 9. " IGATE     ,Index pulse gating option 0h = Disable gating of Index pulse 1h = Gate the index pin with strobe" "0,1"
bitfld.long 0x00 8. "         QAP      ,QEPA input polarity 0h = No effect 1h = Negates QEPA input" "0,1"
textline "                             "
bitfld.long 0x00 7. " QBP       ,QEPB input polarity 0h = No effect 1h = Negates QEPB input" "0,1"
bitfld.long 0x00 6. "         QIP      ,QEPI input polarity 0h = No effect 1h = Negates QEPI input" "0,1"
textline "                             "
bitfld.long 0x00 5. " QSP       ,QEPS input polarity 0h = No effect 1h = Negates QEPS input" "0,1"
group.long 0x2C++0x3
line.long 0x00 "EQEP_QCAP_QPOS_CTL,"
bitfld.long 0x00 31. " PCSHDW    ,Position-compare shadow enable 0h = Shadow disabled, load Immediate 1h = Shadow enabled" "0,1"
bitfld.long 0x00 30. "         PCLOAD   ,Position-compare shadow load mode 0h = Load on QPOSCNT = 0 1h = Load when QPOSCNT = QPOSCMP" "0,1"
textline "                             "
bitfld.long 0x00 29. " PCPOL     ,Polarity of sync output 0h = Active HIGH pulse output 1h = Active LOW pulse output" "0,1"
bitfld.long 0x00 28. "         PCE      ,Position-compare enable/disable 0h = Disable position compare unit 1h = Enable position compare unit" "0,1"
textline "                             "
hexmask.long.word 0x00 16.--27. 1. " PCSPW     ,Select-position-compare sync output pulse width ... 0h = 1 ? 4 ? EQEP_FICLK cycles 1h = 2 ? 4 ? EQEP_FICLK cycles 2h = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles FFFh = 3 ? 4 ? EQEP_FICLK cycles to 4096 ? 4 ? EQEP_FICLK cycles"
bitfld.long 0x00 15. "      CEN      ,Enable EQEP capture 0h = EQEP capture unit is disabled 1h = EQEP capture unit is enabled" "0,1"
textline "                             "
bitfld.long 0x00 4.--6. " CCPS      ,EQEP capture timer clock prescaler 0h = CAPCLK = EQEP_FICLK/1 1h = CAPCLK = EQEP_FICLK/2 2h = CAPCLK = EQEP_FICLK/4 3h = CAPCLK = EQEP_FICLK/8 4h = CAPCLK = EQEP_FICLK/16 5h = CAPCLK = EQEP_FICLK/32 6h = CAPCLK = EQEP_FICLK/64 7h = CAPCLK = EQEP_FICLK/128" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         UPPS     ,Unit position event prescaler 0h = UPEVNT = QCLK/1 1h = UPEVNT = QCLK/2 2h = UPEVNT = QCLK/4 3h = UPEVNT = QCLK/8 4h = UPEVNT = QCLK/16 5h = UPEVNT = QCLK/32 6h = UPEVNT = QCLK/64 7h = UPEVNT = QCLK/128 8h = UPEVNT = QCLK/256 9h = UPEVNT = QCLK/512 Ah = UPEVNT = QCLK/1024 Bh = UPEVNT = QCLK/2048 Ch = Reserved Dh = Reserved Eh = Reserved Fh = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x3
line.long 0x00 "EQEP_QINT_EN_FLG,"
bitfld.long 0x00 27. " UTOI_FLG  ,Unit time out interrupt flag 0h = No interrupt generated 1h = Set by EQEP unit timer period match" "0,1"
bitfld.long 0x00 26. "         IELI_FLG ,Index event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching the" "0,1"
textline "                             "
bitfld.long 0x00 25. " SELI_FLG  ,Strobe event latch interrupt flag 0h = No interrupt generated 1h = This bit is set after latching theEQEP_QPOSSLAT" "0,1"
bitfld.long 0x00 24. "         PCMI_FLG ,EQEP compare match event interrupt flag 0h = No interrupt generated 1h = This bit is set on position-compare match" "0,1"
textline "                             "
bitfld.long 0x00 23. " PCRI_FLG  ,Position-compare ready interrupt flag 0h = No interrupt generated 1h = This bit is set after transferring the shadow register value to the active position compare register." "0,1"
bitfld.long 0x00 22. "         PCOI_FLG ,Position counter overflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter overflow." "0,1"
textline "                             "
bitfld.long 0x00 21. " PCUI_FLG  ,Position counter underflow interrupt flag 0h = No interrupt generated 1h = This bit is set on position counter underflow." "0,1"
bitfld.long 0x00 20. "         WTOI_FLG ,Watchdog timeout interrupt flag 0h = No interrupt generated 1h = Set by watch dog timeout" "0,1"
textline "                             "
bitfld.long 0x00 19. " QDCI_FLG  ,Quadrature direction change interrupt flag 0h = No interrupt generated 1h = This bit is set during change of direction" "0,1"
bitfld.long 0x00 18. "         QPEI_FLG ,Quadrature phase error interrupt flag 0h = No interrupt generated 1h = Set on simultaneous transition of QEPA and QEPB" "0,1"
textline "                             "
bitfld.long 0x00 17. " PCEI_FLG  ,Position counter error interrupt flag 0h = No interrupt generated 1h = Position counter error" "0,1"
bitfld.long 0x00 16. "         INT_FLG  ,Global interrupt status flag 0h = No interrupt generated 1h = Interrupt was generated" "0,1"
textline "                             "
bitfld.long 0x00 11. " UTOI_EN   ,Unit time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 10. "         IELI_EN  ,Index event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 9. " SELI_EN   ,Strobe event latch interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 8. "         PCMI_EN  ,Position-compare match interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 7. " PCRI_EN   ,Position-compare ready interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 6. "         PCOI_EN  ,Position counter overflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 5. " PCUI_EN   ,Position counter underflow interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 4. "         WTOI_EN  ,Watchdog time out interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 3. " QDCI_EN   ,Quadrature direction change interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
bitfld.long 0x00 2. "         QPEI_EN  ,Quadrature phase error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
textline "                             "
bitfld.long 0x00 1. " PCEI_EN   ,Position counter error interrupt enable 0h = Interrupt is disabled 1h = Interrupt is enabled" "0,1"
hgroup.long 0x34++0x3
hide.long 0x00 "EQEP_QINT_CLR_FRC,"
in
textline "                             "
hgroup.long 0x38++0x3
hide.long 0x00 "EQEP_QEP_STS_CT,"
in
textline "                             "
group.long 0x3C++0x3
line.long 0x00 "EQEP_QC_PRD_TLAT,"
hexmask.long.word 0x00 16.--31. 1. " QCTMRLAT  ,The EQEP capture timer value can be latched into this register on two events:"
hexmask.long.word 0x00 0.--15. 1. "      QCPRD    ,This register holds the period count value between the last successive EQEP position events."
group.word 0x40++0x1
line.word 0x00 "EQEP_QCPRDLAT,"
hexmask.word 0x00 0.--15. 1. "     QCPRDLAT  ,The EQEP capture period value can be latched into this register on two events:"
rgroup.long 0x5C++0x3
line.long 0x00 "EQEP_REVID,"
hexmask.long 0x00 0.--31. 1. " REVISION  ,IP Revision"
width 0x0B
tree.end
tree.end
tree "ESM"
tree "ESM0"
base ad:0x700000
width 19.
rgroup.long 0x0++0x3
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME     ,Always reads as 1h. Writes have no affect." "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU           ,Business Unit:2h = Processors" "0,1,2,3"
textline "                            "
hexmask.long.word 0x00 16.--27. 1. " FUNC       ,Module ID. Always read as the assigned functional ID. Writes have no affect."
bitfld.long 0x00 11.--15. "      RTL          ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 8.--10. " MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM       ,Custom. Special version." "0,1,2,3"
textline "                            "
bitfld.long 0x00 0.--5. " MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ESM_INFO,The Info Register gives the configuration information of this ESM."
bitfld.long 0x00 31. " LAST_RESET ,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         PULSE_GROUPS ,Indicates the number of event groups that are pulse (as opposed to level) driven."
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " GROUPS     ,Indicates the total number of groups that exist in the ESM."
group.long 0x8++0x3
line.long 0x00 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x00 0.--3. " KEY        ,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that, after a warm reset, software may observe the state of the ESM before the warm reset and try to debug what may have caused the reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long 0xC++0x3
line.long 0x00 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x00 0.--3. " KEY        ,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x00 0.--7. 1. " STS        ,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h."
hgroup.long 0x14++0x3
hide.long 0x00 "ESM_ERR_STS,Config Error Enable and Clear Register"
in
textline "                            "
group.long 0x18++0x3
line.long 0x00 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x00 0.--7. 1. " MSK        ,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the"
hgroup.long 0x1C++0x3
hide.long 0x00 "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
in
textline "                            "
rgroup.long 0x20++0x3
line.long 0x00 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for High Priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
rgroup.long 0x24++0x3
line.long 0x00 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
rgroup.long 0x28++0x3
line.long 0x00 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
rgroup.long 0x2C++0x3
line.long 0x00 "ESM_HI,Shows which groups have outstanding high priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
wgroup.long 0x30++0x3
line.long 0x00 "ESM_EOI,End of Interrupt Register"
hexmask.long.word 0x00 0.--10. 1. " KEY        ,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If, when the vector is written, there are still pending interrupts, a new pulse will be generated. Reads always return 0."
group.long 0x40++0x3
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. " KEY        ,Pin control key. This field controls behavior of the error pin. Note, during reset the field is 0h, but the error pin is asserted (active low). Immediately after reset, the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. A global soft reset will also CLEAR all pending faults." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x44++0x3
line.long 0x00 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x00 0. " VAL        ,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset, then the value of this field may be 1h after the release of Warm Reset." "0,1"
rgroup.long 0x48++0x3
line.long 0x00 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This field indicates the current value of the time interval counter. See"
group.long 0x4C++0x3
line.long 0x00 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This is the value that will be pre-loaded in to the counter field of the"
group.long 0x400++0x3
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " STS        ,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?)"
hgroup.long 0x404++0x3
hide.long 0x00 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x408++0x3
line.long 0x00 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) If the corresponding bit and the global enable"
hgroup.long 0x40C++0x3
hide.long 0x00 "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x410++0x3
line.long 0x00 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
group.long 0x414++0x3
line.long 0x00 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
hgroup.long 0x418++0x3
hide.long 0x00 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
width 0x0B
tree.end
tree "MCU_ESM0"
base ad:0x40800000
width 19.
rgroup.long 0x0++0x3
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME     ,Always reads as 1h. Writes have no affect." "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU           ,Business Unit:2h = Processors" "0,1,2,3"
textline "                            "
hexmask.long.word 0x00 16.--27. 1. " FUNC       ,Module ID. Always read as the assigned functional ID. Writes have no affect."
bitfld.long 0x00 11.--15. "      RTL          ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 8.--10. " MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM       ,Custom. Special version." "0,1,2,3"
textline "                            "
bitfld.long 0x00 0.--5. " MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ESM_INFO,The Info Register gives the configuration information of this ESM."
bitfld.long 0x00 31. " LAST_RESET ,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         PULSE_GROUPS ,Indicates the number of event groups that are pulse (as opposed to level) driven."
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " GROUPS     ,Indicates the total number of groups that exist in the ESM."
group.long 0x8++0x3
line.long 0x00 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x00 0.--3. " KEY        ,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that, after a warm reset, software may observe the state of the ESM before the warm reset and try to debug what may have caused the reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long 0xC++0x3
line.long 0x00 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x00 0.--3. " KEY        ,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x00 0.--7. 1. " STS        ,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h."
hgroup.long 0x14++0x3
hide.long 0x00 "ESM_ERR_STS,Config Error Enable and Clear Register"
in
textline "                            "
group.long 0x18++0x3
line.long 0x00 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x00 0.--7. 1. " MSK        ,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the"
hgroup.long 0x1C++0x3
hide.long 0x00 "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
in
textline "                            "
rgroup.long 0x20++0x3
line.long 0x00 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for High Priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
rgroup.long 0x24++0x3
line.long 0x00 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
rgroup.long 0x28++0x3
line.long 0x00 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
rgroup.long 0x2C++0x3
line.long 0x00 "ESM_HI,Shows which groups have outstanding high priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
wgroup.long 0x30++0x3
line.long 0x00 "ESM_EOI,End of Interrupt Register"
hexmask.long.word 0x00 0.--10. 1. " KEY        ,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If, when the vector is written, there are still pending interrupts, a new pulse will be generated. Reads always return 0."
group.long 0x40++0x3
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. " KEY        ,Pin control key. This field controls behavior of the error pin. Note, during reset the field is 0h, but the error pin is asserted (active low). Immediately after reset, the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. A global soft reset will also CLEAR all pending faults." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x44++0x3
line.long 0x00 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x00 0. " VAL        ,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset, then the value of this field may be 1h after the release of Warm Reset." "0,1"
rgroup.long 0x48++0x3
line.long 0x00 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This field indicates the current value of the time interval counter. See"
group.long 0x4C++0x3
line.long 0x00 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This is the value that will be pre-loaded in to the counter field of the"
group.long 0x400++0x3
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " STS        ,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?)"
hgroup.long 0x404++0x3
hide.long 0x00 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x408++0x3
line.long 0x00 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) If the corresponding bit and the global enable"
hgroup.long 0x40C++0x3
hide.long 0x00 "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x410++0x3
line.long 0x00 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
group.long 0x414++0x3
line.long 0x00 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
hgroup.long 0x418++0x3
hide.long 0x00 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
width 0x0B
tree.end
tree "WKUP_ESM0"
base ad:0x42080000
width 19.
rgroup.long 0x0++0x3
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME     ,Always reads as 1h. Writes have no affect." "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU           ,Business Unit:2h = Processors" "0,1,2,3"
textline "                            "
hexmask.long.word 0x00 16.--27. 1. " FUNC       ,Module ID. Always read as the assigned functional ID. Writes have no affect."
bitfld.long 0x00 11.--15. "      RTL          ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 8.--10. " MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM       ,Custom. Special version." "0,1,2,3"
textline "                            "
bitfld.long 0x00 0.--5. " MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ESM_INFO,The Info Register gives the configuration information of this ESM."
bitfld.long 0x00 31. " LAST_RESET ,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         PULSE_GROUPS ,Indicates the number of event groups that are pulse (as opposed to level) driven."
textline "                            "
hexmask.long.byte 0x00 0.--7. 1. " GROUPS     ,Indicates the total number of groups that exist in the ESM."
group.long 0x8++0x3
line.long 0x00 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x00 0.--3. " KEY        ,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that, after a warm reset, software may observe the state of the ESM before the warm reset and try to debug what may have caused the reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long 0xC++0x3
line.long 0x00 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x00 0.--3. " KEY        ,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x00 0.--7. 1. " STS        ,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h."
hgroup.long 0x14++0x3
hide.long 0x00 "ESM_ERR_STS,Config Error Enable and Clear Register"
in
textline "                            "
group.long 0x18++0x3
line.long 0x00 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x00 0.--7. 1. " MSK        ,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the"
hgroup.long 0x1C++0x3
hide.long 0x00 "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
in
textline "                            "
rgroup.long 0x20++0x3
line.long 0x00 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for High Priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x2. A value of all ones (0xFFFF) indicates that there are no low priority interrupts pending."
rgroup.long 0x24++0x3
line.long 0x00 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x00 16.--31. 1. " PLS        ,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
hexmask.long.word 0x00 0.--15. 1. "      LVL          ,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0, 1, 2, 3, and 4 are pending, and Global Event 0, and 1 are configured for high priority while Global Events 2, 3, and 4 are configured for low priority, then the value of this field will be 0x0. A value of all ones (0xFFFF) indicates that there are no high priority interrupts pending."
rgroup.long 0x28++0x3
line.long 0x00 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
rgroup.long 0x2C++0x3
line.long 0x00 "ESM_HI,Shows which groups have outstanding high priority interrupts"
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0, bit 1 is for Event Group 1, etc? (bit N is for Event Group N)."
wgroup.long 0x30++0x3
line.long 0x00 "ESM_EOI,End of Interrupt Register"
hexmask.long.word 0x00 0.--10. 1. " KEY        ,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If, when the vector is written, there are still pending interrupts, a new pulse will be generated. Reads always return 0."
group.long 0x40++0x3
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. " KEY        ,Pin control key. This field controls behavior of the error pin. Note, during reset the field is 0h, but the error pin is asserted (active low). Immediately after reset, the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. A global soft reset will also CLEAR all pending faults." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x44++0x3
line.long 0x00 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x00 0. " VAL        ,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset, then the value of this field may be 1h after the release of Warm Reset." "0,1"
rgroup.long 0x48++0x3
line.long 0x00 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This field indicates the current value of the time interval counter. See"
group.long 0x4C++0x3
line.long 0x00 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT      ,This is the value that will be pre-loaded in to the counter field of the"
group.long 0x400++0x3
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " STS        ,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?)"
hgroup.long 0x404++0x3
hide.long 0x00 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x408++0x3
line.long 0x00 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) If the corresponding bit and the global enable"
hgroup.long 0x40C++0x3
hide.long 0x00 "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
group.long 0x410++0x3
line.long 0x00 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
group.long 0x414++0x3
line.long 0x00 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
hexmask.long 0x00 0.--31. 1. " MSK        ,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0, bit 1 is N*32 + 1 etc?) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0."
hgroup.long 0x418++0x3
hide.long 0x00 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0 j = 0h to 4h for MCU_ESM0 j = 0h to 7h for ESM0"
in
textline "                            "
width 0x0B
tree.end
tree.end
tree "FSS"
tree "MCU_FSS0_CFG"
base ad:0x47000000
width 24.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_FSS0_REVISION,Revision Register Used by software to track features, bugs, and compatibility."
hexmask.long.word 0x00 16.--31. 1. " MODID                ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL           ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                 "
bitfld.long 0x00 8.--10. " REVMAJ               ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM           ,Custom Revision" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 0.--5. " REVMIN               ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCU_FSS0_SYSCONFIG,Configuration Register Controls various parameters of the cotroller state."
bitfld.long 0x00 3. " ECC_DISABLE_ADR      ,Block Address ECC Calculation 0h = Block address within ECC calculation 1h = Block address not within ECC calculation" "0,1"
bitfld.long 0x00 2. "         FSS_AES_EN_IPCFG ,Security Enable 0h = Disable security 1h = Enable security" "0,1"
textline "                                 "
bitfld.long 0x00 1. " HB_OSPI              ,Path Select 0h = Select OSPI path 1h = Select Hyperbus interface path" "0,1"
bitfld.long 0x00 0. "         ECC_EN           ,ECC Enable 0h = ECC disabled 1h = ECC enabled" "0,1"
group.long 0x10++0x3
line.long 0x00 "MCU_FSS0_EOI,End Of Interrupt (EOI) MISC Register The End Of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to it for misc interrupt sources. An EOI write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to."
bitfld.long 0x00 0. " EOI_VECTOR           ,EOI Vector Write with bit position of targeted interrupt (example: external FSS ECC is bit 0). Upon write, level interrupt will clear and if un-serviced will issue another pulse interrupt." "0,1"
group.long 0x14++0x3
line.long 0x00 "MCU_FSS0_STATUS_RAW,Interrupt Source Set Register The Interrupt Source Set Register allows the interrupt sources to be manually set when writing 1h to a specific bit. Write 0h = No action Write 1h = Set event Read 0h = No event pending Read 1h = Event pending"
bitfld.long 0x00 2. " ECC_WRITE_NONALIGN   ,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1"
bitfld.long 0x00 1. "         ECC_ERROR_2BIT   ,ECC Error on 2 Bits Not correctable." "0,1"
textline "                                 "
bitfld.long 0x00 0. " ECC_ERROR_1BIT       ,ECC Error on 1 Bit Correctable." "0,1"
hgroup.long 0x18++0x3
hide.long 0x00 "MCU_FSS0_STATUS,Interrupt Source Clear Register The Interrupt Source Clear Register allows the interrupt sources to be manually cleared when writing 1h to a specific bit. Write 0h = No action Write 1h = Clear event Read 0h = No event pending Read 1h = Event pending"
in
textline "                                 "
group.long 0x1C++0x3
line.long 0x00 "MCU_FSS0_ENABLE_SET,Interrupt Source Enable Register The Interrupt Source Enable Register allows the interrupt sources to be manually enabled when writing 1h to a specific bit. Write 0h = No action Write 1h = Enable event Read 0h = Event is disabled Read 1h = Event is enabled"
bitfld.long 0x00 2. " ECC_WRITE_NONALIGN   ,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1"
bitfld.long 0x00 1. "         ECC_ERROR_2BIT   ,ECC Error on 2 Bits Not correctable." "0,1"
textline "                                 "
bitfld.long 0x00 0. " ECC_ERROR_1BIT       ,ECC Error on 1 Bit Correctable." "0,1"
hgroup.long 0x20++0x3
hide.long 0x00 "MCU_FSS0_ENABLE_CLR,Interrupt Source Disable Register The Interrupt Source Disable Register allows the interrupt sources to be manually disabled when writing 1h to a specific bit. Write 0h = No action Write 1h = Disable event Read 0h = Event is disabled Read 1h = Event is enabled"
in
textline "                                 "
group.long 0x30++0x3
line.long 0x00 "MCU_FSS0_ECC_RGSTRT_j,ECC Region Start Register The ECC Region Start Register defines the start of the ECC region in 4 KB steps. Offset = 30h + (j ? 8h); where j = 0h to 3h MCU_FSS0_ECC_RGSTRT_0: 4700 0030h MCU_FSS0_ECC_RGSTRT_1: 4700 0038h MCU_FSS0_ECC_RGSTRT_2: 4700 0046h MCU_FSS0_ECC_RGSTRT_3: 4700 0054h"
hexmask.long.tbyte 0x00 0.--19. 1. " R_START              ,ECC Region Start Address This bit field defines the start of the ECC region in 4 KB steps. Address start = {start[19:0], 000h} 0h = start is 0000 0000h 1h = start is 0000 1000h Ah = start is 0000 A000h"
group.long 0x34++0x3
line.long 0x00 "MCU_FSS0_ECC_RGSIZ_j,ECC Region Size Register The ECC Region Size Register defines the size of the ECC region in 4 KB steps. Offset = 34h + (j ? 8h); where j = 0h to 3h MCU_FSS0_ECC_RGSIZ_0: 4700 0034h MCU_FSS0_ECC_RGSIZ_1: 4700 0042h MCU_FSS0_ECC_RGSIZ_2: 4700 0050h MCU_FSS0_ECC_RGSIZ_3: 4700 0058h"
hexmask.long.tbyte 0x00 0.--19. 1. " R_SIZE               ,ECC Region Size This bit field defines the size of the ECC region in 4 KB steps. 0h = size is zero and disabled 1h = size is 4 KB Ah = size is 40 KB F FFFFh = size is 4 GB"
rgroup.long 0x70++0x3
line.long 0x00 "MCU_FSS0_ECC_BLOCK_ADR,ECC Error Block Address Register The ECC Error Block Address Register holds the current top of stack ECC error block address, this is only valid when the [31] ECC_ERR_VALID bit is set."
hexmask.long 0x00 5.--31. 1. " ECC_ERROR_BLOCK_ADDR ,ECC Error Block Address ECC 32-byte aligned block address"
hgroup.long 0x74++0x3
hide.long 0x00 "MCU_FSS0_ECC_TYPE,ECC Error Type Register The ECC Error Type Register holds the current top of stack ECC error info, this is only valid when the [31] ECC_ERR_VALID bit is set."
in
textline "                                 "
hgroup.long 0x78++0x3
hide.long 0x00 "MCU_FSS0_WRT_TYPE,Error Write Type Register The Error Write Type Register holds the current top of stack write error info, this is only valid when the [31] WRT_ERR_VALID bit is set."
in
textline "                                 "
width 0x0B
tree.end
tree.end
tree "GPIO"
tree "GPIO0"
base ad:0x600000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "GPIO_PID,GPIO Periperal ID Register Updated Reset Value of GPIO_PID[15-11] RTL Bitfield"
bitfld.long 0x00 30.--31. " SCHEME  ,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     FUNC    ,Function code assigned to TCP3"
textline "                              "
bitfld.long 0x00 11.--15. " RTL     ,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    MAJOR   ,Major revision X code" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM  ,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "     MINOR   ,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "GPIO_PCR,Peripheral Control Register"
bitfld.long 0x00 1. " SOFT    ,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x00 0. "     FREE    ,For GPIO, the FREE bit is fixed at 1, which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x00 "GPIO_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x00 0.--15. 1. " EN      ,Per bank interrupt enable 0h = disable, 1h = enable"
group.long 0x10++0x3
line.long 0x00 "GPIO_DIR01,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR1    ,Direction of GPIO bank 1 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR0    ,Direction of GPIO bank 0 bits, 0h = output, 1h = input"
group.long 0x14++0x3
line.long 0x00 "GPIO_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT1    ,Output drive state of GPIO bank 1 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT0    ,Output drive state of GPIO bank 0 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x18++0x3
line.long 0x00 "GPIO_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET1    ,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET0    ,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
hgroup.long 0x1C++0x3
hide.long 0x00 "GPIO_CLR_DATA01,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x20++0x3
line.long 0x00 "GPIO_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN1     ,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN0     ,Status of GPIO bank 0 bits"
group.long 0x24++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS1 ,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS0 ,Writing 1 enables rising edge detection for GPIO bank 0 bits"
hgroup.long 0x28++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x2C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL1 ,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL0 ,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
hgroup.long 0x30++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x34++0x3
hide.long 0x00 "GPIO_INTSTAT01,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x38++0x3
line.long 0x00 "GPIO_DIR23,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR3    ,Direction of GPIO bank 3 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR2    ,Direction of GPIO bank 2 bits, 0h = output, 1h = input"
group.long 0x3C++0x3
line.long 0x00 "GPIO_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT3    ,Output drive state of GPIO bank 3 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT2    ,Output drive state of GPIO bank 2 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x40++0x3
line.long 0x00 "GPIO_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET3    ,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET2    ,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
hgroup.long 0x44++0x3
hide.long 0x00 "GPIO_CLR_DATA23,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x48++0x3
line.long 0x00 "GPIO_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN3     ,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN2     ,Status of GPIO bank 2 bits"
group.long 0x4C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS3 ,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS2 ,Writing 1 enables rising edge detection for GPIO bank 2 bits"
hgroup.long 0x50++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x54++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL3 ,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL2 ,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
hgroup.long 0x58++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x5C++0x3
hide.long 0x00 "GPIO_INTSTAT23,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x60++0x3
line.long 0x00 "GPIO_DIR45,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR5    ,Direction of GPIO bank 5 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR4    ,Direction of GPIO bank 4 bits, 0h = output, 1h = input"
group.long 0x64++0x3
line.long 0x00 "GPIO_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT5    ,Output drive state of GPIO bank 5 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT4    ,Output drive state of GPIO bank 4 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x68++0x3
line.long 0x00 "GPIO_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET5    ,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET4    ,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
hgroup.long 0x6C++0x3
hide.long 0x00 "GPIO_CLR_DATA45,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x70++0x3
line.long 0x00 "GPIO_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN5     ,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN4     ,Status of GPIO bank 4 bits"
group.long 0x74++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS5 ,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS4 ,Writing 1 enables rising edge detection for GPIO bank 4 bits"
hgroup.long 0x78++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x7C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL5 ,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL4 ,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
hgroup.long 0x80++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x84++0x3
hide.long 0x00 "GPIO_INTSTAT45,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x88++0x3
line.long 0x00 "GPIO_DIR67,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR7    ,Direction of GPIO bank 7 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR6    ,Direction of GPIO bank 6 bits, 0h = output, 1h = input"
group.long 0x8C++0x3
line.long 0x00 "GPIO_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT7    ,Output drive state of GPIO bank 7 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT6    ,Output drive state of GPIO bank 6 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x90++0x3
line.long 0x00 "GPIO_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET7    ,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET6    ,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
hgroup.long 0x94++0x3
hide.long 0x00 "GPIO_CLR_DATA67,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x98++0x3
line.long 0x00 "GPIO_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN7     ,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN6     ,Status of GPIO bank 6 bits"
group.long 0x9C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS7 ,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS6 ,Writing 1 enables rising edge detection for GPIO bank 6 bits"
hgroup.long 0xA0++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xA4++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL7 ,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL6 ,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
hgroup.long 0xA8++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xAC++0x3
hide.long 0x00 "GPIO_INTSTAT67,Bank Interrupt Status Register"
in
textline "                              "
group.long 0xB0++0x3
line.long 0x00 "GPIO_DIR8,Direction Register"
hexmask.long.word 0x00 0.--15. 1. " DIR8    ,Direction of GPIO bank 8 bits, 0h = output, 1h = input"
group.long 0xB4++0x3
line.long 0x00 "GPIO_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " OUT8    ,Output drive state of GPIO bank 8 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0xB8++0x3
line.long 0x00 "GPIO_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " SET8    ,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
hgroup.long 0xBC++0x3
hide.long 0x00 "GPIO_CLR_DATA8,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0xC0++0x3
line.long 0x00 "GPIO_IN_DATA8,Bank Status Register"
hexmask.long.word 0x00 0.--15. 1. " IN8     ,Status of GPIO bank 8 bits"
group.long 0xC4++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETRIS8 ,Writing 1 enables rising edge detection for GPIO bank 8 bits"
hgroup.long 0xC8++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xCC++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETFAL8 ,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
hgroup.long 0xD0++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xD4++0x3
hide.long 0x00 "GPIO_INTSTAT8,Bank Interrupt Status Register"
in
textline "                              "
width 0x0B
tree.end
tree "GPIO1"
base ad:0x601000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "GPIO_PID,GPIO Periperal ID Register Updated Reset Value of GPIO_PID[15-11] RTL Bitfield"
bitfld.long 0x00 30.--31. " SCHEME  ,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     FUNC    ,Function code assigned to TCP3"
textline "                              "
bitfld.long 0x00 11.--15. " RTL     ,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    MAJOR   ,Major revision X code" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM  ,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "     MINOR   ,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "GPIO_PCR,Peripheral Control Register"
bitfld.long 0x00 1. " SOFT    ,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x00 0. "     FREE    ,For GPIO, the FREE bit is fixed at 1, which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x00 "GPIO_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x00 0.--15. 1. " EN      ,Per bank interrupt enable 0h = disable, 1h = enable"
group.long 0x10++0x3
line.long 0x00 "GPIO_DIR01,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR1    ,Direction of GPIO bank 1 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR0    ,Direction of GPIO bank 0 bits, 0h = output, 1h = input"
group.long 0x14++0x3
line.long 0x00 "GPIO_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT1    ,Output drive state of GPIO bank 1 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT0    ,Output drive state of GPIO bank 0 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x18++0x3
line.long 0x00 "GPIO_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET1    ,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET0    ,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
hgroup.long 0x1C++0x3
hide.long 0x00 "GPIO_CLR_DATA01,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x20++0x3
line.long 0x00 "GPIO_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN1     ,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN0     ,Status of GPIO bank 0 bits"
group.long 0x24++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS1 ,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS0 ,Writing 1 enables rising edge detection for GPIO bank 0 bits"
hgroup.long 0x28++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x2C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL1 ,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL0 ,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
hgroup.long 0x30++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x34++0x3
hide.long 0x00 "GPIO_INTSTAT01,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x38++0x3
line.long 0x00 "GPIO_DIR23,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR3    ,Direction of GPIO bank 3 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR2    ,Direction of GPIO bank 2 bits, 0h = output, 1h = input"
group.long 0x3C++0x3
line.long 0x00 "GPIO_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT3    ,Output drive state of GPIO bank 3 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT2    ,Output drive state of GPIO bank 2 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x40++0x3
line.long 0x00 "GPIO_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET3    ,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET2    ,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
hgroup.long 0x44++0x3
hide.long 0x00 "GPIO_CLR_DATA23,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x48++0x3
line.long 0x00 "GPIO_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN3     ,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN2     ,Status of GPIO bank 2 bits"
group.long 0x4C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS3 ,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS2 ,Writing 1 enables rising edge detection for GPIO bank 2 bits"
hgroup.long 0x50++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x54++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL3 ,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL2 ,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
hgroup.long 0x58++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x5C++0x3
hide.long 0x00 "GPIO_INTSTAT23,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x60++0x3
line.long 0x00 "GPIO_DIR45,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR5    ,Direction of GPIO bank 5 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR4    ,Direction of GPIO bank 4 bits, 0h = output, 1h = input"
group.long 0x64++0x3
line.long 0x00 "GPIO_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT5    ,Output drive state of GPIO bank 5 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT4    ,Output drive state of GPIO bank 4 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x68++0x3
line.long 0x00 "GPIO_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET5    ,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET4    ,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
hgroup.long 0x6C++0x3
hide.long 0x00 "GPIO_CLR_DATA45,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x70++0x3
line.long 0x00 "GPIO_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN5     ,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN4     ,Status of GPIO bank 4 bits"
group.long 0x74++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS5 ,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS4 ,Writing 1 enables rising edge detection for GPIO bank 4 bits"
hgroup.long 0x78++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x7C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL5 ,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL4 ,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
hgroup.long 0x80++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x84++0x3
hide.long 0x00 "GPIO_INTSTAT45,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x88++0x3
line.long 0x00 "GPIO_DIR67,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR7    ,Direction of GPIO bank 7 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR6    ,Direction of GPIO bank 6 bits, 0h = output, 1h = input"
group.long 0x8C++0x3
line.long 0x00 "GPIO_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT7    ,Output drive state of GPIO bank 7 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT6    ,Output drive state of GPIO bank 6 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x90++0x3
line.long 0x00 "GPIO_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET7    ,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET6    ,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
hgroup.long 0x94++0x3
hide.long 0x00 "GPIO_CLR_DATA67,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x98++0x3
line.long 0x00 "GPIO_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN7     ,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN6     ,Status of GPIO bank 6 bits"
group.long 0x9C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS7 ,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS6 ,Writing 1 enables rising edge detection for GPIO bank 6 bits"
hgroup.long 0xA0++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xA4++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL7 ,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL6 ,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
hgroup.long 0xA8++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xAC++0x3
hide.long 0x00 "GPIO_INTSTAT67,Bank Interrupt Status Register"
in
textline "                              "
group.long 0xB0++0x3
line.long 0x00 "GPIO_DIR8,Direction Register"
hexmask.long.word 0x00 0.--15. 1. " DIR8    ,Direction of GPIO bank 8 bits, 0h = output, 1h = input"
group.long 0xB4++0x3
line.long 0x00 "GPIO_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " OUT8    ,Output drive state of GPIO bank 8 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0xB8++0x3
line.long 0x00 "GPIO_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " SET8    ,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
hgroup.long 0xBC++0x3
hide.long 0x00 "GPIO_CLR_DATA8,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0xC0++0x3
line.long 0x00 "GPIO_IN_DATA8,Bank Status Register"
hexmask.long.word 0x00 0.--15. 1. " IN8     ,Status of GPIO bank 8 bits"
group.long 0xC4++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETRIS8 ,Writing 1 enables rising edge detection for GPIO bank 8 bits"
hgroup.long 0xC8++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xCC++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETFAL8 ,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
hgroup.long 0xD0++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xD4++0x3
hide.long 0x00 "GPIO_INTSTAT8,Bank Interrupt Status Register"
in
textline "                              "
width 0x0B
tree.end
tree "WKUP_GPIO0"
base ad:0x42110000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "GPIO_PID,GPIO Periperal ID Register Updated Reset Value of GPIO_PID[15-11] RTL Bitfield"
bitfld.long 0x00 30.--31. " SCHEME  ,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     FUNC    ,Function code assigned to TCP3"
textline "                              "
bitfld.long 0x00 11.--15. " RTL     ,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    MAJOR   ,Major revision X code" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM  ,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "     MINOR   ,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "GPIO_PCR,Peripheral Control Register"
bitfld.long 0x00 1. " SOFT    ,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x00 0. "     FREE    ,For GPIO, the FREE bit is fixed at 1, which means GPIO runs free in emulation suspend" "0,1"
group.long 0x8++0x3
line.long 0x00 "GPIO_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x00 0.--15. 1. " EN      ,Per bank interrupt enable 0h = disable, 1h = enable"
group.long 0x10++0x3
line.long 0x00 "GPIO_DIR01,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR1    ,Direction of GPIO bank 1 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR0    ,Direction of GPIO bank 0 bits, 0h = output, 1h = input"
group.long 0x14++0x3
line.long 0x00 "GPIO_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT1    ,Output drive state of GPIO bank 1 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT0    ,Output drive state of GPIO bank 0 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x18++0x3
line.long 0x00 "GPIO_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET1    ,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET0    ,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
hgroup.long 0x1C++0x3
hide.long 0x00 "GPIO_CLR_DATA01,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x20++0x3
line.long 0x00 "GPIO_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN1     ,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN0     ,Status of GPIO bank 0 bits"
group.long 0x24++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS1 ,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS0 ,Writing 1 enables rising edge detection for GPIO bank 0 bits"
hgroup.long 0x28++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x2C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL1 ,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL0 ,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
hgroup.long 0x30++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x34++0x3
hide.long 0x00 "GPIO_INTSTAT01,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x38++0x3
line.long 0x00 "GPIO_DIR23,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR3    ,Direction of GPIO bank 3 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR2    ,Direction of GPIO bank 2 bits, 0h = output, 1h = input"
group.long 0x3C++0x3
line.long 0x00 "GPIO_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT3    ,Output drive state of GPIO bank 3 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT2    ,Output drive state of GPIO bank 2 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x40++0x3
line.long 0x00 "GPIO_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET3    ,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET2    ,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
hgroup.long 0x44++0x3
hide.long 0x00 "GPIO_CLR_DATA23,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x48++0x3
line.long 0x00 "GPIO_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN3     ,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN2     ,Status of GPIO bank 2 bits"
group.long 0x4C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS3 ,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS2 ,Writing 1 enables rising edge detection for GPIO bank 2 bits"
hgroup.long 0x50++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x54++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL3 ,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL2 ,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
hgroup.long 0x58++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x5C++0x3
hide.long 0x00 "GPIO_INTSTAT23,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x60++0x3
line.long 0x00 "GPIO_DIR45,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR5    ,Direction of GPIO bank 5 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR4    ,Direction of GPIO bank 4 bits, 0h = output, 1h = input"
group.long 0x64++0x3
line.long 0x00 "GPIO_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT5    ,Output drive state of GPIO bank 5 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT4    ,Output drive state of GPIO bank 4 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x68++0x3
line.long 0x00 "GPIO_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET5    ,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET4    ,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
hgroup.long 0x6C++0x3
hide.long 0x00 "GPIO_CLR_DATA45,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x70++0x3
line.long 0x00 "GPIO_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN5     ,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN4     ,Status of GPIO bank 4 bits"
group.long 0x74++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS5 ,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS4 ,Writing 1 enables rising edge detection for GPIO bank 4 bits"
hgroup.long 0x78++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0x7C++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL5 ,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL4 ,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
hgroup.long 0x80++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0x84++0x3
hide.long 0x00 "GPIO_INTSTAT45,Bank Interrupt Status Register"
in
textline "                              "
group.long 0x88++0x3
line.long 0x00 "GPIO_DIR67,Direction Register"
hexmask.long.word 0x00 16.--31. 1. " DIR7    ,Direction of GPIO bank 7 bits, 0h = output, 1h = input"
hexmask.long.word 0x00 0.--15. 1. "  DIR6    ,Direction of GPIO bank 6 bits, 0h = output, 1h = input"
group.long 0x8C++0x3
line.long 0x00 "GPIO_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " OUT7    ,Output drive state of GPIO bank 7 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  OUT6    ,Output drive state of GPIO bank 6 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0x90++0x3
line.long 0x00 "GPIO_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. " SET7    ,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "  SET6    ,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
hgroup.long 0x94++0x3
hide.long 0x00 "GPIO_CLR_DATA67,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0x98++0x3
line.long 0x00 "GPIO_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. " IN7     ,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  IN6     ,Status of GPIO bank 6 bits"
group.long 0x9C++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETRIS7 ,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETRIS6 ,Writing 1 enables rising edge detection for GPIO bank 6 bits"
hgroup.long 0xA0++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xA4++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x00 16.--31. 1. " SETFAL7 ,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "  SETFAL6 ,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
hgroup.long 0xA8++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xAC++0x3
hide.long 0x00 "GPIO_INTSTAT67,Bank Interrupt Status Register"
in
textline "                              "
group.long 0xB0++0x3
line.long 0x00 "GPIO_DIR8,Direction Register"
hexmask.long.word 0x00 0.--15. 1. " DIR8    ,Direction of GPIO bank 8 bits, 0h = output, 1h = input"
group.long 0xB4++0x3
line.long 0x00 "GPIO_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " OUT8    ,Output drive state of GPIO bank 8 bits, does not affect operation when it is configured as input Reading it returns the output drive state"
group.long 0xB8++0x3
line.long 0x00 "GPIO_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x00 0.--15. 1. " SET8    ,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
hgroup.long 0xBC++0x3
hide.long 0x00 "GPIO_CLR_DATA8,Clear Output Drive State Register"
in
textline "                              "
rgroup.long 0xC0++0x3
line.long 0x00 "GPIO_IN_DATA8,Bank Status Register"
hexmask.long.word 0x00 0.--15. 1. " IN8     ,Status of GPIO bank 8 bits"
group.long 0xC4++0x3
line.long 0x00 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETRIS8 ,Writing 1 enables rising edge detection for GPIO bank 8 bits"
hgroup.long 0xC8++0x3
hide.long 0x00 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
in
textline "                              "
group.long 0xCC++0x3
line.long 0x00 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x00 0.--15. 1. " SETFAL8 ,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
hgroup.long 0xD0++0x3
hide.long 0x00 "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
in
textline "                              "
hgroup.long 0xD4++0x3
hide.long 0x00 "GPIO_INTSTAT8,Bank Interrupt Status Register"
in
textline "                              "
width 0x0B
tree.end
tree.end
tree "GPMC"
tree "GPMC0_CFG"
base ad:0x5390000
width 23.
rgroup.long 0x0++0x3
line.long 0x00 "GPMC_REVISION,This register contains the IP revision code."
hexmask.long 0x00 0.--31. 1. " REVISION                 ,TI internal data. Identifies revision of peripheral."
group.long 0x10++0x3
line.long 0x00 "GPMC_SYSCONFIG,Register related to module software reset and local power management."
bitfld.long 0x00 3.--4. " IDLEMODE                 ,0h = Force-idle. A clock stop request is acknowledged unconditionally. 1h (R/W) = No-idle. A clock stop request is never acknowledged. 2h (R/W) = Smart-idle. Acknowledgment to a clock stop request is given based on the internal activity of the module. 3h (R/W) = Reserved. Do not use." "ForceIdle,NoIdle,SmartIdle,Reserved"
bitfld.long 0x00 1. "              SOFTRESET                ,Software reset. 0h (R/W) = Normal mode 1h (R/W) = The module is reset." "Normal,Reset"
textline "                                "
bitfld.long 0x00 0. " AUTOIDLE                 ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic Interface clock gating strategy is applied, based on the interconnect activity." "FreeRun,AutoRun"
rgroup.long 0x14++0x3
line.long 0x00 "GPMC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE                ,Internal reset monitoring 0h (R) = Internal module reset is ongoing. 1h (R) = Reset is complete." "RstOnGoing,RstDone"
group.long 0x18++0x3
line.long 0x00 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt."
bitfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt Write: 0h = WAIT1EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT1EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT1 input pin has not been detected. 1h = A transition on WAIT1 input pin has been detected." "W1Det0_R_/_W1Det0_W,W1Det1_R_/_W1Det1_W"
bitfld.long 0x00 8. "    WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt Write: 0h = WAIT0EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT0EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT0 input pin has not been detected. 1h = A transition on WAIT0 input pin has been detected." "W0Det0_R_/_W0Det0_W,W0Det1_R_/_W0Det1_W"
textline "                                "
bitfld.long 0x00 1. " TERMINALCOUNTSTATUS      ,Status of the TerminalCountEvent interrupt Write: 0h = TERMINALCOUNTSTATUS bit is unchanged. 1h = TERMINALCOUNTSTATUS bit is reset. Read: 0h = Indicates that CountValue is greater than 0. 1h = Indicates that CountValue is equal to 0." "TCStat0_R_/_TCStat0_W,TCStat1_R_/_TCStat1_W"
bitfld.long 0x00 0. "  FIFOEVENTSTATUS          ,Status of the FIFOEvent interrupt Write: 0h = FIFOEVENTSTATUS bit is unchanged. 1h = FIFOEVENTSTATUS bit is reset. Read: 0h = Indicates that less than 1h = Indicates that at least" "FIFOStat0_R_/_FIFOStat0_W,FIFOStat1_R_/_FIFOStat1_W"
group.long 0x1C++0x3
line.long 0x00 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis."
bitfld.long 0x00 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt 0h (R/W) = Wait1EdgeDetection interrupt is masked. 1h (R/W) = Wait1EdgeDetection event generates an interrupt if occurs." "W1Masked,W1Enabled"
bitfld.long 0x00 8. "              WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt 0h (R/W) = Wait0EdgeDetection interrupt is masked. 1h (R/W) = Wait0EdgeDetection event generates an interrupt if occurs." "W0Masked,W0Enabled"
textline "                                "
bitfld.long 0x00 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode 0h (R/W) = TerminalCountEvent interrupt is masked. 1h (R/W) = TerminalCountEvent interrupt is not masked." "TCMasked,TCEnabled"
bitfld.long 0x00 0. "              FIFOEVENTENABLE          ,Enables the FIFOEvent interrupt 0h (R/W) = FIFOEvent interrupt is masked. 1h (R/W) = FIFOEvent interrupt is not masked." "FIFOMasked,FIFOEnabled"
group.long 0x40++0x3
line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter."
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE        ,Start value of the time-out counter"
bitfld.long 0x00 0. "                   TIMEOUTENABLE            ,Enable bit of the TimeOut feature 0h (R/W) = TimeOut feature is disabled. 1h (R/W) = TimeOut feature is enabled." "TODisabled,TOEnabled"
rgroup.long 0x44++0x3
line.long 0x00 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs."
hexmask.long 0x00 0.--30. 1. " ILLEGALADD               ,Address of illegal access"
hgroup.long 0x48++0x3
hide.long 0x00 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs."
in
textline "                                "
group.long 0x50++0x3
line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC."
bitfld.long 0x00 9. " WAIT1PINPOLARITY         ,Selects the polarity of input pin WAIT1 0h (R/W) = WAIT1 active low 1h (R/W) = WAIT1 active high" "W1ActiveL,W1ActiveH"
bitfld.long 0x00 8. "              WAIT0PINPOLARITY         ,Selects the polarity of input pin WAIT0 0h (R/W) = WAIT0 active low 1h (R/W) = WAIT0 active high" "W0ActiveL,W0ActiveH"
textline "                                "
bitfld.long 0x00 4. " WRITEPROTECT             ,Controls the WP output pin level 0h (R/W) = nWP output pin is low 1h (R/W) = nWP output pin is high" "WPLow,WPHigh"
bitfld.long 0x00 0. "                 NANDFORCEPOSTEDWRITE     ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location 0h (R/W) = Disables Force Posted Write 1h (R/W) = Enables Force Posted Write" "NoForcePWr,ForcePWr"
rgroup.long 0x54++0x3
line.long 0x00 "GPMC_STATUS,The status register provides global status bits of the GPMC."
bitfld.long 0x00 9. " WAIT1STATUS              ,Is a copy of input pin WAIT1. (Reset value is WAIT1 input pin sampled at device reset.) 0h (R) = WAIT1 asserted (inactive state) 1h (R) = WAIT1 deasserted" "W1ActiveL,W1ActiveH"
bitfld.long 0x00 8. "              WAIT0STATUS              ,Is a copy of input pin WAIT0. (Reset value is WAIT0 input pin sampled at device reset.) 0h (R) = WAIT0 asserted (inactive state) 1h (R) = WAIT0 deasserted" "W0ActiveL,W0ActiveH"
textline "                                "
bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS   ,Stores the empty status of the write buffer 0h (R) = Write buffer is not empty. 1h (R) = Write buffer is empty." "b0,b1"
group.long 0x60++0x3
line.long 0x00 "GPMC_CONFIG1_i,The configuration register 1 sets signal control parameters per chip-select. Offset = 60h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 31. " WRAPBURST                ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst 0h (R/W) = Synchronous wrapping burst not supported 1h (R/W) = Synchronous wrapping burst supported" "0,1"
bitfld.long 0x00 30. "                      READMULTIPLE             ,Selects the read single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous, page if asynchronous)" "0,1"
textline "                                "
bitfld.long 0x00 29. " READTYPE                 ,Selects the read mode operation 0h (R/W) = Read asynchronous 1h (R/W) = Read synchronous" "0,1"
bitfld.long 0x00 28. "                      WRITEMULTIPLE            ,Selects the write single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous, considered as single if asynchronous)" "0,1"
textline "                                "
bitfld.long 0x00 27. " WRITETYPE                ,Selects the write mode operation 0h (R/W) = Write asynchronous 1h (R/W) = Write synchronous" "0,1"
bitfld.long 0x00 25.--26. "                      CLKACTIVATIONTIME        ,Output GPMC_CLK activation time 0h (R/W) = First rising edge of GPMC_CLK at start access time 1h (R/W) = First rising edge of GPMC_CLK one GPMC_FICLK cycle after start access time 2h (R/W) = First rising edge of GPMC_CLK two GPMC_FICLK cycles after start access time 3h (R/W) = Reserved" "0,1,2,3"
textline "                                "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length 0h (R/W) = 4 words 1h (R/W) = 8 words 2h (R/W) = 16 words 3h (R/W) = Reserved (1 word = interface size)" "0,1,2,3"
bitfld.long 0x00 22. "                      WAITREADMONITORING       ,Selects the Wait monitoring configuration for Read accesses 0h (R/W) = WAIT pin is not monitored for read accesses. 1h (R/W) = WAIT pin is monitored for read accesses." "0,1"
textline "                                "
bitfld.long 0x00 21. " WAITWRITEMONITORING      ,Selects the Wait monitoring configuration for Write accesses 0h (R/W) = WAIT pin is not monitored for write accesses. 1h (R/W) = WAIT pin is monitored for write accesses." "0,1"
bitfld.long 0x00 18.--19. "                      WAITMONITORINGTIME       ,Selects input pin Wait monitoring time 0h (R/W) = WAIT pin is monitored with valid data. 1h (R/W) = WAIT pin is monitored one GPMC_CLK cycle before valid data. 2h (R/W) = WAIT pin is monitored two GPMC_CLK cycle before valid data. 3h (R/W) = Reserved" "0,1,2,3"
textline "                                "
bitfld.long 0x00 16.--17. " WAITPINSELECT            ,Selects the input WAIT pin for this chip-select 0h (R/W) = Wait input pin is WAIT0. 1h (R/W) = Wait input pin is WAIT1. 2h, 3h = Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "                      DEVICESIZE               ,Selects the device size attached 0h (R/W) = 8 bit 1h (R/W) = 16 bit 2h (R/W) = Reserved 3h (R/W) = Reserved" "0,1,2,3"
textline "                                "
bitfld.long 0x00 10.--11. " DEVICETYPE               ,Selects the attached device type 0h (R/W) = NOR flash-like, asynchronous and synchronous devices 1h (R/W) = Reserved 2h (R/W) = NAND flash-like devices, stream mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 8.--9. "                      MUXADDDATA               ,Enables the address and data multiplexed protocol 0h (R/W) = Nonmultiplexed attached device 1h (R/W) = AAD-multiplexed protocol device 2h (R/W) = Address and data multiplexed attached device 3h (R/W) = Reserved" "0,1,2,3"
textline "                                "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY      ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) 0h (R/W) = x1 latencies 1h (R/W) = x2 latencies" "0,1"
bitfld.long 0x00 0.--1. "                      GPMCFCLKDIVIDER          ,Divides the GPMC_FICLK clock 0h (R/W) = GPMC_CLK frequency = GPMC_FICLK frequency 1h (R/W) = GPMC_CLK frequency = GPMC_FICLK frequency / 2 2h (R/W) = GPMC_CLK frequency = GPMC_FICLK frequency / 3 3h (R/W) = GPMC_CLK frequency = GPMC_FICLK frequency /4" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "GPMC_CONFIG2_i,CS signal timing parameter configuration Offset = 64h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 16.--20. " CSWROFFTIME              ,CS i deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "                     CSRDOFFTIME              ,CS i de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 7. " CSEXTRADELAY             ,CS i Add extra half-GPMC_FICLK cycle 0h (R/W) = CS i Timing control signal is not delayed 1h (R/W) = CS i Timing control signal is delayed of half GPMC_FICLK clock cycle" "0,1"
bitfld.long 0x00 0.--3. "                      CSONTIME                 ,CS i assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x68++0x3
line.long 0x00 "GPMC_CONFIG3_i,nADV signal timing parameter configuration Offset = 68h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME       ,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "                      ADVAADMUXRDOFFTIME       ,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 16.--20. " ADVWROFFTIME             ,nADV deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "                     ADVRDOFFTIME             ,nADV deassertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 7. " ADVEXTRADELAY            ,nADV add extra half-GPMC_FICLK cycle 0h (R/W) = nADV timing control signal is not delayed 1h (R/W) = nADV timing control signal is delayed of half GPMC_FICLK clock cycle" "0,1"
bitfld.long 0x00 4.--6. "                      ADVAADMUXONTIME          ,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--3. " ADVONTIME                ,nADV assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6C++0x3
line.long 0x00 "GPMC_CONFIG4_i,nWE and nOE signals timing parameter configuration Offset = 6Ch + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 24.--28. " WEOFFTIME                ,nWE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "                     WEEXTRADELAY             ,nWE add extra half-GPMC_FICLK cycle 0h (R/W) = nWE timing control signal is not delayed 1h (R/W) = nWE timing control signal is delayed of half-GPMC_FICLK clock cycle" "0,1"
textline "                                "
bitfld.long 0x00 16.--19. " WEONTIME                 ,nWE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13.--15. "                     OEAADMUX_OFFTIME         ,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 8.--12. " OEOFFTIME                ,nOE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "                     OEEXTRADELAY             ,nOE add extra half-GPMC_FICLK cycle 0h (R/W) = nOE timing control signal is not delayed 1h (R/W) = nOE timing control signal is delayed of half-GPMC_FICLK clock cycle" "0,1"
textline "                                "
bitfld.long 0x00 4.--6. " OEAADMUX_ONTIME          ,nOE assertion time for the first address phase in an AAD-mux access" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "                      OEONTIME                 ,nOE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x3
line.long 0x00 "GPMC_CONFIG5_i,RdAccessTime and CycleTime timing parameters configuration Offset = 70h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME      ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "                     RDACCESSTIME             ,Delay between start cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 8.--12. " WRCYCLETIME              ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "                     RDCYCLETIME              ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x74++0x3
line.long 0x00 "GPMC_CONFIG6_i,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration Offset = 74h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 24.--28. " WRACCESSTIME             ,Delay from start access time to the GPMC_FICLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--19. "                     WRDATAONADMUXBUS         ,Specifies on which GPMC_FICLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY         ,Chip-select high pulse delay between successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "                     CYCLE2CYCLESAMECSEN      ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1"
textline "                                "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN      ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1"
bitfld.long 0x00 0.--3. "                      BUSTURNAROUND            ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x78++0x3
line.long 0x00 "GPMC_CONFIG7_i,CS address mapping configuration Offset = 78h + (i * 30h), where: i = 0 to 3"
bitfld.long 0x00 8.--11. " MASKADDRESS              ,CS mask address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "                     CSVALID                  ,CS enable 0h (R/W) = CS disabled 1h (R/W) = CS enabled" "0,1"
textline "                                "
bitfld.long 0x00 0.--5. " BASEADDRESS              ,CSi base address where i = 0 to 3 (16-MB minimum granularity) bits [5-0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
wgroup.long 0x7C++0x3
line.long 0x00 "GPMC_NAND_COMMAND_i,This register is not a true register, only an address location. Offset = 7Ch + (i * 30h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " GPMC_NAND_COMMAND        ,This register is not a true register, only an address location. Writing data at the"
wgroup.long 0x80++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_i,This register is not a true register, only an address location. Offset = 80h + (i * 30h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " GPMC_NAND_ADDRESS        ,This register is not a true register, only an address location. Writing data at the"
group.long 0x84++0x3
line.long 0x00 "GPMC_NAND_DATA_i,This register is not a true register, only an address location. Offset = 84h + (i * 30h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " GPMC_NAND_DATA           ,This register is not a true register, only an address location. Reading data from the"
group.long 0x1E0++0x3
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1 Some of the GPMC features described in this section may not be supported on this family of devices. For more information, see , GPMC Not Supported Features."
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION        ,Define the number of GPMC_FICLK cycles to be subtracted from RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, CSRDOFFTIME, CSWROFFTIME, ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, WEOFFTIME" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 27. "                      ENABLEOPTIMIZEDACCESS    ,Enables access cycle optimization 0h (R/W) = Access cycle optimization is disabled. 1h (R/W) = Access cycle optimization is enabled." "OptDisabled,OptEnabled"
textline "                                "
bitfld.long 0x00 24.--26. " ENGINECSSELECTOR         ,Selects the chip-select where Prefetch Postwrite engine is active" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23. "                      PFPWENROUNDROBIN         ,Enables the PFPW RoundRobin arbitration 0h (R/W) = Prefetch Postwrite engine round robin arbitration is disabled. 1h (R/W) = Prefetch Postwrite engine round robin arbitration is enabled." "RRDisabled,RREnabled"
textline "                                "
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO         ,When an arbitration occurs between a DMA and a PFPW engine access, the DMA is always serviced. If the PFPWEnRoundRobin is enabled," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--14. 1. "                     FIFOTHRESHOLD            ,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request"
textline "                                "
bitfld.long 0x00 7. " ENABLEENGINE             ,Enables the Prefetch Postwite engine 0h (R/W) = Prefetch Postwrite engine is disabled. 1h (R/W) = Prefetch Postwrite engine is enabled." "PPDisabled,PPEnabled"
bitfld.long 0x00 4.--5. "             WAITPINSELECTOR          ,Select which wait pin edge detector should start the engine in synchronized mode 0h (R/W) = Selects Wait0 EdgeDetection 1h (R/W) = Selects Wait1 EdgeDetection 2h, 3h = Reserved" "W0,W1,W2,W3"
textline "                                "
bitfld.long 0x00 3. " SYNCHROMODE              ,Selects when the engine starts the access to chip-select 0h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set 1h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set AND wait to nonwait edge detection on the selected wait pin" "AtStart,AtStartAndWait"
bitfld.long 0x00 2. "         DMAMODE                  ,Selects interrupt synchronization or DMA request synchronization 0h (R/W) = Interrupt synchronization is enabled. Only interrupt line is activated on FIFO threshold crossing. 1h (R/W) = DMA request synchronization is enabled. A DMA request protocol is used." "InterruptSync,DMAReqSync"
textline "                                "
bitfld.long 0x00 0. " ACCESSMODE               ,Selects prefetch read or write-posting accesses 0h (R/W) = Prefetch read mode 1h (R/W) = Write-posting mode" "PrefetchRead,WritePosting"
group.long 0x1E4++0x3
line.long 0x00 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2"
hexmask.long.word 0x00 0.--13. 1. " TRANSFERCOUNT            ,Selects the number of bytes to be read or written by the engine to the selected chip-select"
group.long 0x1EC++0x3
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control"
bitfld.long 0x00 0. " STARTENGINE              ,Resets the FIFO pointer and starts the engine Write: 0h = Stops the engine. 1h = Resets the FIFO pointer to 0h in prefetch mode and 40h in postwrite mode and starts the engine. Read: 0h = Engine is stopped. 1h = Engine is running." "Stop,Start"
rgroup.long 0x1F0++0x3
line.long 0x00 "GPMC_PREFETCH_STATUS,Prefetch engine status"
hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER              ,Number of available bytes to be read or number of free empty byte places to be written"
bitfld.long 0x00 16. "                     FIFOTHRESHOLDSTATUS      ,Set when FIFOPointer exceeds FIFOThreshold value 0h (R) = FIFOPointer smaller or equal to FIFOThreshold. Writing to this bit has no effect. 1h (R) = FIFOPointer greater than FIFOThreshold. Writing to this bit has no effect." "SmallerThanThres,GreaterThanThres"
textline "                                "
hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE               ,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value"
group.long 0x1F4++0x3
line.long 0x00 "GPMC_ECC_CONFIG,ECC configuration"
bitfld.long 0x00 16. " ECCALGORITHM             ,ECC algorithm used 0h (R/W) = Hamming code 1h (R/W) = BCH code" "0,1"
bitfld.long 0x00 12.--13. "                      ECCBCHTSEL               ,Error correction capability used for BCH 0h (R/W) = Up to 4 bits error correction (t = 4) 1h (R/W) = Up to 8 bits error correction (t = 8) 2h (R/W) = Up to 16 bits error correction (t = 16) 3h (R/W) = Reserved" "0,1,2,3"
textline "                                "
bitfld.long 0x00 8.--11. " ECCWRAPMODE              ,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "                     ECC16B                   ,Selects an ECC calculated on 16 columns 0h (R/W) = ECC calculated on 8 columns 1h (R/W) = ECC calculated on 16 columns" "EightCol,SixteenCol"
textline "                                "
bitfld.long 0x00 4.--6. " ECCTOPSECTOR             ,Number of sectors to process with the BCH algorithm 1h = 2 sectors" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1.--3. "                      ECCCS                    ,Selects the CS where ECC is computed 0h (R/W) = CS0 1h (R/W) = CS1 2h (R/W) = CS2 3h (R/W) = CS3 Other: Reserved" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
textline "                                "
bitfld.long 0x00 0. " ECCENABLE                ,Enables the ECC feature 0h (R/W) = ECC disabled 1h (R/W) = ECC enabled" "ECCDisabled,ECCEnabled"
group.long 0x1F8++0x3
line.long 0x00 "GPMC_ECC_CONTROL,ECC control"
bitfld.long 0x00 8. " ECCCLEAR                 ,Clear all ECC result registers" "0,1"
bitfld.long 0x00 0.--3. "                      ECCPOINTER               ,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Writing other values disables the ECC engine (ECCENABLE bit of 0h (R/W) = Writing 0h disables the ECC engine (ECCENABLE bit of 1h (R/W) = ECC result register 1 selected 2h (R/W) = ECC result register 2 selected 3h (R/W) = ECC result register 3 selected 4h (R/W) = ECC result register 4 selected 5h (R/W) = ECC result register 5 selected 6h (R/W) = ECC result register 6 selected 7h (R/W) = ECC result register 7 selected 8h (R/W) = ECC result register 8 selected 9h (R/W) = ECC result register 9 selected" "NoEffect1,ECCRes1,ECCRes2,ECCRes3,ECCRes4,ECCRes5,ECCRes6,ECCRes7,ECCRes8,ECCRes9,10,11,12,13,14,15"
group.long 0x1FC++0x3
line.long 0x00 "GPMC_ECC_SIZE_CONFIG,ECC size"
hexmask.long.byte 0x00 22.--29. 1. " ECCSIZE1                 ,Defines Hamming code ECC size 1 in bytes"
hexmask.long.byte 0x00 12.--19. 1. "                     ECCSIZE0                 ,Defines Hamming code ECC size 0 in bytes"
textline "                                "
bitfld.long 0x00 8. " ECC9RESULTSIZE           ,Selects ECC size for ECC 9 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
bitfld.long 0x00 7. "               ECC8RESULTSIZE           ,Selects ECC size for ECC 8 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
textline "                                "
bitfld.long 0x00 6. " ECC7RESULTSIZE           ,Selects ECC size for ECC 7 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
bitfld.long 0x00 5. "               ECC6RESULTSIZE           ,Selects ECC size for ECC 6 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
textline "                                "
bitfld.long 0x00 4. " ECC5RESULTSIZE           ,Selects ECC size for ECC 5 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
bitfld.long 0x00 3. "               ECC4RESULTSIZE           ,Selects ECC size for ECC 4 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
textline "                                "
bitfld.long 0x00 2. " ECC3RESULTSIZE           ,Selects ECC size for ECC 3 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
bitfld.long 0x00 1. "               ECC2RESULTSIZE           ,Selects ECC size for ECC 2 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
textline "                                "
bitfld.long 0x00 0. " ECC1RESULTSIZE           ,Selects ECC size for ECC 1 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "Size0Sel,Size1Sel"
rgroup.long 0x200++0x3
line.long 0x00 "GPMC_ECCj_RESULT,ECC result register Offset = 200h + (j * 4h), where: j = 0 to 8"
bitfld.long 0x00 27. " P2048O                   ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1"
bitfld.long 0x00 26. "                      P1024O                   ,Odd row parity bit 1024" "0,1"
textline "                                "
bitfld.long 0x00 25. " P512O                    ,Odd row parity bit 512" "0,1"
bitfld.long 0x00 24. "                      P256O                    ,Odd row parity bit 256" "0,1"
textline "                                "
bitfld.long 0x00 23. " P128O                    ,Odd row parity bit 128" "0,1"
bitfld.long 0x00 22. "                      P64O                     ,Odd row parity bit 64" "0,1"
textline "                                "
bitfld.long 0x00 21. " P32O                     ,Odd row parity bit 32" "0,1"
bitfld.long 0x00 20. "                      P16O                     ,Odd row parity bit 16" "0,1"
textline "                                "
bitfld.long 0x00 19. " P8O                      ,Odd row parity bit 8" "0,1"
bitfld.long 0x00 18. "                      P4O                      ,Odd Column Parity bit 4" "0,1"
textline "                                "
bitfld.long 0x00 17. " P2O                      ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x00 16. "                      P1O                      ,Odd Column Parity bit 1" "0,1"
textline "                                "
bitfld.long 0x00 11. " P2048E                   ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1"
bitfld.long 0x00 10. "                      P1024E                   ,Even row parity bit 1024" "0,1"
textline "                                "
bitfld.long 0x00 9. " P512E                    ,Even row parity bit 512" "0,1"
bitfld.long 0x00 8. "                      P256E                    ,Even row parity bit 256" "0,1"
textline "                                "
bitfld.long 0x00 7. " P128E                    ,Even row parity bit 128" "0,1"
bitfld.long 0x00 6. "                      P64E                     ,Even row parity bit 64" "0,1"
textline "                                "
bitfld.long 0x00 5. " P32E                     ,Even row parity bit 32" "0,1"
bitfld.long 0x00 4. "                      P16E                     ,Even row parity bit 16" "0,1"
textline "                                "
bitfld.long 0x00 3. " P8E                      ,Even row parity bit 8" "0,1"
bitfld.long 0x00 2. "                      P4E                      ,Even column parity bit 4" "0,1"
textline "                                "
bitfld.long 0x00 1. " P2E                      ,Even column parity bit 2" "0,1"
bitfld.long 0x00 0. "                      P1E                      ,Even column parity bit 1" "0,1"
rgroup.long 0x240++0x3
line.long 0x00 "GPMC_BCH_RESULT0_i,BCH ECC result (bits 0 to 31) Offset = 240h + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_0             ,BCH ECC result (bits 0 to 31)"
rgroup.long 0x244++0x3
line.long 0x00 "GPMC_BCH_RESULT1_i,BCH ECC result (bits 32 to 63) Offset = 244h + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_1             ,BCH ECC result (bits 32 to 63)"
rgroup.long 0x248++0x3
line.long 0x00 "GPMC_BCH_RESULT2_i,BCH ECC result (bits 64 to 95) Offset = 248h + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_2             ,BCH ECC result (bits 64 to 95)"
rgroup.long 0x24C++0x3
line.long 0x00 "GPMC_BCH_RESULT3_i,BCH ECC result (bits 96 to 127) Offset = 24Ch + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_3             ,BCH ECC result (bits 96 to 127)"
wgroup.long 0x2D0++0x3
line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface."
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA                 ,Data to be included in the BCH calculation"
rgroup.long 0x300++0x3
line.long 0x00 "GPMC_BCH_RESULT4_i,BCH ECC result (bits 128 to 159) Offset = 300h + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_4             ,BCH ECC result (bits 128 to 159)"
rgroup.long 0x304++0x3
line.long 0x00 "GPMC_BCH_RESULT5_i,BCH ECC result (bits 160 to 191) Offset = 304h + (i * 10h), where: i = 0 to 3"
hexmask.long 0x00 0.--31. 1. " BCH_RESULT_5             ,BCH ECC result (bits 160 to 191)"
rgroup.long 0x308++0x3
line.long 0x00 "GPMC_BCH_RESULT6_i,BCH ECC result (bits 192 to 207) Offset = 308h + (i * 10h), where: i = 0 to 3"
hexmask.long.word 0x00 0.--15. 1. " BCH_RESULT_6             ,BCH ECC result (bits 192 to 207)"
width 0x0B
tree.end
tree.end
tree "GPU"
tree "GPU0_KLIOMP1_HL_MMRS"
base ad:0x700FE00
width 21.
group.long 0x0++0x3
line.long 0x00 "GPU_REVISION,See IPG spec for more details."
rgroup.long 0x4++0x3
line.long 0x00 "GPU_HWINFO,"
bitfld.long 0x00 2. " MEM_BUS_WIDTH                ,Memory bus width Read 0h = 64 bits Read 1h = 128 bits" "0,1"
bitfld.long 0x00 0.--1. "   SYS_BUS_WIDTH               ,System bus width" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "GPU_SYSCONFIG,"
bitfld.long 0x00 4.--5. " STANDBY_MODE                 ,Clock standby mode:" "0,1,2,3"
bitfld.long 0x00 2.--3. "   IDLE_MODE                   ,Clock idle mode:" "0,1,2,3"
group.long 0x24++0x3
line.long 0x00 "GPU_IRQSTATUS_RAW_0,"
bitfld.long 0x00 0. " INIT_MINTERRUPT_RAW          ,Interrupt 0 raw event:" "0,1"
group.long 0x28++0x3
line.long 0x00 "GPU_IRQSTATUS_RAW_1,"
bitfld.long 0x00 0. " TARGET_SINTERRUPT_RAW        ,Interrupt 1 raw event:" "0,1"
group.long 0x2C++0x3
line.long 0x00 "GPU_IRQSTATUS_RAW_2,"
bitfld.long 0x00 0. " THALIA_IRQ_RAW               ,Interrupt 1 raw event:" "0,1"
group.long 0x30++0x3
line.long 0x00 "GPU_IRQSTATUS_0,"
bitfld.long 0x00 0. " INIT_MINTERRUPT_STATUS       ,Interrupt 0 raw event:" "0,1"
group.long 0x34++0x3
line.long 0x00 "GPU_IRQSTATUS_1,"
bitfld.long 0x00 0. " TARGET_SINTERRUPT_STATUS     ,Interrupt 0 raw event:" "0,1"
group.long 0x38++0x3
line.long 0x00 "GPU_IRQSTATUS_2,"
bitfld.long 0x00 0. " THALIA_IRQ_STATUS            ,Interrupt 0 raw event:" "0,1"
group.long 0x3C++0x3
line.long 0x00 "GPU_IRQENABLE_SET_0,"
bitfld.long 0x00 0. " INIT_MINTERRUPT_ENABLE       ,To enable interrupt:" "0,1"
group.long 0x40++0x3
line.long 0x00 "GPU_IRQENABLE_SET_1,"
bitfld.long 0x00 0. " TARGET_SINTERRUPT_ENABLE     ,To enable interrupt:" "0,1"
group.long 0x44++0x3
line.long 0x00 "GPU_IRQENABLE_SET_2,"
bitfld.long 0x00 0. " THALIA_IRQ_ENABLE            ,To enable interrupt:" "0,1"
group.long 0x48++0x3
line.long 0x00 "GPU_IRQENABLE_CLR_0,"
bitfld.long 0x00 0. " INIT_MINTERRUPT_DISABLE      ,To disable interrupt:" "0,1"
group.long 0x4C++0x3
line.long 0x00 "GPU_IRQENABLE_CLR_1,"
bitfld.long 0x00 0. " TARGET_SINTERRUPT_DISABLE    ,To disable interrupt:" "0,1"
group.long 0x50++0x3
line.long 0x00 "GPU_IRQENABLE_CLR_2,"
bitfld.long 0x00 0. " THALIA_IRQ_DISABLE           ,To disable interrupt:" "0,1"
group.long 0x100++0x3
line.long 0x00 "GPU_PAGE_CONFIG,"
bitfld.long 0x00 31. " THALIA_INT_BYPASS            ,Bypass OCP IPG interrupt logic" "0,1"
bitfld.long 0x00 3.--4. "   OCP_PAGE_SIZE               ,Defines the page size on OCP memory interface:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 2. " MEM_PAGE_CHECK_EN            ,To enable page boundary checking:" "0,1"
bitfld.long 0x00 0.--1. "   MEM_PAGE_SIZE               ,Defines the page size on internal memory interface:" "0,1,2,3"
group.long 0x104++0x3
line.long 0x00 "GPU_INTERRUPT_EVENT,"
bitfld.long 0x00 18. " TARGET_INVALID_OCP_CMD       ,Invalid command from OCP:" "0,1"
bitfld.long 0x00 17. "   TARGET_CMD_FIFO_FULL        ,Command FIFO full:" "0,1"
textline "                              "
bitfld.long 0x00 16. " TARGET_RESP_FIFO_FULL        ,Response FIFO full:" "0,1"
bitfld.long 0x00 13. "   INT_MEM_REQ_FIFO_OVERRUN_1  ,Memory request FIFO overrun:" "0,1"
textline "                              "
bitfld.long 0x00 12. " INIT_READ_TAG_FIFO_OVERRUN_1 ,Read tag FIFO overrun:" "0,1"
bitfld.long 0x00 11. "   INIT_PAGE_CROSS_ERROR_1     ,Memory page had been crossed during a burst:" "0,1"
textline "                              "
bitfld.long 0x00 10. " INIT_RESP_ERROR_1            ,Receiving error response:" "0,1"
bitfld.long 0x00 9. "   INIT_RESP_UNUSED_TAG_1      ,Receiving response on an unused OCP TAG:" "0,1"
textline "                              "
bitfld.long 0x00 8. " INIT_RESP_UNEXPECTED_1       ,Receiving response when not expected:" "0,1"
bitfld.long 0x00 5. "   INIT_MEM_REQ_FIFO_OVERRUN_0 ,Memory request FIFO overrun:" "0,1"
textline "                              "
bitfld.long 0x00 4. " INIT_READ_TAG_FIFO_OVERRUN_0 ,Read tag FIFO overrun:" "0,1"
bitfld.long 0x00 3. "   INIT_PAGE_CROSS_ERROR_0     ,Memory page had been crossed during a burst." "0,1"
textline "                              "
bitfld.long 0x00 2. " INIT_RESP_ERROR_0            ,Receiving error response:" "0,1"
bitfld.long 0x00 1. "   INIT_RESP_UNUSED_TAG_0      ,Receiving response on an unused OCP TAG:" "0,1"
textline "                              "
bitfld.long 0x00 0. " INIT_RESP_UNEXPECTED_0       ,Receiving response when not expected:" "0,1"
group.long 0x108++0x3
line.long 0x00 "GPU_DEBUG_CONFIG,"
bitfld.long 0x00 5. " SELECT_INT_IDLE              ,To select which idle the disconnect protocol should act on:" "0,1"
bitfld.long 0x00 4. "   FORCE_PASS_DATA             ,Forces the initiator to pass data independent of disconnect protocol:" "0,1"
textline "                              "
bitfld.long 0x00 2.--3. " FORCE_INIT_IDLE              ,Forces initiator idle:" "0,1,2,3"
bitfld.long 0x00 0.--1. "   FORCE_TARGET_IDLE           ,Forces target idle:" "0,1,2,3"
rgroup.long 0x10C++0x3
line.long 0x00 "GPU_DEBUG_STATUS_0,Port0 Debug Status Register"
bitfld.long 0x00 31. " CMD_DEBUG_STATE              ,Target command state-machine:" "0,1"
bitfld.long 0x00 30. "   CMD_RESP_DEBUG_STATE        ,Target response state-machine:" "0,1"
textline "                              "
bitfld.long 0x00 29. " TARGET_IDLE                  ,Target idle" "0,1"
bitfld.long 0x00 28. "   RESP_FIFO_FULL              ,Target response FIFO full" "0,1"
textline "                              "
bitfld.long 0x00 27. " CMD_FIFO_FULL                ,Target command FIFO full" "0,1"
bitfld.long 0x00 26. "   RESP_ERROR                  ,Respond to OCP with error, which could be caused by either address misalignment or invalid byte enable." "0,1"
textline "                              "
bitfld.long 0x00 21.--25. " WHICH_TARGET_REGISTER        ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18.--20. "  TARGET_CMD_OUT              ,Command received from OCP:" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 17. " INIT_MSTANDBY                ,Status of init_MStandby signal" "0,1"
bitfld.long 0x00 16. "   INIT_MWAIT                  ,Status of init_MWait signal" "0,1"
textline "                              "
bitfld.long 0x00 15. " INIT_MDISCREQ                ,Request to disconnect from OCP interface" "0,1"
bitfld.long 0x00 13.--14. "   INIT_MDISCACK               ,Disconnect status of the OCP interface:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 12. " INIT_SCONNECT_2              ,Defines whether to wait in M_WAIT state for MConnect FSM:" "0,1"
bitfld.long 0x00 11. "   INIT_SCONNECT_1             ,Defines the busy-ness state of the slave:" "0,1"
textline "                              "
bitfld.long 0x00 10. " INIT_SCONNECT_0              ,Disconnect from slave:" "0,1"
bitfld.long 0x00 8.--9. "   INIT_MCONNECT               ,Initiator MConnect state:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6.--7. " TARGET_SIDLEACK              ,Acknowledge the SIdleAck state-machine:" "0,1,2,3"
bitfld.long 0x00 4.--5. "   TARGET_SDISCACK             ,Acknowledge the SDiscAck state-machine:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3. " TARGET_SIDLEREQ              ,Request the target to go idle:" "0,1"
bitfld.long 0x00 2. "   TARGET_SCONNECT             ,Target SConnect bit 0 state:" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TARGET_MCONNECT              ,Target MConnect state:" "0,1,2,3"
rgroup.long 0x110++0x3
line.long 0x00 "GPU_DEBUG_STATUS_1,Port1 Debug Status Register"
bitfld.long 0x00 31. " CMD_DEBUG_STATE              ,Target command state-machine:" "0,1"
bitfld.long 0x00 30. "   CMD_RESP_DEBUG_STATE        ,Target response state-machine:" "0,1"
textline "                              "
bitfld.long 0x00 29. " TARGET_IDLE                  ,Target idle" "0,1"
bitfld.long 0x00 28. "   RESP_FIFO_FULL              ,Target response FIFO full" "0,1"
textline "                              "
bitfld.long 0x00 27. " CMD_FIFO_FULL                ,Target command FIFO full" "0,1"
bitfld.long 0x00 26. "   RESP_ERROR                  ,Respond to OCP with error, which could be caused by either address misalignment or invalid byte enable." "0,1"
textline "                              "
bitfld.long 0x00 21.--25. " WHICH_TARGET_REGISTER        ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18.--20. "  TARGET_CMD_OUT              ,Command received from OCP:" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 17. " INIT_MSTANDBY                ,Status of init_MStandby signal" "0,1"
bitfld.long 0x00 16. "   INIT_MWAIT                  ,Status of init_MWait signal" "0,1"
textline "                              "
bitfld.long 0x00 15. " INIT_MDISCREQ                ,Request to disconnect from OCP interface" "0,1"
bitfld.long 0x00 13.--14. "   INIT_MDISCACK               ,Disconnect status of the OCP interface:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 12. " INIT_SCONNECT_2              ,Defines whether to wait in M_WAIT state for MConnect FSM:" "0,1"
bitfld.long 0x00 11. "   INIT_SCONNECT_1             ,Defines the busy-ness state of the slave:" "0,1"
textline "                              "
bitfld.long 0x00 10. " INIT_SCONNECT_0              ,Disconnect from slave:" "0,1"
bitfld.long 0x00 8.--9. "   INIT_MCONNECT               ,Initiator MConnect state:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 6.--7. " TARGET_SIDLEACK              ,Acknowledge the SIdleAck state-machine:" "0,1,2,3"
bitfld.long 0x00 4.--5. "   TARGET_SDISCACK             ,Acknowledge the SDiscAck state-machine:" "0,1,2,3"
textline "                              "
bitfld.long 0x00 3. " TARGET_SIDLEREQ              ,Request the target to go idle:" "0,1"
bitfld.long 0x00 2. "   TARGET_SCONNECT             ,Target SConnect bit 0 state:" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TARGET_MCONNECT              ,Target MConnect state:" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "GTC0_GTC_CFG0"
base ad:0xA80000
width 13.
rgroup.long 0x0++0x3
line.long 0x00 "GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the MMR generator."
hexmask.long 0x00 0.--31. 1. " REV        ,TI internal data. Identifies revision of peripheral."
rgroup.long 0x4++0x3
line.long 0x00 "GTC_GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the GTC peripheral."
hexmask.long 0x00 0.--31. 1. " REV        ,TI internal data. Identifies revision of peripheral."
group.long 0x8++0x3
line.long 0x00 "GTC_PUSHEVT,Selects which bit of the count value to output as a push event for global timesync."
bitfld.long 0x00 0.--5. " EXPBIT_SEL ,This field controls the mux that selects which bit [63:0] of the system counter value is exported on the0h = Select CNTR[0]1h = Select CNTR[1]...3Fh = Select CNTR]63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 0x0B
tree.end
tree "GTC0_GTC_CFG1"
base ad:0xA90000
width 14.
group.long 0x0++0x3
line.long 0x00 "GTC_CNTCR,This register enables the system counter and controls counter operation during debug."
hexmask.long.tbyte 0x00 8.--31. 1. " FCREQ      ,Frequency change request. Indicates the number of the entry in the frequency table to select. For this device, this field is implemented as read-only, pointing to the base frequency table entry (000000h)."
bitfld.long 0x00 1. "    HDBG ,Halt on debug0 = System counter ignores debug halt1 = System counter is halted when debug halt is asserted" "0,1"
textline "                       "
bitfld.long 0x00 0. " EN         ,Enable system counter0 = System counter is disabled1 = System counter is enabled" "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "GTC_CNTSR,This register provides system counter frequency status information."
hexmask.long.tbyte 0x00 8.--31. 1. " FCACK      ,Frequency change ackowledge. Indicates the currently selected entry in the frequency table. For this device, this field is tied to 0."
bitfld.long 0x00 1. "    DBGH ,Debug halt. Indicates if the system counter is halted due to debug.0 = System counter is not halted by a debug halt1 = System counter is halted by a debug halt" "0,1"
group.long 0x8++0x3
line.long 0x00 "GTC_CNTCV_LO,Indicates the current system counter count value and can be used to set the system counter count value."
hexmask.long 0x00 0.--31. 1. " COUNTVALUE ,Indicates bits [31:0] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [31:0]."
group.long 0xC++0x3
line.long 0x00 "GTC_CNTCV_HI,Indicates the current system counter count value and can be used to set the system counter count value."
hexmask.long 0x00 0.--31. 1. " COUNTVALUE ,Indicates bits [63:32] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [63:32]."
group.long 0x20++0x3
line.long 0x00 "GTC_CNTFID0,Indicates base frequency of the system counter. Device bootcode/firmware should write this register with the frequency of the selected GTC clock source before enabling the system counter."
hexmask.long 0x00 0.--31. 1. " FREQVALUE  ,Indicates the base update frequency of the system counter in Hz."
rgroup.long 0x24++0x3
line.long 0x00 "GTC_CNTFID1,Indicates the system counter increment frequency."
hexmask.long 0x00 0.--31. 1. " FREQVALUE  ,Frequency table end indicator. All 0s value marks the end of the frequency table."
width 0x0B
tree.end
tree "GTC0_GTC_CFG2"
base ad:0xAA0000
width 15.
rgroup.long 0x0++0x3
line.long 0x00 "GTC_CNTCVS_LO,Indicates the current system counter count value. It reflects the same value as the CNTCV_LO register."
hexmask.long 0x00 0.--31. 1. " COUNTVALUE ,Indicates bits [31:0] of the system counter value."
rgroup.long 0x4++0x3
line.long 0x00 "GTC_CNTCVS_HI,Indicates the current system counter count value. It reflects the same value as the CNTCV_HI register."
hexmask.long 0x00 0.--31. 1. " COUNTVALUE ,Indicates bits [63:32] of the system counter value."
width 0x0B
tree.end
tree "GTC0_GTC_CFG3"
base ad:0xAB0000
width 13.
rgroup.long 0x0++0x3
line.long 0x00 "GTC_CNTTIDR,Indicates the implemented timers in the memory map and their features. Because the platform does not implement memory-mapped timers, this register is set to all 0s."
bitfld.long 0x00 28.--31. " FRAME7 ,Indicates the features of timer frame 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "  FRAME6 ,Indicates the features of timer frame 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 20.--23. " FRAME5 ,Indicates the features of timer frame 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "  FRAME4 ,Indicates the features of timer frame 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 12.--15. " FRAME3 ,Indicates the features of timer frame 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "  FRAME2 ,Indicates the features of timer frame 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 4.--7. " FRAME1 ,Indicates the features of timer frame 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  FRAME0 ,Indicates the features of timer frame 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "Hyperbus"
tree "MCU_FSS0_HPB_SS_CFG"
base ad:0x47030000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_FSS0_HPB0_SS_REVISION_REG,Revision Register The Revision Register contains the major and minor revisions for the module."
hexmask.long.word 0x00 16.--31. 1. " MODID     ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL          ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ    ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM          ,Custom Revision" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN    ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "MCU_FSS0_HPB0_SS_DLL_STAT_REG,DLL Status Register"
hexmask.long.word 0x00 2.--10. 1. " MDLL_CODE ,MDLL Code The slave delay line length that is currently enabled is determined by the MDLL Code value."
bitfld.long 0x00 1. "  MDLL_CODE_VALID ,MDLL Code Valid" "0,1"
textline "                                        "
bitfld.long 0x00 0. " MDLL_LOCK ,MDLL Lock When this bit is set, it indicates that the master delay line in the MDLL is locked." "0,1"
width 0x0B
tree.end
tree "MCU_FSS0_HPB_CTRL"
base ad:0x47034000
width 25.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_CSR,Controller Status Register The Controller Status Register is used to access the internal status of the HBMC."
bitfld.long 0x00 26. " WRSTOERR ,Write RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest write operation. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset" "0,1"
bitfld.long 0x00 25. "         WTRSERR  ,Write Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest write transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported" "0,1"
textline "                                  "
bitfld.long 0x00 24. " WDECERR  ,Write Decode Error This bit indicates whether access address is acceptable in the latest write transaction. When this bit is set, HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable" "0,1"
bitfld.long 0x00 16. "         WACT     ,Write Active This bit indicates whether write transaction is in progress or not. When receiving write request on write address channel, this bit becomes 1h. When retrieving response signaling on write response channel, this bit becomes 0h. 0h = Write is idle 1h = Write is active" "0,1"
textline "                                  "
bitfld.long 0x00 11. " RDSSTALL ,RDS Stall This bit indicates whether read data transfer from HyperBus memory is stalled (RDS Stall remains LOW) in the latest read transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = RDS is stalled" "0,1"
bitfld.long 0x00 10. "         RRSTOERR ,Read RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest read operation. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset" "0,1"
textline "                                  "
bitfld.long 0x00 9. " RTRSERR  ,Read Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest read transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported" "0,1"
bitfld.long 0x00 8. "         RDECERR  ,Read Decode Error This bit indicates whether access address is acceptable in the latest read transaction. When this bit is set, HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable" "0,1"
textline "                                  "
hexmask.long.byte 0x00 1.--7. 1. " RFU0     ,Reserved"
bitfld.long 0x00 0. "        RACT     ,Read Active This bit indicates whether read transaction is in progress or not. When receiving read request on read address channel, this bit becomes 1h. When retrieving all requested data on read data channel, this bit becomes 0h. 0h = Read is idle 1h = Read is active" "0,1"
group.long 0x4++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_IER,Interrupt Enable Register The HBMC outputs optional interrupt signal by condition enabled by the Interrupt Enable Register."
bitfld.long 0x00 31. " INTP     ,Interrupt Polarity Control This bit is used to choose the polarity of optional interrupt signal (IENOn). 0h = IENOn signal is active low 1h = IENOn signal is active high (Reversed mode)" "0,1"
bitfld.long 0x00 0. "         RPCINTE  ,HyperBus Memory Interrupt Enable 0h = Disable interrupt 1h = Enable interrupt by INT# signal of HyperBus memory" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_ISR,Interrupt Status Register The Interrupt Status Register is used to read the status for the interrupts generated."
bitfld.long 0x00 0. " RPCINTS  ,HyperBus Memory Interrupt 0h = No interrupt 1h = This bit displays interrupt from INT# signal of HyperBus memory" "0,1"
group.long 0x10++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_MBAR_y,Memory Base Address Register for device connected to CS# The base address of addressable region to Hyperflash memory can be set-up using this register. The controller can't assert two chip selects CS0# and CS1# at a time. Hence this register describes how to select chip select. Offset = 10h + (y ? 4h); where y = 0h to 1h"
hexmask.long.byte 0x00 24.--31. 1. " A_MSB    ,MSB 8 bit of the base address of addressable region to HyperBus memory"
hexmask.long.tbyte 0x00 0.--23. 1. "        A_LSB    ,Since register can be set in 16 MB boundary, lower 24 bit is fixed to 0h, if read, this field will always return 0h."
group.long 0x20++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_MCR_y,Memory Configuration Register for CS# Offset = 20h + (y ? 4h); where y = 0h to 1h"
bitfld.long 0x00 31. " MAXEN    ,Maximum Length Enable When this bit is set to 1h, CS# low time can be configurable by MAXLEN bit. 0h = No configurable CS# low time 1h = Configurable CS# low time" "0,1"
hexmask.long.word 0x00 18.--26. 1. "         MAXLEN   ,Maximum Length This bit indicates maximum read/write transaction length to memory. This bit is ignored when MAXEN bit is 0h. 0h = 2 Byte (1 HyperBus CK) 1h = 4 Byte (2 HyperBus CK) 2h = 6 Byte (3 HyperBus CK) .... 1FFh = 1024 Byte (512 HyperBus CK)"
textline "                                  "
bitfld.long 0x00 17. " TCMO     ,True Continuous Merge Option Note that this function can be used with the HyperFlash with specific function. Please confirm whether it is corresponding HyperFlash before enabling this function. When HyperBus memory doesn't accept the 8-bit boundary address, and a wrapping burst access with ARSIZE = 0h and ARADDR0 = 1h is used, this bit must not be set to 1h. 0h = No merging WRAP and INCR 1h = Merging WRAP and INCR" "0,1"
bitfld.long 0x00 16. "         ACS      ,Asymmetry Cache Support This function should be disabled if the HyperBus memory itself supports the asymmetry cache system. 0h = No asymmetry cache system support 1h = Asymmetry cache system support" "0,1"
textline "                                  "
bitfld.long 0x00 5. " CRT      ,Configuration Register Target This bit indicates whether the read or write operation accesses the memory or CR space. This bit is mapped to CA-46 bit in HyperRAM. When using HyperFlash, this bit should be set to 0h. 0h = Memory space 1h = CR space" "0,1"
bitfld.long 0x00 4. "         DEVTYPE  ,Device Type Device type for control target. 0h = HyperFlash 1h = HyperRAM" "0,1"
textline "                                  "
bitfld.long 0x00 0.--1. " WRAPSIZE ,Wrap Size The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0h. When the asymmetry cache support is 1h, this bit should be set the same as wrap size of configuration register in HyperBus memory. 0h = Reserved 1h = 64 Bytes 2h = 16 Bytes 3h = 32 Bytes" "0,1,2,3"
group.long 0x30++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_MTR_y,Memory Timing Register for CS# Memory access timings can be configured using the Memory Timing Register. Offset = 30h + (y ? 4h); where y = 0h to 1h"
bitfld.long 0x00 28.--31. " RCSHI    ,Read Chip Select High Between Operations This bit indicates CS# high time for read between operations. 0h = corresponds to 15 clock cycle Fh = corresponds to 165 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        WCSHI    ,Write Chip Select High Between Operations This bit indicates CS# high time for write between operations. 0h = corresponds to 15 clock cycle Fh = corresponds to 165 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 20.--23. " RCSS     ,Read Chip Select Setup to next CK rising edge This bit indicates CS# setup time for read from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        WCSS     ,Write Chip Select Setup to next CK rising edge This bit indicates CS# setup time for write from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 12.--15. " RCSH     ,Read Chip Select Hold after CK falling edge This bit indicates CS# hold time for read to CS# de-assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        WCSH     ,Write Chip Select Hold after CK falling edge This bit indicates CS# hold time for write to CS# de-assertion. 0h = corresponds to 1 clock cycle Fh = corresponding to 16 clock cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 4.--7. " RFU12    ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        LTCY     ,Latency Cycle Only uses in HyperRAM This bit indicates initial latency code for read/write access. This bit is ignored when the 0h = 5 clock latency 1h = 6 clock latency 2h = Reserved .... Dh = Reserved Eh = 3 clock latency Fh = 4 clock latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_GPOR,General Purpose Output Register Output signal polarity can be configured using the General Purpose Output Register. General Purpose Output register () of the HBMC is not used (see , Hyperbus Not Supported Features)."
hexmask.long 0x00 2.--31. 1. " RFU14    ,Reserved"
bitfld.long 0x00 0.--1. "  GPO      ,General Purpose Output Interface 0h = Output signal polarity is LOW 1h = Output signal polarity is HIGH" "0,1,2,3"
group.long 0x44++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_WPR,Write Protection Register Write protection can be configured using the Write Protection Register."
hexmask.long 0x00 1.--31. 1. " RFU15    ,Reserved"
bitfld.long 0x00 0. "  WP       ,Write Protection Control 0h = Not Protected WP# signal is HIGH 1h = Protected WP# signal is LOW" "0,1"
group.long 0x48++0x3
line.long 0x00 "MCU_FSS0_HPB0_MC_LBR,Loop Back Register Loopback settings can be configured using the Loop Back Register."
hexmask.long 0x00 1.--31. 1. " RFU16    ,Reserved"
bitfld.long 0x00 0. "  LOOPBACK ,The write transaction data written on AXI bus is looped back as the read data from RPC bus. The loop-back is performed between WDAT FIFO and RDAT FIFO in AXI interface controller. 0h = Disable loopback 1h = Enable loopback" "0,1"
width 0x0B
tree.end
tree "MCU_FSS0_HPB_ECC_AGGR"
base ad:0x47060000
width 39.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_REV,Aggregator Revision Register Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME                    ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                        ,Business Unit" "0,1,2,3"
textline "                                                "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                 ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                    ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                "
bitfld.long 0x00 8.--10. " REVMAJ                    ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                    ,Custom Version" "0,1,2,3"
textline "                                                "
bitfld.long 0x00 0.--5. " REVMIN                    ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MCU_FSS0_HPB0_ECC_VECTOR,ECC Vector Register"
in
textline "                                                "
rgroup.long 0xC++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                  ,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator."
group.long 0x3C++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_EOI_REG,End Of Interrupt (EOI) Register"
bitfld.long 0x00 0. " EOI_WR                    ,EOI" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 14. " MEM_ARID_FIFO_PEND        ,Interrupt Pending Status for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "     MEM_AR_FIFO_PEND          ,Interrupt Pending Status for mem_ar_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 12. " MEM_AWID1_FIFO_PEND       ,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1"
bitfld.long 0x00 11. "     MEM_WID1_FIFO_PEND        ,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 10. " MEM_AW1_FIFO_PEND         ,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "     MEM_AWID0_FIFO_PEND       ,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 8. " MEM_WID0_FIFO_PEND        ,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "     MEM_AW0_FIFO_PEND         ,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 6. " MEM_RX_FIFO_PEND          ,Interrupt Pending Status for mem_rx_fifo_pend" "0,1"
bitfld.long 0x00 5. "     MEM_RDAT_FIFO_PEND        ,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 4. " MEM_BDAT1_FIFO_PEND       ,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "     MEM_BDAT0_FIFO_PEND       ,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 2. " MEM_WDAT1_FIFO_PEND       ,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "     MEM_WDAT0_FIFO_PEND       ,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 0. " MEM_ADR_FIFO_PEND         ,Interrupt Pending Status for mem_adr_fifo_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 14. " MEM_ARID_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "     MEM_AR_FIFO_ENABLE_SET    ,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 12. " MEM_AWID1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1"
bitfld.long 0x00 11. "     MEM_WID1_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 10. " MEM_AW1_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "     MEM_AWID0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 8. " MEM_WID0_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "     MEM_AW0_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 6. " MEM_RX_FIFO_ENABLE_SET    ,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1"
bitfld.long 0x00 5. "     MEM_RDAT_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 4. " MEM_BDAT1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "     MEM_BDAT0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 2. " MEM_WDAT1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "     MEM_WDAT0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 0. " MEM_ADR_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                                "
group.long 0x13C++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR                    ,EOI" "0,1"
group.long 0x140++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 14. " MEM_ARID_FIFO_PEND        ,Interrupt Pending Status for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "     MEM_AR_FIFO_PEND          ,Interrupt Pending Status for mem_ar_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 12. " MEM_AWID1_FIFO_PEND       ,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1"
bitfld.long 0x00 11. "     MEM_WID1_FIFO_PEND        ,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 10. " MEM_AW1_FIFO_PEND         ,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "     MEM_AWID0_FIFO_PEND       ,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 8. " MEM_WID0_FIFO_PEND        ,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "     MEM_AW0_FIFO_PEND         ,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 6. " MEM_RX_FIFO_PEND          ,Interrupt Pending Status for mem_rx_fifo_pend" "0,1"
bitfld.long 0x00 5. "     MEM_RDAT_FIFO_PEND        ,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 4. " MEM_BDAT1_FIFO_PEND       ,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "     MEM_BDAT0_FIFO_PEND       ,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 2. " MEM_WDAT1_FIFO_PEND       ,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "     MEM_WDAT0_FIFO_PEND       ,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 0. " MEM_ADR_FIFO_PEND         ,Interrupt Pending Status for mem_adr_fifo_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 14. " MEM_ARID_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "     MEM_AR_FIFO_ENABLE_SET    ,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 12. " MEM_AWID1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1"
bitfld.long 0x00 11. "     MEM_WID1_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 10. " MEM_AW1_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "     MEM_AWID0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 8. " MEM_WID0_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "     MEM_AW0_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 6. " MEM_RX_FIFO_ENABLE_SET    ,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1"
bitfld.long 0x00 5. "     MEM_RDAT_FIFO_ENABLE_SET  ,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 4. " MEM_BDAT1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "     MEM_BDAT0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 2. " MEM_WDAT1_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "     MEM_WDAT0_FIFO_ENABLE_SET ,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1"
textline "                                                "
bitfld.long 0x00 0. " MEM_ADR_FIFO_ENABLE_SET   ,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MCU_FSS0_HPB0_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                                "
group.long 0x200++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT                   ,Interrupt enable set for ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                    ,Interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                                "
group.long 0x208++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt status set for ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                    ,Interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MCU_FSS0_HPB0_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt status clear for ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                    ,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "I2C"
tree "I2C0_CFG"
base ad:0x2000000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree "I2C1_CFG"
base ad:0x2010000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree "I2C2_CFG"
base ad:0x2020000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree "I2C3_CFG"
base ad:0x2030000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree "MCU_I2C0_CFG"
base ad:0x40B00000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree "WKUP_I2C0_CFG"
base ad:0x42120000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 11.--15. " RTL                ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "            MAJOR      ,Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change" "0,1,2,3,4,5,6,7"
textline "                              "
bitfld.long 0x00 6.--7. " CUSTOM             ,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "             MINOR      ,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 14.--15. " SCHEME             ,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "             FUNC       ,Function: Indicates a software compatible module family"
group.long 0x10++0x3
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. " CLKACTIVITY        ,Clock Activity selection bits" "Both_off,Ocp_on,Sys_on,Both_on"
bitfld.long 0x00 3.--4. "      IDLEMODE   ,Idle Mode selection bits" "Force_idle,No_idle,Smart_idle,Smartidle_wakeup"
textline "                              "
bitfld.long 0x00 2. " ENAWAKEUP          ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. "      SRST       ,SoftReset bit" "Normal,Reset"
textline "                              "
bitfld.long 0x00 0. " AUTOIDLE           ,Autoidle bit" "Disabled,Enabled"
wgroup.long 0x20++0x3
line.long 0x00 "I2C_EOI,End Of Interrupt number specification Added Information About I2C_EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used."
bitfld.long 0x00 0. " LINE_NUMBER        ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1"
group.long 0x24++0x3
line.long 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x28++0x3
line.long 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ enabled status." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ enabled status." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy enabled status. Writing into this bit has no effect." "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun enabled status. Writing into this bit has no effect." "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow enabled status. Writing into this bit has no effect." "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ enabled status." "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ enabled status." "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ enabled status." "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ enabled status." "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "Normal,Detected"
group.long 0x2C++0x3
line.long 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable set." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit in" "0,1"
group.long 0x30++0x3
line.long 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 13. "             RDR_IE     ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR]." "0,1"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable clear." "0,1"
bitfld.long 0x00 10. "             XUDF       ,Transmit underflow enable clear." "0,1"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 8. "             BF_IE      ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 6. "             STC_IE     ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 4. "             XRDY_IE    ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]" "0,1"
bitfld.long 0x00 2. "             ARDY_IE    ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
bitfld.long 0x00 0. "             AL_IE      ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit in" "0,1"
group.long 0x34++0x3
line.long 0x00 "I2C_WE,I2C wakeup enable vector."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set."
bitfld.long 0x00 0. " DMARX_ENABLE_SET   ,Receive DMA channel enable set." "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set."
bitfld.long 0x00 0. " DMATX_ENABLE_SET   ,Transmit DMA channel enable set." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear."
bitfld.long 0x00 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "No_effect,Cleared"
group.long 0x44++0x3
line.long 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear."
bitfld.long 0x00 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "No_effect,Cleared"
group.long 0x48++0x3
line.long 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x4C++0x3
line.long 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable."
bitfld.long 0x00 14. " XDR                ,Transmit Draining wakeup set." "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive Draining wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun wakeup set." "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " AAS                ,Address as slave IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 8. "      BF         ,Bus Free IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 5. "      GC         ,General call IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " DRDY               ,Receive/Transmit data ready IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY       ,Register access ready IRQ wakeup set." "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK               ,No acknowledgment IRQ wakeup set." "Disabled,Enabled"
bitfld.long 0x00 0. "      AL         ,Arbitration lost IRQ wakeup set." "Disabled,Enabled"
group.long 0x84++0x3
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)."
bitfld.long 0x00 14. " XDR_IE             ,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR_IE     ,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 11. " ROVR               ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x00 10. "      XUDF       ,Transmit underflow enable set" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 9. " ASS_IE             ,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 8. "      BF_IE      ,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 7. " AERR_IE            ,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 6. "      STC_IE     ,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 5. " GC_IE              ,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 4. "      XRDY_IE    ,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 3. " RRDY_IE            ,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 2. "      ARDY_IE    ,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 1. " NACK_IE            ,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
bitfld.long 0x00 0. "      AL_IE      ,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "Disabled,Enabled"
group.long 0x88++0x3
line.long 0x00 "I2C_STAT,I2C interrupt status vector (legacy)."
bitfld.long 0x00 14. " XDR                ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. "      RDR        ,Receive draining IRQ status" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 12. " BB                 ,Bus busy statusWriting into this bit has no effect" "Not_busy,Busy"
bitfld.long 0x00 11. "      ROVR       ,Receive overrun statusWriting into this bit has no effect" "Normal,Received"
textline "                              "
bitfld.long 0x00 10. " XUDF               ,Transmit underflow statusWriting into this bit has no effect" "No_underflow,Underflow"
bitfld.long 0x00 9. "  AAS        ,Address recognized as slave IRQ status" "No_action,Recognized"
textline "                              "
bitfld.long 0x00 8. " BF                 ,Bus Free IRQ status" "No_action,Free"
bitfld.long 0x00 7. "     AERR       ,Access Error IRQ status" "No_action,Error"
textline "                              "
bitfld.long 0x00 6. " STC                ,Start Condition IRQ status" "No_action,Detected"
bitfld.long 0x00 5. "     GC         ,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "Not_detected,Detected"
textline "                              "
bitfld.long 0x00 4. " XRDY               ,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 3. "     RRDY       ,Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
textline "                              "
bitfld.long 0x00 2. " ARDY               ,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "Not_ready,Ready"
bitfld.long 0x00 1. "     NACK       ,No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit" "Normal,Detected"
textline "                              "
bitfld.long 0x00 0. " AL                 ,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0" "Normal,Detected"
rgroup.long 0x90++0x3
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. " RDONE              ,Reset done bit" "Ongoing,Reset"
group.long 0x94++0x3
line.long 0x00 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x00 15. " RDMA_EN            ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x00 14. "      RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline "                              "
bitfld.long 0x00 8.--13. " RXTRSH             ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "            XDMA_EN    ,Transmit DMA channel enable" "Disabled,Enabled"
textline "                              "
bitfld.long 0x00 6. " TXFIFO_CLR         ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x00 0.--5. "        TXTRSH     ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x3
line.long 0x00 "I2C_CNT,Data counter register"
hexmask.long.word 0x00 0.--15. 1. " DCOUNT             ,Data count"
group.long 0x9C++0x3
line.long 0x00 "I2C_DATA,Data access register"
hexmask.long.byte 0x00 0.--7. 1. " DATA               ,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x3
line.long 0x00 "I2C_CON,I2C configuration register."
bitfld.long 0x00 15. " I2C_EN             ,I2C module enable." "Disabled,Enabled"
bitfld.long 0x00 12.--13. "      OPMODE     ,Operation mode selection." "Fast/Standard,High_Speed,SCCB,Reserved"
textline "                              "
bitfld.long 0x00 11. " STB                ,Start byte mode (master mode only)." "0,1"
bitfld.long 0x00 10. "             MST        ,Master/slave mode." "Slave,Master"
textline "                              "
bitfld.long 0x00 9. " TRX                ,Transmitter/Receiver mode (master mode only)." "0,1"
bitfld.long 0x00 8. "             XSA        ,Expand Slave address." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 7. " XOA0               ,Expand Own address 0." "7-bit,10-bit"
bitfld.long 0x00 6. "        XOA1       ,Expand Own address 1." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 5. " XOA2               ,Expand Own address 2." "7-bit,10-bit"
bitfld.long 0x00 4. "        XOA3       ,Expand Own address 3." "7-bit,10-bit"
textline "                              "
bitfld.long 0x00 1. " STP                ,Stop condition (master mode only)." "0,1"
bitfld.long 0x00 0. "             STT        ,Start condition (master mode only)." "0,1"
group.long 0xA8++0x3
line.long 0x00 "I2C_OA,Own address register"
bitfld.long 0x00 13.--15. " MCODE              ,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "             OA         ,Own address"
group.long 0xAC++0x3
line.long 0x00 "I2C_SA,Slave address register"
hexmask.long.word 0x00 0.--9. 1. " SA                 ,Slave address"
group.long 0xB0++0x3
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC                ,Fast/Standard mode prescale sampling clock divider value"
group.long 0xB4++0x3
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLL             ,High speed mode SCL low time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLL       ,Fast/standard mode SCL low time"
group.long 0xB8++0x3
line.long 0x00 "I2C_SCLH,I2C SCL High Time Register."
hexmask.long.byte 0x00 8.--15. 1. " HSSCLH             ,High speed mode SCL high time"
hexmask.long.byte 0x00 0.--7. 1. "            SCLH       ,Fast/standard mode SCL high time"
group.long 0xBC++0x3
line.long 0x00 "I2C_SYSTEST,I2C System Test Register."
bitfld.long 0x00 15. " ST_EN              ,System test enable." "Disabled,Enabled"
bitfld.long 0x00 14. "      FREE       ,Free running mode (on breakpoint)" "Stop,Free"
textline "                              "
bitfld.long 0x00 12.--13. " TMODE              ,Test mode select." "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. "    SSB        ,Set all status bits in" "No_action,Set"
textline "                              "
bitfld.long 0x00 8. " SCL_I_FUNC         ,SCL line input value (functional mode)." "Low,High"
bitfld.long 0x00 7. "          SCL_O_FUNC ,SCL line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 6. " SDA_I_FUNC         ,SDA line input value (functional mode)." "Low,High"
bitfld.long 0x00 5. "          SDA_O_FUNC ,SDA line output value (functional mode)." "Low,High"
textline "                              "
bitfld.long 0x00 4. " SCCB_E_O           ,SCCB_E line sense output value" "Low,High"
bitfld.long 0x00 3. "          SCL_I      ,SCL line sense input value" "Low,High"
textline "                              "
bitfld.long 0x00 2. " SCL_O              ,SCL line drive output value." "Low,High"
bitfld.long 0x00 1. "          SDA_I      ,SDA line sense input value." "Low,High"
textline "                              "
bitfld.long 0x00 0. " SDA_O              ,SDA line drive output value." "Low,High"
rgroup.long 0xC0++0x3
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register."
bitfld.long 0x00 14.--15. " FIFODEPTH          ,Internal FIFO buffers depth." "0,1,2,3"
bitfld.long 0x00 8.--13. "             RXSTAT     ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                              "
bitfld.long 0x00 0.--5. " TXSTAT             ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x3
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1                ,Own address 1"
group.long 0xC8++0x3
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2                ,Own address 2"
group.long 0xCC++0x3
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3                ,Own address 3"
rgroup.long 0xD0++0x3
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register."
bitfld.long 0x00 3. " OA3_ACT            ,Own Address 3 active." "Not_active,Active"
bitfld.long 0x00 2. "    OA2_ACT    ,Own Address 2 active." "Not_active,Active"
textline "                              "
bitfld.long 0x00 1. " OA1_ACT            ,Own Address 1 active." "Not_active,Active"
bitfld.long 0x00 0. "    OA0_ACT    ,Own Address 0 active." "Not_active,Active"
group.long 0xD4++0x3
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register."
bitfld.long 0x00 3. " OA3_EN             ,Enable I2C Clock Blocking for Own Address 3." "Not_locked,Locked"
bitfld.long 0x00 2. "    OA2_EN     ,Enable I2C Clock Blocking for Own Address 2." "Not_locked,Locked"
textline "                              "
bitfld.long 0x00 1. " OA1_EN             ,Enable I2C Clock Blocking for Own Address 1." "Not_locked,Locked"
bitfld.long 0x00 0. "    OA0_EN     ,Enable I2C Clock Blocking for Own Address 0." "Not_locked,Locked"
width 0x0B
tree.end
tree.end
tree "Interrupt_Routers"
tree "WKUP_GPIOMUX_INTRTR0"
base ad:0x42200000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "WKUP_GPIOMUX_INTRTR0_PID,Identification register"
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "WKUP_GPIOMUX_INTRTR0_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4h); where y = 0h to Fh"
bitfld.long 0x00 0.--5. " ENABLE ,Mux control for interrupt N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 0x0B
tree.end
tree "GPIO_INTRTR0"
base ad:0xA00000
width 24.
rgroup.long 0x0++0x3
line.long 0x00 "GPIO_INTRTR0_PID,Identification register"
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "GPIO_INTRTR0_MUXCNTL_y,Interrupt mux control register"
hexmask.long.byte 0x00 0.--7. 1. " ENABLE ,Mux control for interrupt N"
width 0x0B
tree.end
tree "MAIN2MCU_LVL_INTRTR0"
base ad:0xA10000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "MAIN2MCU_LVL_INTRTR0_PID,Identification register"
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "MAIN2MCU_LVL_INTRTR0_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4h); where y = 0h to 3Fh"
hexmask.long.byte 0x00 0.--7. 1. " ENABLE ,Mux control for interrupt N"
width 0x0B
tree.end
tree "MAIN2MCU_PLS_INTRTR0"
base ad:0xA20000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "MAIN2MCU_PLS_INTRTR0_PID,Identification register"
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "MAIN2MCU_PLS_INTRTR0_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4h); where y = 0h to 2Fh"
bitfld.long 0x00 0.--4. " ENABLE ,Mux control for interrupt N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "MCAN"
tree "MCU_MCAN0_SS"
base ad:0x40520000
width 36.
rgroup.long 0x0++0x3
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "       BU            ,Business Unit (2h = Processors)" "0,1,2,3"
textline "                                             "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "    RTL           ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                             "
bitfld.long 0x00 8.--10. " MAJOR            ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "       CUSTOM        ,Custom Revision" "0,1,2,3"
textline "                                             "
bitfld.long 0x00 0.--5. " MINOR            ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS."
bitfld.long 0x00 6. " EXT_TS_CNTR_EN   ,External Timestamp Counter Enable" "0,1"
bitfld.long 0x00 5. "       AUTOWAKEUP    ,Automatic Wakeup Enable" "0,1"
textline "                                             "
bitfld.long 0x00 4. " WAKEUPREQEN      ,Wakeup Request Enable" "0,1"
bitfld.long 0x00 3. "       DBGSUSP_FREE  ,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS."
bitfld.long 0x00 2. " ENABLE_FDOE      ,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe." "0,1"
bitfld.long 0x00 1. "       MEM_INIT_DONE ,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1"
wgroup.long 0xC++0x3
line.long 0x00 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1"
group.long 0x10++0x3
line.long 0x00 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1"
group.long 0x14++0x3
line.long 0x00 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1"
group.long 0x18++0x3
line.long 0x00 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1"
rgroup.long 0x1C++0x3
line.long 0x00 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt" "0,1"
wgroup.long 0x20++0x3
line.long 0x00 "MCANSS_EOI,End Of Interrupt (EOI) Register"
hexmask.long.byte 0x00 0.--7. 1. " EOI              ,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1h will issue another pulse interrupt. 0h = EOI value for external timestamp interrupt 1h = EOI value for mcan[0] interrupt 2h = EOI value for mcan[1] interrupt"
group.long 0x24++0x3
line.long 0x00 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER        ,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h."
rgroup.long 0x28++0x3
line.long 0x00 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "MCU_MCAN1_SS"
base ad:0x40560000
width 36.
rgroup.long 0x0++0x3
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "       BU            ,Business Unit (2h = Processors)" "0,1,2,3"
textline "                                             "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "    RTL           ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                             "
bitfld.long 0x00 8.--10. " MAJOR            ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "       CUSTOM        ,Custom Revision" "0,1,2,3"
textline "                                             "
bitfld.long 0x00 0.--5. " MINOR            ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS."
bitfld.long 0x00 6. " EXT_TS_CNTR_EN   ,External Timestamp Counter Enable" "0,1"
bitfld.long 0x00 5. "       AUTOWAKEUP    ,Automatic Wakeup Enable" "0,1"
textline "                                             "
bitfld.long 0x00 4. " WAKEUPREQEN      ,Wakeup Request Enable" "0,1"
bitfld.long 0x00 3. "       DBGSUSP_FREE  ,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS."
bitfld.long 0x00 2. " ENABLE_FDOE      ,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe." "0,1"
bitfld.long 0x00 1. "       MEM_INIT_DONE ,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1"
wgroup.long 0xC++0x3
line.long 0x00 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1"
group.long 0x10++0x3
line.long 0x00 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1"
group.long 0x14++0x3
line.long 0x00 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1"
group.long 0x18++0x3
line.long 0x00 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1"
rgroup.long 0x1C++0x3
line.long 0x00 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts."
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt" "0,1"
wgroup.long 0x20++0x3
line.long 0x00 "MCANSS_EOI,End Of Interrupt (EOI) Register"
hexmask.long.byte 0x00 0.--7. 1. " EOI              ,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1h will issue another pulse interrupt. 0h = EOI value for external timestamp interrupt 1h = EOI value for mcan[0] interrupt 2h = EOI value for mcan[1] interrupt"
group.long 0x24++0x3
line.long 0x00 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER        ,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h."
rgroup.long 0x28++0x3
line.long 0x00 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "MCU_MCAN0_CFG"
base ad:0x40528000
width 13.
rgroup.long 0x0++0x3
line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)."
bitfld.long 0x00 28.--31. " REL     ,Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        STEP   ,Step of Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        YEAR   ,Time Stamp Year One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
hexmask.long.byte 0x00 8.--15. 1. " MON     ,Time Stamp Month Two digits, BCD-coded."
hexmask.long.byte 0x00 0.--7. 1. "        DAY    ,Time Stamp Day Two digits, BCD-coded."
rgroup.long 0x4++0x3
line.long 0x00 "MCAN_ENDN,Endian Register Constant 8765 4321h."
hexmask.long 0x00 0.--31. 1. " ETV     ,Endianness Test Value The endianness test value is 8765 4321h."
group.long 0xC++0x3
line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing, transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 MCAN functional clock periods. tq = ([20-16] DBRP + 1) mtq (minimum time quantum = CAN clock period (MCAN functional clock)). The [12-8] DTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The [7-4] DTSEG2 field is Phase_Seg2. Therefore the length of the bit time is (programmed values) [[12-8] DTSEG1 + [7-4] DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0000 0A33h configures the MCAN module for a data phase bit rate of 500 kbit/s. Note: The bit rate configured for the CAN FD data phase via the register must be higher or equal to the bit rate configured for the arbitration phase via the register."
bitfld.long 0x00 23. " TDC     ,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1"
bitfld.long 0x00 16.--20. "         DBRP   ,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 8.--12. " DTSEG1  ,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "        DTSEG2 ,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 0.--3. " DSJW    ,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loop Back Mode and software control of the MCAN TX pin are hardware test modes. Programming of the [6-5] TX field ? 00 may disturb the message transfer on the CAN bus."
bitfld.long 0x00 7. " RX      ,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1"
bitfld.long 0x00 5.--6. "         TX     ,Control of Transmit Pin 0h = Reset value, the MCAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the MCAN TX pin" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4. " LBCK    ,Loop Back Mode 0h = Reset value, Loop Back Mode is disabled 1h = Loop Back Mode is enabled (see , Test Modes)" "0,1"
group.long 0x14++0x3
line.long 0x00 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter is reloaded with the [7-0] WDC field when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag [26] WDI is set. The RAM Watchdog Counter is clocked by the Host clock (MCAN interface clock)."
hexmask.long.byte 0x00 8.--15. 1. " WDV     ,Watchdog Value Actual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x00 0.--7. 1. "        WDC    ,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled."
group.long 0x18++0x3
line.long 0x00 "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits, see , Software Initialization."
bitfld.long 0x00 15. " NISO    ,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1"
bitfld.long 0x00 14. "         TXP    ,Transmit Pause If this bit is set, the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see , Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " EFBI    ,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1"
bitfld.long 0x00 12. "         PXHD   ,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled, the MCAN module will transmit an error frame when it detects a protocol exception condition." "0,1"
textline "                      "
bitfld.long 0x00 9. " BRSE    ,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h, the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1"
bitfld.long 0x00 8. "         FDOE   ,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " TEST    ,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1"
bitfld.long 0x00 6. "         DAR    ,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " MON     ,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1"
bitfld.long 0x00 4. "         CSR    ,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested, first the" "0,1"
textline "                      "
bitfld.long 0x00 3. " CSA     ,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1"
bitfld.long 0x00 2. "         ASM    ,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1"
textline "                      "
bitfld.long 0x00 1. " CCE     ,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1"
bitfld.long 0x00 0. "         INIT   ,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the software has to assure that the previous value written to the MCAN_CCCR[0] INIT bit has been accepted by reading the MCAN_CCCR[0] INIT bit before setting the MCAN_CCCR[0] INIT bit to a new value." "0,1"
group.long 0x1C++0x3
line.long 0x00 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 MCAN functional clock periods. tq = ([24-16] NBRP + 1) mtq. The [15-8] NTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The [6-0] NTSEG2 field is Phase_Seg2. Therefore the length of the bit time is (programmed values) [[15-8] NTSEG1 + [6-0] NTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
hexmask.long.byte 0x00 25.--31. 1. " NSJW    ,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
hexmask.long.word 0x00 16.--24. 1. "        NBRP   ,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
textline "                      "
hexmask.long.byte 0x00 8.--15. 1. " NTSEG1  ,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
hexmask.long.byte 0x00 0.--6. 1. "        NTSEG2 ,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0600 0A03h configures the MCAN module for a bit rate of 500 kbit/s."
group.long 0x20++0x3
line.long 0x00 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting, selection of internal/external timestamp vector. For a description of the Timestamp Counter, see , Timestamp Generation."
bitfld.long 0x00 16.--19. " TCP     ,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note:With CAN FD an external counter is required for timestamp generation (MCAN_TSCC[1-0] TSS = 2h)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        TSS    ,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3"
group.long 0x24++0x3
line.long 0x00 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter."
hexmask.long.word 0x00 0.--15. 1. " TSC     ,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to the MCAN_TSCV register."
group.long 0x28++0x3
line.long 0x00 "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period, selection of timeout counter operation mode. For a description of the Timeout Counter, see , Timeout Counter."
hexmask.long.word 0x00 16.--31. 1. " TOP     ,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."
bitfld.long 0x00 1.--2. "      TOS    ,Timeout Select When operating in Continuous mode, a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3"
textline "                      "
bitfld.long 0x00 0. " ETOC    ,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1"
group.long 0x2C++0x3
line.long 0x00 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter."
hexmask.long.word 0x00 0.--15. 1. " TOC     ,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the"
rgroup.long 0x40++0x3
line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter, CAN Error Logging."
hexmask.long.byte 0x00 16.--23. 1. " CEL     ,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the"
bitfld.long 0x00 15. "        RP     ,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1"
textline "                      "
hexmask.long.byte 0x00 8.--14. 1. " REC     ,Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127."
hexmask.long.byte 0x00 0.--7. 1. "        TEC    ,Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set, the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN protocol error is detected, but the MCAN_ECR[23-16] CEL field is still incremented."
rgroup.long 0x44++0x3
line.long 0x00 "MCAN_PSR,Protocol Status Register CAN protocol controller status, transmitter delay compensation value."
hexmask.long.byte 0x00 16.--22. 1. " TDCV    ,Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the"
bitfld.long 0x00 14. "        PXE    ,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1"
textline "                      "
bitfld.long 0x00 13. " RFDF    ,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU, no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1"
bitfld.long 0x00 12. "         RBRS   ,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1"
textline "                      "
bitfld.long 0x00 11. " RESI    ,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1"
bitfld.long 0x00 8.--10. "         DLEC   ,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7"
textline "                      "
bitfld.long 0x00 7. " BO      ,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1"
bitfld.long 0x00 6. "         EW     ,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1"
textline "                      "
bitfld.long 0x00 5. " EP      ,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1"
bitfld.long 0x00 3.--4. "         ACT    ,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is operating as transmitter Note:ACT is set to 0h by a Protocol Exception Event." "0,1,2,3"
textline "                      "
bitfld.long 0x00 0.--2. " LEC     ,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame has the wrong format. 3h = AckError: The message transmitted by the MCAN module was not acknowledged by another node. 4h = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5h = Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the Host CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6h = CRCError: The CRC check sum of a received message was incorrect. The CRC of an incom-ing message does not match with the CRC calculated from the received data. 7h = NoChange: Any read access to the Protocol Status Register re-initializes the Note:When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in the MCAN_PSR[10-8] DLEC field instead of the MCAN_PSR[2-0] LEC field. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length."
hexmask.long.byte 0x00 8.--14. 1. " TDCO    ,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)."
hexmask.long.byte 0x00 0.--6. 1. "        TDCF   ,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled when the"
hgroup.long 0x50++0x3
hide.long 0x00 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register. The configuration of the register controls whether an interrupt is generated. The configuration of the register controls on which interrupt line an interrupt is signalled."
in
textline "                      "
group.long 0x54++0x3
line.long 0x00 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line."
bitfld.long 0x00 29. " ARAE    ,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 28. "         PEDE   ,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 27. " PEAE    ,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 26. "         WDIE   ,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 25. " BOE     ,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 24. "         EWE    ,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 23. " EPE     ,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 22. "         ELOE   ,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 21. " BEUE    ,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 20. "         BECE   ,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 19. " DRX     ,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x00 18. "         TOOE   ,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 17. " MRAFE   ,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 16. "         TSWE   ,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 15. " TEFLE   ,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 14. "         TEFFE  ,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " TEFWE   ,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 12. "         TEFNE  ,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 11. " TFEE    ,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 10. "         TCFE   ,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 9. " TCE     ,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 8. "         HPME   ,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " RF1LE   ,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 6. "         RF1FE  ,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " RF1WE   ,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 4. "         RF1NE  ,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 3. " RF0LE   ,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 2. "         RF0FE  ,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 1. " RF0WE   ,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 0. "         RF0NE  ,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
group.long 0x58++0x3
line.long 0x00 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via the [0] EINT0 and [1] EINT1 bits."
bitfld.long 0x00 29. " ARAL    ,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 28. "         PEDL   ,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 27. " PEAL    ,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 26. "         WDIL   ,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 25. " BOL     ,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 24. "         EWL    ,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 23. " EPL     ,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 22. "         ELOL   ,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 21. " BEUL    ,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 20. "         BECL   ,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 19. " DRXL    ,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 18. "         TOOL   ,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 17. " MRAFL   ,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 16. "         TSWL   ,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 15. " TEFLL   ,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 14. "         TEFFL  ,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 13. " TEFWL   ,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 12. "         TEFNL  ,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 11. " TFEL    ,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 10. "         TCFL   ,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 9. " TCL     ,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 8. "         HPML   ,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 7. " RF1LL   ,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 6. "         RF1FL  ,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 5. " RF1WL   ,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 4. "         RF1NL  ,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 3. " RF0LL   ,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 2. "         RF0FL  ,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 1. " RF0WL   ,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 0. "         RF0NL  ,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
group.long 0x5C++0x3
line.long 0x00 "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits."
bitfld.long 0x00 1. " EINT1   ,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1"
bitfld.long 0x00 0. "         EINT0  ,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )."
bitfld.long 0x00 4.--5. " ANFS    ,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3"
bitfld.long 0x00 2.--3. "         ANFE   ,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3"
textline "                      "
bitfld.long 0x00 1. " RRFS    ,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1"
bitfld.long 0x00 0. "         RRFE   ,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1"
group.long 0x84++0x3
line.long 0x00 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements, pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )."
hexmask.long.byte 0x00 16.--23. 1. " LSS     ,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements > 80h (128) = Values greater than 128 are interpreted as 128"
hexmask.long.word 0x00 2.--15. 1. "        FLSSA  ,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see"
group.long 0x88++0x3
line.long 0x00 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements, pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )."
hexmask.long.byte 0x00 16.--22. 1. " LSE     ,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements > 40h (64) = Values greater than 64 are interpreted as 64"
hexmask.long.word 0x00 2.--15. 1. "        FLESA  ,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see"
group.long 0x90++0x3
line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939."
hexmask.long 0x00 0.--28. 1. " EIDM    ,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
rgroup.long 0x94++0x3
line.long 0x00 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages."
bitfld.long 0x00 15. " FLST    ,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "         FIDX   ,Filter Index Index of matching filter element. Range is 0 to"
textline "                      "
bitfld.long 0x00 6.--7. " MSI     ,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3"
bitfld.long 0x00 0.--5. "         BIDX   ,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x98++0x3
hide.long 0x00 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. Aflag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register."
in
textline "                      "
hgroup.long 0x9C++0x3
hide.long 0x00 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register."
in
textline "                      "
group.long 0xA0++0x3
line.long 0x00 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode, watermark, size and start address."
bitfld.long 0x00 31. " F0OM    ,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "         F0WM   ,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( > 40h (64) = Watermark interrupt disabled"
textline "                      "
hexmask.long.byte 0x00 16.--22. 1. " F0S     ,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to"
hexmask.long.word 0x00 2.--15. 1. "        F0SA   ,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see"
rgroup.long 0xA4++0x3
line.long 0x00 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication, put index, get index and fill level."
bitfld.long 0x00 25. " RF0L    ,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will not set this flag." "0,1"
bitfld.long 0x00 24. "         F0F    ,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1"
textline "                      "
bitfld.long 0x00 16.--21. " F0PI    ,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        F0GI   ,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
hexmask.long.byte 0x00 0.--6. 1. " F0FL    ,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64."
group.long 0xA8++0x3
line.long 0x00 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers, updates get index and fill level."
bitfld.long 0x00 0.--5. " F0AI    ,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAC++0x3
line.long 0x00 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section."
hexmask.long.word 0x00 2.--15. 1. " RBSA    ,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address, see ). Also used to reference debug messages A, B, C. Note:Debug feature is not supported."
group.long 0xB0++0x3
line.long 0x00 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode, watermark, size and start address."
bitfld.long 0x00 31. " F1OM    ,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "         F1WM   ,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( > 40h (64) = Watermark interrupt disabled"
textline "                      "
hexmask.long.byte 0x00 16.--22. 1. " F1S     ,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to"
hexmask.long.word 0x00 2.--15. 1. "        F1SA   ,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see"
rgroup.long 0xB4++0x3
line.long 0x00 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication, put index, get index and fill level."
bitfld.long 0x00 30.--31. " DMS     ,Debug Message Status 0h = Idle state, wait for reception of debug messages, DMA request is cleared 1h = Debug message A received 2h = Debug messages A, B received 3h = Debug messages A, B, C received, DMA request is set Note:Debug feature is not supported." "0,1,2,3"
bitfld.long 0x00 25. "         RF1L   ,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will not set this flag." "0,1"
textline "                      "
bitfld.long 0x00 24. " F1F     ,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1"
bitfld.long 0x00 16.--21. "         F1PI   ,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
bitfld.long 0x00 8.--13. " F1GI    ,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--6. 1. "        F1FL   ,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64."
group.long 0xB8++0x3
line.long 0x00 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers, updates get index and fill level."
bitfld.long 0x00 0.--5. " F1AI    ,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC++0x3
line.long 0x00 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames."
bitfld.long 0x00 8.--10. " RBDS    ,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "         F1DS   ,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7"
textline "                      "
bitfld.long 0x00 0.--2. " F0DS    ,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by the MCAN_RXESC register are stored to the Rx Buffer respectively Rx FIFO element. The rest of the frame's data field is ignored." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode, Tx FIFO/Queue size, number of dedicated Tx buffers, Tx buffer start address."
bitfld.long 0x00 30. " TFQM    ,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1"
bitfld.long 0x00 24.--29. "         TFQS   ,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 20h (32) = Values greater than 32 are interpreted as 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
bitfld.long 0x00 16.--21. " NDTB    ,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers > 20h (32) = Values greater than 32 are interpreted as 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "        TBSA   ,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."
rgroup.long 0xC4++0x3
line.long 0x00 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index, Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (the register not yet updated)."
bitfld.long 0x00 21. " TFQF    ,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1"
bitfld.long 0x00 16.--20. "         TFQPI  ,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 8.--12. " TFGI    ,Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "        TFFL   ,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC8++0x3
line.long 0x00 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only."
bitfld.long 0x00 0.--2. " TBDS    ,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size MCAN_TXESC[2-0] TBDS, the bytes not defined by the Tx Buffer are transmitted as CCh (padding bytes)." "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x00 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been cancelled via the register. The bits are set only for those Tx Buffers configured via the register. After a bit has been set, a Tx scan (see , Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register the register. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via the flag ? after successful transmission together with the corresponding bit ? when the transmission has not yet been started at the point of cancellation ? when the transmission has been aborted due to lost arbitration ? when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding bit is set for all unsuccessful transmissions. Note: The bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding bit is reset."
bitfld.long 0x00 31. " TRP31   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 30. "         TRP30  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 29. " TRP29   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 28. "         TRP28  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 27. " TRP27   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 26. "         TRP26  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 25. " TRP25   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 24. "         TRP24  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 23. " TRP23   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 22. "         TRP22  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 21. " TRP21   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 20. "         TRP20  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 19. " TRP19   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 18. "         TRP18  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 17. " TRP17   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 16. "         TRP16  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 15. " TRP15   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 14. "         TRP14  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 13. " TRP13   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 12. "         TRP12  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 11. " TRP11   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 10. "         TRP10  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 9. " TRP9    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 8. "         TRP8   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 7. " TRP7    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 6. "         TRP6   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 5. " TRP5    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 4. "         TRP4   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 3. " TRP3    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 2. "         TRP2   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 1. " TRP1    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 0. "         TRP0   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
hgroup.long 0xD0++0x3
hide.long 0x00 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple Tx Buffers with one write to the register. The bits are set only for those Tx Buffers configured via the register. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding bit already set), this add request is ignored."
in
textline "                      "
hgroup.long 0xD4++0x3
hide.long 0x00 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the Host CPU to set cancellation requests for multiple Tx Buffers with one write to the register. The bits are set only for those Tx Buffers configured via the register. The bits remain set until the corresponding bit of the register is reset."
in
textline "                      "
rgroup.long 0xD8++0x3
line.long 0x00 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions, set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of register the register."
bitfld.long 0x00 31. " TO31    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 30. "         TO30   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 29. " TO29    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 28. "         TO28   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 27. " TO27    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 26. "         TO26   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 25. " TO25    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 24. "         TO24   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 23. " TO23    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 22. "         TO22   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 21. " TO21    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 20. "         TO20   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 19. " TO19    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 18. "         TO18   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 17. " TO17    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 16. "         TO16   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 15. " TO15    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 14. "         TO14   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 13. " TO13    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 12. "         TO12   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 11. " TO11    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 10. "         TO10   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 9. " TO9     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 8. "         TO8    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 7. " TO7     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 6. "         TO6    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 5. " TO5     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 4. "         TO4    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 3. " TO3     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 2. "         TO2    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 1. " TO1     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 0. "         TO0    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
rgroup.long 0xDC++0x3
line.long 0x00 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation, set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is cleared after a cancellation was requested via the register. In case the corresponding bit was not set at the point of cancellation, [n] CF bit is set immediately. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of the register."
bitfld.long 0x00 31. " CF31    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 30. "         CF30   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 29. " CF29    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 28. "         CF28   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 27. " CF27    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 26. "         CF26   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 25. " CF25    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 24. "         CF24   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 23. " CF23    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 22. "         CF22   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 21. " CF21    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 20. "         CF20   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 19. " CF19    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 18. "         CF18   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 17. " CF17    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 16. "         CF16   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 15. " CF15    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 14. "         CF14   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 13. " CF13    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 12. "         CF12   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 11. " CF11    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 10. "         CF10   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 9. " CF9     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 8. "         CF8    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 7. " CF7     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 6. "         CF6    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 5. " CF5     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 4. "         CF4    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 3. " CF3     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 2. "         CF2    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 1. " CF1     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 0. "         CF0    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
group.long 0xE0++0x3
line.long 0x00 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers."
bitfld.long 0x00 31. " TIE31   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 30. "         TIE30  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 29. " TIE29   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 28. "         TIE28  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 27. " TIE27   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 26. "         TIE26  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 25. " TIE25   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 24. "         TIE24  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 23. " TIE23   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 22. "         TIE22  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 21. " TIE21   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 20. "         TIE20  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 19. " TIE19   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 18. "         TIE18  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 17. " TIE17   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 16. "         TIE16  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 15. " TIE15   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 14. "         TIE14  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 13. " TIE13   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 12. "         TIE12  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 11. " TIE11   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 10. "         TIE10  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 9. " TIE9    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 8. "         TIE8   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 7. " TIE7    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 6. "         TIE6   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 5. " TIE5    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 4. "         TIE4   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 3. " TIE3    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 2. "         TIE2   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 1. " TIE1    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 0. "         TIE0   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
group.long 0xE4++0x3
line.long 0x00 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers."
bitfld.long 0x00 31. " CFIE31  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 30. "         CFIE30 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 29. " CFIE29  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 28. "         CFIE28 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 27. " CFIE27  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 26. "         CFIE26 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 25. " CFIE25  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 24. "         CFIE24 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 23. " CFIE23  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 22. "         CFIE22 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 21. " CFIE21  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 20. "         CFIE20 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 19. " CFIE19  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 18. "         CFIE18 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 17. " CFIE17  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 16. "         CFIE16 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 15. " CFIE15  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 14. "         CFIE14 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " CFIE13  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 12. "         CFIE12 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 11. " CFIE11  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 10. "         CFIE10 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 9. " CFIE9   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 8. "         CFIE8  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " CFIE7   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 6. "         CFIE6  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " CFIE5   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 4. "         CFIE4  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 3. " CFIE3   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 2. "         CFIE2  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 1. " CFIE1   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 0. "         CFIE0  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
group.long 0xF0++0x3
line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark, size and start address."
bitfld.long 0x00 24.--29. " EFWM    ,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( > 20h (32) = Watermark interrupt disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        EFS    ,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements > 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
hexmask.long.word 0x00 2.--15. 1. " EFSA    ,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see"
rgroup.long 0xF4++0x3
line.long 0x00 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication, put index, get index, and fill level."
bitfld.long 0x00 25. " TEFL    ,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero." "0,1"
bitfld.long 0x00 24. "         EFF    ,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1"
textline "                      "
bitfld.long 0x00 16.--20. " EFPI    ,Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        EFGI   ,Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 0.--5. " EFFL    ,Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x3
line.long 0x00 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements, updates get index and fill level."
bitfld.long 0x00 0.--4. " EFAI    ,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "MCU_MCAN1_CFG"
base ad:0x40568000
width 13.
rgroup.long 0x0++0x3
line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)."
bitfld.long 0x00 28.--31. " REL     ,Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        STEP   ,Step of Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        YEAR   ,Time Stamp Year One digit, BCD-coded." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
hexmask.long.byte 0x00 8.--15. 1. " MON     ,Time Stamp Month Two digits, BCD-coded."
hexmask.long.byte 0x00 0.--7. 1. "        DAY    ,Time Stamp Day Two digits, BCD-coded."
rgroup.long 0x4++0x3
line.long 0x00 "MCAN_ENDN,Endian Register Constant 8765 4321h."
hexmask.long 0x00 0.--31. 1. " ETV     ,Endianness Test Value The endianness test value is 8765 4321h."
group.long 0xC++0x3
line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing, transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 MCAN functional clock periods. tq = ([20-16] DBRP + 1) mtq (minimum time quantum = CAN clock period (MCAN functional clock)). The [12-8] DTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The [7-4] DTSEG2 field is Phase_Seg2. Therefore the length of the bit time is (programmed values) [[12-8] DTSEG1 + [7-4] DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0000 0A33h configures the MCAN module for a data phase bit rate of 500 kbit/s. Note: The bit rate configured for the CAN FD data phase via the register must be higher or equal to the bit rate configured for the arbitration phase via the register."
bitfld.long 0x00 23. " TDC     ,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1"
bitfld.long 0x00 16.--20. "         DBRP   ,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 8.--12. " DTSEG1  ,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "        DTSEG2 ,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 0.--3. " DSJW    ,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loop Back Mode and software control of the MCAN TX pin are hardware test modes. Programming of the [6-5] TX field ? 00 may disturb the message transfer on the CAN bus."
bitfld.long 0x00 7. " RX      ,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1"
bitfld.long 0x00 5.--6. "         TX     ,Control of Transmit Pin 0h = Reset value, the MCAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the MCAN TX pin" "0,1,2,3"
textline "                      "
bitfld.long 0x00 4. " LBCK    ,Loop Back Mode 0h = Reset value, Loop Back Mode is disabled 1h = Loop Back Mode is enabled (see , Test Modes)" "0,1"
group.long 0x14++0x3
line.long 0x00 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter is reloaded with the [7-0] WDC field when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag [26] WDI is set. The RAM Watchdog Counter is clocked by the Host clock (MCAN interface clock)."
hexmask.long.byte 0x00 8.--15. 1. " WDV     ,Watchdog Value Actual Message RAM Watchdog Counter Value."
hexmask.long.byte 0x00 0.--7. 1. "        WDC    ,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled."
group.long 0x18++0x3
line.long 0x00 "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits, see , Software Initialization."
bitfld.long 0x00 15. " NISO    ,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1"
bitfld.long 0x00 14. "         TXP    ,Transmit Pause If this bit is set, the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see , Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " EFBI    ,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1"
bitfld.long 0x00 12. "         PXHD   ,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled, the MCAN module will transmit an error frame when it detects a protocol exception condition." "0,1"
textline "                      "
bitfld.long 0x00 9. " BRSE    ,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h, the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1"
bitfld.long 0x00 8. "         FDOE   ,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " TEST    ,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1"
bitfld.long 0x00 6. "         DAR    ,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " MON     ,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1"
bitfld.long 0x00 4. "         CSR    ,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested, first the" "0,1"
textline "                      "
bitfld.long 0x00 3. " CSA     ,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1"
bitfld.long 0x00 2. "         ASM    ,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1"
textline "                      "
bitfld.long 0x00 1. " CCE     ,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1"
bitfld.long 0x00 0. "         INIT   ,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the software has to assure that the previous value written to the MCAN_CCCR[0] INIT bit has been accepted by reading the MCAN_CCCR[0] INIT bit before setting the MCAN_CCCR[0] INIT bit to a new value." "0,1"
group.long 0x1C++0x3
line.long 0x00 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 MCAN functional clock periods. tq = ([24-16] NBRP + 1) mtq. The [15-8] NTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The [6-0] NTSEG2 field is Phase_Seg2. Therefore the length of the bit time is (programmed values) [[15-8] NTSEG1 + [6-0] NTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point."
hexmask.long.byte 0x00 25.--31. 1. " NSJW    ,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
hexmask.long.word 0x00 16.--24. 1. "        NBRP   ,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
textline "                      "
hexmask.long.byte 0x00 8.--15. 1. " NTSEG1  ,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
hexmask.long.byte 0x00 0.--6. 1. "        NTSEG2 ,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0600 0A03h configures the MCAN module for a bit rate of 500 kbit/s."
group.long 0x20++0x3
line.long 0x00 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting, selection of internal/external timestamp vector. For a description of the Timestamp Counter, see , Timestamp Generation."
bitfld.long 0x00 16.--19. " TCP     ,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note:With CAN FD an external counter is required for timestamp generation (MCAN_TSCC[1-0] TSS = 2h)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        TSS    ,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3"
group.long 0x24++0x3
line.long 0x00 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter."
hexmask.long.word 0x00 0.--15. 1. " TSC     ,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to the MCAN_TSCV register."
group.long 0x28++0x3
line.long 0x00 "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period, selection of timeout counter operation mode. For a description of the Timeout Counter, see , Timeout Counter."
hexmask.long.word 0x00 16.--31. 1. " TOP     ,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."
bitfld.long 0x00 1.--2. "      TOS    ,Timeout Select When operating in Continuous mode, a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3"
textline "                      "
bitfld.long 0x00 0. " ETOC    ,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1"
group.long 0x2C++0x3
line.long 0x00 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter."
hexmask.long.word 0x00 0.--15. 1. " TOC     ,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the"
rgroup.long 0x40++0x3
line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter, CAN Error Logging."
hexmask.long.byte 0x00 16.--23. 1. " CEL     ,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the"
bitfld.long 0x00 15. "        RP     ,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1"
textline "                      "
hexmask.long.byte 0x00 8.--14. 1. " REC     ,Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127."
hexmask.long.byte 0x00 0.--7. 1. "        TEC    ,Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set, the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN protocol error is detected, but the MCAN_ECR[23-16] CEL field is still incremented."
rgroup.long 0x44++0x3
line.long 0x00 "MCAN_PSR,Protocol Status Register CAN protocol controller status, transmitter delay compensation value."
hexmask.long.byte 0x00 16.--22. 1. " TDCV    ,Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the"
bitfld.long 0x00 14. "        PXE    ,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1"
textline "                      "
bitfld.long 0x00 13. " RFDF    ,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU, no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1"
bitfld.long 0x00 12. "         RBRS   ,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1"
textline "                      "
bitfld.long 0x00 11. " RESI    ,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1"
bitfld.long 0x00 8.--10. "         DLEC   ,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7"
textline "                      "
bitfld.long 0x00 7. " BO      ,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1"
bitfld.long 0x00 6. "         EW     ,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1"
textline "                      "
bitfld.long 0x00 5. " EP      ,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1"
bitfld.long 0x00 3.--4. "         ACT    ,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is operating as transmitter Note:ACT is set to 0h by a Protocol Exception Event." "0,1,2,3"
textline "                      "
bitfld.long 0x00 0.--2. " LEC     ,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame has the wrong format. 3h = AckError: The message transmitted by the MCAN module was not acknowledged by another node. 4h = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5h = Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the Host CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6h = CRCError: The CRC check sum of a received message was incorrect. The CRC of an incom-ing message does not match with the CRC calculated from the received data. 7h = NoChange: Any read access to the Protocol Status Register re-initializes the Note:When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in the MCAN_PSR[10-8] DLEC field instead of the MCAN_PSR[2-0] LEC field. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x00 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length."
hexmask.long.byte 0x00 8.--14. 1. " TDCO    ,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)."
hexmask.long.byte 0x00 0.--6. 1. "        TDCF   ,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled when the"
hgroup.long 0x50++0x3
hide.long 0x00 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register. The configuration of the register controls whether an interrupt is generated. The configuration of the register controls on which interrupt line an interrupt is signalled."
in
textline "                      "
group.long 0x54++0x3
line.long 0x00 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line."
bitfld.long 0x00 29. " ARAE    ,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 28. "         PEDE   ,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 27. " PEAE    ,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 26. "         WDIE   ,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 25. " BOE     ,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 24. "         EWE    ,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 23. " EPE     ,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 22. "         ELOE   ,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 21. " BEUE    ,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 20. "         BECE   ,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 19. " DRX     ,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x00 18. "         TOOE   ,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 17. " MRAFE   ,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 16. "         TSWE   ,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 15. " TEFLE   ,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 14. "         TEFFE  ,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " TEFWE   ,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 12. "         TEFNE  ,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 11. " TFEE    ,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 10. "         TCFE   ,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 9. " TCE     ,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 8. "         HPME   ,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " RF1LE   ,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 6. "         RF1FE  ,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " RF1WE   ,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 4. "         RF1NE  ,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 3. " RF0LE   ,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 2. "         RF0FE  ,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 1. " RF0WE   ,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
bitfld.long 0x00 0. "         RF0NE  ,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1"
group.long 0x58++0x3
line.long 0x00 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via the [0] EINT0 and [1] EINT1 bits."
bitfld.long 0x00 29. " ARAL    ,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 28. "         PEDL   ,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 27. " PEAL    ,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 26. "         WDIL   ,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 25. " BOL     ,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 24. "         EWL    ,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 23. " EPL     ,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 22. "         ELOL   ,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 21. " BEUL    ,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 20. "         BECL   ,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 19. " DRXL    ,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 18. "         TOOL   ,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 17. " MRAFL   ,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 16. "         TSWL   ,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 15. " TEFLL   ,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 14. "         TEFFL  ,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 13. " TEFWL   ,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 12. "         TEFNL  ,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 11. " TFEL    ,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 10. "         TCFL   ,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 9. " TCL     ,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 8. "         HPML   ,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 7. " RF1LL   ,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 6. "         RF1FL  ,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 5. " RF1WL   ,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 4. "         RF1NL  ,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 3. " RF0LL   ,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 2. "         RF0FL  ,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
textline "                      "
bitfld.long 0x00 1. " RF0WL   ,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
bitfld.long 0x00 0. "         RF0NL  ,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1"
group.long 0x5C++0x3
line.long 0x00 "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits."
bitfld.long 0x00 1. " EINT1   ,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1"
bitfld.long 0x00 0. "         EINT0  ,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )."
bitfld.long 0x00 4.--5. " ANFS    ,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3"
bitfld.long 0x00 2.--3. "         ANFE   ,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3"
textline "                      "
bitfld.long 0x00 1. " RRFS    ,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1"
bitfld.long 0x00 0. "         RRFE   ,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1"
group.long 0x84++0x3
line.long 0x00 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements, pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )."
hexmask.long.byte 0x00 16.--23. 1. " LSS     ,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements > 80h (128) = Values greater than 128 are interpreted as 128"
hexmask.long.word 0x00 2.--15. 1. "        FLSSA  ,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see"
group.long 0x88++0x3
line.long 0x00 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements, pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )."
hexmask.long.byte 0x00 16.--22. 1. " LSE     ,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements > 40h (64) = Values greater than 64 are interpreted as 64"
hexmask.long.word 0x00 2.--15. 1. "        FLESA  ,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see"
group.long 0x90++0x3
line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939."
hexmask.long 0x00 0.--28. 1. " EIDM    ,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."
rgroup.long 0x94++0x3
line.long 0x00 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages."
bitfld.long 0x00 15. " FLST    ,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "         FIDX   ,Filter Index Index of matching filter element. Range is 0 to"
textline "                      "
bitfld.long 0x00 6.--7. " MSI     ,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3"
bitfld.long 0x00 0.--5. "         BIDX   ,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x98++0x3
hide.long 0x00 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. Aflag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register."
in
textline "                      "
hgroup.long 0x9C++0x3
hide.long 0x00 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register."
in
textline "                      "
group.long 0xA0++0x3
line.long 0x00 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode, watermark, size and start address."
bitfld.long 0x00 31. " F0OM    ,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "         F0WM   ,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( > 40h (64) = Watermark interrupt disabled"
textline "                      "
hexmask.long.byte 0x00 16.--22. 1. " F0S     ,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to"
hexmask.long.word 0x00 2.--15. 1. "        F0SA   ,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see"
rgroup.long 0xA4++0x3
line.long 0x00 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication, put index, get index and fill level."
bitfld.long 0x00 25. " RF0L    ,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will not set this flag." "0,1"
bitfld.long 0x00 24. "         F0F    ,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1"
textline "                      "
bitfld.long 0x00 16.--21. " F0PI    ,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "        F0GI   ,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
hexmask.long.byte 0x00 0.--6. 1. " F0FL    ,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64."
group.long 0xA8++0x3
line.long 0x00 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers, updates get index and fill level."
bitfld.long 0x00 0.--5. " F0AI    ,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAC++0x3
line.long 0x00 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section."
hexmask.long.word 0x00 2.--15. 1. " RBSA    ,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address, see ). Also used to reference debug messages A, B, C. Note:Debug feature is not supported."
group.long 0xB0++0x3
line.long 0x00 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode, watermark, size and start address."
bitfld.long 0x00 31. " F1OM    ,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "         F1WM   ,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( > 40h (64) = Watermark interrupt disabled"
textline "                      "
hexmask.long.byte 0x00 16.--22. 1. " F1S     ,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to"
hexmask.long.word 0x00 2.--15. 1. "        F1SA   ,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see"
rgroup.long 0xB4++0x3
line.long 0x00 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication, put index, get index and fill level."
bitfld.long 0x00 30.--31. " DMS     ,Debug Message Status 0h = Idle state, wait for reception of debug messages, DMA request is cleared 1h = Debug message A received 2h = Debug messages A, B received 3h = Debug messages A, B, C received, DMA request is set Note:Debug feature is not supported." "0,1,2,3"
bitfld.long 0x00 25. "         RF1L   ,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will not set this flag." "0,1"
textline "                      "
bitfld.long 0x00 24. " F1F     ,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1"
bitfld.long 0x00 16.--21. "         F1PI   ,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
bitfld.long 0x00 8.--13. " F1GI    ,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--6. 1. "        F1FL   ,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64."
group.long 0xB8++0x3
line.long 0x00 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers, updates get index and fill level."
bitfld.long 0x00 0.--5. " F1AI    ,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC++0x3
line.long 0x00 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames."
bitfld.long 0x00 8.--10. " RBDS    ,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "         F1DS   ,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7"
textline "                      "
bitfld.long 0x00 0.--2. " F0DS    ,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by the MCAN_RXESC register are stored to the Rx Buffer respectively Rx FIFO element. The rest of the frame's data field is ignored." "0,1,2,3,4,5,6,7"
group.long 0xC0++0x3
line.long 0x00 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode, Tx FIFO/Queue size, number of dedicated Tx buffers, Tx buffer start address."
bitfld.long 0x00 30. " TFQM    ,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1"
bitfld.long 0x00 24.--29. "         TFQS   ,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 20h (32) = Values greater than 32 are interpreted as 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
bitfld.long 0x00 16.--21. " NDTB    ,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers > 20h (32) = Values greater than 32 are interpreted as 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "        TBSA   ,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."
rgroup.long 0xC4++0x3
line.long 0x00 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index, Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (the register not yet updated)."
bitfld.long 0x00 21. " TFQF    ,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1"
bitfld.long 0x00 16.--20. "         TFQPI  ,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 8.--12. " TFGI    ,Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "        TFFL   ,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC8++0x3
line.long 0x00 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only."
bitfld.long 0x00 0.--2. " TBDS    ,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size MCAN_TXESC[2-0] TBDS, the bytes not defined by the Tx Buffer are transmitted as CCh (padding bytes)." "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x00 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been cancelled via the register. The bits are set only for those Tx Buffers configured via the register. After a bit has been set, a Tx scan (see , Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register the register. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via the flag ? after successful transmission together with the corresponding bit ? when the transmission has not yet been started at the point of cancellation ? when the transmission has been aborted due to lost arbitration ? when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding bit is set for all unsuccessful transmissions. Note: The bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding bit is reset."
bitfld.long 0x00 31. " TRP31   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 30. "         TRP30  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 29. " TRP29   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 28. "         TRP28  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 27. " TRP27   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 26. "         TRP26  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 25. " TRP25   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 24. "         TRP24  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 23. " TRP23   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 22. "         TRP22  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 21. " TRP21   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 20. "         TRP20  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 19. " TRP19   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 18. "         TRP18  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 17. " TRP17   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 16. "         TRP16  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 15. " TRP15   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 14. "         TRP14  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 13. " TRP13   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 12. "         TRP12  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 11. " TRP11   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 10. "         TRP10  ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 9. " TRP9    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 8. "         TRP8   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 7. " TRP7    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 6. "         TRP6   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 5. " TRP5    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 4. "         TRP4   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 3. " TRP3    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 2. "         TRP2   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
textline "                      "
bitfld.long 0x00 1. " TRP1    ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
bitfld.long 0x00 0. "         TRP0   ,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1"
hgroup.long 0xD0++0x3
hide.long 0x00 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple Tx Buffers with one write to the register. The bits are set only for those Tx Buffers configured via the register. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding bit already set), this add request is ignored."
in
textline "                      "
hgroup.long 0xD4++0x3
hide.long 0x00 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the Host CPU to set cancellation requests for multiple Tx Buffers with one write to the register. The bits are set only for those Tx Buffers configured via the register. The bits remain set until the corresponding bit of the register is reset."
in
textline "                      "
rgroup.long 0xD8++0x3
line.long 0x00 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions, set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of register the register."
bitfld.long 0x00 31. " TO31    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 30. "         TO30   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 29. " TO29    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 28. "         TO28   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 27. " TO27    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 26. "         TO26   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 25. " TO25    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 24. "         TO24   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 23. " TO23    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 22. "         TO22   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 21. " TO21    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 20. "         TO20   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 19. " TO19    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 18. "         TO18   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 17. " TO17    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 16. "         TO16   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 15. " TO15    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 14. "         TO14   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 13. " TO13    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 12. "         TO12   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 11. " TO11    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 10. "         TO10   ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 9. " TO9     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 8. "         TO8    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 7. " TO7     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 6. "         TO6    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 5. " TO5     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 4. "         TO4    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 3. " TO3     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 2. "         TO2    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
textline "                      "
bitfld.long 0x00 1. " TO1     ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
bitfld.long 0x00 0. "         TO0    ,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1"
rgroup.long 0xDC++0x3
line.long 0x00 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation, set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is cleared after a cancellation was requested via the register. In case the corresponding bit was not set at the point of cancellation, [n] CF bit is set immediately. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of the register."
bitfld.long 0x00 31. " CF31    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 30. "         CF30   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 29. " CF29    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 28. "         CF28   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 27. " CF27    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 26. "         CF26   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 25. " CF25    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 24. "         CF24   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 23. " CF23    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 22. "         CF22   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 21. " CF21    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 20. "         CF20   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 19. " CF19    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 18. "         CF18   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 17. " CF17    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 16. "         CF16   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 15. " CF15    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 14. "         CF14   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 13. " CF13    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 12. "         CF12   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 11. " CF11    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 10. "         CF10   ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 9. " CF9     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 8. "         CF8    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 7. " CF7     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 6. "         CF6    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 5. " CF5     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 4. "         CF4    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 3. " CF3     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 2. "         CF2    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
textline "                      "
bitfld.long 0x00 1. " CF1     ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
bitfld.long 0x00 0. "         CF0    ,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1"
group.long 0xE0++0x3
line.long 0x00 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers."
bitfld.long 0x00 31. " TIE31   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 30. "         TIE30  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 29. " TIE29   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 28. "         TIE28  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 27. " TIE27   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 26. "         TIE26  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 25. " TIE25   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 24. "         TIE24  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 23. " TIE23   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 22. "         TIE22  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 21. " TIE21   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 20. "         TIE20  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 19. " TIE19   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 18. "         TIE18  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 17. " TIE17   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 16. "         TIE16  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 15. " TIE15   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 14. "         TIE14  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 13. " TIE13   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 12. "         TIE12  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 11. " TIE11   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 10. "         TIE10  ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 9. " TIE9    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 8. "         TIE8   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 7. " TIE7    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 6. "         TIE6   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 5. " TIE5    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 4. "         TIE4   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 3. " TIE3    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 2. "         TIE2   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
textline "                      "
bitfld.long 0x00 1. " TIE1    ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
bitfld.long 0x00 0. "         TIE0   ,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1"
group.long 0xE4++0x3
line.long 0x00 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers."
bitfld.long 0x00 31. " CFIE31  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 30. "         CFIE30 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 29. " CFIE29  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 28. "         CFIE28 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 27. " CFIE27  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 26. "         CFIE26 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 25. " CFIE25  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 24. "         CFIE24 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 23. " CFIE23  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 22. "         CFIE22 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 21. " CFIE21  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 20. "         CFIE20 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 19. " CFIE19  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 18. "         CFIE18 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 17. " CFIE17  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 16. "         CFIE16 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 15. " CFIE15  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 14. "         CFIE14 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 13. " CFIE13  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 12. "         CFIE12 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 11. " CFIE11  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 10. "         CFIE10 ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 9. " CFIE9   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 8. "         CFIE8  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 7. " CFIE7   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 6. "         CFIE6  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 5. " CFIE5   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 4. "         CFIE4  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 3. " CFIE3   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 2. "         CFIE2  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
textline "                      "
bitfld.long 0x00 1. " CFIE1   ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
bitfld.long 0x00 0. "         CFIE0  ,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1"
group.long 0xF0++0x3
line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark, size and start address."
bitfld.long 0x00 24.--29. " EFWM    ,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( > 20h (32) = Watermark interrupt disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        EFS    ,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements > 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                      "
hexmask.long.word 0x00 2.--15. 1. " EFSA    ,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see"
rgroup.long 0xF4++0x3
line.long 0x00 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication, put index, get index, and fill level."
bitfld.long 0x00 25. " TEFL    ,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero." "0,1"
bitfld.long 0x00 24. "         EFF    ,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1"
textline "                      "
bitfld.long 0x00 16.--20. " EFPI    ,Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "        EFGI   ,Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                      "
bitfld.long 0x00 0.--5. " EFFL    ,Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x3
line.long 0x00 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements, updates get index and fill level."
bitfld.long 0x00 0.--4. " EFAI    ,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "MCU_MCAN0_MSGMEM_RAM"
base ad:0x40700000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator."
bitfld.long 0x00 30.--31. " SCHEME                    ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                ,Business Unit" "0,1,2,3"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                 ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL            ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " REVMAJ                    ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM            ,Custom Version" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--5. " REVMIN                    ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
in
textline "                                         "
rgroup.long 0xC++0x3
line.long 0x00 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                  ,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator."
group.long 0x3C++0x3
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR                    ,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND       ,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_PEND       ,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_ENABLE_SET ,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_ENABLE_SET ,Interrupt Enable Set for MSGMEM_PEND" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                         "
group.long 0x13C++0x3
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR                    ,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
group.long 0x140++0x3
line.long 0x00 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND       ,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_PEND       ,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x3
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_ENABLE_SET ,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_ENABLE_SET ,Interrupt Enable Set for MSGMEM_PEND" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                         "
group.long 0x200++0x3
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT                   ,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "     PARITY            ,Interrupt Enable Set for Parity Errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                         "
group.long 0x208++0x3
line.long 0x00 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY            ,Interrupt Status Set for Parity Errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY            ,Interrupt Status Clear for Parity Errors" "0,1,2,3"
width 0x0B
tree.end
tree "MCU_MCAN1_MSGMEM_RAM"
base ad:0x40701000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator."
bitfld.long 0x00 30.--31. " SCHEME                    ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                ,Business Unit" "0,1,2,3"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                 ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL            ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " REVMAJ                    ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM            ,Custom Version" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 0.--5. " REVMIN                    ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
in
textline "                                         "
rgroup.long 0xC++0x3
line.long 0x00 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                  ,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator."
group.long 0x3C++0x3
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR                    ,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND       ,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_PEND       ,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_ENABLE_SET ,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_ENABLE_SET ,Interrupt Enable Set for MSGMEM_PEND" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                         "
group.long 0x13C++0x3
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR                    ,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
group.long 0x140++0x3
line.long 0x00 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND       ,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_PEND       ,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x3
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_ENABLE_SET ,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "     MSGMEM_ENABLE_SET ,Interrupt Enable Set for MSGMEM_PEND" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                         "
group.long 0x200++0x3
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT                   ,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "     PARITY            ,Interrupt Enable Set for Parity Errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                         "
group.long 0x208++0x3
line.long 0x00 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY            ,Interrupt Status Set for Parity Errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                   ,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY            ,Interrupt Status Clear for Parity Errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "MCASP"
tree "MCASP0_CFG"
base ad:0x2B00000
width 24.
rgroup.long 0x0++0x3
line.long 0x00 "MCASP_PID,"
bitfld.long 0x00 30.--31. " SCHEME    ," "0,1,2,3"
bitfld.long 0x00 28.--29. "            RESV     ," "0,1,2,3"
textline "                                 "
hexmask.long.word 0x00 16.--27. 1. " FUNCTION  ,McASP"
bitfld.long 0x00 11.--15. "         RTL      ," "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 8.--10. " REVMAJOR  ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "            CUSTOM   ,non-custom" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 0.--5. " REVMINOR  ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register."
hexmask.long 0x00 6.--31. 1. " RSV       ,Reserved as per PDR 35"
bitfld.long 0x00 2.--5. "     Other    ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--1. " IDLE_MODE ,Idle Mode" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "MCASP_PFUNC,"
bitfld.long 0x00 31. " AFSR      ,AFSR PFUNC 31" "MCASP,GPIO"
bitfld.long 0x00 30. "        AHCLKR   ,AHCLKR PFUNC 30" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PFUNC 29" "MCASP,GPIO"
bitfld.long 0x00 28. "        AFSX     ,AFSX PFUNC 28" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PFUNC 27" "MCASP,GPIO"
bitfld.long 0x00 26. "        ACLKX    ,ACLKX PFUNC 26" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PFUNC 25" "MCASP,GPIO"
hexmask.long.word 0x00 16.--24. 1. "        RESV1    ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PFUNC BIT 15" "MCASP,GPIO"
bitfld.long 0x00 14. "        AXR14    ,AXR PFUNC BIT 14" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PFUNC BIT 13" "MCASP,GPIO"
bitfld.long 0x00 12. "        AXR12    ,AXR PFUNC BIT 12" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PFUNC BIT 11" "MCASP,GPIO"
bitfld.long 0x00 10. "        AXR10    ,AXR PFUNC BIT 10" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PFUNC BIT 9" "MCASP,GPIO"
bitfld.long 0x00 8. "        AXR8     ,AXR PFUNC BIT 8" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PFUNC BIT 7" "MCASP,GPIO"
bitfld.long 0x00 6. "        AXR6     ,AXR PFUNC BIT 6" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PFUNC BIT 5" "MCASP,GPIO"
bitfld.long 0x00 4. "        AXR4     ,AXR PFUNC BIT 4" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PFUNC BIT 3" "MCASP,GPIO"
bitfld.long 0x00 2. "        AXR2     ,AXR PFUNC BIT 2" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PFUNC BIT 1" "MCASP,GPIO"
bitfld.long 0x00 0. "        AXR0     ,AXR PFUNC BIT 0" "MCASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "MCASP_PDIR,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDIR 31" "INPUT,OUTPUT"
bitfld.long 0x00 30. "       AHCLKR   ,AHCLKR PDIR 30" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIR 29" "INPUT,OUTPUT"
bitfld.long 0x00 28. "       AFSX     ,AFSX PDIR 28" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIR 27" "INPUT,OUTPUT"
bitfld.long 0x00 26. "       ACLKX    ,ACLKX PDIR 26" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIR 25" "INPUT,OUTPUT"
hexmask.long.word 0x00 16.--24. 1. "       RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIR BIT 15" "INPUT,OUTPUT"
bitfld.long 0x00 14. "       AXR14    ,AXR PDIR BIT 14" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIR BIT 13" "INPUT,OUTPUT"
bitfld.long 0x00 12. "       AXR12    ,AXR PDIR BIT 12" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIR BIT 11" "INPUT,OUTPUT"
bitfld.long 0x00 10. "       AXR10    ,AXR PDIR BIT 10" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIR BIT 9" "INPUT,OUTPUT"
bitfld.long 0x00 8. "       AXR8     ,AXR PDIR BIT 8" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIR BIT 7" "INPUT,OUTPUT"
bitfld.long 0x00 6. "       AXR6     ,AXR PDIR BIT 6" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIR BIT 5" "INPUT,OUTPUT"
bitfld.long 0x00 4. "       AXR4     ,AXR PDIR BIT 4" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIR BIT 3" "INPUT,OUTPUT"
bitfld.long 0x00 2. "       AXR2     ,AXR PDIR BIT 2" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIR BIT 1" "INPUT,OUTPUT"
bitfld.long 0x00 0. "       AXR0     ,AXR PDIR BIT 0" "INPUT,OUTPUT"
group.long 0x18++0x3
line.long 0x00 "MCASP_PDOUT,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDOUT 31" "DRV0,DRV1"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDOUT 30" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDOUT 29" "DRV0,DRV1"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDOUT 28" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDOUT 27" "DRV0,DRV1"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDOUT 26" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDOUT 25" "DRV0,DRV1"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDOUT BIT 15" "DRV0,DRV1"
bitfld.long 0x00 14. "         AXR14    ,AXR PDOUT BIT 14" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDOUT BIT 13" "DRV0,DRV1"
bitfld.long 0x00 12. "         AXR12    ,AXR PDOUT BIT 12" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDOUT BIT 11" "DRV0,DRV1"
bitfld.long 0x00 10. "         AXR10    ,AXR PDOUT BIT 10" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDOUT BIT 9" "DRV0,DRV1"
bitfld.long 0x00 8. "         AXR8     ,AXR PDOUT BIT 8" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDOUT BIT 7" "DRV0,DRV1"
bitfld.long 0x00 6. "         AXR6     ,AXR PDOUT BIT 6" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDOUT BIT 5" "DRV0,DRV1"
bitfld.long 0x00 4. "         AXR4     ,AXR PDOUT BIT 4" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDOUT BIT 3" "DRV0,DRV1"
bitfld.long 0x00 2. "         AXR2     ,AXR PDOUT BIT 2" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDOUT BIT 1" "DRV0,DRV1"
bitfld.long 0x00 0. "         AXR0     ,AXR PDOUT BIT 0" "DRV0,DRV1"
rgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read, regardless of the state of PFUNC and PDIR."
bitfld.long 0x00 31. " AFSR      ,AFSR PDIN 31" "LOW,HIGH"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDIN 30" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIN 29" "LOW,HIGH"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDIN 28" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIN 27" "LOW,HIGH"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDIN 26" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIN 25" "LOW,HIGH"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIN BIT 15" "LOW,HIGH"
bitfld.long 0x00 14. "         AXR14    ,AXR PDIN BIT 14" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIN BIT 13" "LOW,HIGH"
bitfld.long 0x00 12. "         AXR12    ,AXR PDIN BIT 12" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIN BIT 11" "LOW,HIGH"
bitfld.long 0x00 10. "         AXR10    ,AXR PDIN BIT 10" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIN BIT 9" "LOW,HIGH"
bitfld.long 0x00 8. "         AXR8     ,AXR PDIN BIT 8" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIN BIT 7" "LOW,HIGH"
bitfld.long 0x00 6. "         AXR6     ,AXR PDIN BIT 6" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIN BIT 5" "LOW,HIGH"
bitfld.long 0x00 4. "         AXR4     ,AXR PDIN BIT 4" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIN BIT 3" "LOW,HIGH"
bitfld.long 0x00 2. "         AXR2     ,AXR PDIN BIT 2" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIN BIT 1" "LOW,HIGH"
bitfld.long 0x00 0. "         AXR0     ,AXR PDIN BIT 0" "LOW,HIGH"
wgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic high on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDSET 31" "NOEFFECT,SET"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDSET 30" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDSET 29" "NOEFFECT,SET"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDSET 28" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDSET 27" "NOEFFECT,SET"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDSET 26" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDSET 25" "NOEFFECT,SET"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDSET BIT 15" "NOEFFECT,SET"
bitfld.long 0x00 14. "     AXR14    ,AXR PDSET BIT 14" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDSET BIT 13" "NOEFFECT,SET"
bitfld.long 0x00 12. "     AXR12    ,AXR PDSET BIT 12" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDSET BIT 11" "NOEFFECT,SET"
bitfld.long 0x00 10. "     AXR10    ,AXR PDSET BIT 10" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDSET BIT 9" "NOEFFECT,SET"
bitfld.long 0x00 8. "     AXR8     ,AXR PDSET BIT 8" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDSET BIT 7" "NOEFFECT,SET"
bitfld.long 0x00 6. "     AXR6     ,AXR PDSET BIT 6" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDSET BIT 5" "NOEFFECT,SET"
bitfld.long 0x00 4. "     AXR4     ,AXR PDSET BIT 4" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDSET BIT 3" "NOEFFECT,SET"
bitfld.long 0x00 2. "     AXR2     ,AXR PDSET BIT 2" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDSET BIT 1" "NOEFFECT,SET"
bitfld.long 0x00 0. "     AXR0     ,AXR PDSET BIT 0" "NOEFFECT,SET"
group.long 0x20++0x3
line.long 0x00 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic low on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDCLR 31" "NOEFFECT,CLEAR"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDCLR 30" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDCLR 29" "NOEFFECT,CLEAR"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDCLR 28" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDCLR 27" "NOEFFECT,CLEAR"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDCLR 26" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDCLR 25" "NOEFFECT,CLEAR"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDCLR BIT 15" "NOEFFECT,CLEAR"
bitfld.long 0x00 14. "     AXR14    ,AXR PDCLR BIT 14" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDCLR BIT 13" "NOEFFECT,CLEAR"
bitfld.long 0x00 12. "     AXR12    ,AXR PDCLR BIT 12" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDCLR BIT 11" "NOEFFECT,CLEAR"
bitfld.long 0x00 10. "     AXR10    ,AXR PDCLR BIT 10" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDCLR BIT 9" "NOEFFECT,CLEAR"
bitfld.long 0x00 8. "     AXR8     ,AXR PDCLR BIT 8" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDCLR BIT 7" "NOEFFECT,CLEAR"
bitfld.long 0x00 6. "     AXR6     ,AXR PDCLR BIT 6" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDCLR BIT 5" "NOEFFECT,CLEAR"
bitfld.long 0x00 4. "     AXR4     ,AXR PDCLR BIT 4" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDCLR BIT 3" "NOEFFECT,CLEAR"
bitfld.long 0x00 2. "     AXR2     ,AXR PDCLR BIT 2" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDCLR BIT 1" "NOEFFECT,CLEAR"
bitfld.long 0x00 0. "     AXR0     ,AXR PDCLR BIT 0" "NOEFFECT,CLEAR"
group.long 0x30++0x3
line.long 0x00 "MCASP_TLGC,for IODFT"
hexmask.long.word 0x00 16.--31. 1. " RESV      ,Reserved"
bitfld.long 0x00 14.--15. "         MT       ,MISR on/off trigger command" "CONTINUOUS,TLECEXP,NOEFFECT,NOEFFECT1"
textline "                                 "
bitfld.long 0x00 9.--13. " RESV1     ,Reserved" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 8. "   MMS      ,Source of MISR input" "OUTREG,INREG"
textline "                                 "
bitfld.long 0x00 7. " ESEL      ,Output enable select" "TEST,FUNC"
bitfld.long 0x00 6. "         TOEN     ,Test output enable control" "ENABLED,DISABLED"
textline "                                 "
bitfld.long 0x00 4.--5. " MC        ,States of MISR" "DLRESULTS,HOLDCURRENT,LOADINITIAL,MISRENABLE"
bitfld.long 0x00 1.--3. "  PC       ,Pattern code" "FUNCTIONAL,RANDOMXOR,RANDOMXNOR,4BITSHIFTER,RESERVED,RESERVED1,RESERVED2,RESERVED3"
textline "                                 "
bitfld.long 0x00 0. " TM        ,Tie high; do not write to this bit" "RESERVED,FUNCTIONAL"
group.long 0x34++0x3
line.long 0x00 "MCASP_TLMR,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLMR      ,Contains test result signature"
group.long 0x38++0x3
line.long 0x00 "MCASP_TLEC,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLEC      ,Contains number of cycles during which MISR sig will be accumulated"
group.long 0x44++0x3
line.long 0x00 "MCASP_GBLCTL,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x48++0x3
line.long 0x00 "MCASP_AMUTE,"
bitfld.long 0x00 12. " XDMAERR   ,MUTETXDMAERR occur" "DISABLE,ENABLE"
bitfld.long 0x00 11. "      RDMAERR  ,MUTERXDMAERR occur" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 10. " XCKFAIL   ,XMT bad clock" "DISABLE,ENABLE"
bitfld.long 0x00 9. "      RCKFAIL  ,RCV bad clock" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 8. " XSYNCERR  ,XMT unexpected FS" "DISABLE,ENABLE"
bitfld.long 0x00 7. "      RSYNCERR ,RCV unexpected FS" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 6. " XUNDRN    ,XMT underrun occurs" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      ROVRN    ,RCV overun occurs" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " INSTAT    ,status of mute in pin" "ACTIVE,INACTIVE"
bitfld.long 0x00 3. "     INEN     ,drive AMUTE active on mute in active" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " INPOL     ,Mute input polarity" "ACTHIGH,ACTLOW"
bitfld.long 0x00 0.--1. "      MUTEN    ,AMUTE pin enable" "DISABLE,ERRHIGH,ERRLOW,3"
group.long 0x4C++0x3
line.long 0x00 "MCASP_LBCTL,"
bitfld.long 0x00 4. " IOLBEN    ,IO loopback enable" "DISABLE,ENABLE"
bitfld.long 0x00 2.--3. "      MODE     ,Loop back clock source generator" "RESERVED,XMTCLK,RESERVED1,RESERVED2"
textline "                                 "
bitfld.long 0x00 1. " ORD       ,Loopback order" "ODD,EVEN"
bitfld.long 0x00 0. "         DLBEN    ,Loop back mode" "DISABLE,ENABLE"
group.long 0x50++0x3
line.long 0x00 "MCASP_TXDITCTL,"
bitfld.long 0x00 3. " VB        ,Valib bit for odd TDM" "ZEROSTUFF,ONESTUFF"
bitfld.long 0x00 2. "    VA       ,Valib bit for even TDM" "ZEROSTUFF,ONESTUFF"
textline "                                 "
bitfld.long 0x00 0. " DITEN     ,XMT DIT Mode Enable" "DISABLE,ENABLE"
group.long 0x60++0x3
line.long 0x00 "MCASP_GBLCTLR,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x64++0x3
line.long 0x00 "MCASP_RXMASK,"
bitfld.long 0x00 31. " RMASK31   ,RMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      RMASK30  ,RMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " RMASK29   ,RMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      RMASK28  ,RMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " RMASK27   ,RMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      RMASK26  ,RMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " RMASK25   ,RMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      RMASK24  ,RMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " RMASK23   ,RMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      RMASK22  ,RMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " RMASK21   ,RMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      RMASK20  ,RMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " RMASK19   ,RMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      RMASK18  ,RMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " RMASK17   ,RMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      RMASK16  ,RMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " RMASK15   ,RMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      RMASK14  ,RMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " RMASK13   ,RMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      RMASK12  ,RMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " RMASK11   ,RMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      RMASK10  ,RMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " RMASK9    ,RMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      RMASK8   ,RMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " RMASK7    ,RMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      RMASK6   ,RMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " RMASK5    ,RMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      RMASK4   ,RMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " RMASK3    ,RMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      RMASK2   ,RMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " RMASK1    ,RMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      RMASK0   ,RMASK BIT 0" "USEMASK,NOMASK"
group.long 0x68++0x3
line.long 0x00 "MCASP_RXFMT,"
bitfld.long 0x00 16.--17. " RDATDLY   ,RCV Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         RRVRS    ,RCV serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " RPAD      ,Pad value" "ZERO,ONE,RPBIT,3"
bitfld.long 0x00 8.--12. "        RPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " RSSZ      ,RCV slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       RBUSEL   ,Write to RBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " RROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0x6C++0x3
line.long 0x00 "MCASP_RXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " RMOD      ,RCV Frame sync mode"
bitfld.long 0x00 4. "         FRWID    ,RCV Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSRM      ,RCV frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSRP     ,RCV Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0x70++0x3
line.long 0x00 "MCASP_ACLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKRADJ  ,CLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKRP     ,RCV Clock Polarity" "FALLINGEDGE,RISINGEDGE"
bitfld.long 0x00 5. "  CLKRM    ,RCV clock source" "EXTERNAL,INTERNAL"
textline "                                 "
bitfld.long 0x00 0.--4. " CLKRDIV   ,RCV clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0x74++0x3
line.long 0x00 "MCASP_AHCLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKRADJ ,HCLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKRM    ,High Freq RCV clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKRP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV  ,RCV clock Divide Ratio"
group.long 0x78++0x3
line.long 0x00 "MCASP_RXTDM,"
bitfld.long 0x00 31. " RTDMS31   ,RCV mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     RTDMS30  ,RCV mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " RTDMS29   ,RCV mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     RTDMS28  ,RCV mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " RTDMS27   ,RCV mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     RTDMS26  ,RCV mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " RTDMS25   ,RCV mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     RTDMS24  ,RCV mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " RTDMS23   ,RCV mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     RTDMS22  ,RCV mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " RTDMS21   ,RCV mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     RTDMS20  ,RCV mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " RTDMS19   ,RCV mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     RTDMS18  ,RCV mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " RTDMS17   ,RCV mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     RTDMS16  ,RCV mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " RTDMS15   ,RCV mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     RTDMS14  ,RCV mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " RTDMS13   ,RCV mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     RTDMS12  ,RCV mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " RTDMS11   ,RCV mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     RTDMS10  ,RCV mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " RTDMS9    ,RCV mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     RTDMS8   ,RCV mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " RTDMS7    ,RCV mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     RTDMS6   ,RCV mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " RTDMS5    ,RCV mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     RTDMS4   ,RCV mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RTDMS3    ,RCV mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     RTDMS2   ,RCV mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RTDMS1    ,RCV mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     RTDMS0   ,RCV mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0x7C++0x3
line.long 0x00 "MCASP_EVTCTLR,"
bitfld.long 0x00 7. " RSTAFRM   ,RCV Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      RDATA    ,RCV Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,RCV Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      RDMAERR  ,RCV DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      RSYNCERR ,RCV Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "DISABLE,ENABLE"
group.long 0x80++0x3
line.long 0x00 "MCASP_RXSTAT,"
bitfld.long 0x00 8. " RERR      ,RCV Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      RDMAERR  ,RCV DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " RSTAFRM   ,Start of Frame-RCV" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     RDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     RTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     RSYNCERR ,Unexpected RCV Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0x84++0x3
line.long 0x00 "MCASP_RXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " RSLOTCNT  ,Current RCV time slot count"
group.long 0x88++0x3
line.long 0x00 "MCASP_RXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " RCNT      ,RCV clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           RMAX     ,RCV clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " RMIN      ,RCV clock minimum boundary"
bitfld.long 0x00 0.--3. "           RPS      ,RCV clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0x8C++0x3
line.long 0x00 "MCASP_REVTCTL,"
bitfld.long 0x00 0. " RDATDMA   ,RCV data DMA request" "ENABLE,DISABLE"
group.long 0xA0++0x3
line.long 0x00 "MCASP_GBLCTLX,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLKR  ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0xA4++0x3
line.long 0x00 "MCASP_TXMASK,"
bitfld.long 0x00 31. " XMASK31   ,XMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      XMASK30  ,XMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " XMASK29   ,XMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      XMASK28  ,XMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " XMASK27   ,XMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      XMASK26  ,XMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " XMASK25   ,XMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      XMASK24  ,XMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " XMASK23   ,XMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      XMASK22  ,XMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " XMASK21   ,XMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      XMASK20  ,XMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " XMASK19   ,XMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      XMASK18  ,XMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " XMASK17   ,XMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      XMASK16  ,XMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " XMASK15   ,XMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      XMASK14  ,XMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " XMASK13   ,XMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      XMASK12  ,XMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " XMASK11   ,XMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      XMASK10  ,XMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " XMASK9    ,XMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      XMASK8   ,XMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " XMASK7    ,XMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      XMASK6   ,XMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " XMASK5    ,XMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      XMASK4   ,XMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " XMASK3    ,XMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      XMASK2   ,XMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " XMASK1    ,XMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      XMASK0   ,XMASK BIT 0" "USEMASK,NOMASK"
group.long 0xA8++0x3
line.long 0x00 "MCASP_TXFMT,"
bitfld.long 0x00 16.--17. " XDATDLY   ,XMT Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         XRVRS    ,XMT serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " XPAD      ,Pad value" "ZERO,ONE,XPBIT,3"
bitfld.long 0x00 8.--12. "        XPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " XSSZ      ,XMT slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       XBUSEL   ,Write to XBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " XROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0xAC++0x3
line.long 0x00 "MCASP_TXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " XMOD      ,XMT Frame sync mode"
bitfld.long 0x00 4. "         FXWID    ,XMT Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSXM      ,XMT frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSXP     ,XMT Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0xB0++0x3
line.long 0x00 "MCASP_ACLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKXADJ  ,CLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKXP     ,XMT Clock Polarity" "RISINGEDGE,FALLINGEDGE"
bitfld.long 0x00 6. "  ASYNC    ,XMT/RCV operation sync /Async" "SYNC,ASYNC"
textline "                                 "
bitfld.long 0x00 5. " CLKXM     ,XMT clock source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0.--4. "     CLKXDIV  ,XMT clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0xB4++0x3
line.long 0x00 "MCASP_AHCLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKXADJ ,HCLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKXM    ,High Freq XMT clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKXP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV  ,XMT clock Divide Ratio"
group.long 0xB8++0x3
line.long 0x00 "MCASP_TXTDM,"
bitfld.long 0x00 31. " XTDMS31   ,XMT mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     XTDMS30  ,XMT mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " XTDMS29   ,XMT mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     XTDMS28  ,XMT mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " XTDMS27   ,XMT mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     XTDMS26  ,XMT mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " XTDMS25   ,XMT mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     XTDMS24  ,XMT mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " XTDMS23   ,XMT mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     XTDMS22  ,XMT mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " XTDMS21   ,XMT mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     XTDMS20  ,XMT mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " XTDMS19   ,XMT mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     XTDMS18  ,XMT mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " XTDMS17   ,XMT mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     XTDMS16  ,XMT mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " XTDMS15   ,XMT mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     XTDMS14  ,XMT mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " XTDMS13   ,XMT mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     XTDMS12  ,XMT mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " XTDMS11   ,XMT mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     XTDMS10  ,XMT mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " XTDMS9    ,XMT mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     XTDMS8   ,XMT mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " XTDMS7    ,XMT mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     XTDMS6   ,XMT mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " XTDMS5    ,XMT mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     XTDMS4   ,XMT mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " XTDMS3    ,XMT mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     XTDMS2   ,XMT mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " XTDMS1    ,XMT mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     XTDMS0   ,XMT mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0xBC++0x3
line.long 0x00 "MCASP_EVTCTLX,"
bitfld.long 0x00 7. " XSTAFRM   ,XMT Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      XDATA    ,XMT Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,XMT Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      XDMAERR  ,XMT DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      XSYNCERR ,XMT Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Interrupt" "DISABLE,ENABLE"
group.long 0xC0++0x3
line.long 0x00 "MCASP_TXSTAT,"
bitfld.long 0x00 8. " XERR      ,XMT Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      XDMAERR  ,XMT DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " XSTAFRM   ,Start of Frame-XMT" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     XDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     XTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     XSYNCERR ,Unexpected XMT Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0xC4++0x3
line.long 0x00 "MCASP_TXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT  ,Current XMT time slot count during reset the value of this register is 0b0101111111 [0x17f] and after reset 0"
group.long 0xC8++0x3
line.long 0x00 "MCASP_TXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " XCNT      ,XMT clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           XMAX     ,XMT clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " XMIN      ,XMT clock minimum boundary"
bitfld.long 0x00 7. "           RESV     ,Reserved" "0,1"
textline "                                 "
bitfld.long 0x00 0.--3. " XPS       ,XMT clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0xCC++0x3
line.long 0x00 "MCASP_XEVTCTL,"
bitfld.long 0x00 0. " XDATDMA   ,XMT data DMA request" "ENABLE,DISABLE"
group.long 0xD0++0x3
line.long 0x00 "MCASP_CLKADJEN,"
bitfld.long 0x00 0. " ENABLE    ,One-shot clock adjust enable" "DISABLE,ENABLE"
group.long 0x100++0x3
line.long 0x00 "MCASP_DITCSRA0,"
hexmask.long 0x00 0.--31. 1. " DITCSRA0  ,Left [Even TDM slot ] Channel status"
group.long 0x104++0x3
line.long 0x00 "MCASP_DITCSRA1,"
hexmask.long 0x00 0.--31. 1. " DITCSRA1  ,Left [Even TDM slot ] Channel status"
group.long 0x108++0x3
line.long 0x00 "MCASP_DITCSRA2,"
hexmask.long 0x00 0.--31. 1. " DITCSRA2  ,Left [Even TDM slot ] Channel status Register"
group.long 0x10C++0x3
line.long 0x00 "MCASP_DITCSRA3,"
hexmask.long 0x00 0.--31. 1. " DITCSRA3  ,Left [Even TDM slot ] Channel status Register"
group.long 0x110++0x3
line.long 0x00 "MCASP_DITCSRA4,"
hexmask.long 0x00 0.--31. 1. " DITCSRA4  ,Left [Even TDM slot ] Channel status"
group.long 0x114++0x3
line.long 0x00 "MCASP_DITCSRA5,"
hexmask.long 0x00 0.--31. 1. " DITCSRA5  ,Left [Even TDM slot ] Channel status"
group.long 0x118++0x3
line.long 0x00 "MCASP_DITCSRB0,"
hexmask.long 0x00 0.--31. 1. " DITCSRB0  ,Right [odd TDM slot ] Channel status"
group.long 0x11C++0x3
line.long 0x00 "MCASP_DITCSRB1,"
hexmask.long 0x00 0.--31. 1. " DITCSRB1  ,Right [odd TDM slot ] Channel status"
group.long 0x120++0x3
line.long 0x00 "MCASP_DITCSRB2,"
hexmask.long 0x00 0.--31. 1. " DITCSRB2  ,Right [odd TDM slot ] Channel status"
group.long 0x124++0x3
line.long 0x00 "MCASP_DITCSRB3,"
hexmask.long 0x00 0.--31. 1. " DITCSRB3  ,Right [odd TDM slot ] Channel status"
group.long 0x128++0x3
line.long 0x00 "MCASP_DITCSRB4,"
hexmask.long 0x00 0.--31. 1. " DITCSRB4  ,Right [odd TDM slot ] Channel status"
group.long 0x12C++0x3
line.long 0x00 "MCASP_DITCSRB5,"
hexmask.long 0x00 0.--31. 1. " DITCSRB5  ,Right [odd TDM slot ] Channel status"
group.long 0x130++0x3
line.long 0x00 "MCASP_DITUDRA0,"
hexmask.long 0x00 0.--31. 1. " DITUDRA0  ,Left [Even TDM slot ] User Data"
group.long 0x134++0x3
line.long 0x00 "MCASP_DITUDRA1,"
hexmask.long 0x00 0.--31. 1. " DITUDRA1  ,Left [Even TDM slot ] User Data"
group.long 0x138++0x3
line.long 0x00 "MCASP_DITUDRA2,"
hexmask.long 0x00 0.--31. 1. " DITUDRA2  ,Left [Even TDM slot ] User Data"
group.long 0x13C++0x3
line.long 0x00 "MCASP_DITUDRA3,"
hexmask.long 0x00 0.--31. 1. " DITUDRA3  ,Left [Even TDM slot ] User Data"
group.long 0x140++0x3
line.long 0x00 "MCASP_DITUDRA4,"
hexmask.long 0x00 0.--31. 1. " DITUDRA4  ,Left [Even TDM slot ] User Data"
group.long 0x144++0x3
line.long 0x00 "MCASP_DITUDRA5,"
hexmask.long 0x00 0.--31. 1. " DITUDRA5  ,Left [Even TDM slot ] User Data"
group.long 0x148++0x3
line.long 0x00 "MCASP_DITUDRB0,"
hexmask.long 0x00 0.--31. 1. " DITUDRB0  ,Right [odd TDM slot ] User Data"
group.long 0x14C++0x3
line.long 0x00 "MCASP_DITUDRB1,"
hexmask.long 0x00 0.--31. 1. " DITUDRB1  ,Right [odd TDM slot ] User Data"
group.long 0x150++0x3
line.long 0x00 "MCASP_DITUDRB2,"
hexmask.long 0x00 0.--31. 1. " DITUDRB2  ,Right [odd TDM slot ] User Data"
group.long 0x154++0x3
line.long 0x00 "MCASP_DITUDRB3,"
hexmask.long 0x00 0.--31. 1. " DITUDRB3  ,Right [odd TDM slot ] User Data"
group.long 0x158++0x3
line.long 0x00 "MCASP_DITUDRB4,"
hexmask.long 0x00 0.--31. 1. " DITUDRB4  ,Right [odd TDM slot ] User Data"
group.long 0x15C++0x3
line.long 0x00 "MCASP_DITUDRB5,"
hexmask.long 0x00 0.--31. 1. " DITUDRB5  ,Right [odd TDM slot ] User Data"
group.long 0x180++0x3
line.long 0x00 "MCASP_XRSRCTL0,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x184++0x3
line.long 0x00 "MCASP_XRSRCTL1,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x188++0x3
line.long 0x00 "MCASP_XRSRCTL2,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x18C++0x3
line.long 0x00 "MCASP_XRSRCTL3,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x190++0x3
line.long 0x00 "MCASP_XRSRCTL4,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x194++0x3
line.long 0x00 "MCASP_XRSRCTL5,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x198++0x3
line.long 0x00 "MCASP_XRSRCTL6,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x19C++0x3
line.long 0x00 "MCASP_XRSRCTL7,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A0++0x3
line.long 0x00 "MCASP_XRSRCTL8,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A4++0x3
line.long 0x00 "MCASP_XRSRCTL9,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A8++0x3
line.long 0x00 "MCASP_XRSRCTL10,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1AC++0x3
line.long 0x00 "MCASP_XRSRCTL11,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B0++0x3
line.long 0x00 "MCASP_XRSRCTL12,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B4++0x3
line.long 0x00 "MCASP_XRSRCTL13,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B8++0x3
line.long 0x00 "MCASP_XRSRCTL14,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1BC++0x3
line.long 0x00 "MCASP_XRSRCTL15,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x200++0x3
line.long 0x00 "MCASP_TXBUF0,"
hexmask.long 0x00 0.--31. 1. " XBUF0     ,Transmit Buffer 0"
group.long 0x204++0x3
line.long 0x00 "MCASP_TXBUF1,"
hexmask.long 0x00 0.--31. 1. " XBUF1     ,Transmit Buffer 1"
group.long 0x208++0x3
line.long 0x00 "MCASP_TXBUF2,"
hexmask.long 0x00 0.--31. 1. " XBUF2     ,Transmit Buffer 2"
group.long 0x20C++0x3
line.long 0x00 "MCASP_TXBUF3,"
hexmask.long 0x00 0.--31. 1. " XBUF3     ,Transmit Buffer 3"
group.long 0x210++0x3
line.long 0x00 "MCASP_TXBUF4,"
hexmask.long 0x00 0.--31. 1. " XBUF4     ,Transmit Buffer 4"
group.long 0x214++0x3
line.long 0x00 "MCASP_TXBUF5,"
hexmask.long 0x00 0.--31. 1. " XBUF5     ,Transmit Buffer 5"
group.long 0x218++0x3
line.long 0x00 "MCASP_TXBUF6,"
hexmask.long 0x00 0.--31. 1. " XBUF6     ,Transmit Buffer 6"
group.long 0x21C++0x3
line.long 0x00 "MCASP_TXBUF7,"
hexmask.long 0x00 0.--31. 1. " XBUF7     ,Transmit Buffer 7"
group.long 0x220++0x3
line.long 0x00 "MCASP_TXBUF8,"
hexmask.long 0x00 0.--31. 1. " XBUF8     ,Transmit Buffer 8"
group.long 0x224++0x3
line.long 0x00 "MCASP_TXBUF9,"
hexmask.long 0x00 0.--31. 1. " XBUF9     ,Transmit Buffer 9"
group.long 0x228++0x3
line.long 0x00 "MCASP_TXBUF10,"
hexmask.long 0x00 0.--31. 1. " XBUF10    ,Transmit Buffer 10"
group.long 0x22C++0x3
line.long 0x00 "MCASP_TXBUF11,"
hexmask.long 0x00 0.--31. 1. " XBUF11    ,Transmit Buffer 11"
group.long 0x230++0x3
line.long 0x00 "MCASP_TXBUF12,"
hexmask.long 0x00 0.--31. 1. " XBUF12    ,Transmit Buffer 12"
group.long 0x234++0x3
line.long 0x00 "MCASP_TXBUF13,"
hexmask.long 0x00 0.--31. 1. " XBUF13    ,Transmit Buffer 13"
group.long 0x238++0x3
line.long 0x00 "MCASP_TXBUF14,"
hexmask.long 0x00 0.--31. 1. " XBUF14    ,Transmit Buffer 14"
group.long 0x23C++0x3
line.long 0x00 "MCASP_TXBUF15,"
hexmask.long 0x00 0.--31. 1. " XBUF15    ,Transmit Buffer 15"
group.long 0x280++0x3
line.long 0x00 "MCASP_RXBUF0,"
hexmask.long 0x00 0.--31. 1. " RBUF0     ,Receive Buffer 0"
group.long 0x284++0x3
line.long 0x00 "MCASP_RXBUF1,"
hexmask.long 0x00 0.--31. 1. " RBUF1     ,Receive Buffer 1"
group.long 0x288++0x3
line.long 0x00 "MCASP_RXBUF2,"
hexmask.long 0x00 0.--31. 1. " RBUF2     ,Receive Buffer 2"
group.long 0x28C++0x3
line.long 0x00 "MCASP_RXBUF3,"
hexmask.long 0x00 0.--31. 1. " RBUF3     ,Receive Buffer 3"
group.long 0x290++0x3
line.long 0x00 "MCASP_RXBUF4,"
hexmask.long 0x00 0.--31. 1. " RBUF4     ,Receive Buffer 4"
group.long 0x294++0x3
line.long 0x00 "MCASP_RXBUF5,"
hexmask.long 0x00 0.--31. 1. " RBUF5     ,Receive Buffer 5"
group.long 0x298++0x3
line.long 0x00 "MCASP_RXBUF6,"
hexmask.long 0x00 0.--31. 1. " RBUF6     ,Receive Buffer 6"
group.long 0x29C++0x3
line.long 0x00 "MCASP_RXBUF7,"
hexmask.long 0x00 0.--31. 1. " RBUF7     ,Receive Buffer 7"
group.long 0x2A0++0x3
line.long 0x00 "MCASP_RXBUF8,"
hexmask.long 0x00 0.--31. 1. " RBUF8     ,Receive Buffer 8"
group.long 0x2A4++0x3
line.long 0x00 "MCASP_RXBUF9,"
hexmask.long 0x00 0.--31. 1. " RBUF9     ,Receive Buffer 9"
group.long 0x2A8++0x3
line.long 0x00 "MCASP_RXBUF10,"
hexmask.long 0x00 0.--31. 1. " RBUF10    ,Receive Buffer 10"
group.long 0x2AC++0x3
line.long 0x00 "MCASP_RXBUF11,"
hexmask.long 0x00 0.--31. 1. " RBUF11    ,Receive Buffer 11"
group.long 0x2B0++0x3
line.long 0x00 "MCASP_RXBUF12,"
hexmask.long 0x00 0.--31. 1. " RBUF12    ,Receive Buffer 12"
group.long 0x2B4++0x3
line.long 0x00 "MCASP_RXBUF13,"
hexmask.long 0x00 0.--31. 1. " RBUF13    ,Receive Buffer 13"
group.long 0x2B8++0x3
line.long 0x00 "MCASP_RXBUF14,"
hexmask.long 0x00 0.--31. 1. " RBUF14    ,Receive Buffer 14"
group.long 0x2BC++0x3
line.long 0x00 "MCASP_RXBUF15,"
hexmask.long 0x00 0.--31. 1. " RBUF15    ,Receive Buffer 15"
group.long 0x1000++0x3
line.long 0x00 "MCASP_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " WENA      ,Write FIFO enable bit. 0h (R/W) = Write FIFO is disabled. The WLVL bit in the Write FIFO status register ( 1h (R/W) = Write FIFO is enabled. If Write FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            WNUMEVT  ,Write word count per DMA event (32 bit). When the Write FIFO has space for at least WNUMEVT words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as transmitters. This value must be set prior to enabling the Write FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA   ,Write word count per transfer (32 bit words). Upon a transmit DMA event from the McASP, WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the Write FIFO. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3-16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x1004++0x3
line.long 0x00 "MCASP_WFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " WLVL      ,Write level (read-only). Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Write FIFO. 1h (R/W) = 1 word currently in Write FIFO. 2h (R/W) = 2 words currently in Write FIFO. 3h (R/W) = 3 to 64 words currently in Write FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
group.long 0x1008++0x3
line.long 0x00 "MCASP_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " RENA      ,Read FIFO enable bit. 0h (R/W) = Read FIFO is disabled. The RLVL bit in the Read FIFO status register ( 1h (R/W) = Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            RNUMEVT  ,Read word count per DMA event (32 bit). When the Read FIFO contains at least RNUMEVT words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as receivers. This value must be set prior to enabling the Read FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h = FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA   ,Read word count per transfer (32 bit words). Upon a receive DMA event from the McASP, the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO. 10h = 3 to 16 words from 3h to 10h. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x100C++0x3
line.long 0x00 "MCASP_RFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " RLVL      ,Read level (read-only). Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Read FIFO. 1h (R/W) = 1 word currently in Read FIFO. 2h (R/W) = 2 words currently in Read FIFO. 3h (R/W) = 3 to 64 words currently in Read FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
width 0x0B
tree.end
tree "MCASP1_CFG"
base ad:0x2B10000
width 24.
rgroup.long 0x0++0x3
line.long 0x00 "MCASP_PID,"
bitfld.long 0x00 30.--31. " SCHEME    ," "0,1,2,3"
bitfld.long 0x00 28.--29. "            RESV     ," "0,1,2,3"
textline "                                 "
hexmask.long.word 0x00 16.--27. 1. " FUNCTION  ,McASP"
bitfld.long 0x00 11.--15. "         RTL      ," "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 8.--10. " REVMAJOR  ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "            CUSTOM   ,non-custom" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 0.--5. " REVMINOR  ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register."
hexmask.long 0x00 6.--31. 1. " RSV       ,Reserved as per PDR 35"
bitfld.long 0x00 2.--5. "     Other    ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--1. " IDLE_MODE ,Idle Mode" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "MCASP_PFUNC,"
bitfld.long 0x00 31. " AFSR      ,AFSR PFUNC 31" "MCASP,GPIO"
bitfld.long 0x00 30. "        AHCLKR   ,AHCLKR PFUNC 30" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PFUNC 29" "MCASP,GPIO"
bitfld.long 0x00 28. "        AFSX     ,AFSX PFUNC 28" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PFUNC 27" "MCASP,GPIO"
bitfld.long 0x00 26. "        ACLKX    ,ACLKX PFUNC 26" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PFUNC 25" "MCASP,GPIO"
hexmask.long.word 0x00 16.--24. 1. "        RESV1    ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PFUNC BIT 15" "MCASP,GPIO"
bitfld.long 0x00 14. "        AXR14    ,AXR PFUNC BIT 14" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PFUNC BIT 13" "MCASP,GPIO"
bitfld.long 0x00 12. "        AXR12    ,AXR PFUNC BIT 12" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PFUNC BIT 11" "MCASP,GPIO"
bitfld.long 0x00 10. "        AXR10    ,AXR PFUNC BIT 10" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PFUNC BIT 9" "MCASP,GPIO"
bitfld.long 0x00 8. "        AXR8     ,AXR PFUNC BIT 8" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PFUNC BIT 7" "MCASP,GPIO"
bitfld.long 0x00 6. "        AXR6     ,AXR PFUNC BIT 6" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PFUNC BIT 5" "MCASP,GPIO"
bitfld.long 0x00 4. "        AXR4     ,AXR PFUNC BIT 4" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PFUNC BIT 3" "MCASP,GPIO"
bitfld.long 0x00 2. "        AXR2     ,AXR PFUNC BIT 2" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PFUNC BIT 1" "MCASP,GPIO"
bitfld.long 0x00 0. "        AXR0     ,AXR PFUNC BIT 0" "MCASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "MCASP_PDIR,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDIR 31" "INPUT,OUTPUT"
bitfld.long 0x00 30. "       AHCLKR   ,AHCLKR PDIR 30" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIR 29" "INPUT,OUTPUT"
bitfld.long 0x00 28. "       AFSX     ,AFSX PDIR 28" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIR 27" "INPUT,OUTPUT"
bitfld.long 0x00 26. "       ACLKX    ,ACLKX PDIR 26" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIR 25" "INPUT,OUTPUT"
hexmask.long.word 0x00 16.--24. 1. "       RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIR BIT 15" "INPUT,OUTPUT"
bitfld.long 0x00 14. "       AXR14    ,AXR PDIR BIT 14" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIR BIT 13" "INPUT,OUTPUT"
bitfld.long 0x00 12. "       AXR12    ,AXR PDIR BIT 12" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIR BIT 11" "INPUT,OUTPUT"
bitfld.long 0x00 10. "       AXR10    ,AXR PDIR BIT 10" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIR BIT 9" "INPUT,OUTPUT"
bitfld.long 0x00 8. "       AXR8     ,AXR PDIR BIT 8" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIR BIT 7" "INPUT,OUTPUT"
bitfld.long 0x00 6. "       AXR6     ,AXR PDIR BIT 6" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIR BIT 5" "INPUT,OUTPUT"
bitfld.long 0x00 4. "       AXR4     ,AXR PDIR BIT 4" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIR BIT 3" "INPUT,OUTPUT"
bitfld.long 0x00 2. "       AXR2     ,AXR PDIR BIT 2" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIR BIT 1" "INPUT,OUTPUT"
bitfld.long 0x00 0. "       AXR0     ,AXR PDIR BIT 0" "INPUT,OUTPUT"
group.long 0x18++0x3
line.long 0x00 "MCASP_PDOUT,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDOUT 31" "DRV0,DRV1"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDOUT 30" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDOUT 29" "DRV0,DRV1"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDOUT 28" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDOUT 27" "DRV0,DRV1"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDOUT 26" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDOUT 25" "DRV0,DRV1"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDOUT BIT 15" "DRV0,DRV1"
bitfld.long 0x00 14. "         AXR14    ,AXR PDOUT BIT 14" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDOUT BIT 13" "DRV0,DRV1"
bitfld.long 0x00 12. "         AXR12    ,AXR PDOUT BIT 12" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDOUT BIT 11" "DRV0,DRV1"
bitfld.long 0x00 10. "         AXR10    ,AXR PDOUT BIT 10" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDOUT BIT 9" "DRV0,DRV1"
bitfld.long 0x00 8. "         AXR8     ,AXR PDOUT BIT 8" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDOUT BIT 7" "DRV0,DRV1"
bitfld.long 0x00 6. "         AXR6     ,AXR PDOUT BIT 6" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDOUT BIT 5" "DRV0,DRV1"
bitfld.long 0x00 4. "         AXR4     ,AXR PDOUT BIT 4" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDOUT BIT 3" "DRV0,DRV1"
bitfld.long 0x00 2. "         AXR2     ,AXR PDOUT BIT 2" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDOUT BIT 1" "DRV0,DRV1"
bitfld.long 0x00 0. "         AXR0     ,AXR PDOUT BIT 0" "DRV0,DRV1"
rgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read, regardless of the state of PFUNC and PDIR."
bitfld.long 0x00 31. " AFSR      ,AFSR PDIN 31" "LOW,HIGH"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDIN 30" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIN 29" "LOW,HIGH"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDIN 28" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIN 27" "LOW,HIGH"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDIN 26" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIN 25" "LOW,HIGH"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIN BIT 15" "LOW,HIGH"
bitfld.long 0x00 14. "         AXR14    ,AXR PDIN BIT 14" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIN BIT 13" "LOW,HIGH"
bitfld.long 0x00 12. "         AXR12    ,AXR PDIN BIT 12" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIN BIT 11" "LOW,HIGH"
bitfld.long 0x00 10. "         AXR10    ,AXR PDIN BIT 10" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIN BIT 9" "LOW,HIGH"
bitfld.long 0x00 8. "         AXR8     ,AXR PDIN BIT 8" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIN BIT 7" "LOW,HIGH"
bitfld.long 0x00 6. "         AXR6     ,AXR PDIN BIT 6" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIN BIT 5" "LOW,HIGH"
bitfld.long 0x00 4. "         AXR4     ,AXR PDIN BIT 4" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIN BIT 3" "LOW,HIGH"
bitfld.long 0x00 2. "         AXR2     ,AXR PDIN BIT 2" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIN BIT 1" "LOW,HIGH"
bitfld.long 0x00 0. "         AXR0     ,AXR PDIN BIT 0" "LOW,HIGH"
wgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic high on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDSET 31" "NOEFFECT,SET"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDSET 30" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDSET 29" "NOEFFECT,SET"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDSET 28" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDSET 27" "NOEFFECT,SET"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDSET 26" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDSET 25" "NOEFFECT,SET"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDSET BIT 15" "NOEFFECT,SET"
bitfld.long 0x00 14. "     AXR14    ,AXR PDSET BIT 14" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDSET BIT 13" "NOEFFECT,SET"
bitfld.long 0x00 12. "     AXR12    ,AXR PDSET BIT 12" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDSET BIT 11" "NOEFFECT,SET"
bitfld.long 0x00 10. "     AXR10    ,AXR PDSET BIT 10" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDSET BIT 9" "NOEFFECT,SET"
bitfld.long 0x00 8. "     AXR8     ,AXR PDSET BIT 8" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDSET BIT 7" "NOEFFECT,SET"
bitfld.long 0x00 6. "     AXR6     ,AXR PDSET BIT 6" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDSET BIT 5" "NOEFFECT,SET"
bitfld.long 0x00 4. "     AXR4     ,AXR PDSET BIT 4" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDSET BIT 3" "NOEFFECT,SET"
bitfld.long 0x00 2. "     AXR2     ,AXR PDSET BIT 2" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDSET BIT 1" "NOEFFECT,SET"
bitfld.long 0x00 0. "     AXR0     ,AXR PDSET BIT 0" "NOEFFECT,SET"
group.long 0x20++0x3
line.long 0x00 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic low on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDCLR 31" "NOEFFECT,CLEAR"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDCLR 30" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDCLR 29" "NOEFFECT,CLEAR"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDCLR 28" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDCLR 27" "NOEFFECT,CLEAR"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDCLR 26" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDCLR 25" "NOEFFECT,CLEAR"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDCLR BIT 15" "NOEFFECT,CLEAR"
bitfld.long 0x00 14. "     AXR14    ,AXR PDCLR BIT 14" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDCLR BIT 13" "NOEFFECT,CLEAR"
bitfld.long 0x00 12. "     AXR12    ,AXR PDCLR BIT 12" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDCLR BIT 11" "NOEFFECT,CLEAR"
bitfld.long 0x00 10. "     AXR10    ,AXR PDCLR BIT 10" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDCLR BIT 9" "NOEFFECT,CLEAR"
bitfld.long 0x00 8. "     AXR8     ,AXR PDCLR BIT 8" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDCLR BIT 7" "NOEFFECT,CLEAR"
bitfld.long 0x00 6. "     AXR6     ,AXR PDCLR BIT 6" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDCLR BIT 5" "NOEFFECT,CLEAR"
bitfld.long 0x00 4. "     AXR4     ,AXR PDCLR BIT 4" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDCLR BIT 3" "NOEFFECT,CLEAR"
bitfld.long 0x00 2. "     AXR2     ,AXR PDCLR BIT 2" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDCLR BIT 1" "NOEFFECT,CLEAR"
bitfld.long 0x00 0. "     AXR0     ,AXR PDCLR BIT 0" "NOEFFECT,CLEAR"
group.long 0x30++0x3
line.long 0x00 "MCASP_TLGC,for IODFT"
hexmask.long.word 0x00 16.--31. 1. " RESV      ,Reserved"
bitfld.long 0x00 14.--15. "         MT       ,MISR on/off trigger command" "CONTINUOUS,TLECEXP,NOEFFECT,NOEFFECT1"
textline "                                 "
bitfld.long 0x00 9.--13. " RESV1     ,Reserved" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 8. "   MMS      ,Source of MISR input" "OUTREG,INREG"
textline "                                 "
bitfld.long 0x00 7. " ESEL      ,Output enable select" "TEST,FUNC"
bitfld.long 0x00 6. "         TOEN     ,Test output enable control" "ENABLED,DISABLED"
textline "                                 "
bitfld.long 0x00 4.--5. " MC        ,States of MISR" "DLRESULTS,HOLDCURRENT,LOADINITIAL,MISRENABLE"
bitfld.long 0x00 1.--3. "  PC       ,Pattern code" "FUNCTIONAL,RANDOMXOR,RANDOMXNOR,4BITSHIFTER,RESERVED,RESERVED1,RESERVED2,RESERVED3"
textline "                                 "
bitfld.long 0x00 0. " TM        ,Tie high; do not write to this bit" "RESERVED,FUNCTIONAL"
group.long 0x34++0x3
line.long 0x00 "MCASP_TLMR,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLMR      ,Contains test result signature"
group.long 0x38++0x3
line.long 0x00 "MCASP_TLEC,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLEC      ,Contains number of cycles during which MISR sig will be accumulated"
group.long 0x44++0x3
line.long 0x00 "MCASP_GBLCTL,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x48++0x3
line.long 0x00 "MCASP_AMUTE,"
bitfld.long 0x00 12. " XDMAERR   ,MUTETXDMAERR occur" "DISABLE,ENABLE"
bitfld.long 0x00 11. "      RDMAERR  ,MUTERXDMAERR occur" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 10. " XCKFAIL   ,XMT bad clock" "DISABLE,ENABLE"
bitfld.long 0x00 9. "      RCKFAIL  ,RCV bad clock" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 8. " XSYNCERR  ,XMT unexpected FS" "DISABLE,ENABLE"
bitfld.long 0x00 7. "      RSYNCERR ,RCV unexpected FS" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 6. " XUNDRN    ,XMT underrun occurs" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      ROVRN    ,RCV overun occurs" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " INSTAT    ,status of mute in pin" "ACTIVE,INACTIVE"
bitfld.long 0x00 3. "     INEN     ,drive AMUTE active on mute in active" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " INPOL     ,Mute input polarity" "ACTHIGH,ACTLOW"
bitfld.long 0x00 0.--1. "      MUTEN    ,AMUTE pin enable" "DISABLE,ERRHIGH,ERRLOW,3"
group.long 0x4C++0x3
line.long 0x00 "MCASP_LBCTL,"
bitfld.long 0x00 4. " IOLBEN    ,IO loopback enable" "DISABLE,ENABLE"
bitfld.long 0x00 2.--3. "      MODE     ,Loop back clock source generator" "RESERVED,XMTCLK,RESERVED1,RESERVED2"
textline "                                 "
bitfld.long 0x00 1. " ORD       ,Loopback order" "ODD,EVEN"
bitfld.long 0x00 0. "         DLBEN    ,Loop back mode" "DISABLE,ENABLE"
group.long 0x50++0x3
line.long 0x00 "MCASP_TXDITCTL,"
bitfld.long 0x00 3. " VB        ,Valib bit for odd TDM" "ZEROSTUFF,ONESTUFF"
bitfld.long 0x00 2. "    VA       ,Valib bit for even TDM" "ZEROSTUFF,ONESTUFF"
textline "                                 "
bitfld.long 0x00 0. " DITEN     ,XMT DIT Mode Enable" "DISABLE,ENABLE"
group.long 0x60++0x3
line.long 0x00 "MCASP_GBLCTLR,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x64++0x3
line.long 0x00 "MCASP_RXMASK,"
bitfld.long 0x00 31. " RMASK31   ,RMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      RMASK30  ,RMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " RMASK29   ,RMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      RMASK28  ,RMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " RMASK27   ,RMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      RMASK26  ,RMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " RMASK25   ,RMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      RMASK24  ,RMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " RMASK23   ,RMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      RMASK22  ,RMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " RMASK21   ,RMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      RMASK20  ,RMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " RMASK19   ,RMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      RMASK18  ,RMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " RMASK17   ,RMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      RMASK16  ,RMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " RMASK15   ,RMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      RMASK14  ,RMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " RMASK13   ,RMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      RMASK12  ,RMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " RMASK11   ,RMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      RMASK10  ,RMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " RMASK9    ,RMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      RMASK8   ,RMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " RMASK7    ,RMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      RMASK6   ,RMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " RMASK5    ,RMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      RMASK4   ,RMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " RMASK3    ,RMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      RMASK2   ,RMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " RMASK1    ,RMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      RMASK0   ,RMASK BIT 0" "USEMASK,NOMASK"
group.long 0x68++0x3
line.long 0x00 "MCASP_RXFMT,"
bitfld.long 0x00 16.--17. " RDATDLY   ,RCV Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         RRVRS    ,RCV serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " RPAD      ,Pad value" "ZERO,ONE,RPBIT,3"
bitfld.long 0x00 8.--12. "        RPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " RSSZ      ,RCV slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       RBUSEL   ,Write to RBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " RROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0x6C++0x3
line.long 0x00 "MCASP_RXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " RMOD      ,RCV Frame sync mode"
bitfld.long 0x00 4. "         FRWID    ,RCV Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSRM      ,RCV frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSRP     ,RCV Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0x70++0x3
line.long 0x00 "MCASP_ACLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKRADJ  ,CLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKRP     ,RCV Clock Polarity" "FALLINGEDGE,RISINGEDGE"
bitfld.long 0x00 5. "  CLKRM    ,RCV clock source" "EXTERNAL,INTERNAL"
textline "                                 "
bitfld.long 0x00 0.--4. " CLKRDIV   ,RCV clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0x74++0x3
line.long 0x00 "MCASP_AHCLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKRADJ ,HCLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKRM    ,High Freq RCV clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKRP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV  ,RCV clock Divide Ratio"
group.long 0x78++0x3
line.long 0x00 "MCASP_RXTDM,"
bitfld.long 0x00 31. " RTDMS31   ,RCV mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     RTDMS30  ,RCV mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " RTDMS29   ,RCV mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     RTDMS28  ,RCV mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " RTDMS27   ,RCV mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     RTDMS26  ,RCV mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " RTDMS25   ,RCV mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     RTDMS24  ,RCV mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " RTDMS23   ,RCV mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     RTDMS22  ,RCV mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " RTDMS21   ,RCV mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     RTDMS20  ,RCV mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " RTDMS19   ,RCV mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     RTDMS18  ,RCV mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " RTDMS17   ,RCV mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     RTDMS16  ,RCV mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " RTDMS15   ,RCV mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     RTDMS14  ,RCV mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " RTDMS13   ,RCV mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     RTDMS12  ,RCV mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " RTDMS11   ,RCV mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     RTDMS10  ,RCV mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " RTDMS9    ,RCV mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     RTDMS8   ,RCV mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " RTDMS7    ,RCV mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     RTDMS6   ,RCV mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " RTDMS5    ,RCV mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     RTDMS4   ,RCV mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RTDMS3    ,RCV mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     RTDMS2   ,RCV mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RTDMS1    ,RCV mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     RTDMS0   ,RCV mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0x7C++0x3
line.long 0x00 "MCASP_EVTCTLR,"
bitfld.long 0x00 7. " RSTAFRM   ,RCV Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      RDATA    ,RCV Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,RCV Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      RDMAERR  ,RCV DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      RSYNCERR ,RCV Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "DISABLE,ENABLE"
group.long 0x80++0x3
line.long 0x00 "MCASP_RXSTAT,"
bitfld.long 0x00 8. " RERR      ,RCV Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      RDMAERR  ,RCV DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " RSTAFRM   ,Start of Frame-RCV" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     RDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     RTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     RSYNCERR ,Unexpected RCV Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0x84++0x3
line.long 0x00 "MCASP_RXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " RSLOTCNT  ,Current RCV time slot count"
group.long 0x88++0x3
line.long 0x00 "MCASP_RXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " RCNT      ,RCV clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           RMAX     ,RCV clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " RMIN      ,RCV clock minimum boundary"
bitfld.long 0x00 0.--3. "           RPS      ,RCV clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0x8C++0x3
line.long 0x00 "MCASP_REVTCTL,"
bitfld.long 0x00 0. " RDATDMA   ,RCV data DMA request" "ENABLE,DISABLE"
group.long 0xA0++0x3
line.long 0x00 "MCASP_GBLCTLX,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLKR  ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0xA4++0x3
line.long 0x00 "MCASP_TXMASK,"
bitfld.long 0x00 31. " XMASK31   ,XMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      XMASK30  ,XMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " XMASK29   ,XMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      XMASK28  ,XMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " XMASK27   ,XMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      XMASK26  ,XMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " XMASK25   ,XMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      XMASK24  ,XMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " XMASK23   ,XMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      XMASK22  ,XMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " XMASK21   ,XMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      XMASK20  ,XMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " XMASK19   ,XMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      XMASK18  ,XMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " XMASK17   ,XMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      XMASK16  ,XMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " XMASK15   ,XMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      XMASK14  ,XMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " XMASK13   ,XMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      XMASK12  ,XMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " XMASK11   ,XMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      XMASK10  ,XMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " XMASK9    ,XMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      XMASK8   ,XMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " XMASK7    ,XMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      XMASK6   ,XMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " XMASK5    ,XMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      XMASK4   ,XMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " XMASK3    ,XMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      XMASK2   ,XMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " XMASK1    ,XMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      XMASK0   ,XMASK BIT 0" "USEMASK,NOMASK"
group.long 0xA8++0x3
line.long 0x00 "MCASP_TXFMT,"
bitfld.long 0x00 16.--17. " XDATDLY   ,XMT Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         XRVRS    ,XMT serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " XPAD      ,Pad value" "ZERO,ONE,XPBIT,3"
bitfld.long 0x00 8.--12. "        XPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " XSSZ      ,XMT slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       XBUSEL   ,Write to XBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " XROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0xAC++0x3
line.long 0x00 "MCASP_TXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " XMOD      ,XMT Frame sync mode"
bitfld.long 0x00 4. "         FXWID    ,XMT Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSXM      ,XMT frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSXP     ,XMT Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0xB0++0x3
line.long 0x00 "MCASP_ACLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKXADJ  ,CLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKXP     ,XMT Clock Polarity" "RISINGEDGE,FALLINGEDGE"
bitfld.long 0x00 6. "  ASYNC    ,XMT/RCV operation sync /Async" "SYNC,ASYNC"
textline "                                 "
bitfld.long 0x00 5. " CLKXM     ,XMT clock source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0.--4. "     CLKXDIV  ,XMT clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0xB4++0x3
line.long 0x00 "MCASP_AHCLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKXADJ ,HCLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKXM    ,High Freq XMT clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKXP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV  ,XMT clock Divide Ratio"
group.long 0xB8++0x3
line.long 0x00 "MCASP_TXTDM,"
bitfld.long 0x00 31. " XTDMS31   ,XMT mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     XTDMS30  ,XMT mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " XTDMS29   ,XMT mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     XTDMS28  ,XMT mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " XTDMS27   ,XMT mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     XTDMS26  ,XMT mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " XTDMS25   ,XMT mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     XTDMS24  ,XMT mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " XTDMS23   ,XMT mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     XTDMS22  ,XMT mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " XTDMS21   ,XMT mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     XTDMS20  ,XMT mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " XTDMS19   ,XMT mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     XTDMS18  ,XMT mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " XTDMS17   ,XMT mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     XTDMS16  ,XMT mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " XTDMS15   ,XMT mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     XTDMS14  ,XMT mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " XTDMS13   ,XMT mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     XTDMS12  ,XMT mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " XTDMS11   ,XMT mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     XTDMS10  ,XMT mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " XTDMS9    ,XMT mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     XTDMS8   ,XMT mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " XTDMS7    ,XMT mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     XTDMS6   ,XMT mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " XTDMS5    ,XMT mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     XTDMS4   ,XMT mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " XTDMS3    ,XMT mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     XTDMS2   ,XMT mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " XTDMS1    ,XMT mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     XTDMS0   ,XMT mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0xBC++0x3
line.long 0x00 "MCASP_EVTCTLX,"
bitfld.long 0x00 7. " XSTAFRM   ,XMT Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      XDATA    ,XMT Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,XMT Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      XDMAERR  ,XMT DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      XSYNCERR ,XMT Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Interrupt" "DISABLE,ENABLE"
group.long 0xC0++0x3
line.long 0x00 "MCASP_TXSTAT,"
bitfld.long 0x00 8. " XERR      ,XMT Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      XDMAERR  ,XMT DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " XSTAFRM   ,Start of Frame-XMT" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     XDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     XTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     XSYNCERR ,Unexpected XMT Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0xC4++0x3
line.long 0x00 "MCASP_TXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT  ,Current XMT time slot count during reset the value of this register is 0b0101111111 [0x17f] and after reset 0"
group.long 0xC8++0x3
line.long 0x00 "MCASP_TXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " XCNT      ,XMT clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           XMAX     ,XMT clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " XMIN      ,XMT clock minimum boundary"
bitfld.long 0x00 7. "           RESV     ,Reserved" "0,1"
textline "                                 "
bitfld.long 0x00 0.--3. " XPS       ,XMT clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0xCC++0x3
line.long 0x00 "MCASP_XEVTCTL,"
bitfld.long 0x00 0. " XDATDMA   ,XMT data DMA request" "ENABLE,DISABLE"
group.long 0xD0++0x3
line.long 0x00 "MCASP_CLKADJEN,"
bitfld.long 0x00 0. " ENABLE    ,One-shot clock adjust enable" "DISABLE,ENABLE"
group.long 0x100++0x3
line.long 0x00 "MCASP_DITCSRA0,"
hexmask.long 0x00 0.--31. 1. " DITCSRA0  ,Left [Even TDM slot ] Channel status"
group.long 0x104++0x3
line.long 0x00 "MCASP_DITCSRA1,"
hexmask.long 0x00 0.--31. 1. " DITCSRA1  ,Left [Even TDM slot ] Channel status"
group.long 0x108++0x3
line.long 0x00 "MCASP_DITCSRA2,"
hexmask.long 0x00 0.--31. 1. " DITCSRA2  ,Left [Even TDM slot ] Channel status Register"
group.long 0x10C++0x3
line.long 0x00 "MCASP_DITCSRA3,"
hexmask.long 0x00 0.--31. 1. " DITCSRA3  ,Left [Even TDM slot ] Channel status Register"
group.long 0x110++0x3
line.long 0x00 "MCASP_DITCSRA4,"
hexmask.long 0x00 0.--31. 1. " DITCSRA4  ,Left [Even TDM slot ] Channel status"
group.long 0x114++0x3
line.long 0x00 "MCASP_DITCSRA5,"
hexmask.long 0x00 0.--31. 1. " DITCSRA5  ,Left [Even TDM slot ] Channel status"
group.long 0x118++0x3
line.long 0x00 "MCASP_DITCSRB0,"
hexmask.long 0x00 0.--31. 1. " DITCSRB0  ,Right [odd TDM slot ] Channel status"
group.long 0x11C++0x3
line.long 0x00 "MCASP_DITCSRB1,"
hexmask.long 0x00 0.--31. 1. " DITCSRB1  ,Right [odd TDM slot ] Channel status"
group.long 0x120++0x3
line.long 0x00 "MCASP_DITCSRB2,"
hexmask.long 0x00 0.--31. 1. " DITCSRB2  ,Right [odd TDM slot ] Channel status"
group.long 0x124++0x3
line.long 0x00 "MCASP_DITCSRB3,"
hexmask.long 0x00 0.--31. 1. " DITCSRB3  ,Right [odd TDM slot ] Channel status"
group.long 0x128++0x3
line.long 0x00 "MCASP_DITCSRB4,"
hexmask.long 0x00 0.--31. 1. " DITCSRB4  ,Right [odd TDM slot ] Channel status"
group.long 0x12C++0x3
line.long 0x00 "MCASP_DITCSRB5,"
hexmask.long 0x00 0.--31. 1. " DITCSRB5  ,Right [odd TDM slot ] Channel status"
group.long 0x130++0x3
line.long 0x00 "MCASP_DITUDRA0,"
hexmask.long 0x00 0.--31. 1. " DITUDRA0  ,Left [Even TDM slot ] User Data"
group.long 0x134++0x3
line.long 0x00 "MCASP_DITUDRA1,"
hexmask.long 0x00 0.--31. 1. " DITUDRA1  ,Left [Even TDM slot ] User Data"
group.long 0x138++0x3
line.long 0x00 "MCASP_DITUDRA2,"
hexmask.long 0x00 0.--31. 1. " DITUDRA2  ,Left [Even TDM slot ] User Data"
group.long 0x13C++0x3
line.long 0x00 "MCASP_DITUDRA3,"
hexmask.long 0x00 0.--31. 1. " DITUDRA3  ,Left [Even TDM slot ] User Data"
group.long 0x140++0x3
line.long 0x00 "MCASP_DITUDRA4,"
hexmask.long 0x00 0.--31. 1. " DITUDRA4  ,Left [Even TDM slot ] User Data"
group.long 0x144++0x3
line.long 0x00 "MCASP_DITUDRA5,"
hexmask.long 0x00 0.--31. 1. " DITUDRA5  ,Left [Even TDM slot ] User Data"
group.long 0x148++0x3
line.long 0x00 "MCASP_DITUDRB0,"
hexmask.long 0x00 0.--31. 1. " DITUDRB0  ,Right [odd TDM slot ] User Data"
group.long 0x14C++0x3
line.long 0x00 "MCASP_DITUDRB1,"
hexmask.long 0x00 0.--31. 1. " DITUDRB1  ,Right [odd TDM slot ] User Data"
group.long 0x150++0x3
line.long 0x00 "MCASP_DITUDRB2,"
hexmask.long 0x00 0.--31. 1. " DITUDRB2  ,Right [odd TDM slot ] User Data"
group.long 0x154++0x3
line.long 0x00 "MCASP_DITUDRB3,"
hexmask.long 0x00 0.--31. 1. " DITUDRB3  ,Right [odd TDM slot ] User Data"
group.long 0x158++0x3
line.long 0x00 "MCASP_DITUDRB4,"
hexmask.long 0x00 0.--31. 1. " DITUDRB4  ,Right [odd TDM slot ] User Data"
group.long 0x15C++0x3
line.long 0x00 "MCASP_DITUDRB5,"
hexmask.long 0x00 0.--31. 1. " DITUDRB5  ,Right [odd TDM slot ] User Data"
group.long 0x180++0x3
line.long 0x00 "MCASP_XRSRCTL0,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x184++0x3
line.long 0x00 "MCASP_XRSRCTL1,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x188++0x3
line.long 0x00 "MCASP_XRSRCTL2,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x18C++0x3
line.long 0x00 "MCASP_XRSRCTL3,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x190++0x3
line.long 0x00 "MCASP_XRSRCTL4,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x194++0x3
line.long 0x00 "MCASP_XRSRCTL5,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x198++0x3
line.long 0x00 "MCASP_XRSRCTL6,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x19C++0x3
line.long 0x00 "MCASP_XRSRCTL7,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A0++0x3
line.long 0x00 "MCASP_XRSRCTL8,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A4++0x3
line.long 0x00 "MCASP_XRSRCTL9,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A8++0x3
line.long 0x00 "MCASP_XRSRCTL10,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1AC++0x3
line.long 0x00 "MCASP_XRSRCTL11,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B0++0x3
line.long 0x00 "MCASP_XRSRCTL12,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B4++0x3
line.long 0x00 "MCASP_XRSRCTL13,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B8++0x3
line.long 0x00 "MCASP_XRSRCTL14,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1BC++0x3
line.long 0x00 "MCASP_XRSRCTL15,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x200++0x3
line.long 0x00 "MCASP_TXBUF0,"
hexmask.long 0x00 0.--31. 1. " XBUF0     ,Transmit Buffer 0"
group.long 0x204++0x3
line.long 0x00 "MCASP_TXBUF1,"
hexmask.long 0x00 0.--31. 1. " XBUF1     ,Transmit Buffer 1"
group.long 0x208++0x3
line.long 0x00 "MCASP_TXBUF2,"
hexmask.long 0x00 0.--31. 1. " XBUF2     ,Transmit Buffer 2"
group.long 0x20C++0x3
line.long 0x00 "MCASP_TXBUF3,"
hexmask.long 0x00 0.--31. 1. " XBUF3     ,Transmit Buffer 3"
group.long 0x210++0x3
line.long 0x00 "MCASP_TXBUF4,"
hexmask.long 0x00 0.--31. 1. " XBUF4     ,Transmit Buffer 4"
group.long 0x214++0x3
line.long 0x00 "MCASP_TXBUF5,"
hexmask.long 0x00 0.--31. 1. " XBUF5     ,Transmit Buffer 5"
group.long 0x218++0x3
line.long 0x00 "MCASP_TXBUF6,"
hexmask.long 0x00 0.--31. 1. " XBUF6     ,Transmit Buffer 6"
group.long 0x21C++0x3
line.long 0x00 "MCASP_TXBUF7,"
hexmask.long 0x00 0.--31. 1. " XBUF7     ,Transmit Buffer 7"
group.long 0x220++0x3
line.long 0x00 "MCASP_TXBUF8,"
hexmask.long 0x00 0.--31. 1. " XBUF8     ,Transmit Buffer 8"
group.long 0x224++0x3
line.long 0x00 "MCASP_TXBUF9,"
hexmask.long 0x00 0.--31. 1. " XBUF9     ,Transmit Buffer 9"
group.long 0x228++0x3
line.long 0x00 "MCASP_TXBUF10,"
hexmask.long 0x00 0.--31. 1. " XBUF10    ,Transmit Buffer 10"
group.long 0x22C++0x3
line.long 0x00 "MCASP_TXBUF11,"
hexmask.long 0x00 0.--31. 1. " XBUF11    ,Transmit Buffer 11"
group.long 0x230++0x3
line.long 0x00 "MCASP_TXBUF12,"
hexmask.long 0x00 0.--31. 1. " XBUF12    ,Transmit Buffer 12"
group.long 0x234++0x3
line.long 0x00 "MCASP_TXBUF13,"
hexmask.long 0x00 0.--31. 1. " XBUF13    ,Transmit Buffer 13"
group.long 0x238++0x3
line.long 0x00 "MCASP_TXBUF14,"
hexmask.long 0x00 0.--31. 1. " XBUF14    ,Transmit Buffer 14"
group.long 0x23C++0x3
line.long 0x00 "MCASP_TXBUF15,"
hexmask.long 0x00 0.--31. 1. " XBUF15    ,Transmit Buffer 15"
group.long 0x280++0x3
line.long 0x00 "MCASP_RXBUF0,"
hexmask.long 0x00 0.--31. 1. " RBUF0     ,Receive Buffer 0"
group.long 0x284++0x3
line.long 0x00 "MCASP_RXBUF1,"
hexmask.long 0x00 0.--31. 1. " RBUF1     ,Receive Buffer 1"
group.long 0x288++0x3
line.long 0x00 "MCASP_RXBUF2,"
hexmask.long 0x00 0.--31. 1. " RBUF2     ,Receive Buffer 2"
group.long 0x28C++0x3
line.long 0x00 "MCASP_RXBUF3,"
hexmask.long 0x00 0.--31. 1. " RBUF3     ,Receive Buffer 3"
group.long 0x290++0x3
line.long 0x00 "MCASP_RXBUF4,"
hexmask.long 0x00 0.--31. 1. " RBUF4     ,Receive Buffer 4"
group.long 0x294++0x3
line.long 0x00 "MCASP_RXBUF5,"
hexmask.long 0x00 0.--31. 1. " RBUF5     ,Receive Buffer 5"
group.long 0x298++0x3
line.long 0x00 "MCASP_RXBUF6,"
hexmask.long 0x00 0.--31. 1. " RBUF6     ,Receive Buffer 6"
group.long 0x29C++0x3
line.long 0x00 "MCASP_RXBUF7,"
hexmask.long 0x00 0.--31. 1. " RBUF7     ,Receive Buffer 7"
group.long 0x2A0++0x3
line.long 0x00 "MCASP_RXBUF8,"
hexmask.long 0x00 0.--31. 1. " RBUF8     ,Receive Buffer 8"
group.long 0x2A4++0x3
line.long 0x00 "MCASP_RXBUF9,"
hexmask.long 0x00 0.--31. 1. " RBUF9     ,Receive Buffer 9"
group.long 0x2A8++0x3
line.long 0x00 "MCASP_RXBUF10,"
hexmask.long 0x00 0.--31. 1. " RBUF10    ,Receive Buffer 10"
group.long 0x2AC++0x3
line.long 0x00 "MCASP_RXBUF11,"
hexmask.long 0x00 0.--31. 1. " RBUF11    ,Receive Buffer 11"
group.long 0x2B0++0x3
line.long 0x00 "MCASP_RXBUF12,"
hexmask.long 0x00 0.--31. 1. " RBUF12    ,Receive Buffer 12"
group.long 0x2B4++0x3
line.long 0x00 "MCASP_RXBUF13,"
hexmask.long 0x00 0.--31. 1. " RBUF13    ,Receive Buffer 13"
group.long 0x2B8++0x3
line.long 0x00 "MCASP_RXBUF14,"
hexmask.long 0x00 0.--31. 1. " RBUF14    ,Receive Buffer 14"
group.long 0x2BC++0x3
line.long 0x00 "MCASP_RXBUF15,"
hexmask.long 0x00 0.--31. 1. " RBUF15    ,Receive Buffer 15"
group.long 0x1000++0x3
line.long 0x00 "MCASP_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " WENA      ,Write FIFO enable bit. 0h (R/W) = Write FIFO is disabled. The WLVL bit in the Write FIFO status register ( 1h (R/W) = Write FIFO is enabled. If Write FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            WNUMEVT  ,Write word count per DMA event (32 bit). When the Write FIFO has space for at least WNUMEVT words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as transmitters. This value must be set prior to enabling the Write FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA   ,Write word count per transfer (32 bit words). Upon a transmit DMA event from the McASP, WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the Write FIFO. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3-16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x1004++0x3
line.long 0x00 "MCASP_WFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " WLVL      ,Write level (read-only). Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Write FIFO. 1h (R/W) = 1 word currently in Write FIFO. 2h (R/W) = 2 words currently in Write FIFO. 3h (R/W) = 3 to 64 words currently in Write FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
group.long 0x1008++0x3
line.long 0x00 "MCASP_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " RENA      ,Read FIFO enable bit. 0h (R/W) = Read FIFO is disabled. The RLVL bit in the Read FIFO status register ( 1h (R/W) = Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            RNUMEVT  ,Read word count per DMA event (32 bit). When the Read FIFO contains at least RNUMEVT words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as receivers. This value must be set prior to enabling the Read FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h = FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA   ,Read word count per transfer (32 bit words). Upon a receive DMA event from the McASP, the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO. 10h = 3 to 16 words from 3h to 10h. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x100C++0x3
line.long 0x00 "MCASP_RFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " RLVL      ,Read level (read-only). Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Read FIFO. 1h (R/W) = 1 word currently in Read FIFO. 2h (R/W) = 2 words currently in Read FIFO. 3h (R/W) = 3 to 64 words currently in Read FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
width 0x0B
tree.end
tree "MCASP2_CFG"
base ad:0x2B20000
width 24.
rgroup.long 0x0++0x3
line.long 0x00 "MCASP_PID,"
bitfld.long 0x00 30.--31. " SCHEME    ," "0,1,2,3"
bitfld.long 0x00 28.--29. "            RESV     ," "0,1,2,3"
textline "                                 "
hexmask.long.word 0x00 16.--27. 1. " FUNCTION  ,McASP"
bitfld.long 0x00 11.--15. "         RTL      ," "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 8.--10. " REVMAJOR  ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "            CUSTOM   ,non-custom" "0,1,2,3"
textline "                                 "
bitfld.long 0x00 0.--5. " REVMINOR  ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register."
hexmask.long 0x00 6.--31. 1. " RSV       ,Reserved as per PDR 35"
bitfld.long 0x00 2.--5. "     Other    ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                 "
bitfld.long 0x00 0.--1. " IDLE_MODE ,Idle Mode" "0,1,2,3"
group.long 0x10++0x3
line.long 0x00 "MCASP_PFUNC,"
bitfld.long 0x00 31. " AFSR      ,AFSR PFUNC 31" "MCASP,GPIO"
bitfld.long 0x00 30. "        AHCLKR   ,AHCLKR PFUNC 30" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PFUNC 29" "MCASP,GPIO"
bitfld.long 0x00 28. "        AFSX     ,AFSX PFUNC 28" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PFUNC 27" "MCASP,GPIO"
bitfld.long 0x00 26. "        ACLKX    ,ACLKX PFUNC 26" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PFUNC 25" "MCASP,GPIO"
hexmask.long.word 0x00 16.--24. 1. "        RESV1    ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PFUNC BIT 15" "MCASP,GPIO"
bitfld.long 0x00 14. "        AXR14    ,AXR PFUNC BIT 14" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PFUNC BIT 13" "MCASP,GPIO"
bitfld.long 0x00 12. "        AXR12    ,AXR PFUNC BIT 12" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PFUNC BIT 11" "MCASP,GPIO"
bitfld.long 0x00 10. "        AXR10    ,AXR PFUNC BIT 10" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PFUNC BIT 9" "MCASP,GPIO"
bitfld.long 0x00 8. "        AXR8     ,AXR PFUNC BIT 8" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PFUNC BIT 7" "MCASP,GPIO"
bitfld.long 0x00 6. "        AXR6     ,AXR PFUNC BIT 6" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PFUNC BIT 5" "MCASP,GPIO"
bitfld.long 0x00 4. "        AXR4     ,AXR PFUNC BIT 4" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PFUNC BIT 3" "MCASP,GPIO"
bitfld.long 0x00 2. "        AXR2     ,AXR PFUNC BIT 2" "MCASP,GPIO"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PFUNC BIT 1" "MCASP,GPIO"
bitfld.long 0x00 0. "        AXR0     ,AXR PFUNC BIT 0" "MCASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "MCASP_PDIR,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDIR 31" "INPUT,OUTPUT"
bitfld.long 0x00 30. "       AHCLKR   ,AHCLKR PDIR 30" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIR 29" "INPUT,OUTPUT"
bitfld.long 0x00 28. "       AFSX     ,AFSX PDIR 28" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIR 27" "INPUT,OUTPUT"
bitfld.long 0x00 26. "       ACLKX    ,ACLKX PDIR 26" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIR 25" "INPUT,OUTPUT"
hexmask.long.word 0x00 16.--24. 1. "       RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIR BIT 15" "INPUT,OUTPUT"
bitfld.long 0x00 14. "       AXR14    ,AXR PDIR BIT 14" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIR BIT 13" "INPUT,OUTPUT"
bitfld.long 0x00 12. "       AXR12    ,AXR PDIR BIT 12" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIR BIT 11" "INPUT,OUTPUT"
bitfld.long 0x00 10. "       AXR10    ,AXR PDIR BIT 10" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIR BIT 9" "INPUT,OUTPUT"
bitfld.long 0x00 8. "       AXR8     ,AXR PDIR BIT 8" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIR BIT 7" "INPUT,OUTPUT"
bitfld.long 0x00 6. "       AXR6     ,AXR PDIR BIT 6" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIR BIT 5" "INPUT,OUTPUT"
bitfld.long 0x00 4. "       AXR4     ,AXR PDIR BIT 4" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIR BIT 3" "INPUT,OUTPUT"
bitfld.long 0x00 2. "       AXR2     ,AXR PDIR BIT 2" "INPUT,OUTPUT"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIR BIT 1" "INPUT,OUTPUT"
bitfld.long 0x00 0. "       AXR0     ,AXR PDIR BIT 0" "INPUT,OUTPUT"
group.long 0x18++0x3
line.long 0x00 "MCASP_PDOUT,"
bitfld.long 0x00 31. " AFSR      ,AFSR PDOUT 31" "DRV0,DRV1"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDOUT 30" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDOUT 29" "DRV0,DRV1"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDOUT 28" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDOUT 27" "DRV0,DRV1"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDOUT 26" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDOUT 25" "DRV0,DRV1"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDOUT BIT 15" "DRV0,DRV1"
bitfld.long 0x00 14. "         AXR14    ,AXR PDOUT BIT 14" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDOUT BIT 13" "DRV0,DRV1"
bitfld.long 0x00 12. "         AXR12    ,AXR PDOUT BIT 12" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDOUT BIT 11" "DRV0,DRV1"
bitfld.long 0x00 10. "         AXR10    ,AXR PDOUT BIT 10" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDOUT BIT 9" "DRV0,DRV1"
bitfld.long 0x00 8. "         AXR8     ,AXR PDOUT BIT 8" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDOUT BIT 7" "DRV0,DRV1"
bitfld.long 0x00 6. "         AXR6     ,AXR PDOUT BIT 6" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDOUT BIT 5" "DRV0,DRV1"
bitfld.long 0x00 4. "         AXR4     ,AXR PDOUT BIT 4" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDOUT BIT 3" "DRV0,DRV1"
bitfld.long 0x00 2. "         AXR2     ,AXR PDOUT BIT 2" "DRV0,DRV1"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDOUT BIT 1" "DRV0,DRV1"
bitfld.long 0x00 0. "         AXR0     ,AXR PDOUT BIT 0" "DRV0,DRV1"
rgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read, regardless of the state of PFUNC and PDIR."
bitfld.long 0x00 31. " AFSR      ,AFSR PDIN 31" "LOW,HIGH"
bitfld.long 0x00 30. "         AHCLKR   ,AHCLKR PDIN 30" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDIN 29" "LOW,HIGH"
bitfld.long 0x00 28. "         AFSX     ,AFSX PDIN 28" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDIN 27" "LOW,HIGH"
bitfld.long 0x00 26. "         ACLKX    ,ACLKX PDIN 26" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDIN 25" "LOW,HIGH"
hexmask.long.word 0x00 16.--24. 1. "         RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDIN BIT 15" "LOW,HIGH"
bitfld.long 0x00 14. "         AXR14    ,AXR PDIN BIT 14" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDIN BIT 13" "LOW,HIGH"
bitfld.long 0x00 12. "         AXR12    ,AXR PDIN BIT 12" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDIN BIT 11" "LOW,HIGH"
bitfld.long 0x00 10. "         AXR10    ,AXR PDIN BIT 10" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDIN BIT 9" "LOW,HIGH"
bitfld.long 0x00 8. "         AXR8     ,AXR PDIN BIT 8" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDIN BIT 7" "LOW,HIGH"
bitfld.long 0x00 6. "         AXR6     ,AXR PDIN BIT 6" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDIN BIT 5" "LOW,HIGH"
bitfld.long 0x00 4. "         AXR4     ,AXR PDIN BIT 4" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDIN BIT 3" "LOW,HIGH"
bitfld.long 0x00 2. "         AXR2     ,AXR PDIN BIT 2" "LOW,HIGH"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDIN BIT 1" "LOW,HIGH"
bitfld.long 0x00 0. "         AXR0     ,AXR PDIN BIT 0" "LOW,HIGH"
wgroup.long 0x1C++0x3
line.long 0x00 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic high on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDSET 31" "NOEFFECT,SET"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDSET 30" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDSET 29" "NOEFFECT,SET"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDSET 28" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDSET 27" "NOEFFECT,SET"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDSET 26" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDSET 25" "NOEFFECT,SET"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDSET BIT 15" "NOEFFECT,SET"
bitfld.long 0x00 14. "     AXR14    ,AXR PDSET BIT 14" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDSET BIT 13" "NOEFFECT,SET"
bitfld.long 0x00 12. "     AXR12    ,AXR PDSET BIT 12" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDSET BIT 11" "NOEFFECT,SET"
bitfld.long 0x00 10. "     AXR10    ,AXR PDSET BIT 10" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDSET BIT 9" "NOEFFECT,SET"
bitfld.long 0x00 8. "     AXR8     ,AXR PDSET BIT 8" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDSET BIT 7" "NOEFFECT,SET"
bitfld.long 0x00 6. "     AXR6     ,AXR PDSET BIT 6" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDSET BIT 5" "NOEFFECT,SET"
bitfld.long 0x00 4. "     AXR4     ,AXR PDSET BIT 4" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDSET BIT 3" "NOEFFECT,SET"
bitfld.long 0x00 2. "     AXR2     ,AXR PDSET BIT 2" "NOEFFECT,SET"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDSET BIT 1" "NOEFFECT,SET"
bitfld.long 0x00 0. "     AXR0     ,AXR PDSET BIT 0" "NOEFFECT,SET"
group.long 0x20++0x3
line.long 0x00 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic low on the pin."
bitfld.long 0x00 31. " AFSR      ,AFSR PDCLR 31" "NOEFFECT,CLEAR"
bitfld.long 0x00 30. "     AHCLKR   ,AHCLKR PDCLR 30" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 29. " ACLKR     ,ACLKR PDCLR 29" "NOEFFECT,CLEAR"
bitfld.long 0x00 28. "     AFSX     ,AFSX PDCLR 28" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 27. " AHCLKX    ,AHCLKX PDCLR 27" "NOEFFECT,CLEAR"
bitfld.long 0x00 26. "     ACLKX    ,ACLKX PDCLR 26" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 25. " AMUTE     ,AMUTE PDCLR 25" "NOEFFECT,CLEAR"
hexmask.long.word 0x00 16.--24. 1. "     RESV     ,Reserved"
textline "                                 "
bitfld.long 0x00 15. " AXR15     ,AXR PDCLR BIT 15" "NOEFFECT,CLEAR"
bitfld.long 0x00 14. "     AXR14    ,AXR PDCLR BIT 14" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 13. " AXR13     ,AXR PDCLR BIT 13" "NOEFFECT,CLEAR"
bitfld.long 0x00 12. "     AXR12    ,AXR PDCLR BIT 12" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 11. " AXR11     ,AXR PDCLR BIT 11" "NOEFFECT,CLEAR"
bitfld.long 0x00 10. "     AXR10    ,AXR PDCLR BIT 10" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 9. " AXR9      ,AXR PDCLR BIT 9" "NOEFFECT,CLEAR"
bitfld.long 0x00 8. "     AXR8     ,AXR PDCLR BIT 8" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 7. " AXR7      ,AXR PDCLR BIT 7" "NOEFFECT,CLEAR"
bitfld.long 0x00 6. "     AXR6     ,AXR PDCLR BIT 6" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 5. " AXR5      ,AXR PDCLR BIT 5" "NOEFFECT,CLEAR"
bitfld.long 0x00 4. "     AXR4     ,AXR PDCLR BIT 4" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 3. " AXR3      ,AXR PDCLR BIT 3" "NOEFFECT,CLEAR"
bitfld.long 0x00 2. "     AXR2     ,AXR PDCLR BIT 2" "NOEFFECT,CLEAR"
textline "                                 "
bitfld.long 0x00 1. " AXR1      ,AXR PDCLR BIT 1" "NOEFFECT,CLEAR"
bitfld.long 0x00 0. "     AXR0     ,AXR PDCLR BIT 0" "NOEFFECT,CLEAR"
group.long 0x30++0x3
line.long 0x00 "MCASP_TLGC,for IODFT"
hexmask.long.word 0x00 16.--31. 1. " RESV      ,Reserved"
bitfld.long 0x00 14.--15. "         MT       ,MISR on/off trigger command" "CONTINUOUS,TLECEXP,NOEFFECT,NOEFFECT1"
textline "                                 "
bitfld.long 0x00 9.--13. " RESV1     ,Reserved" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 8. "   MMS      ,Source of MISR input" "OUTREG,INREG"
textline "                                 "
bitfld.long 0x00 7. " ESEL      ,Output enable select" "TEST,FUNC"
bitfld.long 0x00 6. "         TOEN     ,Test output enable control" "ENABLED,DISABLED"
textline "                                 "
bitfld.long 0x00 4.--5. " MC        ,States of MISR" "DLRESULTS,HOLDCURRENT,LOADINITIAL,MISRENABLE"
bitfld.long 0x00 1.--3. "  PC       ,Pattern code" "FUNCTIONAL,RANDOMXOR,RANDOMXNOR,4BITSHIFTER,RESERVED,RESERVED1,RESERVED2,RESERVED3"
textline "                                 "
bitfld.long 0x00 0. " TM        ,Tie high; do not write to this bit" "RESERVED,FUNCTIONAL"
group.long 0x34++0x3
line.long 0x00 "MCASP_TLMR,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLMR      ,Contains test result signature"
group.long 0x38++0x3
line.long 0x00 "MCASP_TLEC,for IODFT"
hexmask.long 0x00 0.--31. 1. " TLEC      ,Contains number of cycles during which MISR sig will be accumulated"
group.long 0x44++0x3
line.long 0x00 "MCASP_GBLCTL,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x48++0x3
line.long 0x00 "MCASP_AMUTE,"
bitfld.long 0x00 12. " XDMAERR   ,MUTETXDMAERR occur" "DISABLE,ENABLE"
bitfld.long 0x00 11. "      RDMAERR  ,MUTERXDMAERR occur" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 10. " XCKFAIL   ,XMT bad clock" "DISABLE,ENABLE"
bitfld.long 0x00 9. "      RCKFAIL  ,RCV bad clock" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 8. " XSYNCERR  ,XMT unexpected FS" "DISABLE,ENABLE"
bitfld.long 0x00 7. "      RSYNCERR ,RCV unexpected FS" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 6. " XUNDRN    ,XMT underrun occurs" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      ROVRN    ,RCV overun occurs" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " INSTAT    ,status of mute in pin" "ACTIVE,INACTIVE"
bitfld.long 0x00 3. "     INEN     ,drive AMUTE active on mute in active" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " INPOL     ,Mute input polarity" "ACTHIGH,ACTLOW"
bitfld.long 0x00 0.--1. "      MUTEN    ,AMUTE pin enable" "DISABLE,ERRHIGH,ERRLOW,3"
group.long 0x4C++0x3
line.long 0x00 "MCASP_LBCTL,"
bitfld.long 0x00 4. " IOLBEN    ,IO loopback enable" "DISABLE,ENABLE"
bitfld.long 0x00 2.--3. "      MODE     ,Loop back clock source generator" "RESERVED,XMTCLK,RESERVED1,RESERVED2"
textline "                                 "
bitfld.long 0x00 1. " ORD       ,Loopback order" "ODD,EVEN"
bitfld.long 0x00 0. "         DLBEN    ,Loop back mode" "DISABLE,ENABLE"
group.long 0x50++0x3
line.long 0x00 "MCASP_TXDITCTL,"
bitfld.long 0x00 3. " VB        ,Valib bit for odd TDM" "ZEROSTUFF,ONESTUFF"
bitfld.long 0x00 2. "    VA       ,Valib bit for even TDM" "ZEROSTUFF,ONESTUFF"
textline "                                 "
bitfld.long 0x00 0. " DITEN     ,XMT DIT Mode Enable" "DISABLE,ENABLE"
group.long 0x60++0x3
line.long 0x00 "MCASP_GBLCTLR,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLR   ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0x64++0x3
line.long 0x00 "MCASP_RXMASK,"
bitfld.long 0x00 31. " RMASK31   ,RMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      RMASK30  ,RMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " RMASK29   ,RMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      RMASK28  ,RMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " RMASK27   ,RMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      RMASK26  ,RMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " RMASK25   ,RMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      RMASK24  ,RMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " RMASK23   ,RMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      RMASK22  ,RMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " RMASK21   ,RMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      RMASK20  ,RMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " RMASK19   ,RMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      RMASK18  ,RMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " RMASK17   ,RMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      RMASK16  ,RMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " RMASK15   ,RMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      RMASK14  ,RMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " RMASK13   ,RMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      RMASK12  ,RMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " RMASK11   ,RMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      RMASK10  ,RMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " RMASK9    ,RMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      RMASK8   ,RMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " RMASK7    ,RMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      RMASK6   ,RMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " RMASK5    ,RMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      RMASK4   ,RMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " RMASK3    ,RMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      RMASK2   ,RMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " RMASK1    ,RMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      RMASK0   ,RMASK BIT 0" "USEMASK,NOMASK"
group.long 0x68++0x3
line.long 0x00 "MCASP_RXFMT,"
bitfld.long 0x00 16.--17. " RDATDLY   ,RCV Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         RRVRS    ,RCV serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " RPAD      ,Pad value" "ZERO,ONE,RPBIT,3"
bitfld.long 0x00 8.--12. "        RPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " RSSZ      ,RCV slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       RBUSEL   ,Write to RBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " RROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0x6C++0x3
line.long 0x00 "MCASP_RXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " RMOD      ,RCV Frame sync mode"
bitfld.long 0x00 4. "         FRWID    ,RCV Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSRM      ,RCV frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSRP     ,RCV Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0x70++0x3
line.long 0x00 "MCASP_ACLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKRADJ  ,CLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKRP     ,RCV Clock Polarity" "FALLINGEDGE,RISINGEDGE"
bitfld.long 0x00 5. "  CLKRM    ,RCV clock source" "EXTERNAL,INTERNAL"
textline "                                 "
bitfld.long 0x00 0.--4. " CLKRDIV   ,RCV clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0x74++0x3
line.long 0x00 "MCASP_AHCLKRCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKRADJ ,HCLKRDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKRM    ,High Freq RCV clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKRP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV  ,RCV clock Divide Ratio"
group.long 0x78++0x3
line.long 0x00 "MCASP_RXTDM,"
bitfld.long 0x00 31. " RTDMS31   ,RCV mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     RTDMS30  ,RCV mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " RTDMS29   ,RCV mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     RTDMS28  ,RCV mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " RTDMS27   ,RCV mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     RTDMS26  ,RCV mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " RTDMS25   ,RCV mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     RTDMS24  ,RCV mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " RTDMS23   ,RCV mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     RTDMS22  ,RCV mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " RTDMS21   ,RCV mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     RTDMS20  ,RCV mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " RTDMS19   ,RCV mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     RTDMS18  ,RCV mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " RTDMS17   ,RCV mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     RTDMS16  ,RCV mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " RTDMS15   ,RCV mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     RTDMS14  ,RCV mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " RTDMS13   ,RCV mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     RTDMS12  ,RCV mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " RTDMS11   ,RCV mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     RTDMS10  ,RCV mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " RTDMS9    ,RCV mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     RTDMS8   ,RCV mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " RTDMS7    ,RCV mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     RTDMS6   ,RCV mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " RTDMS5    ,RCV mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     RTDMS4   ,RCV mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RTDMS3    ,RCV mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     RTDMS2   ,RCV mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RTDMS1    ,RCV mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     RTDMS0   ,RCV mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0x7C++0x3
line.long 0x00 "MCASP_EVTCTLR,"
bitfld.long 0x00 7. " RSTAFRM   ,RCV Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      RDATA    ,RCV Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,RCV Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      RDMAERR  ,RCV DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      RSYNCERR ,RCV Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "DISABLE,ENABLE"
group.long 0x80++0x3
line.long 0x00 "MCASP_RXSTAT,"
bitfld.long 0x00 8. " RERR      ,RCV Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      RDMAERR  ,RCV DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " RSTAFRM   ,Start of Frame-RCV" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     RDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " RLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     RTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " RCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     RSYNCERR ,Unexpected RCV Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " ROVRN     ,RCV Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0x84++0x3
line.long 0x00 "MCASP_RXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " RSLOTCNT  ,Current RCV time slot count"
group.long 0x88++0x3
line.long 0x00 "MCASP_RXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " RCNT      ,RCV clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           RMAX     ,RCV clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " RMIN      ,RCV clock minimum boundary"
bitfld.long 0x00 0.--3. "           RPS      ,RCV clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0x8C++0x3
line.long 0x00 "MCASP_REVTCTL,"
bitfld.long 0x00 0. " RDATDMA   ,RCV data DMA request" "ENABLE,DISABLE"
group.long 0xA0++0x3
line.long 0x00 "MCASP_GBLCTLX,"
bitfld.long 0x00 12. " XFRST     ,Frame sync generator reset" "RESET,ACTIVE"
bitfld.long 0x00 11. "       XSMRST   ,XMT state machine reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 10. " XSRCLR    ,XMT serializer clear" "CLEAR,ACTIVE"
bitfld.long 0x00 9. "       XHCLKRST ,XMT High Freq clk Divider" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 8. " XCLKRST   ,XMT clock divder reset" "RESET,ACTIVE"
bitfld.long 0x00 4. "       RFRST    ,Frame sync generator reset" "RESET,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " RSMRST    ,RCV state machine reset" "RESET,ACTIVE"
bitfld.long 0x00 2. "       RSRCLKR  ,RCV serializer clear" "CLEAR,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " RHCLKRST  ,RCV High Freq clk Divider" "RESET,ACTIVE"
bitfld.long 0x00 0. "       RCLKRST  ,RCV clock divder reset" "RESET,ACTIVE"
group.long 0xA4++0x3
line.long 0x00 "MCASP_TXMASK,"
bitfld.long 0x00 31. " XMASK31   ,XMASK BIT 31" "USEMASK,NOMASK"
bitfld.long 0x00 30. "      XMASK30  ,XMASK BIT 30" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 29. " XMASK29   ,XMASK BIT 29" "USEMASK,NOMASK"
bitfld.long 0x00 28. "      XMASK28  ,XMASK BIT 28" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 27. " XMASK27   ,XMASK BIT 27" "USEMASK,NOMASK"
bitfld.long 0x00 26. "      XMASK26  ,XMASK BIT 26" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 25. " XMASK25   ,XMASK BIT 25" "USEMASK,NOMASK"
bitfld.long 0x00 24. "      XMASK24  ,XMASK BIT 24" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 23. " XMASK23   ,XMASK BIT 23" "USEMASK,NOMASK"
bitfld.long 0x00 22. "      XMASK22  ,XMASK BIT 22" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 21. " XMASK21   ,XMASK BIT 21" "USEMASK,NOMASK"
bitfld.long 0x00 20. "      XMASK20  ,XMASK BIT 20" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 19. " XMASK19   ,XMASK BIT 19" "USEMASK,NOMASK"
bitfld.long 0x00 18. "      XMASK18  ,XMASK BIT 18" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 17. " XMASK17   ,XMASK BIT 17" "USEMASK,NOMASK"
bitfld.long 0x00 16. "      XMASK16  ,XMASK BIT 16" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 15. " XMASK15   ,XMASK BIT 15" "USEMASK,NOMASK"
bitfld.long 0x00 14. "      XMASK14  ,XMASK BIT 14" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 13. " XMASK13   ,XMASK BIT 13" "USEMASK,NOMASK"
bitfld.long 0x00 12. "      XMASK12  ,XMASK BIT 12" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 11. " XMASK11   ,XMASK BIT 11" "USEMASK,NOMASK"
bitfld.long 0x00 10. "      XMASK10  ,XMASK BIT 10" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 9. " XMASK9    ,XMASK BIT 9" "USEMASK,NOMASK"
bitfld.long 0x00 8. "      XMASK8   ,XMASK BIT 8" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 7. " XMASK7    ,XMASK BIT 7" "USEMASK,NOMASK"
bitfld.long 0x00 6. "      XMASK6   ,XMASK BIT 6" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 5. " XMASK5    ,XMASK BIT 5" "USEMASK,NOMASK"
bitfld.long 0x00 4. "      XMASK4   ,XMASK BIT 4" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 3. " XMASK3    ,XMASK BIT 3" "USEMASK,NOMASK"
bitfld.long 0x00 2. "      XMASK2   ,XMASK BIT 2" "USEMASK,NOMASK"
textline "                                 "
bitfld.long 0x00 1. " XMASK1    ,XMASK BIT 1" "USEMASK,NOMASK"
bitfld.long 0x00 0. "      XMASK0   ,XMASK BIT 0" "USEMASK,NOMASK"
group.long 0xA8++0x3
line.long 0x00 "MCASP_TXFMT,"
bitfld.long 0x00 16.--17. " XDATDLY   ,XMT Frame sync delay" "0BIT,1BIT,2BIT,3"
bitfld.long 0x00 15. "         XRVRS    ,XMT serial stream bit order" "LSBFIRST,MSBFIRST"
textline "                                 "
bitfld.long 0x00 13.--14. " XPAD      ,Pad value" "ZERO,ONE,XPBIT,3"
bitfld.long 0x00 8.--12. "        XPBIT    ,Pad bit position" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
textline "                                 "
bitfld.long 0x00 4.--7. " XSSZ      ,XMT slot Size" "RSV,RSV1,RSV2,8BITS,RSV3,12BITS,RSV4,16BITS,RSV5,20BITS,RSV6,24BITS,RSV7,28BITS,RSV8,32BITS"
bitfld.long 0x00 3. "       XBUSEL   ,Write to XBUF using CPU/DMA" "VBUSP,VBUS"
textline "                                 "
bitfld.long 0x00 0.--2. " XROT      ,Right Rotate Value" "NONE,4BITS,8BITS,12BITS,16BITS,20BITS,24BITS,28BITS"
group.long 0xAC++0x3
line.long 0x00 "MCASP_TXFMCTL,"
hexmask.long.word 0x00 7.--15. 1. " XMOD      ,XMT Frame sync mode"
bitfld.long 0x00 4. "         FXWID    ,XMT Frame sync Duration" "BIT,WORD"
textline "                                 "
bitfld.long 0x00 1. " FSXM      ,XMT frame sync External" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0. "     FSXP     ,XMT Frame sync Polarity" "RISINGEDGE,FALLINGEDGE"
group.long 0xB0++0x3
line.long 0x00 "MCASP_ACLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      CLKXADJ  ,CLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 7. " CLKXP     ,XMT Clock Polarity" "RISINGEDGE,FALLINGEDGE"
bitfld.long 0x00 6. "  ASYNC    ,XMT/RCV operation sync /Async" "SYNC,ASYNC"
textline "                                 "
bitfld.long 0x00 5. " CLKXM     ,XMT clock source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 0.--4. "     CLKXDIV  ,XMT clock devide ratio" "0,0x01,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
group.long 0xB4++0x3
line.long 0x00 "MCASP_AHCLKXCTL,"
bitfld.long 0x00 20. " BUSY      ,Status: logical OR of DIVBUSY, ADJBUSY" "NOTBUSY,BUSY"
bitfld.long 0x00 19. "      DIVBUSY  ,Status: divide ratio change in progress?" "NOTBUSY,BUSY"
textline "                                 "
bitfld.long 0x00 18. " ADJBUSY   ,Status: one-shot adjustment in progress?" "NOTBUSY,BUSY"
bitfld.long 0x00 16.--17. "      HCLKXADJ ,HCLKXDIV one-shot adjustment" "PLUSZERO,MINUSONE,PLUSONE,PLUSZER0"
textline "                                 "
bitfld.long 0x00 15. " HCLKXM    ,High Freq XMT clock Source" "EXTERNAL,INTERNAL"
bitfld.long 0x00 14. "     HCLKXP   ,High Freq clock Polarity Before diviser" "NOTINVERTED,INVERTED"
textline "                                 "
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV  ,XMT clock Divide Ratio"
group.long 0xB8++0x3
line.long 0x00 "MCASP_TXTDM,"
bitfld.long 0x00 31. " XTDMS31   ,XMT mode during TDM time slot 31" "INACTIVE,ACTIVE"
bitfld.long 0x00 30. "     XTDMS30  ,XMT mode during TDM time slot 30" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 29. " XTDMS29   ,XMT mode during TDM time slot 29" "INACTIVE,ACTIVE"
bitfld.long 0x00 28. "     XTDMS28  ,XMT mode during TDM time slot 28" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 27. " XTDMS27   ,XMT mode during TDM time slot 27" "INACTIVE,ACTIVE"
bitfld.long 0x00 26. "     XTDMS26  ,XMT mode during TDM time slot 26" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 25. " XTDMS25   ,XMT mode during TDM time slot 25" "INACTIVE,ACTIVE"
bitfld.long 0x00 24. "     XTDMS24  ,XMT mode during TDM time slot 24" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 23. " XTDMS23   ,XMT mode during TDM time slot 23" "INACTIVE,ACTIVE"
bitfld.long 0x00 22. "     XTDMS22  ,XMT mode during TDM time slot 22" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 21. " XTDMS21   ,XMT mode during TDM time slot 21" "INACTIVE,ACTIVE"
bitfld.long 0x00 20. "     XTDMS20  ,XMT mode during TDM time slot 20" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 19. " XTDMS19   ,XMT mode during TDM time slot 19" "INACTIVE,ACTIVE"
bitfld.long 0x00 18. "     XTDMS18  ,XMT mode during TDM time slot 18" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 17. " XTDMS17   ,XMT mode during TDM time slot 17" "INACTIVE,ACTIVE"
bitfld.long 0x00 16. "     XTDMS16  ,XMT mode during TDM time slot 16" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 15. " XTDMS15   ,XMT mode during TDM time slot 15" "INACTIVE,ACTIVE"
bitfld.long 0x00 14. "     XTDMS14  ,XMT mode during TDM time slot 14" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 13. " XTDMS13   ,XMT mode during TDM time slot 13" "INACTIVE,ACTIVE"
bitfld.long 0x00 12. "     XTDMS12  ,XMT mode during TDM time slot 12" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 11. " XTDMS11   ,XMT mode during TDM time slot 11" "INACTIVE,ACTIVE"
bitfld.long 0x00 10. "     XTDMS10  ,XMT mode during TDM time slot 10" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 9. " XTDMS9    ,XMT mode during TDM time slot 9" "INACTIVE,ACTIVE"
bitfld.long 0x00 8. "     XTDMS8   ,XMT mode during TDM time slot 8" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 7. " XTDMS7    ,XMT mode during TDM time slot 7" "INACTIVE,ACTIVE"
bitfld.long 0x00 6. "     XTDMS6   ,XMT mode during TDM time slot 6" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 5. " XTDMS5    ,XMT mode during TDM time slot 5" "INACTIVE,ACTIVE"
bitfld.long 0x00 4. "     XTDMS4   ,XMT mode during TDM time slot 4" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 3. " XTDMS3    ,XMT mode during TDM time slot 3" "INACTIVE,ACTIVE"
bitfld.long 0x00 2. "     XTDMS2   ,XMT mode during TDM time slot 2" "INACTIVE,ACTIVE"
textline "                                 "
bitfld.long 0x00 1. " XTDMS1    ,XMT mode during TDM time slot 1" "INACTIVE,ACTIVE"
bitfld.long 0x00 0. "     XTDMS0   ,XMT mode during TDM time slot 0" "INACTIVE,ACTIVE"
group.long 0xBC++0x3
line.long 0x00 "MCASP_EVTCTLX,"
bitfld.long 0x00 7. " XSTAFRM   ,XMT Start of Frame Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 5. "      XDATA    ,XMT Data Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,XMT Last Slot Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 3. "      XDMAERR  ,XMT DMA Bus Error" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Clock Interrupt" "DISABLE,ENABLE"
bitfld.long 0x00 1. "      XSYNCERR ,XMT Unexpected FSR Interrupt" "DISABLE,ENABLE"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Interrupt" "DISABLE,ENABLE"
group.long 0xC0++0x3
line.long 0x00 "MCASP_TXSTAT,"
bitfld.long 0x00 8. " XERR      ,XMT Error" "NOERROR,ERROR"
bitfld.long 0x00 7. "      XDMAERR  ,XMT DMA bus error" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 6. " XSTAFRM   ,Start of Frame-XMT" "NOTOCCUR,OCCUR"
bitfld.long 0x00 5. "     XDATA    ,Data Ready Flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 4. " XLAST     ,Last Slot Interrupt Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 3. "     XTDMSLOT ,EvenOdd Slot" "ODDSLOT,EVENSLOT"
textline "                                 "
bitfld.long 0x00 2. " XCKFAIL   ,Bad Transmit Flag" "NOTOCCUR,OCCUR"
bitfld.long 0x00 1. "     XSYNCERR ,Unexpected XMT Frame sync flag" "NOTOCCUR,OCCUR"
textline "                                 "
bitfld.long 0x00 0. " XUNDRN    ,XMT Underrun Flag" "NOTOCCUR,OCCUR"
rgroup.long 0xC4++0x3
line.long 0x00 "MCASP_TXTDMSLOT,"
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT  ,Current XMT time slot count during reset the value of this register is 0b0101111111 [0x17f] and after reset 0"
group.long 0xC8++0x3
line.long 0x00 "MCASP_TXCLKCHK,"
hexmask.long.byte 0x00 24.--31. 1. " XCNT      ,XMT clock count value"
hexmask.long.byte 0x00 16.--23. 1. "           XMAX     ,XMT clock maximum boundary"
textline "                                 "
hexmask.long.byte 0x00 8.--15. 1. " XMIN      ,XMT clock minimum boundary"
bitfld.long 0x00 7. "           RESV     ,Reserved" "0,1"
textline "                                 "
bitfld.long 0x00 0.--3. " XPS       ,XMT clock check prescaler" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128,DIVBY256,9,10,11,12,13,14,15"
group.long 0xCC++0x3
line.long 0x00 "MCASP_XEVTCTL,"
bitfld.long 0x00 0. " XDATDMA   ,XMT data DMA request" "ENABLE,DISABLE"
group.long 0xD0++0x3
line.long 0x00 "MCASP_CLKADJEN,"
bitfld.long 0x00 0. " ENABLE    ,One-shot clock adjust enable" "DISABLE,ENABLE"
group.long 0x100++0x3
line.long 0x00 "MCASP_DITCSRA0,"
hexmask.long 0x00 0.--31. 1. " DITCSRA0  ,Left [Even TDM slot ] Channel status"
group.long 0x104++0x3
line.long 0x00 "MCASP_DITCSRA1,"
hexmask.long 0x00 0.--31. 1. " DITCSRA1  ,Left [Even TDM slot ] Channel status"
group.long 0x108++0x3
line.long 0x00 "MCASP_DITCSRA2,"
hexmask.long 0x00 0.--31. 1. " DITCSRA2  ,Left [Even TDM slot ] Channel status Register"
group.long 0x10C++0x3
line.long 0x00 "MCASP_DITCSRA3,"
hexmask.long 0x00 0.--31. 1. " DITCSRA3  ,Left [Even TDM slot ] Channel status Register"
group.long 0x110++0x3
line.long 0x00 "MCASP_DITCSRA4,"
hexmask.long 0x00 0.--31. 1. " DITCSRA4  ,Left [Even TDM slot ] Channel status"
group.long 0x114++0x3
line.long 0x00 "MCASP_DITCSRA5,"
hexmask.long 0x00 0.--31. 1. " DITCSRA5  ,Left [Even TDM slot ] Channel status"
group.long 0x118++0x3
line.long 0x00 "MCASP_DITCSRB0,"
hexmask.long 0x00 0.--31. 1. " DITCSRB0  ,Right [odd TDM slot ] Channel status"
group.long 0x11C++0x3
line.long 0x00 "MCASP_DITCSRB1,"
hexmask.long 0x00 0.--31. 1. " DITCSRB1  ,Right [odd TDM slot ] Channel status"
group.long 0x120++0x3
line.long 0x00 "MCASP_DITCSRB2,"
hexmask.long 0x00 0.--31. 1. " DITCSRB2  ,Right [odd TDM slot ] Channel status"
group.long 0x124++0x3
line.long 0x00 "MCASP_DITCSRB3,"
hexmask.long 0x00 0.--31. 1. " DITCSRB3  ,Right [odd TDM slot ] Channel status"
group.long 0x128++0x3
line.long 0x00 "MCASP_DITCSRB4,"
hexmask.long 0x00 0.--31. 1. " DITCSRB4  ,Right [odd TDM slot ] Channel status"
group.long 0x12C++0x3
line.long 0x00 "MCASP_DITCSRB5,"
hexmask.long 0x00 0.--31. 1. " DITCSRB5  ,Right [odd TDM slot ] Channel status"
group.long 0x130++0x3
line.long 0x00 "MCASP_DITUDRA0,"
hexmask.long 0x00 0.--31. 1. " DITUDRA0  ,Left [Even TDM slot ] User Data"
group.long 0x134++0x3
line.long 0x00 "MCASP_DITUDRA1,"
hexmask.long 0x00 0.--31. 1. " DITUDRA1  ,Left [Even TDM slot ] User Data"
group.long 0x138++0x3
line.long 0x00 "MCASP_DITUDRA2,"
hexmask.long 0x00 0.--31. 1. " DITUDRA2  ,Left [Even TDM slot ] User Data"
group.long 0x13C++0x3
line.long 0x00 "MCASP_DITUDRA3,"
hexmask.long 0x00 0.--31. 1. " DITUDRA3  ,Left [Even TDM slot ] User Data"
group.long 0x140++0x3
line.long 0x00 "MCASP_DITUDRA4,"
hexmask.long 0x00 0.--31. 1. " DITUDRA4  ,Left [Even TDM slot ] User Data"
group.long 0x144++0x3
line.long 0x00 "MCASP_DITUDRA5,"
hexmask.long 0x00 0.--31. 1. " DITUDRA5  ,Left [Even TDM slot ] User Data"
group.long 0x148++0x3
line.long 0x00 "MCASP_DITUDRB0,"
hexmask.long 0x00 0.--31. 1. " DITUDRB0  ,Right [odd TDM slot ] User Data"
group.long 0x14C++0x3
line.long 0x00 "MCASP_DITUDRB1,"
hexmask.long 0x00 0.--31. 1. " DITUDRB1  ,Right [odd TDM slot ] User Data"
group.long 0x150++0x3
line.long 0x00 "MCASP_DITUDRB2,"
hexmask.long 0x00 0.--31. 1. " DITUDRB2  ,Right [odd TDM slot ] User Data"
group.long 0x154++0x3
line.long 0x00 "MCASP_DITUDRB3,"
hexmask.long 0x00 0.--31. 1. " DITUDRB3  ,Right [odd TDM slot ] User Data"
group.long 0x158++0x3
line.long 0x00 "MCASP_DITUDRB4,"
hexmask.long 0x00 0.--31. 1. " DITUDRB4  ,Right [odd TDM slot ] User Data"
group.long 0x15C++0x3
line.long 0x00 "MCASP_DITUDRB5,"
hexmask.long 0x00 0.--31. 1. " DITUDRB5  ,Right [odd TDM slot ] User Data"
group.long 0x180++0x3
line.long 0x00 "MCASP_XRSRCTL0,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x184++0x3
line.long 0x00 "MCASP_XRSRCTL1,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x188++0x3
line.long 0x00 "MCASP_XRSRCTL2,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x18C++0x3
line.long 0x00 "MCASP_XRSRCTL3,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x190++0x3
line.long 0x00 "MCASP_XRSRCTL4,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x194++0x3
line.long 0x00 "MCASP_XRSRCTL5,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x198++0x3
line.long 0x00 "MCASP_XRSRCTL6,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x19C++0x3
line.long 0x00 "MCASP_XRSRCTL7,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A0++0x3
line.long 0x00 "MCASP_XRSRCTL8,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A4++0x3
line.long 0x00 "MCASP_XRSRCTL9,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1A8++0x3
line.long 0x00 "MCASP_XRSRCTL10,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1AC++0x3
line.long 0x00 "MCASP_XRSRCTL11,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B0++0x3
line.long 0x00 "MCASP_XRSRCTL12,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B4++0x3
line.long 0x00 "MCASP_XRSRCTL13,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1B8++0x3
line.long 0x00 "MCASP_XRSRCTL14,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x1BC++0x3
line.long 0x00 "MCASP_XRSRCTL15,"
bitfld.long 0x00 5. " RRDY      ,Receive buffer ready" "EMPTY,DATA"
bitfld.long 0x00 4. "        XRDY     ,Transmit buffer ready" "DATA,EMPTY"
textline "                                 "
bitfld.long 0x00 2.--3. " DISMOD    ,Serializer drive state" "TRI,RSV,DRV0,DRV1"
bitfld.long 0x00 0.--1. "         SRMOD    ,Serializer Mode" "INACTIVE,XMT,RCV,3"
group.long 0x200++0x3
line.long 0x00 "MCASP_TXBUF0,"
hexmask.long 0x00 0.--31. 1. " XBUF0     ,Transmit Buffer 0"
group.long 0x204++0x3
line.long 0x00 "MCASP_TXBUF1,"
hexmask.long 0x00 0.--31. 1. " XBUF1     ,Transmit Buffer 1"
group.long 0x208++0x3
line.long 0x00 "MCASP_TXBUF2,"
hexmask.long 0x00 0.--31. 1. " XBUF2     ,Transmit Buffer 2"
group.long 0x20C++0x3
line.long 0x00 "MCASP_TXBUF3,"
hexmask.long 0x00 0.--31. 1. " XBUF3     ,Transmit Buffer 3"
group.long 0x210++0x3
line.long 0x00 "MCASP_TXBUF4,"
hexmask.long 0x00 0.--31. 1. " XBUF4     ,Transmit Buffer 4"
group.long 0x214++0x3
line.long 0x00 "MCASP_TXBUF5,"
hexmask.long 0x00 0.--31. 1. " XBUF5     ,Transmit Buffer 5"
group.long 0x218++0x3
line.long 0x00 "MCASP_TXBUF6,"
hexmask.long 0x00 0.--31. 1. " XBUF6     ,Transmit Buffer 6"
group.long 0x21C++0x3
line.long 0x00 "MCASP_TXBUF7,"
hexmask.long 0x00 0.--31. 1. " XBUF7     ,Transmit Buffer 7"
group.long 0x220++0x3
line.long 0x00 "MCASP_TXBUF8,"
hexmask.long 0x00 0.--31. 1. " XBUF8     ,Transmit Buffer 8"
group.long 0x224++0x3
line.long 0x00 "MCASP_TXBUF9,"
hexmask.long 0x00 0.--31. 1. " XBUF9     ,Transmit Buffer 9"
group.long 0x228++0x3
line.long 0x00 "MCASP_TXBUF10,"
hexmask.long 0x00 0.--31. 1. " XBUF10    ,Transmit Buffer 10"
group.long 0x22C++0x3
line.long 0x00 "MCASP_TXBUF11,"
hexmask.long 0x00 0.--31. 1. " XBUF11    ,Transmit Buffer 11"
group.long 0x230++0x3
line.long 0x00 "MCASP_TXBUF12,"
hexmask.long 0x00 0.--31. 1. " XBUF12    ,Transmit Buffer 12"
group.long 0x234++0x3
line.long 0x00 "MCASP_TXBUF13,"
hexmask.long 0x00 0.--31. 1. " XBUF13    ,Transmit Buffer 13"
group.long 0x238++0x3
line.long 0x00 "MCASP_TXBUF14,"
hexmask.long 0x00 0.--31. 1. " XBUF14    ,Transmit Buffer 14"
group.long 0x23C++0x3
line.long 0x00 "MCASP_TXBUF15,"
hexmask.long 0x00 0.--31. 1. " XBUF15    ,Transmit Buffer 15"
group.long 0x280++0x3
line.long 0x00 "MCASP_RXBUF0,"
hexmask.long 0x00 0.--31. 1. " RBUF0     ,Receive Buffer 0"
group.long 0x284++0x3
line.long 0x00 "MCASP_RXBUF1,"
hexmask.long 0x00 0.--31. 1. " RBUF1     ,Receive Buffer 1"
group.long 0x288++0x3
line.long 0x00 "MCASP_RXBUF2,"
hexmask.long 0x00 0.--31. 1. " RBUF2     ,Receive Buffer 2"
group.long 0x28C++0x3
line.long 0x00 "MCASP_RXBUF3,"
hexmask.long 0x00 0.--31. 1. " RBUF3     ,Receive Buffer 3"
group.long 0x290++0x3
line.long 0x00 "MCASP_RXBUF4,"
hexmask.long 0x00 0.--31. 1. " RBUF4     ,Receive Buffer 4"
group.long 0x294++0x3
line.long 0x00 "MCASP_RXBUF5,"
hexmask.long 0x00 0.--31. 1. " RBUF5     ,Receive Buffer 5"
group.long 0x298++0x3
line.long 0x00 "MCASP_RXBUF6,"
hexmask.long 0x00 0.--31. 1. " RBUF6     ,Receive Buffer 6"
group.long 0x29C++0x3
line.long 0x00 "MCASP_RXBUF7,"
hexmask.long 0x00 0.--31. 1. " RBUF7     ,Receive Buffer 7"
group.long 0x2A0++0x3
line.long 0x00 "MCASP_RXBUF8,"
hexmask.long 0x00 0.--31. 1. " RBUF8     ,Receive Buffer 8"
group.long 0x2A4++0x3
line.long 0x00 "MCASP_RXBUF9,"
hexmask.long 0x00 0.--31. 1. " RBUF9     ,Receive Buffer 9"
group.long 0x2A8++0x3
line.long 0x00 "MCASP_RXBUF10,"
hexmask.long 0x00 0.--31. 1. " RBUF10    ,Receive Buffer 10"
group.long 0x2AC++0x3
line.long 0x00 "MCASP_RXBUF11,"
hexmask.long 0x00 0.--31. 1. " RBUF11    ,Receive Buffer 11"
group.long 0x2B0++0x3
line.long 0x00 "MCASP_RXBUF12,"
hexmask.long 0x00 0.--31. 1. " RBUF12    ,Receive Buffer 12"
group.long 0x2B4++0x3
line.long 0x00 "MCASP_RXBUF13,"
hexmask.long 0x00 0.--31. 1. " RBUF13    ,Receive Buffer 13"
group.long 0x2B8++0x3
line.long 0x00 "MCASP_RXBUF14,"
hexmask.long 0x00 0.--31. 1. " RBUF14    ,Receive Buffer 14"
group.long 0x2BC++0x3
line.long 0x00 "MCASP_RXBUF15,"
hexmask.long 0x00 0.--31. 1. " RBUF15    ,Receive Buffer 15"
group.long 0x1000++0x3
line.long 0x00 "MCASP_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " WENA      ,Write FIFO enable bit. 0h (R/W) = Write FIFO is disabled. The WLVL bit in the Write FIFO status register ( 1h (R/W) = Write FIFO is enabled. If Write FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            WNUMEVT  ,Write word count per DMA event (32 bit). When the Write FIFO has space for at least WNUMEVT words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as transmitters. This value must be set prior to enabling the Write FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA   ,Write word count per transfer (32 bit words). Upon a transmit DMA event from the McASP, WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the Write FIFO. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3-16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x1004++0x3
line.long 0x00 "MCASP_WFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " WLVL      ,Write level (read-only). Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Write FIFO. 1h (R/W) = 1 word currently in Write FIFO. 2h (R/W) = 2 words currently in Write FIFO. 3h (R/W) = 3 to 64 words currently in Write FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
group.long 0x1008++0x3
line.long 0x00 "MCASP_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset"
bitfld.long 0x00 16. " RENA      ,Read FIFO enable bit. 0h (R/W) = Read FIFO is disabled. The RLVL bit in the Read FIFO status register ( 1h (R/W) = Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled prior to taking McASP out of reset." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "            RNUMEVT  ,Read word count per DMA event (32 bit). When the Read FIFO contains at least RNUMEVT words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number of serializers enabled as receivers. This value must be set prior to enabling the Read FIFO. 40h = 3 to 64 words from 3h to 40h. FFh = Reserved from 41h = FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 64 words from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
textline "                                 "
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA   ,Read word count per transfer (32 bit words). Upon a receive DMA event from the McASP, the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO. 10h = 3 to 16 words from 3h to 10h. FFh = Reserved from 11h to FFh. 0h (R/W) = 0 words 1h (R/W) = 1 word 2h (R/W) = 2 words 3h (R/W) = 3 to 16 words from 3h to 10h. 11h (R/W) = Reserved from 11h to FFh."
rgroup.long 0x100C++0x3
line.long 0x00 "MCASP_RFIFOSTS,"
hexmask.long.byte 0x00 0.--7. 1. " RLVL      ,Read level (read-only). Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh. 0h (R/W) = 0 words currently in Read FIFO. 1h (R/W) = 1 word currently in Read FIFO. 2h (R/W) = 2 words currently in Read FIFO. 3h (R/W) = 3 to 64 words currently in Read FIFO from 3h to 40h. 41h (R/W) = Reserved from 41h to FFh."
width 0x0B
tree.end
tree.end
tree "MCSPI"
tree "MCSPI0_CFG"
base ad:0x2100000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCSPI1_CFG"
base ad:0x2110000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCSPI2_CFG"
base ad:0x2120000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCSPI3_CFG"
base ad:0x2130000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCSPI4_CFG"
base ad:0x2140000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCU_MCSPI0_CFG"
base ad:0x40300000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCU_MCSPI1_CFG"
base ad:0x40310000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree "MCU_MCSPI2_CFG"
base ad:0x40320000
width 20.
rgroup.long 0x0++0x3
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP Revision"
rgroup.long 0x4++0x3
line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 7.--31. 1. " RSVD                 ,Reserved"
bitfld.long 0x00 6. "               RETMODE              ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1"
textline "                             "
bitfld.long 0x00 1.--5. " FFNBYTE              ,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "0,FF16bytes,FF32bytes,UNKN_MNEMO,FF64bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF128bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,FF256bytes,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO,UNKN_MNEMO"
bitfld.long 0x00 0. "             USEFIFO              ,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "NoFIFO,FIFOEn"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
hexmask.long 0x00 4.--31. 1. " RSVD                 ,Reads returns 0"
bitfld.long 0x00 2.--3. "               IDLEMODE             ,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only. 1h (R/W) = No-idle mode: local target never enters IDLE state. Backup mode, for debug only. 2h (R/W) = Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's clock stop requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state." "ForceIdle,NoIdle,SmartIdle,SmartIdleWakeUp"
textline "                             "
bitfld.long 0x00 1. " FREEEMU              ,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "EmuEn,EmuDis"
bitfld.long 0x00 0. "                 SOFTRESET            ,Software reset. (Optional) 0h (R/W) = Reset done, no pending action 1h (R/W) = Initiate software reset" "ResetDone_/_NoAction,SoftReset_/_ResetOnGoing"
rgroup.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,This register contains the revision number."
hexmask.long 0x00 0.--31. 1. " REVISION             ,IP revision"
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 8.--9. " CLOCKACTIVITY        ,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface clock may be switched off. 3h (R/W) = Interface and functional clocks are maintained." "None,OCP,FUNC,Both"
bitfld.long 0x00 3.--4. "                   SIDLEMODE            ,Power management 0h (R/W) = If an IDLE request is detected, the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the 1h (R/W) = If an IDLE request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally. 2h (R/W) = If an IDLE request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit 3h (R/W) = Reserved - do not use." "Force,No,Smart,Rsvd"
textline "                             "
bitfld.long 0x00 2. " ENAWAKEUP            ,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "NoWakeUp,On"
bitfld.long 0x00 1. "               SOFTRESET            ,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "Off,On"
textline "                             "
bitfld.long 0x00 0. " AUTOIDLE             ,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied, based on the configuration interface activity." "Off,On"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information."
bitfld.long 0x00 0. " RESETDONE            ,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "InProgress,Completed"
hgroup.long 0x118++0x3
hide.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
in
textline "                             "
group.long 0x11C++0x3
line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 17. " EOW_ENABLE           ,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 16. "            WKE                  ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 14. " RX3_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 13. "            TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 12. " TX3_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 10. "            RX2_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 8. "            TX2_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 6. " RX1_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 5. "            TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 4. " TX1_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 3. "            RX0_OVERFLOW_ENABLE  ,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 2. " RX0_FULL_ENABLE      ,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
bitfld.long 0x00 1. "            TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
textline "                             "
bitfld.long 0x00 0. " TX0_EMPTY_ENABLE     ,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "IrqDisabled,IrqEnabled"
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information, see , MCSPI Not Supported Features."
bitfld.long 0x00 0. " WKEN                 ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system, even if the global control bit 1h (R/W) = The event is allowed to wake-up the system if the global control bit" "NoWakeUp,WakeUp"
group.long 0x124++0x3
line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode."
bitfld.long 0x00 11. " SSB                  ,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "Off,SetThemAll"
bitfld.long 0x00 10. "             SPIENDIR             ,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "Out,In"
textline "                             "
bitfld.long 0x00 9. " SPIDATDIR1           ,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
bitfld.long 0x00 8. "                    SPIDATDIR0           ,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "Out,In"
textline "                             "
bitfld.long 0x00 7. " WAKD                 ,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "DrivenLow,DrivenHigh"
bitfld.long 0x00 6. "             SPICLK               ,SPICLK line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 5. " SPIDAT_1             ,SPIDAT[1] line (signal data value)" "0,1"
bitfld.long 0x00 4. "                      SPIDAT_0             ,SPIDAT[0] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 3. " SPIEN_3              ,SPIEN[3] line (signal data value)" "0,1"
bitfld.long 0x00 2. "                      SPIEN_2              ,SPIEN[2] line (signal data value)" "0,1"
textline "                             "
bitfld.long 0x00 1. " SPIEN_1              ,SPIEN[1] line (signal data value)" "0,1"
bitfld.long 0x00 0. "                      SPIEN_0              ,SPIEN[0] line (signal data value)" "0,1"
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface."
bitfld.long 0x00 8. " FDAA                 ,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "NoShadowReg,ShadowRegen"
bitfld.long 0x00 7. "            MOA                  ,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "NoMultiAccess,MultiAcces"
textline "                             "
bitfld.long 0x00 4.--6. " INITDLY              ,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) = The controller wait 32 MCSPI bus clock" "Nodelay,4ClkDly,8ClkDly,16ClkDly,32ClkDly,5,6,7"
bitfld.long 0x00 3. "               SYSTEM_TEST          ,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "Off,On"
textline "                             "
bitfld.long 0x00 2. " MS                   ,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "Master,Slave"
bitfld.long 0x00 1. "                 PIN34                ,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "4PinMode,3PinMode"
textline "                             "
bitfld.long 0x00 0. " SINGLE               ,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "Multi,Single"
group.long 0x12C++0x3
line.long 0x00 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x130++0x3
line.long 0x00 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x134++0x3
line.long 0x00 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x138++0x3
line.long 0x00 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x13C++0x3
line.long 0x00 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x140++0x3
line.long 0x00 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i."
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x144++0x3
line.long 0x00 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x148++0x3
line.long 0x00 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x14C++0x3
line.long 0x00 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x150++0x3
line.long 0x00 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x154++0x3
line.long 0x00 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x158++0x3
line.long 0x00 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x15C++0x3
line.long 0x00 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1"
group.long 0x160++0x3
line.long 0x00 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x164++0x3
line.long 0x00 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x168++0x3
line.long 0x00 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x00 29. " CLKG                 ,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x00 28. "                      FFER                 ,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1"
textline "                             "
bitfld.long 0x00 27. " FFEW                 ,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1"
bitfld.long 0x00 25.--26. "                      TCS0                 ,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
textline "                             "
bitfld.long 0x00 24. " SBPOL                ,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1"
bitfld.long 0x00 23. "                      SBE                  ,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
textline "                             "
bitfld.long 0x00 21.--22. " SPIENSLV             ,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only on SPIEN[3]" "0,1,2,3"
bitfld.long 0x00 20. "                      FORCE                ,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1"
textline "                             "
bitfld.long 0x00 19. " TURBO                ,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1"
bitfld.long 0x00 18. "                      IS                   ,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
textline "                             "
bitfld.long 0x00 17. " DPE1                 ,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x00 16. "                      DPE0                 ,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
textline "                             "
bitfld.long 0x00 15. " DMAR                 ,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x00 14. "                      DMAW                 ,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1"
textline "                             "
bitfld.long 0x00 12.--13. " TRM                  ,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
bitfld.long 0x00 7.--11. "                      WL                   ,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) = The MCSPI word is 8 bits long 8h (R/W) = The MCSPI word is 9 bits long 9h (R/W) = The MCSPI word is 10 bits long Ah (R/W) = The MCSPI word is 11 bits long Bh (R/W) = The MCSPI word is 12 bits long Ch (R/W) = The MCSPI word is 13 bits long Dh (R/W) = The MCSPI word is 14 bits long Eh (R/W) = The MCSPI word is 15 bits long Fh (R/W) = The MCSPI word is 16 bits long 10h (R/W) = The MCSPI word is 17 bits long 11h (R/W) = The MCSPI word is 18 bits long 12h (R/W) = The MCSPI word is 19 bits long 13h (R/W) = The MCSPI word is 20 bits long 14h (R/W) = The MCSPI word is 21 bits long 15h (R/W) = The MCSPI word is 22 bits long 16h (R/W) = The MCSPI word is 23 bits long 17h (R/W) = The MCSPI word is 24 bits long 18h (R/W) = The MCSPI word is 25 bits long 19h (R/W) = The MCSPI word is 26 bits long 1Ah (R/W) = The MCSPI word is 27 bits long 1Bh (R/W) = The MCSPI word is 28 bits long 1Ch (R/W) = The MCSPI word is 29 bits long 1Dh (R/W) = The MCSPI word is 30 bits long 1Eh (R/W) = The MCSPI word is 31 bits long 1Fh (R/W) = The MCSPI word is 32 bits long" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                             "
bitfld.long 0x00 6. " EPOL                 ,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1"
bitfld.long 0x00 2.--5. "                      CLKD                 ,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when 0h (R/W) = 1 1h (R/W) = 2 2h (R/W) = 4 3h (R/W) = 8 4h (R/W) = 16 5h (R/W) = 32 6h (R/W) = 64 7h (R/W) = 128 8h (R/W) = 256 9h (R/W) = 512 Ah (R/W) = 1024 Bh (R/W) = 2048 Ch (R/W) = 4096 Dh (R/W) = 8192 Eh (R/W) = 16384 Fh (R/W) = 32768" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                             "
bitfld.long 0x00 1. " POL                  ,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x00 0. "                      PHA                  ,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1"
rgroup.long 0x16C++0x3
line.long 0x00 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i."
bitfld.long 0x00 6. " RXFFF                ,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x00 5. "                      RXFFE                ,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 4. " TXFFF                ,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
bitfld.long 0x00 3. "                      TXFFE                ,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
textline "                             "
bitfld.long 0x00 2. " EOT                  ,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer). 1h (R) = This flag is automatically set to one at the end of an MCSPI transfer." "0,1"
bitfld.long 0x00 1. "                      TXS                  ,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1"
textline "                             "
bitfld.long 0x00 0. " RXS                  ,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1"
group.long 0x170++0x3
line.long 0x00 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i."
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK               ,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080."
bitfld.long 0x00 0. "                     EN                   ,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1"
group.long 0x174++0x3
line.long 0x00 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " TDATA                ,Channel i data to transmit"
rgroup.long 0x178++0x3
line.long 0x00 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link, whatever MCSPI word length is."
hexmask.long 0x00 0.--31. 1. " RDATA                ,Channel i received data"
group.long 0x17C++0x3
line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer."
hexmask.long.word 0x00 16.--31. 1. " WCNT                 ,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word"
hexmask.long.byte 0x00 8.--15. 1. "                   AFL                  ,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
textline "                             "
hexmask.long.byte 0x00 0.--7. 1. " AEL                  ,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFTDATA             ,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when"
rgroup.long 0x1A0++0x3
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled."
hexmask.long 0x00 0.--31. 1. " DAFRDATA             ,FIFO data received with DMA 256 bit aligned address. This field is only used when"
width 0x0B
tree.end
tree.end
tree "MCU_ARMSS_CCMR5"
base ad:0x400F0000
width 13.
group.long 0x0++0x3
line.long 0x00 "CCMSR1,Shows the Error and Self test Status of the CPU CPU Compare block."
bitfld.long 0x00 16. " CMPE1   ,This is the CMPE1 field" "0,1"
bitfld.long 0x00 8. "   STC1 ,This is the STC1 field" "0,1"
textline "                      "
bitfld.long 0x00 1. " STET1   ,This is the STET1 field" "0,1"
bitfld.long 0x00 0. "   STE1 ,This is the STE1 field" "0,1"
group.long 0x4++0x3
line.long 0x00 "CCMKEYR1,Selects Operating mode of CPU Compare block."
bitfld.long 0x00 0.--3. " MKEY1   ,This is the MKEY1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x3
line.long 0x00 "CCMSR3,Shows the Error and Self test Status of the CPU CPU Compare block."
bitfld.long 0x00 16. " CMPE3   ,This is the CMPE3 field" "0,1"
bitfld.long 0x00 8. "   STC3 ,This is the STC3 field" "0,1"
textline "                      "
bitfld.long 0x00 1. " STET3   ,This is the STET3 field" "0,1"
bitfld.long 0x00 0. "   STE3 ,This is the STE3 field" "0,1"
group.long 0x14++0x3
line.long 0x00 "CCMKEYR3,Selects Operating mode of CPU Compare block."
bitfld.long 0x00 0.--3. " MKEY3   ,This is the MKEY3 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "CCMPOLCNTRL,Selects Operating mode of CPU Compare block."
hexmask.long.byte 0x00 0.--7. 1. " POL_INV ,This is the Polarity Inversion field"
width 0x0B
tree.end
tree "MCU_PDMA0"
base ad:0x40710000
width 35.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_PDMA0_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                      ,bu" "0,1,2,3"
textline "                                            "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID               ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                  ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                            "
bitfld.long 0x00 8.--10. " REVMAJ                  ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                  ,Custom version" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 0.--5. " REVMIN                  ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MCU_PDMA0_ECC_VECTOR,ECC Vector Register"
in
textline "                                            "
rgroup.long 0xC++0x3
line.long 0x00 "MCU_PDMA0_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "MCU_PDMA0_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCU_PDMA0_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCU_PDMA0_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MCU_PDMA0_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                            "
group.long 0x13C++0x3
line.long 0x00 "MCU_PDMA0_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "MCU_PDMA0_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MCU_PDMA0_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MCU_PDMA0_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                            "
group.long 0x200++0x3
line.long 0x00 "MCU_PDMA0_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                 ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                  ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MCU_PDMA0_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                            "
group.long 0x208++0x3
line.long 0x00 "MCU_PDMA0_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MCU_PDMA0_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MCU_PDMA1"
base ad:0x40711000
width 35.
rgroup.long 0x0++0x3
line.long 0x00 "MCU_PDMA1_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                      ,bu" "0,1,2,3"
textline "                                            "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID               ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                  ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                            "
bitfld.long 0x00 8.--10. " REVMAJ                  ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                  ,Custom version" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 0.--5. " REVMIN                  ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MCU_PDMA1_ECC_VECTOR,ECC Vector Register"
in
textline "                                            "
rgroup.long 0xC++0x3
line.long 0x00 "MCU_PDMA1_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "MCU_PDMA1_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "MCU_PDMA1_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
textline "                                            "
bitfld.long 0x00 1. " TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MCU_PDMA1_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
textline "                                            "
bitfld.long 0x00 1. " TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MCU_PDMA1_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                            "
group.long 0x13C++0x3
line.long 0x00 "MCU_PDMA1_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "MCU_PDMA1_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
textline "                                            "
bitfld.long 0x00 1. " TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MCU_PDMA1_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
textline "                                            "
bitfld.long 0x00 1. " TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MCU_PDMA1_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                            "
group.long 0x200++0x3
line.long 0x00 "MCU_PDMA1_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                 ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                  ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MCU_PDMA1_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                            "
group.long 0x208++0x3
line.long 0x00 "MCU_PDMA1_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MCU_PDMA1_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MMCSD"
tree "MMCSD0_SS_CFG"
base ad:0x4F90000
width 26.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD0_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem."
hexmask.long.word 0x00 16.--31. 1. " MOD_ID           ,Module ID"
bitfld.long 0x00 11.--15. "      RTL_VER           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                   "
bitfld.long 0x00 8.--10. " MAJ_REV          ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom Version" "0,1,2,3"
textline "                                   "
bitfld.long 0x00 0.--5. " MIN_REV          ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification."
bitfld.long 0x00 24.--29. " TUNINGCOUNT      ,This field controls the corecfg_tuningcount port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "        ASYNCWKUPENA      ,This field controls the corecfg_asyncwkupena port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 12.--15. " CQFMUL           ,This field controls the corecfg_cqfmul port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "        CQFVAL            ,This field controls the corecfg_cqfval port on the controller."
group.long 0x14++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the LSB fields in the register inside the Host Controller."
bitfld.long 0x00 30.--31. " SLOTTYPE         ,This field controls the corecfg_slottype port on the controller." "0,1,2,3"
bitfld.long 0x00 29. "         ASYNCHINTRSUPPORT ,This field controls the corecfg_asynchintrsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 26. " SUPPORT1P8VOLT   ,This field controls the corecfg_1p8voltsupport port on the controller." "0,1"
bitfld.long 0x00 25. "         SUPPORT3P0VOLT    ,This field controls the corecfg_3p0voltsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 24. " SUPPORT3P3VOLT   ,This field controls the corecfg_3p3voltsupport port on the controller." "0,1"
bitfld.long 0x00 23. "         SUSPRESSUPPORT    ,This field controls the corecfg_suspressupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 22. " SDMASUPPORT      ,This field controls the corecfg_sdmasupport port on the controller." "0,1"
bitfld.long 0x00 21. "         HIGHSPEEDSUPPORT  ,This field controls the corecfg_highspeedsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 19. " ADMA2SUPPORT     ,This field controls the corecfg_adma2support port on the controller." "0,1"
bitfld.long 0x00 18. "         SUPPORT8BIT       ,This field controls the corecfg_8bitsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 16.--17. " MAXBLKLENGTH     ,This field controls the corecfg_maxblklength port on the controller." "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "         BASECLKFREQ       ,This field controls the corecfg_baseclkfreq port on the controller."
textline "                                   "
bitfld.long 0x00 7. " TIMEOUTCLKUNIT   ,This field controls the corecfg_timeoutclkunit port on the controller." "0,1"
bitfld.long 0x00 0.--5. "         TIMEOUTCLKFREQ    ,This field controls the corecfg_timeoutclkfreq port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the MSB fields in the register inside the Host Controller."
bitfld.long 0x00 31. " HS400SUPPORT     ,This field controls the corecfg_hs400support port on the controller." "0,1"
bitfld.long 0x00 28. "         SUPPORT1P8VDD2    ,This field controls the corecfg_1p8vdd2support port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 27. " ADMA3SUPPORT     ,This field controls the corecfg_adma3support port on the controller." "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         CLOCKMULTIPLIER   ,This field controls the corecfg_clockmultiplier port on the controller."
textline "                                   "
bitfld.long 0x00 14.--15. " RETUNINGMODES    ,This field controls the corecfg_retuningmodes port on the controller." "0,1,2,3"
bitfld.long 0x00 13. "         TUNINGFORSDR50    ,This field controls the corecfg_tuningforsdr50 port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 8.--11. " RETUNINGTIMERCNT ,This field controls the corecfg_retuningtimercnt port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        TYPE4SUPPORT      ,This field controls the corecfg_type4support port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 6. " DDRIVERSUPPORT   ,This field controls the corecfg_ddriversupport port on the controller." "0,1"
bitfld.long 0x00 5. "         CDRIVERSUPPORT    ,This field controls the corecfg_cdriversupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 4. " ADRIVERSUPPORT   ,This field controls the corecfg_adriversupport port on the controller." "0,1"
bitfld.long 0x00 2. "         DDR50SUPPORT      ,This field controls the corecfg_ddr50support port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 1. " SDR104SUPPORT    ,This field controls the corecfg_sdr104support port on the controller." "0,1"
bitfld.long 0x00 0. "         SDR50SUPPORT      ,This field controls the corecfg_sdr50support port on the controller." "0,1"
group.long 0x1C++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the LSB fields in the register inside the Host Controller."
hexmask.long.byte 0x00 16.--23. 1. " MAXCURRENT1P8V   ,This field controls the corecfg_maxcurrent1p8v port on the controller."
hexmask.long.byte 0x00 8.--15. 1. "        MAXCURRENT3P0V    ,This field controls the corecfg_maxcurrent3p0v port on the controller."
textline "                                   "
hexmask.long.byte 0x00 0.--7. 1. " MAXCURRENT3P3V   ,This field controls the corecfg_maxcurrent3p3v port on the controller."
group.long 0x20++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the MSB fields in the register inside the Host Controller."
hexmask.long.byte 0x00 0.--7. 1. " MAXCURRENTVDD2   ,This field controls the corecfg_maxcurrentvdd2 port on the controller."
group.long 0x24++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for Initialization inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " INITPRESETVAL    ,This field controls the corecfg_initpresetval port on the controller."
group.long 0x28++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for Default Speed inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " DSPDPRESETVAL    ,This field controls the corecfg_dspdpresetval port on the controller."
group.long 0x2C++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for High Speed inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " HSPDPRESETVAL    ,This field controls the corecfg_hspdpresetval port on the controller."
group.long 0x30++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR12 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR12PRESETVAL   ,This field controls the corecfg_sdr12presetval port on the controller."
group.long 0x34++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR25 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR25PRESETVAL   ,This field controls the corecfg_sdr25presetval port on the controller."
group.long 0x38++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR50 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR50PRESETVAL   ,This field controls the corecfg_sdr50presetval port on the controller."
group.long 0x3C++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR104 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR104PRESETVAL  ,This field controls the corecfg_sdr104presetval port on the controller."
group.long 0x40++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for DDR50 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " DDR50PRESETVAL   ,This field controls the corecfg_ddr50presetval port on the controller."
group.long 0x44++0x3
line.long 0x00 "MMCSD0_SS_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for HS400 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " HS400PRESETVAL   ,This field controls the corecfg_hs400presetval port on the controller."
rgroup.long 0x60++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
bitfld.long 0x00 31. " SDHC_CMDIDLE     ,This field reflects the value of the sdhc_cmdidle port on the controller." "0,1"
hexmask.long.word 0x00 0.--15. 1. "         DMADEBUGBUS       ,This field reflects the value of the sdhc_dmadebugbus port on the controller."
rgroup.long 0x64++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " CMDDEBUGBUS      ,This field reflects the value of the sdhc_cmddebugbus port on the controller."
rgroup.long 0x68++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " TXDDEBUGBUS      ,This field reflects the value of the sdhc_txddebugbus port on the controller."
rgroup.long 0x6C++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " RXDDEBUGBUS0     ,This field reflects the value of the sdhc_rxddebugbus0 port on the controller."
rgroup.long 0x70++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " RXDDEBUGBUS1     ,This field reflects the value of the sdhc_rxddebugbus1 port on the controller."
rgroup.long 0x74++0x3
line.long 0x00 "MMCSD0_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " TUNDEBUGBUS      ,This field reflects the value of the sdhc_tundebugbus port on the controller."
group.long 0x100++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 31. " IOMUX_ENABLE     ,This field controls the phyctrl_enable_iomuxing port on the PHY." "0,1"
bitfld.long 0x00 20.--22. "         DR_TY             ,This field controls the phyctrl_dr_ty port on the PHY." "0,1,2,3,4,5,6,7"
textline "                                   "
bitfld.long 0x00 17. " RETRIM           ,This field controls the phyctrl_retrim port on the PHY." "0,1"
bitfld.long 0x00 16. "         EN_RTRIM          ,This field controls the phyctrl_en_rtrim port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 4.--7. " DLL_TRM_ICP      ,This field controls the phyctrl_dll_trm_icp port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "        ENDLL             ,This field controls the phyctrl_endll port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0. " PDB              ,This field controls the phyctrl_pdb port on the PHY." "0,1"
group.long 0x104++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 29. " OD_RELEASE_STRB  ,This field controls the phyctrl_OD_release_strb port on the PHY." "0,1"
bitfld.long 0x00 28. "         OD_RELEASE_CMD    ,This field controls the phyctrl_OD_release_cmd port on the PHY." "0,1"
textline "                                   "
hexmask.long.byte 0x00 16.--23. 1. " OD_RELEASE_DAT   ,This field controls the phyctrl_OD_release_dat port on the PHY."
bitfld.long 0x00 13. "        ODEN_STRB         ,This field controls the phyctrl_oden_strb port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 12. " ODEN_CMD         ,This field controls the phyctrl_oden_cmd port on the PHY." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         ODEN_DAT          ,This field controls the phyctrl_oden_dat port on the PHY."
group.long 0x108++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 29. " PU_STRB          ,This field controls the phyctrl_pu_strb port on the PHY." "0,1"
bitfld.long 0x00 28. "         PU_CMD            ,This field controls the phyctrl_pu_cmd port on the PHY." "0,1"
textline "                                   "
hexmask.long.byte 0x00 16.--23. 1. " PU_DAT           ,This field controls the phyctrl_pu_dat port on the PHY."
bitfld.long 0x00 13. "        REN_STRB          ,This field controls the phyctrl_ren_strb port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 12. " REN_CMD          ,This field controls the phyctrl_ren_cmd port on the PHY." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         REN_DAT           ,This field controls the phyctrl_ren_dat port on the PHY."
group.long 0x10C++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 24.--27. " STRBSEL          ,This field controls the phyctrl_strbsel port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20. "        OTAPDLYENA        ,This field controls the phyctrl_otapdlyena port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 12.--15. " OTAPDLYSEL       ,This field controls the phyctrl_otapdlysel port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "        ITAPCHGWIN        ,This field controls the phyctrl_itapchgwin port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 8. " ITAPDLYENA       ,This field controls the phyctrl_itapdlyena port on the PHY." "0,1"
bitfld.long 0x00 0.--4. "         ITAPDLYSEL        ,This field controls the phyctrl_itapdlysel port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x110++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 17. " SELDLYTXCLK      ,This field controls the phyctrl_seldlytxclk port on the PHY." "0,1"
bitfld.long 0x00 16. "         SELDLYRXCLK       ,This field controls the phyctrl_seldlyrxclk port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 9. " SEL100           ,This field controls the phyctrl_sel100 port on the PHY." "0,1"
bitfld.long 0x00 8. "         SEL50             ,This field controls the phyctrl_sel50 port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0.--2. " CLKBUFSEL        ,This field controls the phyctrl_clkbufsel port on the PHY." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "MMCSD0_SS_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 31. " BISTENABLE       ,This field controls the phyctrl_bistenable port on the PHY." "0,1"
bitfld.long 0x00 30. "         BISTSTART         ,This field controls the phyctrl_biststart port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 24.--27. " BISTMODE         ,This field controls the phyctrl_bistmode port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "        TESTCTRL          ,This field controls the phyctrl_testctrl port on the PHY."
rgroup.long 0x130++0x3
line.long 0x00 "MMCSD0_SS_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Host Controller PHY ports. For detailed functionality of the Host Controller PHY status ports please refer to its specification."
bitfld.long 0x00 4.--7. " RTRIM            ,This field reflects the value of the phyctrl_rtrim port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        BISTDONE          ,This field reflects the value of the phyctrl_bistdone port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 2. " EXR_NINST        ,This field reflects the value of the phyctrl_exr_ninst port on the PHY." "0,1"
bitfld.long 0x00 1. "         CALDONE           ,This field reflects the value of the phyctrl_caldone port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0. " DLLRDY           ,This field reflects the value of the phyctrl_dllrdy port on the PHY." "0,1"
rgroup.long 0x134++0x3
line.long 0x00 "MMCSD0_SS_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Host Controller PHY ports. For detailed functionality of the Host Controller PHY status ports please refer to its specification."
hexmask.long 0x00 0.--31. 1. " BISTSTATUS       ,This field reflects the value of the phyctrl_biststatus port on the PHY."
width 0x0B
tree.end
tree "MMCSD0_ECC_AGGR_RXMEM"
base ad:0x2A24000
width 34.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD0_RXECC_REV,Aggregator Revision Register Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,Business Unit" "0,1,2,3"
textline "                                           "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                           "
bitfld.long 0x00 8.--10. " REVMAJ           ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom Version" "0,1,2,3"
textline "                                           "
bitfld.long 0x00 0.--5. " REVMIN           ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MMCSD0_RXECC_VECTOR,ECC Vector Register"
in
textline "                                           "
rgroup.long 0xC++0x3
line.long 0x00 "MMCSD0_RXECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS         ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "MMCSD0_RXECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,SEC EOI" "0,1"
group.long 0x40++0x3
line.long 0x00 "MMCSD0_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 0. " RXMEM_PEND       ,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MMCSD0_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " RXMEM_ENABLE_SET ,Interrupt Enable Set for rxmem_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MMCSD0_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x13C++0x3
line.long 0x00 "MMCSD0_RXECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,DED EOI" "0,1"
group.long 0x140++0x3
line.long 0x00 "MMCSD0_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 0. " RXMEM_PEND       ,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MMCSD0_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " RXMEM_ENABLE_SET ,Interrupt Enable Set for rxmem_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MMCSD0_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x200++0x3
line.long 0x00 "MMCSD0_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT          ,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MMCSD0_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                           "
group.long 0x208++0x3
line.long 0x00 "MMCSD0_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MMCSD0_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MMCSD1_ECC_AGGR_RXMEM"
base ad:0x2A26000
width 34.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD1_RXECC_REV,Aggregator Revision Register Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,Business Unit" "0,1,2,3"
textline "                                           "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                           "
bitfld.long 0x00 8.--10. " REVMAJ           ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom Version" "0,1,2,3"
textline "                                           "
bitfld.long 0x00 0.--5. " REVMIN           ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MMCSD1_RXECC_VECTOR,ECC Vector Register"
in
textline "                                           "
rgroup.long 0xC++0x3
line.long 0x00 "MMCSD1_RXECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS         ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "MMCSD1_RXECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,SEC EOI" "0,1"
group.long 0x40++0x3
line.long 0x00 "MMCSD1_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 0. " RXMEM_PEND       ,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MMCSD1_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " RXMEM_ENABLE_SET ,Interrupt Enable Set for rxmem_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MMCSD1_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x13C++0x3
line.long 0x00 "MMCSD1_RXECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,DED EOI" "0,1"
group.long 0x140++0x3
line.long 0x00 "MMCSD1_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 0. " RXMEM_PEND       ,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MMCSD1_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " RXMEM_ENABLE_SET ,Interrupt Enable Set for rxmem_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MMCSD1_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x200++0x3
line.long 0x00 "MMCSD1_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT          ,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MMCSD1_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                           "
group.long 0x208++0x3
line.long 0x00 "MMCSD1_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MMCSD1_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MMCSD1_ECC_AGGR_TXMEM"
base ad:0x2A27000
width 34.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD1_TXECC_REV,Aggregator Revision Register Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,Business Unit" "0,1,2,3"
textline "                                           "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                           "
bitfld.long 0x00 8.--10. " REVMAJ           ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom Version" "0,1,2,3"
textline "                                           "
bitfld.long 0x00 0.--5. " REVMIN           ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MMCSD1_TXECC_VECTOR,ECC Vector Register"
in
textline "                                           "
rgroup.long 0xC++0x3
line.long 0x00 "MMCSD1_TXECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS         ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "MMCSD1_TXECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,SEC EOI" "0,1"
group.long 0x40++0x3
line.long 0x00 "MMCSD1_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 0. " TXMEM_PEND       ,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MMCSD1_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " TXMEM_ENABLE_SET ,Interrupt Enable Set for txmem_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MMCSD1_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x13C++0x3
line.long 0x00 "MMCSD1_TXECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,DED EOI" "0,1"
group.long 0x140++0x3
line.long 0x00 "MMCSD1_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 0. " TXMEM_PEND       ,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MMCSD1_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " TXMEM_ENABLE_SET ,Interrupt Enable Set for txmem_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MMCSD1_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x200++0x3
line.long 0x00 "MMCSD1_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT          ,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MMCSD1_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                           "
group.long 0x208++0x3
line.long 0x00 "MMCSD1_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MMCSD1_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MMCSD1_CTL_CFG"
base ad:0x4FA0000
width 32.
group.word 0x0++0x1
line.word 0x00 "MMCSD1_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x00 0.--15. 1. "             SDMA_ADDRESS             ,32-bit Block Count (SDMA System Address) Low When the When the (1) SDMA System Address ( This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (after a transaction has stopped). Reading this register during SDMA transfers may return an invalid value. The Host Driver (HD) shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the (2) 32-bit Block Count ( Host Controller Version 4.10 re-defines this register as 32-bit Block Count. In version 4.00, this register may be used as 32-bit block count only for Auto CMD23 to set the argument of the CMD23 while executing Auto CMD23. The Host Controller would decrement the block count of this register every block transfer and data transfer stops when the count reaches zero."
group.word 0x2++0x1
line.word 0x00 "MMCSD1_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x00 0.--15. 1. "             SDMA_ADDRESS             ,32-bit Block Count (SDMA System Address) High This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
group.word 0x4++0x1
line.word 0x00 "MMCSD1_BLOCK_SIZE,This register is used to configure the number of bytes in a data block."
bitfld.word 0x00 12.--14. "             SDMA_BUF_SIZE            ,Host SDMA Buffer Size To perform long DMA transfer, System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry out) 4h: 64KB (Detects A15 Carry out) 5h: 128KB (Detects A16 Carry out) 6h: 256KB (Detects A17 Carry out) 7h: 512KB (Detects A18 Carry out)" "0,1,2,3,4,5,6,7"
hexmask.word 0x00 0.--11. 1. "                 XFER_BLK_SIZE            ,Transfer Block Size This field specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. 0000h: No Data Transfer 0001h: 1 Byte 0002h: 2 Bytes 0003h: 3 Bytes 0004h: 4 Bytes .... 01FFh: 511 Bytes 0200h: 512 Bytes .... 0800h: 2048 Bytes"
group.word 0x6++0x1
line.word 0x00 "MMCSD1_BLOCK_COUNT,This register is used to configure the number of data blocks."
hexmask.word 0x00 0.--15. 1. "             XFER_BLK_CNT             ,16-bit Block Count Host Controller Version 4.10 extends block count to 32-bit. Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: (1) If the (2) If the Use of 16-bit/32-bit Block Count register is enabled when the The Host Driver shall set this register to a value between 1h and the maximum block count. The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred. This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored. 0000h: Stop Count 0001h: 1 Block 0002h: 2 Blocks .... FFFFh: 65535 Blocks"
group.word 0x8++0x1
line.word 0x00 "MMCSD1_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument."
hexmask.word 0x00 0.--15. 1. "             CMD_ARG1                 ,Command Argument 1 Low The SD Command Argument is specified as bit 23-8 of Command-Format."
group.word 0xA++0x1
line.word 0x00 "MMCSD1_ARGUMENT1_HI,This register contains higher bits of SD Command Argument."
hexmask.word 0x00 0.--15. 1. "             CMD_ARG1                 ,Command Argument 1 High The SD Command Argument is specified as bit 39-24 of Command-Format."
group.word 0xC++0x1
line.word 0x00 "MMCSD1_TRANSFER_MODE,"
bitfld.word 0x00 8. "             RESP_INTR_DIS            ,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits Command Complete Interrupt ( If Host Controller checks response error, sets this bit to 1h and sets the 0h: Response Interrupt is enabled 1h: Response Interrupt is disabled" "0,1"
bitfld.word 0x00 7. "                 RESP_ERR_CHK_ENA         ,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, this bit is set to 0h and the If Host Controller checks response error, sets this bit to 1h and sets the Response Interrupt Disable bit to 1h ( The 0h: Response Error Check is disabled 1h: Response Error Check is enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " RESP_TYPE                ,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1"
bitfld.word 0x00 5. "                 MULTI_BLK_SEL            ,Multi/Single Block Select This bit enables multiple block data transfers. 0h: Single Block 1h: Multiple Block" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_XFER_DIR            ,Data Transfer Direction Select This bit defines the direction of data transfers. 0h: Write (Host to Card) 1h: Read (Card to Host)" "0,1"
bitfld.word 0x00 2.--3. "                 AUTO_CMD_ENA             ,Auto CMD Enable This field determines use of auto command functions. There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation), this field is set to 0h. (1) Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 1h, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the When When (2) Auto CMD23 Enable: When this bit field is set to 2h, the Host Controller issues a CMD23 automatically before issuing a command specified in the The following conditions are required to use the Auto CMD23: Auto CMD23 Supported (Host Controller Version is 3.00 or later). A memory card that supports CMD23 (SCR[33] = 1h). If DMA is used, it shall be ADMA. Only when CMD18 or CMD25 is issued. Auto CMD23 can be used with or without ADMA. By writing the 32-bit block count value for CMD23 is set to 32-bit Block Count ( (3) Auto CMD Auto Select (Version 4.10): As CMD23 is optional for SD memory card except UHS 104 card, if card supports CMD23, Auto CMD 23 should be used instead of Auto CMD12. Host Controller Version 4.10 defines this 'Auto CMD Auto Select' mode. Selection of Auto CMD depends on setting of the 0h: Auto Command Disabled 1h: Auto CMD12 Enable 2h: Auto CMD23 Enable 3h: Reserved" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 1. " BLK_CNT_ENA              ,Block Count Enable This bit is used to enable the 0h: Disable 1h: Enable" "0,1"
bitfld.word 0x00 0. "                 DMA_ENA                  ,DMA Enable DMA can be enabled only if the 0h: Disable 1h: Enable" "0,1"
group.word 0xE++0x1
line.word 0x00 "MMCSD1_COMMAND,This register is used to program the Command for host controller."
bitfld.word 0x00 8.--13. "             CMD_INDEX                ,Command Index This bit shall be set to the command number (CMD0-63, ACMD0-63)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 6.--7. "                CMD_TYPE                 ,Command Type There are three types of special commands. Suspend, Resume and Abort. These bits shall be set to 0h for all other commands. Suspend Command: Resume Command: Abort Command: 0h: Normal 1h: Suspend 2h: Resume 3h: Abort" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " DATA_PRESENT             ,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following: 0h: No Data Present 1h: Data Present" "0,1"
bitfld.word 0x00 4. "                 CMD_INDEX_CHK_ENA        ,Command Index Check Enable If this bit is set to 1h, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0h, the Index field is not checked. 0h: Disable 1h: Enable" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " CMD_CRC_CHK_ENA          ,Command CRC Check Enable If this bit is set to 1h, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0h, the CRC field is not checked. 0h: Disable 1h: Enable" "0,1"
bitfld.word 0x00 2. "                 SUB_CMD                  ,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the Host Driver manages whether main or sub command. Host Controller does not refer to this bit to issue a command. 0h: Sub Command 1h: Main Command" "0,1"
textline "                                                 "
bitfld.word 0x00 0.--1. " RESP_TYPE_SEL            ,Response Type Select 0h: No Response 1h: Response length 136 2h: Response length 48 3h: Response length 48 check Busy after response" "0,1,2,3"
group.long 0x20++0x3
line.long 0x00 "MMCSD1_DATA_PORT,This register is used to access internal buffer."
hexmask.long 0x00 0.--31. 1. "         BUF_RD_DATA              ,Buffer Data The Host Controller Buffer can be accessed through this 32-bit Data Port Register."
rgroup.long 0x24++0x3
line.long 0x00 "MMCSD1_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register."
bitfld.long 0x00 31. "         UHS2_IF_DETECTION        ,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( After UHS-II IF is detected, this bit is cleared by when EIDL is detected on D0 lane, UHS-II Interface Enable is set to 0h ( 1h: UHS-II IF is detected 0h: UHS-II IF is not detected" "0,1"
bitfld.long 0x00 30. "                 UHS2_IF_LANE_SYNC        ,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( In case of Version 4.00, this bit indicates completion of Device PHY Initialization by detecting LIDL LSS on D1 lane. From Version 4.10, Host Controller may implement a specific PHY verification method and PHY Initialization Failure can be indicated by keeping this bit to 0h even LIDL LSS is detected on D1 lane. Host Driver detects PHY Initialization Failure by timeout. This bit is cleared by when D0 lane is set to EIDL, UHS-II Interface Enable is set to 0h ( 1h: UHS-II PHY is initialized 0h: UHS-II PHY is not initialized" "0,1"
textline "                                                 "
bitfld.long 0x00 29. " UHS2_DORMANT             ,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( RCLK may be stopped in dormant state, by setting SD Clock Enable to 0h in the Clock Control register ( In case of the card enters Hibernate Mode (RCLK is stopped), Host Driver may turn off VDD1 by clearing SD Bus Power for VDD1 bit in the 1h: In DORMANT state 0h: Not in DORMANT state" "0,1"
bitfld.long 0x00 28. "                 SUB_COMMAND_STS          ,Sub Command Status The 1h: Sub Command Status 0h: Main Command Status" "0,1"
textline "                                                 "
bitfld.long 0x00 27. " CMD_NOT_ISS_BY_ERR       ,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the 1h: Command cannot be issued 0h: No error for issuing a command" "0,1"
bitfld.long 0x00 24. "                 SDIF_CMDIN               ,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors, and for debugging." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " SDIF_DAT3IN              ,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[3]. D23 - DAT[3]" "0,1"
bitfld.long 0x00 22. "                 SDIF_DAT2IN              ,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[2]. D22 - DAT[2]" "0,1"
textline "                                                 "
bitfld.long 0x00 21. " SDIF_DAT1IN              ,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[1]. D21 - DAT[1]" "0,1"
bitfld.long 0x00 20. "                 SDIF_DAT0IN              ,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D20 - DAT[0]" "0,1"
textline "                                                 "
bitfld.long 0x00 19. " WRITE_PROTECT            ,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin. 0h: Write protected (SDWP# = 1) 1h: Write enabled (SDWP# = 0)" "0,1"
bitfld.long 0x00 18. "                 CARD_DETECT              ,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin. 0h: No Card present (SDCD# = 1) 1h: Card present (SDCD# = 0)" "0,1"
textline "                                                 "
bitfld.long 0x00 17. " CARD_STATE_STABLE        ,Card State Stable This bit is used for testing. If it is 0h, the Card Detect Pin Level is not stable. If this bit is set to 1h, it means the Card Detect Pin Level is stable. The 0h: Reset of Debouncing 1h: No Card or Inserted" "0,1"
bitfld.long 0x00 16. "                 CARD_INSERTED            ,Card Inserted This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the If a Card is removed while its power is on and its clock is oscillating, the HC shall clear the 0h: Reset or Debouncing or No Card 1h: Card Inserted" "0,1"
textline "                                                 "
bitfld.long 0x00 11. " BUF_RD_ENA               ,Buffer Read Enable This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h, readable data exists in the buffer. A change of this bit from 1h to 0h occurs when all the block data is read from the buffer. A change of this bit from 0h to 1h occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0h: Read Disable 1h: Read Enable" "0,1"
bitfld.long 0x00 10. "                 BUF_WR_ENA               ,Buffer Write Enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h, data can be written to the buffer. A change of this bit from 1h to 0h occurs when all the block data is written to the buffer. A change of this bit from 0h to 1h occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt. 0h: Write Disable 1h: Write Enable" "0,1"
textline "                                                 "
bitfld.long 0x00 9. " RD_XFER_ACTIVE           ,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer. This bit is set to 1h for either of the following conditions: This bit is cleared to 0h for either of the following conditions: 1h: Transferring data 0h: No valid data" "0,1"
bitfld.long 0x00 8. "                 WR_XFER_ACTIVE           ,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active. If this bit is 0h, it means no valid write data exists in the HC. This bit is set in either of the following cases: This bit is cleared in either of the following cases: 1h: Transferring data 0h: No valid data" "0,1"
textline "                                                 "
bitfld.long 0x00 7. " SDIF_DAT7IN              ,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D07 - DAT[7]" "0,1"
bitfld.long 0x00 6. "                 SDIF_DAT6IN              ,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D06 - DAT[6]" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " SDIF_DAT5IN              ,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D05 - DAT[5]" "0,1"
bitfld.long 0x00 4. "                 SDIF_DAT4IN              ,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D04 - DAT[4]" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " RETUNING_REQ             ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting the Changing of this bit from 0h to 1h generates Re-Tuning Event. This bit isn't set to 1h if the 1h: Sampling clock needs re-tuning 0h: Fixed or well tuned sampling clock" "0,1"
bitfld.long 0x00 2. "                 DATA_LINE_ACTIVE         ,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use. 1h: DAT line active 0h: DAT line inactive" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " INHIBIT_DAT              ,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (for example R1b, R5b type). Changing from 1h to 0h generates a Transfer Complete interrupt in the 1h: Cannot issue command which uses the DAT line 0h: Can issue command which uses the DAT line" "0,1"
bitfld.long 0x00 0. "                 INHIBIT_CMD              ,Command Inhibit (CMD) 1h: Host Controller is not ready to issue a command 0h: Host Controller is ready to issue a command Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status keeps indicating 1h while any of response error statuses is set to 1h, Command Not Issued by Error in this register is set to 1h or the" "0,1"
group.byte 0x28++0x0
line.byte 0x00 "MMCSD1_HOST_CONTROL1,This register is used to program DMA modes, LED control, data transfer width, High Speed enable, card detect test level and signal selection."
bitfld.byte 0x00 7. "               CD_SIG_SEL               ,Card Detect Signal Detection This bit selects source for card detection. 1h: The card detect test level is selected 0h: SDCD# is selected (for normal use)" "0,1"
bitfld.byte 0x00 6. "                 CD_TEST_LEVEL            ,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set. 1h: Card Inserted 0h: No Card" "0,1"
textline "                                                 "
bitfld.byte 0x00 5. " EXT_DATA_WIDTH           ,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 2h in the 1h: 8-bit Bus Width 0h: Bus Width is Selected by Data Transfer Width" "0,1"
bitfld.byte 0x00 3.--4. "                 DMA_SELECT               ,DMA Select This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the (1) Up to Version 3.00: (2) Version 4.00 or later: Support of 64-bit DMA and 128-bit Descriptor is indicated by the" "0,1,2,3"
textline "                                                 "
bitfld.byte 0x00 2. " HIGH_SPEED_ENA           ,High Speed Enable (SD Mode Only) This bit is optional. Before setting this bit, the HD shall check the If the 1h: High Speed Mode 0h: Normal Speed Mode" "0,1"
bitfld.byte 0x00 1. "                 DATA_WIDTH               ,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode. 1h: 4 bit mode 0h: 1 bit mode" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " LED_CONTROL              ,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction. 1h: LED on 0h: LED off" "0,1"
group.byte 0x29++0x0
line.byte 0x00 "MMCSD1_POWER_CONTROL,This register is used to program the SD Bus power and voltage level."
bitfld.byte 0x00 5.--7. "               UHS2_VOLTAGE             ,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2. This field can be set to 5h if the 111b: Not used 110b: Not used 101b: 1.8 V 100b: Reserved for 1.2 V 011b ? 001b: Reserved 000b: VDD2 Not Supported" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "                 UHS2_POWER               ,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2. 1h: Power on 0h: Power off" "0,1"
textline "                                                 "
bitfld.byte 0x00 1.--3. " SD_BUS_VOLTAGE           ,SD Bus Voltage Select for VDD1 By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the 111b: 3.3 V (Flattop.) 110b: 3.0 V (Typ.) 101b: 1.8 V (Typ.) for Embedded 100b ? 000b: Reserved" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0. "                 SD_BUS_POWER             ,SD Bus Power for VDD1 Before setting this bit, the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared, the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state), and drive SDCLK to low level. If card is connected to Host Controller, Host Controller shall set these lines to low before stopping to supply VDD1. In UHS-II mode, before clearing this bit, Host Driver shall clear the 1h: Power on 0h: Power off" "0,1"
group.byte 0x2A++0x0
line.byte 0x00 "MMCSD1_BLOCK_GAP_CONTROL,This register is used to program the block gap request, read wait control and interrupt at block gap."
bitfld.byte 0x00 7. "               BOOT_ACK_ENA             ,Boot Acknowledge Check To check for the boot acknowledge in boot operation. 1h: Wait for boot ack from eMMC card 0h: Will not wait for boot ack from eMMC card" "0,1"
bitfld.byte 0x00 6. "                 ALT_BOOT_MODE            ,Alternative Boot Mode To start boot code access in alternative mode. 1h: To start alternate boot mode access 0h: To stop alternate boot mode access" "0,1"
textline "                                                 "
bitfld.byte 0x00 5. " BOOT_ENABLE              ,Boot Enable To start boot code access. 1h: To start boot code access 0h: To stop boot code access" "0,1"
bitfld.byte 0x00 3. "                 INTRPT_AT_BLK_GAP        ,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0h. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card." "0,1"
textline "                                                 "
bitfld.byte 0x00 2. " RDWAIT_CTRL              ,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1h otherwise DAT line conflict may occur. If this bit is set to 0h, Suspend/Resume cannot be supported. In UHS-II mode, Read Wait is disabled and DAT[2] line is used for Interrupt Signal from UHS-II Card. 1h: Enable Read Wait Control 0h: Disable Read Wait Control" "0,1"
bitfld.byte 0x00 1. "                 CONTINUE                 ,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0h ( The Host Controller automatically clears this bit when the transaction re-starts. If In SD mode, this bit is cleared in either of the following cases: Therefore it is not necessary for Host driver to set this bit to 0h. If 1h: Restart 0h: Ignored" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " STOP_AT_BLK_GAP          ,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA, SDMA and ADMA transfers. Until the transfer complete is set to 1h, indicating a transfer completion the HD shall leave this bit set to 1h. Clearing both the In case of UHS-II, a transaction can be stopped at the boundary of DATA Burst (Flow Control basis). Host Controller waits for sending Flow Control MSG until the 1h: Stop 0h: Transfer" "0,1"
group.byte 0x2B++0x0
line.byte 0x00 "MMCSD1_WAKEUP_CONTROL,This register is used to program the wakeup functionality. The register is mandatory for the HC, but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus, by setting the [0] SD_BUS_POWER bit to 1h, when wakeup event via card interrupt is desired."
bitfld.byte 0x00 2. "               CARD_REMOVAL             ,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1"
bitfld.byte 0x00 1. "                 CARD_INSERTION           ,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " CARD_INTERRUPT           ,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h. 1h: Enable 0h: Disable" "0,1"
group.word 0x2C++0x1
line.word 0x00 "MMCSD1_CLOCK_CONTROL,This register is used to program the Clock frequency select, Clock generator select, Clock enable, Internal clock state fields. At the initialization of the HC, the HD shall set the SDCLK Frequency Select ([15-8] SDCLK_FRQSEL) according to the register. This register controls SDCLK in SD Mode and RCLK in UHS-II mode."
hexmask.word.byte 0x00 8.--15. 1. "             SDCLK_FRQSEL             ,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities register ( Only the following settings are allowed. (1) 8-bit Divided Clock Mode: Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The three default divider values can be calculated by the frequency that is defined by the 400 KHz divider value 25 MHz divider value 50 MHz divider value According to the Physical Layer Specification, the maximum SD Clock frequency is 25 MHz in normal speed mode and 50 MHz in high speed mode, and shall never exceed this limit. The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) / divisor Thus, choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency. For example, if the (2) 10-bit Divided Clock Mode: (3) Programmable Clock Mode: This field depends on setting of the If If"
bitfld.word 0x00 6.--7. "                SDCLK_FRQSEL_UPBITS      ,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to the" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " CLKGEN_SEL               ,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h: Programmable Clock Mode 0h: Divided Clock Mode" "0,1"
bitfld.word 0x00 3. "                 PLL_ENA                  ,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable ( (1) When (2) When 1h: PLL is enabled 0h: PLL is in low power mode" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " SD_CLK_ENA               ,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h. The 1h: Enable providing SDCLK or RCLK 0h: Disable providing SDCLK or RCLK" "0,1"
bitfld.word 0x00 1. "                 INT_CLK_STABLE           ,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller which supports PLL Enable sets this status to 0h once when PLL Enable is changed 0h to 1h and then this status is set to 1h when PLL is locked (PLL uses an internal clock in stable as a reference clock which is enabled by the 1h: Ready 0h: Not Ready" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " INT_CLK_ENA              ,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1h. When clock oscillation is stable, the HC shall set the 1h: Oscillate 0h: Stop" "0,1"
group.byte 0x2E++0x0
line.byte 0x00 "MMCSD1_TIMEOUT_CONTROL,The register sets the data timeout counter value. At the initialization of the HC, the HD shall set the Data Timeout Counter Value according to the register."
bitfld.byte 0x00 0.--3. "               COUNTER_VALUE            ,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected. Refer to the 1111: Reserved 1110: TMCLK ? 2 -------------------- -------------------- 0001: TMCLK ? 2 0000: TMCLK ? 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x2F++0x0
line.byte 0x00 "MMCSD1_SOFTWARE_RESET,This register is used to program the software reset for data, command and for all. A reset pulse is generated when writing 1h to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0h."
bitfld.byte 0x00 2. "               SWRST_FOR_DAT            ,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset. The following registers and bits are cleared by this bit: 1h: Reset 0h: Work" "0,1"
bitfld.byte 0x00 1. "                 SWRST_FOR_CMD            ,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command. From Version 4.10, this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit (including response error statuses related to Command Inhibit (CMD) control - The following registers and bits are cleared by this bit: Response error statuses related to Command Inhibit (CMD) - 1h: Reset 0h: Work" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " SWRST_FOR_ALL            ,Software Reset for All This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0h. During its initialization, the HD shall set this bit to 1h to reset the HC. The HC shall reset this bit to 0h when Capabilities registers are valid and the HD can read them. Additional use of 'Software Reset For All' may not affect the value of the Capabilities registers. If this bit is set to 1h, the SD card shall reset itself and must be re-initialized by the HD. 1h: Reset 0h: Work" "0,1"
hgroup.word 0x30++0x1
hide.word 0x00 "MMCSD1_NORMAL_INTR_STS,This register gives the status of all the interrupts. The Normal Interrupt Signal Enable (see register) affects read of this register, but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1h. For all bits except Card Interrupt ([8] CARD_INTR) and Error Interrupt ([15] ERROR_INTR), writing 1h to a bit clears it. The [8] CARD_INTR bit is cleared when the card stops asserting the interrupt: that is when the Card Driver services the Interrupt condition."
in
textline "                                                 "
hgroup.word 0x32++0x1
hide.word 0x00 "MMCSD1_ERROR_INTR_STS,This register gives the status of the error interrupts. Status defined in this register can be enabled by the register, but not by the register. The Interrupt is generated when the register is enabled and at least one of the statuses is set to 1h. Writing to 1h clears the bit and writing to 0h keeps the bit unchanged. More than one status can be cleared at the one register write."
in
textline "                                                 "
group.word 0x34++0x1
line.word 0x00 "MMCSD1_NORMAL_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.word 0x00 15. "             BIT15_FIXED0             ,Fixed to 0 The HC shall control error Interrupts using the" "0,1"
bitfld.word 0x00 14. "                 BOOT_COMPLETE            ,Boot Terminate Interrupt Enable 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 13. " RCV_BOOT_ACK             ,Boot Acknowledge Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 12. "                 RETUNING_EVENT           ,Re-Tuning Event Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " INTC                     ,INT_C Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts." "0,1"
bitfld.word 0x00 10. "                 INTB                     ,INT_B Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts." "0,1"
textline "                                                 "
bitfld.word 0x00 9. " INTA                     ,INT_A Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts." "0,1"
bitfld.word 0x00 8. "                 CARD_INTERRUPT           ,Card Interrupt Status Enable If this bit is set to 0h, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the By setting this bit to 0h, interrupt input should be masked by implementation so that the interrupt Input is not affected by external signal in any state (for example: floating). 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 7. " CARD_REMOVAL             ,Card Removal Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 6. "                 CARD_INSERTION           ,Card Insertion Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 5. " BUF_RD_READY             ,Buffer Read Ready Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 4. "                 BUF_WR_READY             ,Buffer Write Ready Status Enable 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 3. " DMA_INTERRUPT            ,DMA Interrupt Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 2. "                 BLK_GAP_EVENT            ,Block Gap Event Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " XFER_COMPLETE            ,Transfer Complete Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 0. "                 CMD_COMPLETE             ,Command Complete Status Enable 0h: Masked 1h: Enabled" "0,1"
group.word 0x36++0x1
line.word 0x00 "MMCSD1_ERROR_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.word 0x00 12.--15. "             VENDOR_SPECIFIC          ,Vendor Specific Error Status Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Response Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Tuning Error Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,ADMA Error Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Auto CMD Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 7. "                 CURR_LIMIT               ,Current Limit Error Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DATA_ENDBIT              ,Data End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 5. "                 DATA_CRC                 ,Data CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_TIMEOUT             ,Data Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Command Index Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Command End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Command CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Command Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
group.word 0x38++0x1
line.word 0x00 "MMCSD1_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation."
bitfld.word 0x00 15. "             BIT15_FIXED0             ,Fixed to 0 The HD shall control error Interrupts using the" "0,1"
bitfld.word 0x00 14. "                 BOOT_COMPLETE            ,Boot Terminate Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 13. " RCV_BOOT_ACK             ,Boot Acknowledge Receive Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 12. "                 RETUNING_EVENT           ,Re-Tuning Event Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " INTC                     ,INT_C Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 10. "                 INTB                     ,INT_B Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 9. " INTA                     ,INT_A Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 8. "                 CARD_INTERRUPT           ,Card Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 7. " CARD_REMOVAL             ,Card Removal Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 6. "                 CARD_INSERTION           ,Card Insertion Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 5. " BUF_RD_READY             ,Buffer Read Ready Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 4. "                 BUF_WR_READY             ,Buffer Write Ready Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " DMA_INTERRUPT            ,DMA Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 2. "                 BLK_GAP_EVENT            ,Block Gap Event Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " XFER_COMPLETE            ,Transfer Complete Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 0. "                 CMD_COMPLETE             ,Command Complete Signal Enable 0h: Masked 1h: Enabled" "0,1"
group.word 0x3A++0x1
line.word 0x00 "MMCSD1_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation."
bitfld.word 0x00 12.--15. "             VENDOR_SPECIFIC          ,Vendor Specific Error Signal Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Response Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Tuning Error Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,ADMA Error Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Auto CMD Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 7. "                 CURR_LIMIT               ,Current Limit Error Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DATA_ENDBIT              ,Data End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 5. "                 DATA_CRC                 ,Data CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_TIMEOUT             ,Data Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Command Index Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Command End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Command CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Command Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
rgroup.word 0x3C++0x1
line.word 0x00 "MMCSD1_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01. This register is valid only when the Auto CMD Error is set."
bitfld.word 0x00 7. "             CMD_NOT_ISSUED           ,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: No Error 1h: Not Issued" "0,1"
bitfld.word 0x00 4. "                 INDEX                    ,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command. 0h: No Error 1h: Error" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " ENDBIT                   ,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h. 0h: No Error 1h: End Bit Error Generated" "0,1"
bitfld.word 0x00 2. "                 CRC                      ,Auto CMD CRC Error Occurs when detecting a CRC error in the command response. 0h: No Error 1h: CRC Error Generated" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " TIMEOUT                  ,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1h, the other error status bits (D04 - D02) are meaningless. 0h: No Error 1h: Timeout" "0,1"
bitfld.word 0x00 0. "                 ACMD12_NOT_EXEC          ,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1h, other error status bits (D04 - D01) are meaningless. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: Executed 1h: Not Executed" "0,1"
group.word 0x3E++0x1
line.word 0x00 "MMCSD1_HOST_CONTROL2,This register is used to program UHS Mode Select, Driver Strength Select, Execute Tuning, Sampling Clock Select, Asynchronous Interrupt Enable and Preset Value Enable."
bitfld.word 0x00 15. "             PRESET_VALUE_ENA         ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When the If this bit is set to 0h, SDCLK Frequency Select, Clock Generator Select in the If this bit is set to 1h, SDCLK Frequency Select, Clock Generator Select in the 0h: SDCLK and Driver Strength are controlled by Host Driver 1h: Automatic Selection by Preset Value are Enabled" "0,1"
bitfld.word 0x00 14. "                 ASYNCH_INTR_ENA          ,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and the 0h: Disabled 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 13. " BIT64_ADDRESSING         ,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets this bit depends on addressing mode of installed OS. Refer to 64-bit System Address Support in the 0h: 32-bits Addressing 1h: 64-bits Addressing" "0,1"
bitfld.word 0x00 12. "                 HOST_VER40_ENA           ,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00, support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version 4.10, supported 32-bit Block Count for all operations. Functions of following fields are modified. SDMA uses the ADMA3 is selected by 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1h. Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register instead of SDMA System Address register ( 0h: Version 3.00 Compatible Mode 1h: Version 4.Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " CMD23_ENA                ,CMD23 Enable In memory card initialization, Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h), this bit is set to 1h. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 datatransfer. Refer to" "0,1"
bitfld.word 0x00 10. "                 ADMA2_LEN_MODE           ,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit. 0h: 16-bit Data Length Mode 1h: 26-bit Data Length Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 9. " DRIVER_STRENGTH2         ,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value." "0,1"
bitfld.word 0x00 8. "                 UHS2_INTF_ENABLE         ,UHS-II Interface Enable This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization, this bit shall be set to 1h. Before trying to start SD mode initialization, this bit shall be set to 0h. This bit is used to enable UHS-II IF Detection, Lane Synchronization and In Dormant State in the Host Controller shall not leave unused SD 4-bit Interface lines (CLK, CMD and DAT[3:2]) floating in UHS-II mode by using pull-up or driving to low. When DAT[2] is used as interrupt input in UHS-II mode, DAT[2] of Host Controller is set to input and then DAT[2] of SDIO card is set to output to avoid conflict. 0h: 4-bit SD Interface Enabled 1h: UHS-II Interface Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 7. " SAMPLING_CLK_SELECT      ,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when the 0h: Fixed clock is used to sample data 1h: Tuned clock is used to sample data" "0,1"
bitfld.word 0x00 6. "                 EXECUTE_TUNING           ,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the 0h: Not Tuned or Tuning Completed 1h: Execute Tuning" "0,1"
textline "                                                 "
bitfld.word 0x00 4.--5. " DRIVER_STRENGTH1         ,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the If If 0h: Driver Type B is Selected (Default) 1h: Driver Type A is Selected 2h: Driver Type C is Selected 3h: Driver Type D is Selected" "0,1,2,3"
bitfld.word 0x00 3. "                 V1P8_SIGNAL_ENA          ,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage. Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V. 1.8 V regulator output shall be stable within 5 ms. Host Controller clears this bit if switching to 1.8 V signaling fails. Clearing this bit from 1h to 0h starts changing signal voltage from 1.8 V to 3.3 V. 3.3 V regulator output shall be stable within 5 ms. Host Driver can set this bit to 1h when Host Controller supports 1.8 V signaling (one of support bits is set to 1h: SDR50, SDR104 or DDR50 in the 0h: 3.3 V Signaling 1h: 1.8 V Signaling" "0,1"
textline "                                                 "
bitfld.word 0x00 0.--2. " UHS_MODE_SELECT          ,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode, this field is effective when the If the 0h: SDR12 1h: SDR25 2h: SDR50 3h: SDR104 4h: DDR50 5h: HS400 6h: Reserved 7h: UHS-II When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more details." "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x7
line.quad 0x00 "MMCSD1_CAPABILITIES,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization."
bitfld.quad 0x00 63. " HS400_SUPPORT            ,HS400 Support 0h: HS400 is Not Supported 1h: HS400 is Supported" "0,1"
bitfld.quad 0x00 60. "                 VDD2_1P8_SUPPORT         ,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system. 0h: 1.8 V VDD2 is not supported 1h: 1.8 V VDD2 is supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 59. " ADMA3_SUPPORT            ,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller. 0h: ADMA3 is not supported 1h: ADMA3 is supported" "0,1"
bitfld.quad 0x00 57. "                 SPI_BLK_MODE             ,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 56. " SPI_SUPPORT              ,SPI Mode This bit indicates whether SPI Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1"
hexmask.quad.byte 0x00 48.--55. 1. "                 CLOCK_MULTIPLIER         ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to the FFh: Clock Multiplier M = 256 ---- 02h: Clock Multiplier M = 3 01h: Clock Multiplier M = 2 00h: Clock Multiplier is Not Supported"
textline "                                                 "
bitfld.quad 0x00 46.--47. " RETUNING_MODES           ,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. 0h: Mode 1 1h: Mode 2 2h: Mode 3 3h: Reserved There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue." "0,1,2,3"
bitfld.quad 0x00 45. "                 TUNING_FOR_SDR50         ,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h, this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104). 0h: SDR50 does not require tuning 1h: SDR50 requires tuning" "0,1"
textline "                                                 "
bitfld.quad 0x00 40.--43. " RETUNING_TIMER_CNT       ,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ---- n = 2 ---- Bh = 1024 seconds Fh - Ch = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 38. "                DRIVERD_SUPPORT          ,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling. 0h: Driver Type D is Not Supported 1h: Driver Type D is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 37. " DRIVERC_SUPPORT          ,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling. 0h: Driver Type C is Not Supported 1h: Driver Type C is Supported" "0,1"
bitfld.quad 0x00 36. "                 DRIVERA_SUPPORT          ,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling. 0h: Driver Type A is Not Supported 1h: Driver Type A is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 35. " UHS2_SUPPORT             ,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h, the 0h: UHS-II is Not Supported 1h: UHS-II is Supported" "0,1"
bitfld.quad 0x00 34. "                 DDR50_SUPPORT            ,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not. 0h: DDR50 is Not Supported 1h: DDR50 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 33. " SDR104_SUPPORT           ,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not. SDR104 requires tuning. 0h: SDR104 is Not Supported 1h: SDR104 is Supported" "0,1"
bitfld.quad 0x00 32. "                 SDR50_SUPPORT            ,SDR50 Support (UHS-I Only) If SDR104 is supported, this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not. 0h: SDR50 is Not Supported 1h: SDR50 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 30.--31. " SLOT_TYPE                ,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (2h) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (2h), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System. 0h: Removable Card Slot 1h: Embedded Slot for One Device 2h: Shared Bus Slot (SD Mode) 3h: UHS-II Multiple Embedded Devices" "0,1,2,3"
bitfld.quad 0x00 29. "                 ASYNCH_INTR_SUPPORT      ,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 0h: Asynchronous Interrupt Not Supported 1h: Asynchronous Interrupt Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 28. " ADDR_64BIT_SUPPORT_V3    ,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses this bit as 64-bit System Address support for both V3 and V4 modes. SDMA cannot be used in 64-bit Addressing in Version 3 mode. If this bit is set to 1h, 64-bit ADMA2 with using 96-bit Descriptor may be enabled as follows: In case of Host Controller Version 3, 64-bit ADMA2 is enabled by 0h: 64-bit System Address for V3 is not Supported 1h: 64-bit System Address for V3 is Supported" "0,1"
bitfld.quad 0x00 27. "                 ADDR_64BIT_SUPPORT_V4    ,64-bit System Address Support for V4 This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode. When this bit is set to 1h, full or a part of 64-bit address should be used to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the If this bit is set to 1h, 64-bit DMA Addressing for Version 4 is enabled by setting 0h: 64-bit System Address for V4 is not Supported 1h: 64-bit System Address for V4 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 26. " VOLT_1P8_SUPPORT         ,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V. 0h: 1.8 V Not Supported 1h: 1.8 V Supported" "0,1"
bitfld.quad 0x00 25. "                 VOLT_3P0_SUPPORT         ,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V. 0h: 3.0 V Not Supported 1h: 3.0 V Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 24. " VOLT_3P3_SUPPORT         ,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V. 0h: 3.3 V Not Supported 1h: 3.3 V Supported" "0,1"
bitfld.quad 0x00 23. "                 SUSP_RES_SUPPORT         ,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands. 0h: Not Supported 1h: Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 22. " SDMA_SUPPORT             ,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. Version 4.10 Host Controller shall support SDMA if ADMA2 is supported. 0h: SDMA Not Supported 1h: SDMA Supported" "0,1"
bitfld.quad 0x00 21. "                 HIGH_SPEED_SUPPORT       ,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC). 0h: High Speed Not Supported 1h: High Speed Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 19. " ADMA2_SUPPORT            ,ADMA2 Support 0h: ADMA2 Not support 1h: ADMA2 support" "0,1"
bitfld.quad 0x00 18. "                 BUS_8BIT_SUPPORT         ,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the 0h: 8-bit Bus Width Not Supported 1h: 8-bit Bus Width Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 16.--17. " MAX_BLK_LENGTH           ,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 0h: 512 byte 1h: 1024 byte 2h: 2048 byte 3h: 4096 byte" "0,1,2,3"
hexmask.quad.byte 0x00 8.--15. 1. "                 BASE_CLK_FREQ            ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. 11xx xxxxb: Not Supported 0011 1111b: 63 MHz 0000 0010b: 2 MHz 0000 0001b: 1 MHz 0000 0000b: Get Information via another method (2) 8-bit Base Clock Frequency: This mode is supported by the Host Controller Version 3.00. Unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. FFh: 255 MHz 02h: 2 MHz 01h: 1 MHz 00h: Get Information via another method If the real frequency is 16.5 MHz, the lager value shall be set 0001 0001b (17 MHz) because the Host Driver use this value to calculate the clock divider value (refer to the"
textline "                                                 "
bitfld.quad 0x00 7. " TIMEOUT_CLK_UNIT         ,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "0,1"
bitfld.quad 0x00 0.--5. "                 TIMEOUT_CLK_FREQ         ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.quad 0x48++0x7
line.quad 0x00 "MMCSD1_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage."
hexmask.quad.byte 0x00 32.--39. 1. " VDD2_1P8V                ,Maximum Current for 1.8 V VDD2"
hexmask.quad.byte 0x00 16.--23. 1. "                VDD1_1P8V                ,Maximum Current for 1.8 V VDD1"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " VDD1_3P0V                ,Maximum Current for 3.0 V VDD1"
hexmask.quad.byte 0x00 0.--7. 1. "                VDD1_3P3V                ,Maximum Current for 3.3 V VDD1"
wgroup.word 0x50++0x1
line.word 0x00 "MMCSD1_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented, rather it is an address where the register can be written. Writing 1h: set each bit of the register Writing 0h: no effect By setting a bit in this register, the correspondent bit is set in the"
bitfld.word 0x00 7. "             CMD_NOT_ISS              ,Force Event for Command Not Issued by AUTO CMD12 Error 0h: Not Affected 1h: Command Not Issued By Auto CMD12 Error Status is set" "0,1"
bitfld.word 0x00 5. "                 RESP                     ,Force Event for AUTO CMD Response Error 0h: Not Affected 1h: Auto CMD Response Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " INDEX                    ,Force Event for AUTO CMD Index Error 0h: Not Affected 1h: Auto CMD Index Error Status is set" "0,1"
bitfld.word 0x00 3. "                 ENDBIT                   ,Force Event for AUTO CMD End Bit Error 0h: Not Affected 1h: Auto CMD End bit Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CRC                      ,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD CRC Error Status is set" "0,1"
bitfld.word 0x00 1. "                 TIMEOUT                  ,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD Timeout Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " ACMD_NOT_EXEC            ,Force Event for AUTO CMD12 Not Executed 0h: Not Affected 1h: Auto CMD12 Not Executed Status is set" "0,1"
wgroup.word 0x52++0x1
line.word 0x00 "MMCSD1_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented, rather it is an address where the register can be written. The register is not a physically implemented register. Rather, it is an address at which the register can be written. The effect of a write to this address will be reflected in the register if the corresponding bit of the register is set. Writing 1h: set each bit of the register Writing 0h: no effect"
bitfld.word 0x00 12.--15. "             VEND_SPEC                ,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Force Event for Response Error 0h: Not Affected 1h: Response Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Force Event for Tuning Error 0h: Not Affected 1h: Tuning Error Status is set" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,Force Event for ADMA Error 0h: Not Affected 1h: ADMA Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Force Event for Auto CMD Error 0h: Not Affected 1h: Auto CMD Error Status is set" "0,1"
bitfld.word 0x00 7. "                 CURR_LIM                 ,Force Event for Current Limit Error 0h: Not Affected 1h: Current Limit Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DAT_ENDBIT               ,Force Event for Data End Bit Error 0h: Not Affected 1h: Data End Bit Error Status is set" "0,1"
bitfld.word 0x00 5. "                 DAT_CRC                  ,Force Event for Data CRC Error 0h: Not Affected 1h: CRC Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DAT_TIMEOUT              ,Force Event for Data Timeout Error 0h: Not Affected 1h: Timeout Error Status is set" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Force Event for Command Index Error 0h: Not Affected 1h: Command Index Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Force Event for Command End Bit Error 0h: Not Affected 1h: Command End Bit Error Status is set" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Force Event for Command CRC Error 0h: Not Affected 1h: Command CRC Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Force Event for CMD Timeout Error 0h: Not Affected 1h: Command Timeout Error Status is set" "0,1"
rgroup.byte 0x54++0x0
line.byte 0x00 "MMCSD1_ADMA_ERR_STATUS,When the ADMA Error interrupt occur, this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor."
bitfld.byte 0x00 2. "               ADMA_LENGTH_ERR          ,ADMA Length Mismatch Error This error occurs in the following 2 cases. While the 0h: No Error 1h: Error" "0,1"
bitfld.byte 0x00 0.--1. "                 ADMA_ERR_STATE           ,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '2h' because ADMA never stops in this state. D01 - D00: ADMA Error State when error occurred Contents of SYS_SDR register 0h: ST_STOP (Stop DMA) Points to next of the error descriptor 1h: ST_FDS (Fetch Descriptor) Points to the error descriptor 2h: Never set this state (Not used) 3h: ST_TFR (Transfer Data) Points to the next of the error descriptor" "0,1,2,3"
group.quad 0x58++0x7
line.quad 0x00 "MMCSD1_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer."
hexmask.quad 0x00 0.--63. 1. " ADMA_ADDR                ,ADMA System Address The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this register and assumes it to be 0h. DMA in 64-bit addressing. The 64-bit addressing Host Driver uses all bits of this register and shall program Descriptor Table on 64-bit boundary and set 64-bit boundary address to this register. DMA2/3 ignores lower 3-bit of this register andassumes it to be 0h. If the This register holds byte address of executing command of the Descriptor table. At the start of ADMA2, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. This register is set by ADMA3. Host Driver is not necessary to set this register. The ADMA3 increments address of this register, which points to next line, when every time fetching a Descriptor line. When Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. Register Value - Addressing Mode - 32-bit System Address Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address"
rgroup.word 0x60++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value. When the [15] PRESET_VALUE_ENA bit is set to 1h, SDCLK/RCLK Frequency Select and Clock Generator Select in the register, and Driver Strength Select in the register are automatically set based on the Selected Bus Speed Mode (see ). This means the Host Driver needs not set these fields when preset is enabled. Before starting the initialization sequence, the Host Driver needs to set a clock preset value to SDCLK/RCLK Frequency Select in the register. The [15] PRESET_VALUE_ENA bit can be set after initialization completed. shows the conditions to select one of preset value registers."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x62++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE1,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x64++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE2,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x66++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE3,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x68++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE4,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6A++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE5,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6C++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE6,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6E++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE7,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x72++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE8,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x74++0x1
line.word 0x00 "MMCSD1_PRESET_VALUE10,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
group.quad 0x78++0x7
line.quad 0x00 "MMCSD1_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register."
hexmask.quad 0x00 0.--63. 1. " INTG_DESC_ADDR           ,ADMA3 Integrated Descriptor Address The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the next Descriptor address. The 32-bit addressing Host Driver uses lower 32-bit of this register and shall program Descriptor Table on 32-bit boundary. ADMA3 ignores lower 2-bit of this register and assumes it to be 0h. Writing to 07Bh starts ADMA3 data transfer. The 64-bit addressing Host Driver uses all 64-bit of this register and shall program Descriptor Table on 64-bit boundary. ADMA3 ignores lower 3-bit of this register and assumes it to be 0h. Writing to 07Fh starts ADMA3 data transfer. Register Value - Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address"
group.word 0x80++0x1
line.word 0x00 "MMCSD1_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block."
bitfld.word 0x00 12.--14. "             SDMA_BUF_BOUNDARY        ,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging, SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and requests the Host Driver to update the At the end of transfer, the Host Controller may issue or may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer Complete Interrupt is issued (see These bits shall be supported when the 0h: 4K bytes (Detects A11 carry out) 1h: 8K bytes (Detects A12 carry out) 2h: 16K Bytes (Detects A13 carry out) 3h: 32K Bytes (Detects A14 carry out) 4h: 64K bytes (Detects A15 carry out) 5h: 128K Bytes (Detects A16 carry out) 6h: 256K Bytes (Detects A17 carry out) 7h: 512K Bytes (Detects A18 carry out)" "0,1,2,3,4,5,6,7"
hexmask.word 0x00 0.--11. 1. "                 XFER_BLK_SIZE            ,UHS-II Block Size This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This bit field is effective when the 0000h - No data transfer 0001h - 1 Byte 0002h - 2 Bytes 0003h - 3 Bytes ... ... 01FFh - 511 Bytes 0200h - 512 Bytes ... ... 0800h - 2048 Bytes"
group.long 0x84++0x3
line.long 0x00 "MMCSD1_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks."
hexmask.long 0x00 0.--31. 1. "         XFER_BLK_COUNT           ,UHS-II Block Count This register is effective when the This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored. 00000000h: Stop Count 00000001h: 1 block 00000002h: 2 blocks ... ... FFFFFFFFh: 4G blocks - 1"
group.word 0x9C++0x1
line.word 0x00 "MMCSD1_UHS2_XFER_MODE,This register is used to control the operations of data transfers. On issuing a Command Packet, a Command Packet image is set to UHS-II Command Packet register (see - ) but Host Controller does not analyze the setting of UHS-II Command Packet register. Instead, Host Controller refers setting of this register to issue a Command Packet to make the control easy. Setting of these registers shall be correspondent."
bitfld.word 0x00 15. "             DUPLEX_SELECT            ,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver. 0h: Full Duplex Mode 1h: 2 Lane Half Duplex Mode" "0,1"
bitfld.word 0x00 14. "                 EBSY_WAIT                ,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer. If this bit is set to 1h, Host Controller waits receiving of EBSY packet and on receiving EBSY packet, the Setting of the 0h: Issue a command without busy 1h: Wait EBSY" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " RESP_INTR_DIS            ,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits the 0h: Response Interrupt is enabled 1h: Response Interrupt is disabled" "0,1"
bitfld.word 0x00 7. "                 RESP_ERR_CHK_ENA         ,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, this bit is set to 0h and the 0h: Response Error Check is disabled 1h: Response Error Check is enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " RESP_TYPE                ,Response Type R1/R5 When response error check is enabled, this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1"
bitfld.word 0x00 5. "                 BYTE_MODE                ,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when the 0h: Block Mode 1h: Byte Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_XFER_DIR            ,Data Transfer Direction This bit specifies direction of data transfer when the 0h: Read (Card to Host) 1h: Write (Host to Card)" "0,1"
bitfld.word 0x00 1. "                 BLK_CNT_ENA              ,Block Count Enable This bit specifies whether data transfer uses the 0h: Block Count Disabled 1h: Block Count Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " DMA_ENA                  ,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the 0h: DMA is disabled 1h: DMA is enabled" "0,1"
group.word 0x9E++0x1
line.word 0x00 "MMCSD1_UHS2_COMMAND,This register is used to program the Command for host controller."
bitfld.word 0x00 8.--12. "             PKT_LENGTH               ,UHS-II Command Packet Length A command packet length, which is set in the UHS-II Command Packet register ( 00011b ? 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b ? 10101b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 6.--7. "                CMD_TYPE                 ,Command Type This field is used to distinguish a specific command like abort command. If this field is set to 0h, the UHS-II RES Packet is stored in UHS-II Response register ( 0h: Normal Command 1h: TRANS_ABORT CCMD 2h: CMD12 or SDIO Abort command 3h: Go Dormant Command" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " DATA_PRESENT             ,Data Present This bit specifies whether the command is accompanied by data packet. 0h: No Data Present 1h: Data Present" "0,1"
bitfld.word 0x00 2. "                 SUB_COMMAND              ,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the 0h: Sub Command 1h: Main Command" "0,1"
group.byte 0xB4++0x0
line.byte 0x00 "MMCSD1_UHS2_MESSAGE_SELECT,This register is used to access internal buffer."
bitfld.byte 0x00 0.--1. "               MSG_SEL                  ,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the (assumed for debug usage). 0h: The latest MSG 1h: One MSG before 2h: Two MSGs before 3h: Three MSGs before" "0,1,2,3"
rgroup.long 0xB8++0x3
line.long 0x00 "MMCSD1_UHS2_MESSAGE,This register is used to access internal buffer."
hexmask.long.byte 0x00 24.--31. 1. "         MSG_BYTE3                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hexmask.long.byte 0x00 16.--23. 1. "                MSG_BYTE2                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " MSG_BYTE1                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hexmask.long.byte 0x00 0.--7. 1. "                MSG_BYTE0                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hgroup.word 0xBC++0x1
hide.word 0x00 "MMCSD1_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device."
in
textline "                                                 "
group.byte 0xBE++0x0
line.byte 0x00 "MMCSD1_UHS2_DEVICE_SELECT,UHS-II Device Select Register."
bitfld.byte 0x00 7. "               INT_MSG_ENA              ,INT MSG Enable (Optional) This bit enables receipt of INT MSG. If this bit is set to 1h, receipt of INT MSG is informed by the Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0, INT MSG Interrupt is not supported by the Host Controller. In this case, the 0h: Disabled 1h: Enabled" "0,1"
bitfld.byte 0x00 0.--3. "                 DEV_SEL                  ,UHS-II Device Select Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the The number of devices implemented in the Host Controller is indicated by the 0h: Unselected (Default) 1h: INT MSG of Device ID 1 is selected 2h: INT MSG of Device ID 2 is selected ..... ..... Fh: INT MSG of Device ID 15 is selected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xBF++0x0
line.byte 0x00 "MMCSD1_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h."
hexmask.byte 0x00 0.--7. 1. "               DEV_INTR                 ,UHS II Device Interrupt This register is effective when the The number of the registers to hold INT MSGs is determined by the"
group.word 0xC0++0x1
line.word 0x00 "MMCSD1_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register."
bitfld.word 0x00 1. "             HOST_SDTRAN_RESET        ,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued, SD-TRAN Initialization sequence from CMD8 is required to use UHS-II mode. Assuming that bus power is maintained and CM-TRAN Initialization is not required. Host Controller requires to do followings: (1) SD Clock Enable is maintained (continue to provide RCLK). (2) All setting register is maintained. (3) Internal sequencers are reset to just after power on be able to issue a command. (4) All Interrupt Status, Status Enable and Signal Enable are cleared. (5) Data transfer is terminated and data in buffer is discarded. 0h: Not Affected 1h: Reset SD-TRAN" "0,1"
bitfld.word 0x00 0. "                 HOST_FULL_RESET          ,Host Full Reset On issuing FULL_RESET CCMD, Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to use UHS-II mode. Assuming that bus power is maintained. Host Controller requires to do followings: (1) SD Clock Enable is cleared (internal Clock is still synchronized). (2) All setting register is cleared. (3) Internal sequencers are reset to just after power on. (4) All Interrupt Status, Status Enable and Signal Enable are cleared. 0h: Not Affected 1h: Reset Host Controller" "0,1"
group.word 0xC2++0x1
line.word 0x00 "MMCSD1_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register."
bitfld.word 0x00 4.--7. "             DEADLOCK_TIMEOUT_CTR     ,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for Deadlock (in the Fh: Reserved Eh: TMCLK x 2 .... .... 1h: TMCLK x 2 0h: TMCLK x 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "                CMDRESP_TIMEOUT_CTR      ,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for CMD_RES (in the Fh: Reserved Eh: TMCLK x 2 .... .... 1h: TMCLK x 2 0h: TMCLK x 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xC4++0x3
hide.long 0x00 "MMCSD1_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts."
in
textline "                                                 "
group.long 0xC8++0x3
line.long 0x00 "MMCSD1_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.long 0x00 27.--31. "         VENDOR_SPECFIC           ,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                DEADLOCK_TIMEOUT         ,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " CMD_RESP_TIMEOUT         ,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 15. "                 ADMA2_ADMA3              ,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,TID Error Setting this bit to 1h enables setting of TID Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Framing Error Setting this bit to 1h enables setting of Framing Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,CRC Error Setting this bit to 1h enables setting of CRC Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED            ,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RESP_PKT                 ,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Header Error Setting this bit to 1h enables setting of Header Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
group.long 0xCC++0x3
line.long 0x00 "MMCSD1_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals."
bitfld.long 0x00 27.--31. "         VENDOR_SPECFIC           ,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                DEADLOCK_TIMEOUT         ,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " CMD_RESP_TIMEOUT         ,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 15. "                 ADMA2_ADMA3              ,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED_SIG_ENA    ,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RESP_PKT                 ,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
rgroup.word 0xE0++0x1
line.word 0x00 "MMCSD1_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings."
hexmask.word 0x00 0.--15. 1. "             UHS2_SETTINGS_PTR        ,Pointer for UHS-II Settings Register"
rgroup.word 0xE2++0x1
line.word 0x00 "MMCSD1_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register."
hexmask.word 0x00 0.--15. 1. "             UHS2_CAPABILITIES_PTR    ,Pointer for UHS-II Capabilities Register"
rgroup.word 0xE4++0x1
line.word 0x00 "MMCSD1_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register."
hexmask.word 0x00 0.--15. 1. "             UHS2_TEST_PTR            ,Pointer for UHS-II Test Register"
rgroup.word 0xE6++0x1
line.word 0x00 "MMCSD1_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register."
hexmask.word 0x00 0.--15. 1. "             SHARED_BUS_CTRL_PTR      ,Pointer for Shared Bus Control Register"
rgroup.word 0xE8++0x1
line.word 0x00 "MMCSD1_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register."
hexmask.word 0x00 0.--15. 1. "             VENDOR_SPECFIC_PTR       ,Pointer for Vendor Specific Area"
group.long 0xF4++0x3
line.long 0x00 "MMCSD1_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter."
hexmask.long 0x00 0.--31. 1. "         DATA_TIMEOUT_CNT         ,Boot Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card. The value is in number of SD clock."
group.long 0xF8++0x3
line.long 0x00 "MMCSD1_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK, CMD11 Power Down Timer, Enhanced Strobe and eMMC Hardware Reset."
bitfld.long 0x00 16. "         AUTOGATE_SDCLK           ,Auto Gate SD CLK If this bit is set, SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device. 0h: Disable 1h: Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "                 CMD11_PD_TIMER           ,CMD11 Power Down Timer Value"
textline "                                                 "
bitfld.long 0x00 1. " EMMC_HW_RESET            ,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set. 0h: De-sassert hardware reset pin 1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)" "0,1"
bitfld.long 0x00 0. "                 ENHANCED_STROBE          ,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller." "0,1"
rgroup.word 0xFC++0x1
line.word 0x00 "MMCSD1_SLOT_INT_STS,This register is used to read the interrupt signal for each slot."
hexmask.word.byte 0x00 0.--7. 1. "             INTR_SIG                 ,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot."
rgroup.word 0xFE++0x1
line.word 0x00 "MMCSD1_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number."
hexmask.word.byte 0x00 8.--15. 1. "             VEN_VER_NUM              ,Vendor Version Number The Vendor Version Number is set to 10h (1.0)"
hexmask.word.byte 0x00 0.--7. 1. "                SPEC_VER_NUM             ,Specification Version Number This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version. 0h: SD Host Controller Specification Version 1.00 1h: SD Host Controller Specification Version 2.00 Including the feature of the ADMA and Test Register 2h: SD Host Controller Specification Version 3.00 3h: SD Host Controller Specification Version 4.00 4h: SD Host Controller Specification Version 4.10 Others: Reserved"
group.long 0x100++0x3
line.long 0x00 "MMCSD1_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register."
bitfld.long 0x00 8.--13. "         NUMLANES                 ,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0h: 2 Lanes FD or 2L-HD 1h: Not Used 2h: 3 Lanes 2D1U-FD (Embedded) 3h: 3 Lanes 1D2U-FD (Embedded) 4h: 4 Lanes 2D2U-FD (Embedded) Others: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0. "                POWER_MODE               ,Power Mode This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode. 0h: Fast Mode 1h: Low Power Mode" "0,1"
group.long 0x104++0x3
line.long 0x00 "MMCSD1_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register."
bitfld.long 0x00 20.--23. "         N_LSS_DIR                ,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h: 8 x 16 LSS 1h: 8 x 1 LSS 2h: 8 x 2 LSS 3h: 8 x 3 LSS .... .... Fh: 8 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                N_LSS_SYN                ,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h - 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 15. " HIBERNATE_ENA            ,Hibernate Enable After checking card capability of Hibernate mode, if all devices support Hibernate mode, this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode, VDD1 Power may be off. 0h: Hibernate Disabled 1h: Hibernate Enabled" "0,1"
bitfld.long 0x00 6.--7. "                 SPEED_RANGE              ,Speed Range PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. 0h: Range A (Defalt) 1h: Range B 2h: Reserved 3h: Reserved" "0,1,2,3"
group.quad 0x108++0x7
line.quad 0x00 "MMCSD1_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register."
hexmask.quad.byte 0x00 32.--39. 1. " N_DATA_GAP               ,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS"
bitfld.quad 0x00 16.--17. "                RETRY_COUNT              ,Retry Count Data Burst retry count is set to this field. 00h: Retry Disabled 01h: 1 time 02h: 2 times 03h: 3 times" "0,1,2,3"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " HOST_NFCU                ,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field. The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended considering buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Blocks 03h: 3 Blocks .... .... FFh: 255 Blocks"
rgroup.long 0x110++0x3
line.long 0x00 "MMCSD1_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register."
bitfld.long 0x00 22.--23. "         CORECFG_UHS2_BUS_TOPLOGY ,Bus Topology This field indicates one of bus topologies configured by a Host system. 0h: P2P Connection 1h: Ring Connection 2h: HUB Connection 3h: HUB is Connected in Ring" "0,1,2,3"
bitfld.long 0x00 18.--21. "                 CORECFG_UHS2_MAX_DEVICES ,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller. 0h: Not used 1h: 1 Devices 2h: 2 Devices .... .... Fh: 15 Devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 16.--17. " DEVICE_TYPE              ,Removable/Embedded This field indicates device type configured by a Host system. 0h: Removable Card (P2P) 1h: Embedded Devices 2h: Embedded Devices + Removable Card 3h: Reserved" "0,1,2,3"
bitfld.long 0x00 14. "                 CFG_64BIT_ADDRESSING     ,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller. 0h: 32-bit Addressing is supported 1h: 32-bit and 64-bit Addressing is supported" "0,1"
textline "                                                 "
bitfld.long 0x00 8.--13. " NUM_LANES                ,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller. 0 mean not supported and 1 means supported. D08: 2L-HD D09: 2D1U-FD D10: 1D2U-FD D11: 2D2U-FD D12: Reserved D13: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--7. "                GAP                      ,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM. 0h: Not used 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x 15 mW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 0.--3. " DAP                      ,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD. 0h: 360 mW (Default) 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x 15 mW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x114++0x3
line.long 0x00 "MMCSD1_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register."
bitfld.long 0x00 20.--23. "         N_LSS_DIR                ,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                N_LSS_SYN                ,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 6.--7. " SPEED_RANGE              ,Speed Range This field indicates supported Speed Range by the Host Controller. 0h: Range A (Default) 1h: Range A and Range B 2h: Reserved 3h: Reserved" "0,1,2,3"
rgroup.quad 0x118++0x7
line.quad 0x00 "MMCSD1_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register."
hexmask.quad.byte 0x00 32.--39. 1. " N_DATA_GAP               ,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS"
hexmask.quad.word 0x00 20.--31. 1. "                MAX_BLK_LENGTH           ,Host Maximum Block Length This field indicates maximum block length by the Host Controller. 000h: Not Used 001h: 1 byte 002h: 2 bytes .... .... 200h: 512 bytes .... .... 800h: 2048 bytes 801h - FFFh: Not Used"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " N_FCU                    ,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Block 03h: 3 Block .... .... FFh: 255 Blocks"
wgroup.long 0x120++0x3
line.long 0x00 "MMCSD1_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented, rather it is an address where the register can be written."
bitfld.long 0x00 27.--31. "         VENDOR_SPECIFIC          ,Force Event for Vendor Specific Error 0h: Not Affected 1h: Vendor Specific Error Status is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                TIMEOUT_DEADLOCK         ,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in the 0h: Not affected 1h: Timeout for Deadlock Error status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " TIMEOUT_CMD_RES          ,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in the 0h: Not affected 1h: Timout for CMD_RES Status is set" "0,1"
bitfld.long 0x00 15. "                 ADMA                     ,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in the 0h: Not affected 1h: ADMA Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in the 0h: Not affected 1h: EBSY Error Status is set" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in the 0h: Not affected 1h: Unrecoverable Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in the 0h: Not affected 1h: TID Error Status is set" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in the 0h: Not affected 1h: Framing Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in the 0h: Not affected 1h: CRC Error Status is set" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED            ,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in the 0h: Not affected 1h: Retry expired error status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RES_PKT                  ,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in the 0h: Not affected 1h: RES packet error status is set" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in the 0h: Not affected 1h: Header error status is set" "0,1"
rgroup.long 0x200++0x3
line.long 0x00 "MMCSD1_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE, in BCD format. The current version is rev 5.1. The following table describes the CQBASE+00h: Command Queueing Version."
bitfld.long 0x00 8.--11. "         EMMC_MAJOR_VER_NUM       ,eMMC Major Version Number (digit left of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "                EMMC_MINOR_VER_NUM       ,eMMC Minor Version Number (digit right of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 0.--3. " EMMC_VERSION_SUFFIX      ,eMMC Version Suffix (2nd digit right of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x204++0x3
line.long 0x00 "MMCSD1_CQ_CAPABILITIES,This register is reserved for capability indication."
bitfld.long 0x00 12.--15. "         CF_MUL                   ,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details ( Field Value Description: 0h: 0.001 MHz 1h: 0.01 MHz 2h: 0.1 MHz 3h: 1 MHz 4h: 10 MHz Other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "                CF_VAL                   ,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling. The clock frequency is calculated as ITCFVAL ? ITCFMUL. For example, to encode 19.2 MHz ITCFVAL shall be 192 ? 0.1 MHz = 19.2 MHz"
group.long 0x208++0x3
line.long 0x00 "MMCSD1_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time."
bitfld.long 0x00 12. "         DCMD_ENA                 ,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor, or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Bit Value Description 0h: Task descriptor in slot #31 is a Data Transfer Task Descriptor 1h: Task descriptor in slot #31 is a DCMD Task Descriptor" "0,1"
bitfld.long 0x00 8. "                 TASK_DESC_SIZE           ,This bit indicates whether the task descriptor size is 128 bits or 64 bits. This bit can only be configured when the Bit Value Description 0h: Task descriptor size is 64 bits 1h: Task descriptor size is 128 bits" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " CQ_ENABLE                ,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE). When this bit is 0h, CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller. Before software writes 1h to this bit, software shall verify that the eMMC host controller is in idle state and there are no commands or data transfers ongoing. When software wants to exit command queueing mode, it shall clear all previous tasks if such exist before setting this bit to 0h." "0,1"
group.long 0x20C++0x3
line.long 0x00 "MMCSD1_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time."
bitfld.long 0x00 8. "         CLEAR_ALL_TASKS          ,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state (Halt bit is 1h). When software writes 1h, the value of the register is updated to 1h, and CQE shall reset the Software should poll on this bit until it is set to back 0 and may then resume normal operation, by clearing the Halt bit. CQE does not communicate to the device that the tasks were cleared. It is softwares responsibility to order the device to discard the tasks in its queue using CMDQ_TASK_MGMT command. Writing 0h to this register shall have no effect." "0,1"
bitfld.long 0x00 0. "                 HALT_BIT                 ,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example, issuing a Discard Task command (CMDQ_TASK_MGMT). When software writes 1h, CQE shall complete the ongoing task if such a task is in progress. Once the task is completed and CQE is in idle state, CQE shall not issue new commands and shall indicate so to software by setting this bit to 1h. Software may poll on this bit until it is set to 1h, and may only then send commands on the eMMC bus. In order to exit halt state (resume CQE activity), software shall clear this bit (write 0h). Writing 0h when the value is already 0h shall have no effect." "0,1"
hgroup.long 0x210++0x3
hide.long 0x00 "MMCSD1_CQ_INTR_STS,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event, only if the respective bit is set in the register."
in
textline "                                                 "
group.long 0x214++0x3
line.long 0x00 "MMCSD1_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register. When a bit is set (1h) and the corresponding interrupt condition is active, then the 300 bit in the register is asserted. Interrupt sources that are disabled (0h) are not indicated in the 301 register. This register is bit-index matched to the register."
bitfld.long 0x00 4. "         TASK_ERROR               ,1h: 0h:" "0,1"
bitfld.long 0x00 3. "                 TASK_CLEARED             ,1h: 0h:" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " RESP_ERR_DET             ,1h: 0h:" "0,1"
bitfld.long 0x00 1. "                 TASK_COMPLETE            ,1h: 0h:" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " HALT_COMPLETE            ,1h: 0h:" "0,1"
group.long 0x218++0x3
line.long 0x00 "MMCSD1_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the register is set, then an interrupt is generated. Interrupt sources 305 that are disabled (0h) are still indicated in the register. This register is bit-index matched 306 to the register."
bitfld.long 0x00 4. "         TASK_ERROR               ,When set and the" "0,1"
bitfld.long 0x00 3. "                 TASK_CLEARED             ,When set and the" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " RESP_ERR_DET             ,When set and the" "0,1"
bitfld.long 0x00 1. "                 TASK_COMPLETE            ,When set and the" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " HALT_COMPLETE            ,When set and the" "0,1"
group.long 0x21C++0x3
line.long 0x00 "MMCSD1_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature."
bitfld.long 0x00 31. "         CQINTCOALESC_ENABLE      ,When set to 0h by software, command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor. When set to 1h, the interrupt coalescing mechanism is enabled and coalesced interrupts are generated." "0,1"
bitfld.long 0x00 20. "                 IC_STATUS                ,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0). Bit Value Description 0h: No task completions have occurred since last counter reset (IC counter = 0) 1h: At least one task completion has been counted (IC counter > 0)" "0,1"
textline "                                                 "
bitfld.long 0x00 8.--12. " CTR_THRESHOLD            ,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT = 0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine. The counter stops counting when it reaches the value configured in ICCTH. The maximum allowed value is 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--6. 1. "                TIMEOUT_VAL              ,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts running when a data transfer task with INT = 0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field it generates an interrupt and stops. The timers unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field in the The minimum value is 1h (1024 clock periods) and the maximum value is 7Fh (127 ? 1024 clock periods). For example, a"
group.long 0x220++0x3
line.long 0x00 "MMCSD1_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory."
hexmask.long 0x00 0.--31. 1. "         CQTDLBA_LO               ,This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 ? (Task Descriptor size + Transfer Descriptor size) as configured by Host driver. This address shall be set on Byte1 KByte boundary. The lower 10 bits of this register shall be set to 0h by software and shall be ignored by CQE."
group.long 0x224++0x3
line.long 0x00 "MMCSD1_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory."
hexmask.long 0x00 0.--31. 1. "         CQTDLBA_HI               ,This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 ? (Task Descriptor size + Transfer Descriptor size) as configured by Host driver. This register is reserved when using 32-bit addressing mode."
group.long 0x228++0x3
line.long 0x00 "MMCSD1_CQ_TASK_DOOR_BELL,Using this register, software triggers CQE to process a new task."
hexmask.long 0x00 0.--31. 1. "         CQTDB_VAL                ,Software shall configure the Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. CQE always processes tasks in-order according to the order submitted to the list by the CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. The corresponding bit is cleared to 0h by CQE in one of the following events: (a) When a task execution is completed (with success or error) (b) The task is cleared using (c) All tasks are cleared using (d) CQE is disabled using Software may initiate multiple tasks at the same time (batch submission) by writing 1h to multiple bits of this register in the same transaction. In the case of batch submission: CQE shall process the tasks in order of the task index, starting with the lowest index. If one or more tasks in the batch are marked with QBR, the ordering of execution will be based on said processing order. Writing 0h by software shall have no impact on the hardware, and will not change the value of the register bit."
hgroup.long 0x22C++0x3
hide.long 0x00 "MMCSD1_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks."
in
textline "                                                 "
rgroup.long 0x230++0x3
line.long 0x00 "MMCSD1_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status."
hexmask.long 0x00 0.--31. 1. "         CQDQ_STS                 ,Every time the Host controller receives a queue status register (QSR) from the device, it updates this register with the response of status command (the device's queue status)."
rgroup.long 0x234++0x3
line.long 0x00 "MMCSD1_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device, awaiting execution."
hexmask.long 0x00 0.--31. 1. "         CQDP_TSKS                ,Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet. CQE shall set this bit after receiving a successful response for CMD45. CQE shall clear this bit after the task has completed execution. Software needs to read this register in the task-discard procedure, when the controller is halted, to determine if the task is queued in the device. If the task is queued, the driver sends a CMDQ_TASK_MGMT (CMD48) to the device ordering it to discard the task. Then software clears the task in the CQE. Only then the software orders CQE to resume its operation using"
group.long 0x238++0x3
line.long 0x00 "MMCSD1_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state."
hexmask.long 0x00 0.--31. 1. "         CQTCLR                   ,Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued. This bit can only be written when CQE is in Halt state as indicated in the When software writes 1h to a bit in this register, CQE updates the value to 1h, and starts clearing the data structures related to the task. CQE clears the bit fields (sets a value of 0h) in the Software should poll on the Writing to this register only clears the task in the CQE and does not have impact on the device. In order to discard the task in the device, host software shall send CMDQ_TASK _MGMT while CQE is still in Halt state. Host driver is not allowed to use this register to clear multiple tasks at the same time. Clearing multiple tasks can be done using Writing 0h to a register bit shall have no impact."
group.long 0x240++0x3
line.long 0x00 "MMCSD1_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent."
bitfld.long 0x00 16.--19. "         CMD_BLK_CNTR             ,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue. A value of n means CQE shall send status command on the CMD line, during the transfer of data block A value of 0h means that SEND_QUEUE_STATUS (CMD13) command shall not be sent during the transaction. Instead it will be sent only when the data lines are idle. A value of 1 means that STATUS command is to be sent during the last block of the transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "                CMD_IDLE_TIMER           ,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. When a SEND_QUEUE_STATUS response indicating that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. Timer units are clock periods of theclock whose frequency is specified in the Internal Timer Clock Frequency field in the The minimum value is 1h (1 clock period) and the maximum value is FFFFh (65535 clock periods). Default interval is: 4096 clock periods. For example, a"
group.long 0x244++0x3
line.long 0x00 "MMCSD1_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument."
hexmask.long.word 0x00 0.--15. 1. "         QUEUE_RCA                ,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command."
rgroup.long 0x248++0x3
line.long 0x00 "MMCSD1_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software."
hexmask.long 0x00 0.--31. 1. "         LAST_RESP                ,This register contains the response of the command generated by the last direct command (DCMD) task which was sent. CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31 of the"
rgroup.long 0x250++0x3
line.long 0x00 "MMCSD1_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt."
hexmask.long 0x00 0.--31. 1. "         CQRMEM                   ,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses. Bit Value Description (for any bit i): 1h: When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated 0h: When a R1/R1b response is received, bit i in the device status is ignored The reset value of this register is set to trigger an interrupt on all 'Error' type bits in the device status."
rgroup.long 0x254++0x3
line.long 0x00 "MMCSD1_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the register the task IDs and the command indices of the commands which were executed on the 343 command line and data lines when the error occurred. Software is expected to use this information in the error recovery procedure."
bitfld.long 0x00 31. "         DATERR_VALID             ,This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated, the bit is set to 1h. If a no data transfer is in progress when the error is detected/indicated, the bit is cleared to 0h." "0,1"
bitfld.long 0x00 24.--28. "                 DATERR_TASK_ID           ,This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 16.--21. " DATERR_CMD_INDEX         ,This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "                RESP_MODE_VALID          ,This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated, the bit is set to 1h. If a no command transaction is in progress when the error is detected/indicated, the bit is cleared to 0h." "0,1"
textline "                                                 "
bitfld.long 0x00 8.--12. " RESP_MODE_TASK_ID        ,This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "                RESP_MODE_CMD_INDEX      ,This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x258++0x3
line.long 0x00 "MMCSD1_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response."
bitfld.long 0x00 0.--5. "         LAST_CRI                 ,This field stores the index of the last received command response. CQE shall update the value every time a command response is received." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x25C++0x3
line.long 0x00 "MMCSD1_CQ_CMD_RESP_ARG,This register stores the index of the last received command response."
hexmask.long 0x00 0.--31. 1. "         LAST_CRA                 ,This field stores the argument of the last received command. CQE shall update the value every time a command response is received."
rgroup.long 0x260++0x3
line.long 0x00 "MMCSD1_CQ_ERROR_TASK_ID,CQ Error Task ID Register"
bitfld.long 0x00 0.--4. "         TERR_ID                  ,Task Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "MMCSD1_SS_CFG"
base ad:0x4FB0000
width 26.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD1_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem."
hexmask.long.word 0x00 16.--31. 1. " MOD_ID          ,Module ID"
bitfld.long 0x00 11.--15. "      RTL_VER           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                   "
bitfld.long 0x00 8.--10. " MAJ_REV         ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom Version" "0,1,2,3"
textline "                                   "
bitfld.long 0x00 0.--5. " MIN_REV         ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification."
bitfld.long 0x00 24.--29. " TUNINGCOUNT     ,This field controls the corecfg_tuningcount port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "        ASYNCWKUPENA      ,This field controls the corecfg_asyncwkupena port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 12.--15. " CQFMUL          ,This field controls the corecfg_cqfmul port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "        CQFVAL            ,This field controls the corecfg_cqfval port on the controller."
group.long 0x14++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the LSB fields in the register inside the Host Controller."
bitfld.long 0x00 30.--31. " SLOTTYPE        ,This field controls the corecfg_slottype port on the controller." "0,1,2,3"
bitfld.long 0x00 29. "         ASYNCHINTRSUPPORT ,This field controls the corecfg_asynchintrsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 26. " SUPPORT1P8VOLT  ,This field controls the corecfg_1p8voltsupport port on the controller." "0,1"
bitfld.long 0x00 25. "         SUPPORT3P0VOLT    ,This field controls the corecfg_3p0voltsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 24. " SUPPORT3P3VOLT  ,This field controls the corecfg_3p3voltsupport port on the controller." "0,1"
bitfld.long 0x00 23. "         SUSPRESSUPPORT    ,This field controls the corecfg_suspressupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 22. " SDMASUPPORT     ,This field controls the corecfg_sdmasupport port on the controller." "0,1"
bitfld.long 0x00 21. "         HIGHSPEEDSUPPORT  ,This field controls the corecfg_highspeedsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 19. " ADMA2SUPPORT    ,This field controls the corecfg_adma2support port on the controller." "0,1"
bitfld.long 0x00 18. "         SUPPORT8BIT       ,This field controls the corecfg_8bitsupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 16.--17. " MAXBLKLENGTH    ,This field controls the corecfg_maxblklength port on the controller." "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "         BASECLKFREQ       ,This field controls the corecfg_baseclkfreq port on the controller."
textline "                                   "
bitfld.long 0x00 7. " TIMEOUTCLKUNIT  ,This field controls the corecfg_timeoutclkunit port on the controller." "0,1"
bitfld.long 0x00 0.--5. "         TIMEOUTCLKFREQ    ,This field controls the corecfg_timeoutclkfreq port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the MSB fields in the register inside the Host Controller."
bitfld.long 0x00 28. " SUPPORT1P8VDD2  ,This field controls the corecfg_1p8vdd2support port on the controller." "0,1"
bitfld.long 0x00 27. "         ADMA3SUPPORT      ,This field controls the corecfg_adma3support port on the controller." "0,1"
textline "                                   "
hexmask.long.byte 0x00 16.--23. 1. " CLOCKMULTIPLIER ,This field controls the corecfg_clockmultiplier port on the controller."
bitfld.long 0x00 14.--15. "        RETUNINGMODES     ,This field controls the corecfg_retuningmodes port on the controller." "0,1,2,3"
textline "                                   "
bitfld.long 0x00 13. " TUNINGFORSDR50  ,This field controls the corecfg_tuningforsdr50 port on the controller." "0,1"
bitfld.long 0x00 8.--11. "         RETUNINGTIMERCNT  ,This field controls the corecfg_retuningtimercnt port on the controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                   "
bitfld.long 0x00 7. " TYPE4SUPPORT    ,This field controls the corecfg_type4support port on the controller." "0,1"
bitfld.long 0x00 6. "         DDRIVERSUPPORT    ,This field controls the corecfg_ddriversupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 5. " CDRIVERSUPPORT  ,This field controls the corecfg_cdriversupport port on the controller." "0,1"
bitfld.long 0x00 4. "         ADRIVERSUPPORT    ,This field controls the corecfg_adriversupport port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 2. " DDR50SUPPORT    ,This field controls the corecfg_ddr50support port on the controller." "0,1"
bitfld.long 0x00 1. "         SDR104SUPPORT     ,This field controls the corecfg_sdr104support port on the controller." "0,1"
textline "                                   "
bitfld.long 0x00 0. " SDR50SUPPORT    ,This field controls the corecfg_sdr50support port on the controller." "0,1"
group.long 0x1C++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the LSB fields in the register inside the Host Controller."
hexmask.long.byte 0x00 16.--23. 1. " MAXCURRENT1P8V  ,This field controls the corecfg_maxcurrent1p8v port on the controller."
hexmask.long.byte 0x00 8.--15. 1. "        MAXCURRENT3P0V    ,This field controls the corecfg_maxcurrent3p0v port on the controller."
textline "                                   "
hexmask.long.byte 0x00 0.--7. 1. " MAXCURRENT3P3V  ,This field controls the corecfg_maxcurrent3p3v port on the controller."
group.long 0x20++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the MSB fields in the register inside the Host Controller."
hexmask.long.byte 0x00 0.--7. 1. " MAXCURRENTVDD2  ,This field controls the corecfg_maxcurrentvdd2 port on the controller."
group.long 0x24++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for Initialization inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " INITPRESETVAL   ,This field controls the corecfg_initpresetval port on the controller."
group.long 0x28++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for Default Speed inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " DSPDPRESETVAL   ,This field controls the corecfg_dspdpresetval port on the controller."
group.long 0x2C++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for High Speed inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " HSPDPRESETVAL   ,This field controls the corecfg_hspdpresetval port on the controller."
group.long 0x30++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR12 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR12PRESETVAL  ,This field controls the corecfg_sdr12presetval port on the controller."
group.long 0x34++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR25 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR25PRESETVAL  ,This field controls the corecfg_sdr25presetval port on the controller."
group.long 0x38++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR50 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR50PRESETVAL  ,This field controls the corecfg_sdr50presetval port on the controller."
group.long 0x3C++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for SDR104 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " SDR104PRESETVAL ,This field controls the corecfg_sdr104presetval port on the controller."
group.long 0x40++0x3
line.long 0x00 "MMCSD1_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. For detailed functionality of the Host Controller configuration ports please refer to its specification. This register sets the fields in the Preset Values registers ( to ) for DDR50 inside the Host Controller."
hexmask.long.word 0x00 0.--12. 1. " DDR50PRESETVAL  ,This field controls the corecfg_ddr50presetval port on the controller."
rgroup.long 0x60++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
bitfld.long 0x00 31. " SDHC_CMDIDLE    ,This field reflects the value of the sdhc_cmdidle port on the controller." "0,1"
hexmask.long.word 0x00 0.--15. 1. "         DMADEBUGBUS       ,This field reflects the value of the sdhc_dmadebugbus port on the controller."
rgroup.long 0x64++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " CMDDEBUGBUS     ,This field reflects the value of the sdhc_cmddebugbus port on the controller."
rgroup.long 0x68++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " TXDDEBUGBUS     ,This field reflects the value of the sdhc_txddebugbus port on the controller."
rgroup.long 0x6C++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " RXDDEBUGBUS0    ,This field reflects the value of the sdhc_rxddebugbus0 port on the controller."
rgroup.long 0x70++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " RXDDEBUGBUS1    ,This field reflects the value of the sdhc_rxddebugbus1 port on the controller."
rgroup.long 0x74++0x3
line.long 0x00 "MMCSD1_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller. For detailed functionality of the Host Controller debug ports please refer to its specification."
hexmask.long.word 0x00 0.--15. 1. " TUNDEBUGBUS     ,This field reflects the value of the sdhc_tundebugbus port on the controller."
group.long 0x100++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 31. " IOMUX_ENABLE    ,This field controls the phyctrl_enable_iomuxing port on the PHY." "0,1"
bitfld.long 0x00 20.--22. "         DR_TY             ,This field controls the phyctrl_dr_ty port on the PHY." "0,1,2,3,4,5,6,7"
textline "                                   "
bitfld.long 0x00 17. " RETRIM          ,This field controls the phyctrl_retrim port on the PHY." "0,1"
bitfld.long 0x00 16. "         EN_RTRIM          ,This field controls the phyctrl_en_rtrim port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 4.--7. " DLL_TRM_ICP     ,This field controls the phyctrl_dll_trm_icp port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "        ENDLL             ,This field controls the phyctrl_endll port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0. " PDB             ,This field controls the phyctrl_pdb port on the PHY." "0,1"
group.long 0x104++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 28. " OD_RELEASE_CMD  ,This field controls the phyctrl_OD_release_cmd port on the PHY." "0,1"
bitfld.long 0x00 16.--19. "         OD_RELEASE_DAT    ,This field controls the phyctrl_OD_release_dat port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                   "
bitfld.long 0x00 12. " ODEN_CMD        ,This field controls the phyctrl_oden_cmd port on the PHY." "0,1"
bitfld.long 0x00 0.--3. "         ODEN_DAT          ,This field controls the phyctrl_oden_dat port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x108++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 28. " PU_CMD          ,This field controls the phyctrl_pu_cmd port on the PHY." "0,1"
bitfld.long 0x00 16.--19. "         PU_DAT            ,This field controls the phyctrl_pu_dat port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                   "
bitfld.long 0x00 12. " REN_CMD         ,This field controls the phyctrl_ren_cmd port on the PHY." "0,1"
bitfld.long 0x00 0.--3. "         REN_DAT           ,This field controls the phyctrl_ren_dat port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 20. " OTAPDLYENA      ,This field controls the phyctrl_otapdlyena port on the PHY." "0,1"
bitfld.long 0x00 12.--15. "         OTAPDLYSEL        ,This field controls the phyctrl_otapdlysel port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                   "
bitfld.long 0x00 9. " ITAPCHGWIN      ,This field controls the phyctrl_itapchgwin port on the PHY." "0,1"
bitfld.long 0x00 8. "         ITAPDLYENA        ,This field controls the phyctrl_itapdlyena port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0.--4. " ITAPDLYSEL      ,This field controls the phyctrl_itapdlysel port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x110++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 17. " SELDLYTXCLK     ,This field controls the phyctrl_seldlytxclk port on the PHY." "0,1"
bitfld.long 0x00 16. "         SELDLYRXCLK       ,This field controls the phyctrl_seldlyrxclk port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 9. " SEL100          ,This field controls the phyctrl_sel100 port on the PHY." "0,1"
bitfld.long 0x00 8. "         SEL50             ,This field controls the phyctrl_sel50 port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0.--2. " CLKBUFSEL       ,This field controls the phyctrl_clkbufsel port on the PHY." "0,1,2,3,4,5,6,7"
group.long 0x114++0x3
line.long 0x00 "MMCSD1_SS_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Host Controller PHY. For detailed functionality of the Host Controller PHY control ports please refer to its specification."
bitfld.long 0x00 31. " BISTENABLE      ,This field controls the phyctrl_bistenable port on the PHY." "0,1"
bitfld.long 0x00 30. "         BISTSTART         ,This field controls the phyctrl_biststart port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 24.--27. " BISTMODE        ,This field controls the phyctrl_bistmode port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "        TESTCTRL          ,This field controls the phyctrl_testctrl port on the PHY."
rgroup.long 0x130++0x3
line.long 0x00 "MMCSD1_SS_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Host Controller PHY ports. For detailed functionality of the Host Controller PHY status ports please refer to its specification."
bitfld.long 0x00 4.--7. " RTRIM           ,This field reflects the value of the phyctrl_rtrim port on the PHY." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        BISTDONE          ,This field reflects the value of the phyctrl_bistdone port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 2. " EXR_NINST       ,This field reflects the value of the phyctrl_exr_ninst port on the PHY." "0,1"
bitfld.long 0x00 1. "         CALDONE           ,This field reflects the value of the phyctrl_caldone port on the PHY." "0,1"
textline "                                   "
bitfld.long 0x00 0. " DLLRDY          ,This field reflects the value of the phyctrl_dllrdy port on the PHY." "0,1"
rgroup.long 0x134++0x3
line.long 0x00 "MMCSD1_SS_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Host Controller PHY ports. For detailed functionality of the Host Controller PHY status ports please refer to its specification."
hexmask.long 0x00 0.--31. 1. " BISTSTATUS      ,This field reflects the value of the phyctrl_biststatus port on the PHY."
width 0x0B
tree.end
tree "MMCSD0_ECC_AGGR_TXMEM"
base ad:0x2A25000
width 34.
rgroup.long 0x0++0x3
line.long 0x00 "MMCSD0_TXECC_REV,Aggregator Revision Register Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME           ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,Business Unit" "0,1,2,3"
textline "                                           "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID        ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                           "
bitfld.long 0x00 8.--10. " REVMAJ           ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom Version" "0,1,2,3"
textline "                                           "
bitfld.long 0x00 0.--5. " REVMIN           ,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "MMCSD0_TXECC_VECTOR,ECC Vector Register"
in
textline "                                           "
rgroup.long 0xC++0x3
line.long 0x00 "MMCSD0_TXECC_STAT,Misc Status Register"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS         ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "MMCSD0_TXECC_SEC_EOI_REG,SEC EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,SEC EOI" "0,1"
group.long 0x40++0x3
line.long 0x00 "MMCSD0_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x00 0. " TXMEM_PEND       ,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "MMCSD0_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " TXMEM_ENABLE_SET ,Interrupt Enable Set for txmem_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "MMCSD0_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x13C++0x3
line.long 0x00 "MMCSD0_TXECC_DED_EOI_REG,DED EOI Register"
bitfld.long 0x00 0. " EOI_WR           ,DED EOI" "0,1"
group.long 0x140++0x3
line.long 0x00 "MMCSD0_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x00 0. " TXMEM_PEND       ,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "MMCSD0_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. " TXMEM_ENABLE_SET ,Interrupt Enable Set for txmem_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "MMCSD0_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
in
textline "                                           "
group.long 0x200++0x3
line.long 0x00 "MMCSD0_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. " TIMEOUT          ,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "MMCSD0_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
in
textline "                                           "
group.long 0x208++0x3
line.long 0x00 "MMCSD0_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "MMCSD0_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT          ,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MMCSD0_CTL_CFG"
base ad:0x4F80000
width 32.
group.word 0x0++0x1
line.word 0x00 "MMCSD0_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x00 0.--15. 1. "             SDMA_ADDRESS             ,32-bit Block Count (SDMA System Address) Low When the When the (1) SDMA System Address ( This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (after a transaction has stopped). Reading this register during SDMA transfers may return an invalid value. The Host Driver (HD) shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the (2) 32-bit Block Count ( Host Controller Version 4.10 re-defines this register as 32-bit Block Count. In version 4.00, this register may be used as 32-bit block count only for Auto CMD23 to set the argument of the CMD23 while executing Auto CMD23. The Host Controller would decrement the block count of this register every block transfer and data transfer stops when the count reaches zero."
group.word 0x2++0x1
line.word 0x00 "MMCSD0_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
hexmask.word 0x00 0.--15. 1. "             SDMA_ADDRESS             ,32-bit Block Count (SDMA System Address) High This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10."
group.word 0x4++0x1
line.word 0x00 "MMCSD0_BLOCK_SIZE,This register is used to configure the number of bytes in a data block."
bitfld.word 0x00 12.--14. "             SDMA_BUF_SIZE            ,Host SDMA Buffer Size To perform long DMA transfer, System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry out) 4h: 64KB (Detects A15 Carry out) 5h: 128KB (Detects A16 Carry out) 6h: 256KB (Detects A17 Carry out) 7h: 512KB (Detects A18 Carry out)" "0,1,2,3,4,5,6,7"
hexmask.word 0x00 0.--11. 1. "                 XFER_BLK_SIZE            ,Transfer Block Size This field specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. 0000h: No Data Transfer 0001h: 1 Byte 0002h: 2 Bytes 0003h: 3 Bytes 0004h: 4 Bytes .... 01FFh: 511 Bytes 0200h: 512 Bytes .... 0800h: 2048 Bytes"
group.word 0x6++0x1
line.word 0x00 "MMCSD0_BLOCK_COUNT,This register is used to configure the number of data blocks."
hexmask.word 0x00 0.--15. 1. "             XFER_BLK_CNT             ,16-bit Block Count Host Controller Version 4.10 extends block count to 32-bit. Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: (1) If the (2) If the Use of 16-bit/32-bit Block Count register is enabled when the The Host Driver shall set this register to a value between 1h and the maximum block count. The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred. This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored. 0000h: Stop Count 0001h: 1 Block 0002h: 2 Blocks .... FFFFh: 65535 Blocks"
group.word 0x8++0x1
line.word 0x00 "MMCSD0_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument."
hexmask.word 0x00 0.--15. 1. "             CMD_ARG1                 ,Command Argument 1 Low The SD Command Argument is specified as bit 23-8 of Command-Format."
group.word 0xA++0x1
line.word 0x00 "MMCSD0_ARGUMENT1_HI,This register contains higher bits of SD Command Argument."
hexmask.word 0x00 0.--15. 1. "             CMD_ARG1                 ,Command Argument 1 High The SD Command Argument is specified as bit 39-24 of Command-Format."
group.word 0xC++0x1
line.word 0x00 "MMCSD0_TRANSFER_MODE,"
bitfld.word 0x00 8. "             RESP_INTR_DIS            ,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits Command Complete Interrupt ( If Host Controller checks response error, sets this bit to 1h and sets the 0h: Response Interrupt is enabled 1h: Response Interrupt is disabled" "0,1"
bitfld.word 0x00 7. "                 RESP_ERR_CHK_ENA         ,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, this bit is set to 0h and the If Host Controller checks response error, sets this bit to 1h and sets the Response Interrupt Disable bit to 1h ( The 0h: Response Error Check is disabled 1h: Response Error Check is enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " RESP_TYPE                ,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1"
bitfld.word 0x00 5. "                 MULTI_BLK_SEL            ,Multi/Single Block Select This bit enables multiple block data transfers. 0h: Single Block 1h: Multiple Block" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_XFER_DIR            ,Data Transfer Direction Select This bit defines the direction of data transfers. 0h: Write (Host to Card) 1h: Read (Card to Host)" "0,1"
bitfld.word 0x00 2.--3. "                 AUTO_CMD_ENA             ,Auto CMD Enable This field determines use of auto command functions. There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation), this field is set to 0h. (1) Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 1h, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the When When (2) Auto CMD23 Enable: When this bit field is set to 2h, the Host Controller issues a CMD23 automatically before issuing a command specified in the The following conditions are required to use the Auto CMD23: Auto CMD23 Supported (Host Controller Version is 3.00 or later). A memory card that supports CMD23 (SCR[33] = 1h). If DMA is used, it shall be ADMA. Only when CMD18 or CMD25 is issued. Auto CMD23 can be used with or without ADMA. By writing the 32-bit block count value for CMD23 is set to 32-bit Block Count ( (3) Auto CMD Auto Select (Version 4.10): As CMD23 is optional for SD memory card except UHS 104 card, if card supports CMD23, Auto CMD 23 should be used instead of Auto CMD12. Host Controller Version 4.10 defines this 'Auto CMD Auto Select' mode. Selection of Auto CMD depends on setting of the 0h: Auto Command Disabled 1h: Auto CMD12 Enable 2h: Auto CMD23 Enable 3h: Reserved" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 1. " BLK_CNT_ENA              ,Block Count Enable This bit is used to enable the 0h: Disable 1h: Enable" "0,1"
bitfld.word 0x00 0. "                 DMA_ENA                  ,DMA Enable DMA can be enabled only if the 0h: Disable 1h: Enable" "0,1"
group.word 0xE++0x1
line.word 0x00 "MMCSD0_COMMAND,This register is used to program the Command for host controller."
bitfld.word 0x00 8.--13. "             CMD_INDEX                ,Command Index This bit shall be set to the command number (CMD0-63, ACMD0-63)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 6.--7. "                CMD_TYPE                 ,Command Type There are three types of special commands. Suspend, Resume and Abort. These bits shall be set to 0h for all other commands. Suspend Command: Resume Command: Abort Command: 0h: Normal 1h: Suspend 2h: Resume 3h: Abort" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " DATA_PRESENT             ,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following: 0h: No Data Present 1h: Data Present" "0,1"
bitfld.word 0x00 4. "                 CMD_INDEX_CHK_ENA        ,Command Index Check Enable If this bit is set to 1h, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0h, the Index field is not checked. 0h: Disable 1h: Enable" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " CMD_CRC_CHK_ENA          ,Command CRC Check Enable If this bit is set to 1h, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0h, the CRC field is not checked. 0h: Disable 1h: Enable" "0,1"
bitfld.word 0x00 2. "                 SUB_CMD                  ,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the Host Driver manages whether main or sub command. Host Controller does not refer to this bit to issue a command. 0h: Sub Command 1h: Main Command" "0,1"
textline "                                                 "
bitfld.word 0x00 0.--1. " RESP_TYPE_SEL            ,Response Type Select 0h: No Response 1h: Response length 136 2h: Response length 48 3h: Response length 48 check Busy after response" "0,1,2,3"
group.long 0x20++0x3
line.long 0x00 "MMCSD0_DATA_PORT,This register is used to access internal buffer."
hexmask.long 0x00 0.--31. 1. "         BUF_RD_DATA              ,Buffer Data The Host Controller Buffer can be accessed through this 32-bit Data Port Register."
rgroup.long 0x24++0x3
line.long 0x00 "MMCSD0_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register."
bitfld.long 0x00 31. "         UHS2_IF_DETECTION        ,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( After UHS-II IF is detected, this bit is cleared by when EIDL is detected on D0 lane, UHS-II Interface Enable is set to 0h ( 1h: UHS-II IF is detected 0h: UHS-II IF is not detected" "0,1"
bitfld.long 0x00 30. "                 UHS2_IF_LANE_SYNC        ,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( In case of Version 4.00, this bit indicates completion of Device PHY Initialization by detecting LIDL LSS on D1 lane. From Version 4.10, Host Controller may implement a specific PHY verification method and PHY Initialization Failure can be indicated by keeping this bit to 0h even LIDL LSS is detected on D1 lane. Host Driver detects PHY Initialization Failure by timeout. This bit is cleared by when D0 lane is set to EIDL, UHS-II Interface Enable is set to 0h ( 1h: UHS-II PHY is initialized 0h: UHS-II PHY is not initialized" "0,1"
textline "                                                 "
bitfld.long 0x00 29. " UHS2_DORMANT             ,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( RCLK may be stopped in dormant state, by setting SD Clock Enable to 0h in the Clock Control register ( In case of the card enters Hibernate Mode (RCLK is stopped), Host Driver may turn off VDD1 by clearing SD Bus Power for VDD1 bit in the 1h: In DORMANT state 0h: Not in DORMANT state" "0,1"
bitfld.long 0x00 28. "                 SUB_COMMAND_STS          ,Sub Command Status The 1h: Sub Command Status 0h: Main Command Status" "0,1"
textline "                                                 "
bitfld.long 0x00 27. " CMD_NOT_ISS_BY_ERR       ,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the 1h: Command cannot be issued 0h: No error for issuing a command" "0,1"
bitfld.long 0x00 24. "                 SDIF_CMDIN               ,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors, and for debugging." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " SDIF_DAT3IN              ,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[3]. D23 - DAT[3]" "0,1"
bitfld.long 0x00 22. "                 SDIF_DAT2IN              ,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[2]. D22 - DAT[2]" "0,1"
textline "                                                 "
bitfld.long 0x00 21. " SDIF_DAT1IN              ,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[1]. D21 - DAT[1]" "0,1"
bitfld.long 0x00 20. "                 SDIF_DAT0IN              ,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D20 - DAT[0]" "0,1"
textline "                                                 "
bitfld.long 0x00 19. " WRITE_PROTECT            ,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin. 0h: Write protected (SDWP# = 1) 1h: Write enabled (SDWP# = 0)" "0,1"
bitfld.long 0x00 18. "                 CARD_DETECT              ,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin. 0h: No Card present (SDCD# = 1) 1h: Card present (SDCD# = 0)" "0,1"
textline "                                                 "
bitfld.long 0x00 17. " CARD_STATE_STABLE        ,Card State Stable This bit is used for testing. If it is 0h, the Card Detect Pin Level is not stable. If this bit is set to 1h, it means the Card Detect Pin Level is stable. The 0h: Reset of Debouncing 1h: No Card or Inserted" "0,1"
bitfld.long 0x00 16. "                 CARD_INSERTED            ,Card Inserted This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the If a Card is removed while its power is on and its clock is oscillating, the HC shall clear the 0h: Reset or Debouncing or No Card 1h: Card Inserted" "0,1"
textline "                                                 "
bitfld.long 0x00 11. " BUF_RD_ENA               ,Buffer Read Enable This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h, readable data exists in the buffer. A change of this bit from 1h to 0h occurs when all the block data is read from the buffer. A change of this bit from 0h to 1h occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0h: Read Disable 1h: Read Enable" "0,1"
bitfld.long 0x00 10. "                 BUF_WR_ENA               ,Buffer Write Enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h, data can be written to the buffer. A change of this bit from 1h to 0h occurs when all the block data is written to the buffer. A change of this bit from 0h to 1h occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt. 0h: Write Disable 1h: Write Enable" "0,1"
textline "                                                 "
bitfld.long 0x00 9. " RD_XFER_ACTIVE           ,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer. This bit is set to 1h for either of the following conditions: This bit is cleared to 0h for either of the following conditions: 1h: Transferring data 0h: No valid data" "0,1"
bitfld.long 0x00 8. "                 WR_XFER_ACTIVE           ,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active. If this bit is 0h, it means no valid write data exists in the HC. This bit is set in either of the following cases: This bit is cleared in either of the following cases: 1h: Transferring data 0h: No valid data" "0,1"
textline "                                                 "
bitfld.long 0x00 7. " SDIF_DAT7IN              ,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D07 - DAT[7]" "0,1"
bitfld.long 0x00 6. "                 SDIF_DAT6IN              ,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D06 - DAT[6]" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " SDIF_DAT5IN              ,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D05 - DAT[5]" "0,1"
bitfld.long 0x00 4. "                 SDIF_DAT4IN              ,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors, and for debugging. D04 - DAT[4]" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " RETUNING_REQ             ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting the Changing of this bit from 0h to 1h generates Re-Tuning Event. This bit isn't set to 1h if the 1h: Sampling clock needs re-tuning 0h: Fixed or well tuned sampling clock" "0,1"
bitfld.long 0x00 2. "                 DATA_LINE_ACTIVE         ,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use. 1h: DAT line active 0h: DAT line inactive" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " INHIBIT_DAT              ,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (for example R1b, R5b type). Changing from 1h to 0h generates a Transfer Complete interrupt in the 1h: Cannot issue command which uses the DAT line 0h: Can issue command which uses the DAT line" "0,1"
bitfld.long 0x00 0. "                 INHIBIT_CMD              ,Command Inhibit (CMD) 1h: Host Controller is not ready to issue a command 0h: Host Controller is ready to issue a command Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status keeps indicating 1h while any of response error statuses is set to 1h, Command Not Issued by Error in this register is set to 1h or the" "0,1"
group.byte 0x28++0x0
line.byte 0x00 "MMCSD0_HOST_CONTROL1,This register is used to program DMA modes, LED control, data transfer width, High Speed enable, card detect test level and signal selection."
bitfld.byte 0x00 7. "               CD_SIG_SEL               ,Card Detect Signal Detection This bit selects source for card detection. 1h: The card detect test level is selected 0h: SDCD# is selected (for normal use)" "0,1"
bitfld.byte 0x00 6. "                 CD_TEST_LEVEL            ,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set. 1h: Card Inserted 0h: No Card" "0,1"
textline "                                                 "
bitfld.byte 0x00 5. " EXT_DATA_WIDTH           ,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 2h in the 1h: 8-bit Bus Width 0h: Bus Width is Selected by Data Transfer Width" "0,1"
bitfld.byte 0x00 3.--4. "                 DMA_SELECT               ,DMA Select This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the (1) Up to Version 3.00: (2) Version 4.00 or later: Support of 64-bit DMA and 128-bit Descriptor is indicated by the" "0,1,2,3"
textline "                                                 "
bitfld.byte 0x00 2. " HIGH_SPEED_ENA           ,High Speed Enable (SD Mode Only) This bit is optional. Before setting this bit, the HD shall check the If the 1h: High Speed Mode 0h: Normal Speed Mode" "0,1"
bitfld.byte 0x00 1. "                 DATA_WIDTH               ,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode. 1h: 4 bit mode 0h: 1 bit mode" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " LED_CONTROL              ,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction. 1h: LED on 0h: LED off" "0,1"
group.byte 0x29++0x0
line.byte 0x00 "MMCSD0_POWER_CONTROL,This register is used to program the SD Bus power and voltage level."
bitfld.byte 0x00 5.--7. "               UHS2_VOLTAGE             ,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2. This field can be set to 5h if the 111b: Not used 110b: Not used 101b: 1.8 V 100b: Reserved for 1.2 V 011b ? 001b: Reserved 000b: VDD2 Not Supported" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 4. "                 UHS2_POWER               ,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2. 1h: Power on 0h: Power off" "0,1"
textline "                                                 "
bitfld.byte 0x00 1.--3. " SD_BUS_VOLTAGE           ,SD Bus Voltage Select for VDD1 By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the 111b: 3.3 V (Flattop.) 110b: 3.0 V (Typ.) 101b: 1.8 V (Typ.) for Embedded 100b ? 000b: Reserved" "0,1,2,3,4,5,6,7"
bitfld.byte 0x00 0. "                 SD_BUS_POWER             ,SD Bus Power for VDD1 Before setting this bit, the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared, the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state), and drive SDCLK to low level. If card is connected to Host Controller, Host Controller shall set these lines to low before stopping to supply VDD1. In UHS-II mode, before clearing this bit, Host Driver shall clear the 1h: Power on 0h: Power off" "0,1"
group.byte 0x2A++0x0
line.byte 0x00 "MMCSD0_BLOCK_GAP_CONTROL,This register is used to program the block gap request, read wait control and interrupt at block gap."
bitfld.byte 0x00 7. "               BOOT_ACK_ENA             ,Boot Acknowledge Check To check for the boot acknowledge in boot operation. 1h: Wait for boot ack from eMMC card 0h: Will not wait for boot ack from eMMC card" "0,1"
bitfld.byte 0x00 6. "                 ALT_BOOT_MODE            ,Alternative Boot Mode To start boot code access in alternative mode. 1h: To start alternate boot mode access 0h: To stop alternate boot mode access" "0,1"
textline "                                                 "
bitfld.byte 0x00 5. " BOOT_ENABLE              ,Boot Enable To start boot code access. 1h: To start boot code access 0h: To stop boot code access" "0,1"
bitfld.byte 0x00 3. "                 INTRPT_AT_BLK_GAP        ,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0h. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card." "0,1"
textline "                                                 "
bitfld.byte 0x00 2. " RDWAIT_CTRL              ,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1h otherwise DAT line conflict may occur. If this bit is set to 0h, Suspend/Resume cannot be supported. In UHS-II mode, Read Wait is disabled and DAT[2] line is used for Interrupt Signal from UHS-II Card. 1h: Enable Read Wait Control 0h: Disable Read Wait Control" "0,1"
bitfld.byte 0x00 1. "                 CONTINUE                 ,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0h ( The Host Controller automatically clears this bit when the transaction re-starts. If In SD mode, this bit is cleared in either of the following cases: Therefore it is not necessary for Host driver to set this bit to 0h. If 1h: Restart 0h: Ignored" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " STOP_AT_BLK_GAP          ,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA, SDMA and ADMA transfers. Until the transfer complete is set to 1h, indicating a transfer completion the HD shall leave this bit set to 1h. Clearing both the In case of UHS-II, a transaction can be stopped at the boundary of DATA Burst (Flow Control basis). Host Controller waits for sending Flow Control MSG until the 1h: Stop 0h: Transfer" "0,1"
group.byte 0x2B++0x0
line.byte 0x00 "MMCSD0_WAKEUP_CONTROL,This register is used to program the wakeup functionality. The register is mandatory for the HC, but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus, by setting the [0] SD_BUS_POWER bit to 1h, when wakeup event via card interrupt is desired."
bitfld.byte 0x00 2. "               CARD_REMOVAL             ,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1"
bitfld.byte 0x00 1. "                 CARD_INSERTION           ,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " CARD_INTERRUPT           ,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h. 1h: Enable 0h: Disable" "0,1"
group.word 0x2C++0x1
line.word 0x00 "MMCSD0_CLOCK_CONTROL,This register is used to program the Clock frequency select, Clock generator select, Clock enable, Internal clock state fields. At the initialization of the HC, the HD shall set the SDCLK Frequency Select ([15-8] SDCLK_FRQSEL) according to the register. This register controls SDCLK in SD Mode and RCLK in UHS-II mode."
hexmask.word.byte 0x00 8.--15. 1. "             SDCLK_FRQSEL             ,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities register ( Only the following settings are allowed. (1) 8-bit Divided Clock Mode: Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The three default divider values can be calculated by the frequency that is defined by the 400 KHz divider value 25 MHz divider value 50 MHz divider value According to the Physical Layer Specification, the maximum SD Clock frequency is 25 MHz in normal speed mode and 50 MHz in high speed mode, and shall never exceed this limit. The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) / divisor Thus, choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency. For example, if the (2) 10-bit Divided Clock Mode: (3) Programmable Clock Mode: This field depends on setting of the If If"
bitfld.word 0x00 6.--7. "                SDCLK_FRQSEL_UPBITS      ,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to the" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " CLKGEN_SEL               ,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h: Programmable Clock Mode 0h: Divided Clock Mode" "0,1"
bitfld.word 0x00 3. "                 PLL_ENA                  ,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable ( (1) When (2) When 1h: PLL is enabled 0h: PLL is in low power mode" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " SD_CLK_ENA               ,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h. The 1h: Enable providing SDCLK or RCLK 0h: Disable providing SDCLK or RCLK" "0,1"
bitfld.word 0x00 1. "                 INT_CLK_STABLE           ,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller which supports PLL Enable sets this status to 0h once when PLL Enable is changed 0h to 1h and then this status is set to 1h when PLL is locked (PLL uses an internal clock in stable as a reference clock which is enabled by the 1h: Ready 0h: Not Ready" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " INT_CLK_ENA              ,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1h. When clock oscillation is stable, the HC shall set the 1h: Oscillate 0h: Stop" "0,1"
group.byte 0x2E++0x0
line.byte 0x00 "MMCSD0_TIMEOUT_CONTROL,The register sets the data timeout counter value. At the initialization of the HC, the HD shall set the Data Timeout Counter Value according to the register."
bitfld.byte 0x00 0.--3. "               COUNTER_VALUE            ,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected. Refer to the 1111: Reserved 1110: TMCLK ? 2 -------------------- -------------------- 0001: TMCLK ? 2 0000: TMCLK ? 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x2F++0x0
line.byte 0x00 "MMCSD0_SOFTWARE_RESET,This register is used to program the software reset for data, command and for all. A reset pulse is generated when writing 1h to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0h."
bitfld.byte 0x00 2. "               SWRST_FOR_DAT            ,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset. The following registers and bits are cleared by this bit: 1h: Reset 0h: Work" "0,1"
bitfld.byte 0x00 1. "                 SWRST_FOR_CMD            ,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command. From Version 4.10, this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit (including response error statuses related to Command Inhibit (CMD) control - The following registers and bits are cleared by this bit: Response error statuses related to Command Inhibit (CMD) - 1h: Reset 0h: Work" "0,1"
textline "                                                 "
bitfld.byte 0x00 0. " SWRST_FOR_ALL            ,Software Reset for All This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0h. During its initialization, the HD shall set this bit to 1h to reset the HC. The HC shall reset this bit to 0h when Capabilities registers are valid and the HD can read them. Additional use of 'Software Reset For All' may not affect the value of the Capabilities registers. If this bit is set to 1h, the SD card shall reset itself and must be re-initialized by the HD. 1h: Reset 0h: Work" "0,1"
hgroup.word 0x30++0x1
hide.word 0x00 "MMCSD0_NORMAL_INTR_STS,This register gives the status of all the interrupts. The Normal Interrupt Signal Enable (see register) affects read of this register, but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1h. For all bits except Card Interrupt ([8] CARD_INTR) and Error Interrupt ([15] ERROR_INTR), writing 1h to a bit clears it. The [8] CARD_INTR bit is cleared when the card stops asserting the interrupt: that is when the Card Driver services the Interrupt condition."
in
textline "                                                 "
hgroup.word 0x32++0x1
hide.word 0x00 "MMCSD0_ERROR_INTR_STS,This register gives the status of the error interrupts. Status defined in this register can be enabled by the register, but not by the register. The Interrupt is generated when the register is enabled and at least one of the statuses is set to 1h. Writing to 1h clears the bit and writing to 0h keeps the bit unchanged. More than one status can be cleared at the one register write."
in
textline "                                                 "
group.word 0x34++0x1
line.word 0x00 "MMCSD0_NORMAL_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.word 0x00 15. "             BIT15_FIXED0             ,Fixed to 0 The HC shall control error Interrupts using the" "0,1"
bitfld.word 0x00 14. "                 BOOT_COMPLETE            ,Boot Terminate Interrupt Enable 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 13. " RCV_BOOT_ACK             ,Boot Acknowledge Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 12. "                 RETUNING_EVENT           ,Re-Tuning Event Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " INTC                     ,INT_C Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts." "0,1"
bitfld.word 0x00 10. "                 INTB                     ,INT_B Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts." "0,1"
textline "                                                 "
bitfld.word 0x00 9. " INTA                     ,INT_A Status Enable (Embedded) If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts." "0,1"
bitfld.word 0x00 8. "                 CARD_INTERRUPT           ,Card Interrupt Status Enable If this bit is set to 0h, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the By setting this bit to 0h, interrupt input should be masked by implementation so that the interrupt Input is not affected by external signal in any state (for example: floating). 0h: Masked 1h: Enabled" "0,1"
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bitfld.word 0x00 7. " CARD_REMOVAL             ,Card Removal Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 6. "                 CARD_INSERTION           ,Card Insertion Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 5. " BUF_RD_READY             ,Buffer Read Ready Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 4. "                 BUF_WR_READY             ,Buffer Write Ready Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " DMA_INTERRUPT            ,DMA Interrupt Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 2. "                 BLK_GAP_EVENT            ,Block Gap Event Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " XFER_COMPLETE            ,Transfer Complete Status Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 0. "                 CMD_COMPLETE             ,Command Complete Status Enable 0h: Masked 1h: Enabled" "0,1"
group.word 0x36++0x1
line.word 0x00 "MMCSD0_ERROR_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.word 0x00 12.--15. "             VENDOR_SPECIFIC          ,Vendor Specific Error Status Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Response Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Tuning Error Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,ADMA Error Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Auto CMD Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 7. "                 CURR_LIMIT               ,Current Limit Error Status Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DATA_ENDBIT              ,Data End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 5. "                 DATA_CRC                 ,Data CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_TIMEOUT             ,Data Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Command Index Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Command End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Command CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Command Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
group.word 0x38++0x1
line.word 0x00 "MMCSD0_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation."
bitfld.word 0x00 15. "             BIT15_FIXED0             ,Fixed to 0 The HD shall control error Interrupts using the" "0,1"
bitfld.word 0x00 14. "                 BOOT_COMPLETE            ,Boot Terminate Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 13. " RCV_BOOT_ACK             ,Boot Acknowledge Receive Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 12. "                 RETUNING_EVENT           ,Re-Tuning Event Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " INTC                     ,INT_C Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 10. "                 INTB                     ,INT_B Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 9. " INTA                     ,INT_A Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 8. "                 CARD_INTERRUPT           ,Card Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 7. " CARD_REMOVAL             ,Card Removal Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 6. "                 CARD_INSERTION           ,Card Insertion Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 5. " BUF_RD_READY             ,Buffer Read Ready Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 4. "                 BUF_WR_READY             ,Buffer Write Ready Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " DMA_INTERRUPT            ,DMA Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 2. "                 BLK_GAP_EVENT            ,Block Gap Event Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " XFER_COMPLETE            ,Transfer Complete Signal Enable 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 0. "                 CMD_COMPLETE             ,Command Complete Signal Enable 0h: Masked 1h: Enabled" "0,1"
group.word 0x3A++0x1
line.word 0x00 "MMCSD0_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation."
bitfld.word 0x00 12.--15. "             VENDOR_SPECIFIC          ,Vendor Specific Error Signal Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Response Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Tuning Error Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,ADMA Error Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Auto CMD Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 7. "                 CURR_LIMIT               ,Current Limit Error Signal Enable 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DATA_ENDBIT              ,Data End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 5. "                 DATA_CRC                 ,Data CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_TIMEOUT             ,Data Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Command Index Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Command End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Command CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Command Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1"
rgroup.word 0x3C++0x1
line.word 0x00 "MMCSD0_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01. This register is valid only when the Auto CMD Error is set."
bitfld.word 0x00 7. "             CMD_NOT_ISSUED           ,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: No Error 1h: Not Issued" "0,1"
bitfld.word 0x00 4. "                 INDEX                    ,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command. 0h: No Error 1h: Error" "0,1"
textline "                                                 "
bitfld.word 0x00 3. " ENDBIT                   ,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h. 0h: No Error 1h: End Bit Error Generated" "0,1"
bitfld.word 0x00 2. "                 CRC                      ,Auto CMD CRC Error Occurs when detecting a CRC error in the command response. 0h: No Error 1h: CRC Error Generated" "0,1"
textline "                                                 "
bitfld.word 0x00 1. " TIMEOUT                  ,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1h, the other error status bits (D04 - D02) are meaningless. 0h: No Error 1h: Timeout" "0,1"
bitfld.word 0x00 0. "                 ACMD12_NOT_EXEC          ,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1h, other error status bits (D04 - D01) are meaningless. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: Executed 1h: Not Executed" "0,1"
group.word 0x3E++0x1
line.word 0x00 "MMCSD0_HOST_CONTROL2,This register is used to program UHS Mode Select, Driver Strength Select, Execute Tuning, Sampling Clock Select, Asynchronous Interrupt Enable and Preset Value Enable."
bitfld.word 0x00 15. "             PRESET_VALUE_ENA         ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When the If this bit is set to 0h, SDCLK Frequency Select, Clock Generator Select in the If this bit is set to 1h, SDCLK Frequency Select, Clock Generator Select in the 0h: SDCLK and Driver Strength are controlled by Host Driver 1h: Automatic Selection by Preset Value are Enabled" "0,1"
bitfld.word 0x00 14. "                 ASYNCH_INTR_ENA          ,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and the 0h: Disabled 1h: Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 13. " BIT64_ADDRESSING         ,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets this bit depends on addressing mode of installed OS. Refer to 64-bit System Address Support in the 0h: 32-bits Addressing 1h: 64-bits Addressing" "0,1"
bitfld.word 0x00 12. "                 HOST_VER40_ENA           ,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00, support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version 4.10, supported 32-bit Block Count for all operations. Functions of following fields are modified. SDMA uses the ADMA3 is selected by 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1h. Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register instead of SDMA System Address register ( 0h: Version 3.00 Compatible Mode 1h: Version 4.Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 11. " CMD23_ENA                ,CMD23 Enable In memory card initialization, Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h), this bit is set to 1h. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 datatransfer. Refer to" "0,1"
bitfld.word 0x00 10. "                 ADMA2_LEN_MODE           ,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit. 0h: 16-bit Data Length Mode 1h: 26-bit Data Length Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 9. " DRIVER_STRENGTH2         ,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value." "0,1"
bitfld.word 0x00 8. "                 UHS2_INTF_ENABLE         ,UHS-II Interface Enable This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization, this bit shall be set to 1h. Before trying to start SD mode initialization, this bit shall be set to 0h. This bit is used to enable UHS-II IF Detection, Lane Synchronization and In Dormant State in the Host Controller shall not leave unused SD 4-bit Interface lines (CLK, CMD and DAT[3:2]) floating in UHS-II mode by using pull-up or driving to low. When DAT[2] is used as interrupt input in UHS-II mode, DAT[2] of Host Controller is set to input and then DAT[2] of SDIO card is set to output to avoid conflict. 0h: 4-bit SD Interface Enabled 1h: UHS-II Interface Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 7. " SAMPLING_CLK_SELECT      ,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when the 0h: Fixed clock is used to sample data 1h: Tuned clock is used to sample data" "0,1"
bitfld.word 0x00 6. "                 EXECUTE_TUNING           ,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the 0h: Not Tuned or Tuning Completed 1h: Execute Tuning" "0,1"
textline "                                                 "
bitfld.word 0x00 4.--5. " DRIVER_STRENGTH1         ,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the If If 0h: Driver Type B is Selected (Default) 1h: Driver Type A is Selected 2h: Driver Type C is Selected 3h: Driver Type D is Selected" "0,1,2,3"
bitfld.word 0x00 3. "                 V1P8_SIGNAL_ENA          ,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage. Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V. 1.8 V regulator output shall be stable within 5 ms. Host Controller clears this bit if switching to 1.8 V signaling fails. Clearing this bit from 1h to 0h starts changing signal voltage from 1.8 V to 3.3 V. 3.3 V regulator output shall be stable within 5 ms. Host Driver can set this bit to 1h when Host Controller supports 1.8 V signaling (one of support bits is set to 1h: SDR50, SDR104 or DDR50 in the 0h: 3.3 V Signaling 1h: 1.8 V Signaling" "0,1"
textline "                                                 "
bitfld.word 0x00 0.--2. " UHS_MODE_SELECT          ,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode, this field is effective when the If the 0h: SDR12 1h: SDR25 2h: SDR50 3h: SDR104 4h: DDR50 5h: HS400 6h: Reserved 7h: UHS-II When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more details." "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x7
line.quad 0x00 "MMCSD0_CAPABILITIES,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization."
bitfld.quad 0x00 63. " HS400_SUPPORT            ,HS400 Support 0h: HS400 is Not Supported 1h: HS400 is Supported" "0,1"
bitfld.quad 0x00 60. "                 VDD2_1P8_SUPPORT         ,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system. 0h: 1.8 V VDD2 is not supported 1h: 1.8 V VDD2 is supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 59. " ADMA3_SUPPORT            ,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller. 0h: ADMA3 is not supported 1h: ADMA3 is supported" "0,1"
bitfld.quad 0x00 57. "                 SPI_BLK_MODE             ,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 56. " SPI_SUPPORT              ,SPI Mode This bit indicates whether SPI Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1"
hexmask.quad.byte 0x00 48.--55. 1. "                 CLOCK_MULTIPLIER         ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to the FFh: Clock Multiplier M = 256 ---- 02h: Clock Multiplier M = 3 01h: Clock Multiplier M = 2 00h: Clock Multiplier is Not Supported"
textline "                                                 "
bitfld.quad 0x00 46.--47. " RETUNING_MODES           ,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. 0h: Mode 1 1h: Mode 2 2h: Mode 3 3h: Reserved There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue." "0,1,2,3"
bitfld.quad 0x00 45. "                 TUNING_FOR_SDR50         ,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h, this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104). 0h: SDR50 does not require tuning 1h: SDR50 requires tuning" "0,1"
textline "                                                 "
bitfld.quad 0x00 40.--43. " RETUNING_TIMER_CNT       ,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ---- n = 2 ---- Bh = 1024 seconds Fh - Ch = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 38. "                DRIVERD_SUPPORT          ,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling. 0h: Driver Type D is Not Supported 1h: Driver Type D is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 37. " DRIVERC_SUPPORT          ,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling. 0h: Driver Type C is Not Supported 1h: Driver Type C is Supported" "0,1"
bitfld.quad 0x00 36. "                 DRIVERA_SUPPORT          ,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling. 0h: Driver Type A is Not Supported 1h: Driver Type A is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 35. " UHS2_SUPPORT             ,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h, the 0h: UHS-II is Not Supported 1h: UHS-II is Supported" "0,1"
bitfld.quad 0x00 34. "                 DDR50_SUPPORT            ,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not. 0h: DDR50 is Not Supported 1h: DDR50 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 33. " SDR104_SUPPORT           ,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not. SDR104 requires tuning. 0h: SDR104 is Not Supported 1h: SDR104 is Supported" "0,1"
bitfld.quad 0x00 32. "                 SDR50_SUPPORT            ,SDR50 Support (UHS-I Only) If SDR104 is supported, this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not. 0h: SDR50 is Not Supported 1h: SDR50 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 30.--31. " SLOT_TYPE                ,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (2h) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (2h), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System. 0h: Removable Card Slot 1h: Embedded Slot for One Device 2h: Shared Bus Slot (SD Mode) 3h: UHS-II Multiple Embedded Devices" "0,1,2,3"
bitfld.quad 0x00 29. "                 ASYNCH_INTR_SUPPORT      ,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 0h: Asynchronous Interrupt Not Supported 1h: Asynchronous Interrupt Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 28. " ADDR_64BIT_SUPPORT_V3    ,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses this bit as 64-bit System Address support for both V3 and V4 modes. SDMA cannot be used in 64-bit Addressing in Version 3 mode. If this bit is set to 1h, 64-bit ADMA2 with using 96-bit Descriptor may be enabled as follows: In case of Host Controller Version 3, 64-bit ADMA2 is enabled by 0h: 64-bit System Address for V3 is not Supported 1h: 64-bit System Address for V3 is Supported" "0,1"
bitfld.quad 0x00 27. "                 ADDR_64BIT_SUPPORT_V4    ,64-bit System Address Support for V4 This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode. When this bit is set to 1h, full or a part of 64-bit address should be used to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the If this bit is set to 1h, 64-bit DMA Addressing for Version 4 is enabled by setting 0h: 64-bit System Address for V4 is not Supported 1h: 64-bit System Address for V4 is Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 26. " VOLT_1P8_SUPPORT         ,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V. 0h: 1.8 V Not Supported 1h: 1.8 V Supported" "0,1"
bitfld.quad 0x00 25. "                 VOLT_3P0_SUPPORT         ,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V. 0h: 3.0 V Not Supported 1h: 3.0 V Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 24. " VOLT_3P3_SUPPORT         ,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V. 0h: 3.3 V Not Supported 1h: 3.3 V Supported" "0,1"
bitfld.quad 0x00 23. "                 SUSP_RES_SUPPORT         ,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands. 0h: Not Supported 1h: Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 22. " SDMA_SUPPORT             ,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. Version 4.10 Host Controller shall support SDMA if ADMA2 is supported. 0h: SDMA Not Supported 1h: SDMA Supported" "0,1"
bitfld.quad 0x00 21. "                 HIGH_SPEED_SUPPORT       ,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC). 0h: High Speed Not Supported 1h: High Speed Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 19. " ADMA2_SUPPORT            ,ADMA2 Support 0h: ADMA2 Not support 1h: ADMA2 support" "0,1"
bitfld.quad 0x00 18. "                 BUS_8BIT_SUPPORT         ,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the 0h: 8-bit Bus Width Not Supported 1h: 8-bit Bus Width Supported" "0,1"
textline "                                                 "
bitfld.quad 0x00 16.--17. " MAX_BLK_LENGTH           ,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 0h: 512 byte 1h: 1024 byte 2h: 2048 byte 3h: 4096 byte" "0,1,2,3"
hexmask.quad.byte 0x00 8.--15. 1. "                 BASE_CLK_FREQ            ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. 11xx xxxxb: Not Supported 0011 1111b: 63 MHz 0000 0010b: 2 MHz 0000 0001b: 1 MHz 0000 0000b: Get Information via another method (2) 8-bit Base Clock Frequency: This mode is supported by the Host Controller Version 3.00. Unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. FFh: 255 MHz 02h: 2 MHz 01h: 1 MHz 00h: Get Information via another method If the real frequency is 16.5 MHz, the lager value shall be set 0001 0001b (17 MHz) because the Host Driver use this value to calculate the clock divider value (refer to the"
textline "                                                 "
bitfld.quad 0x00 7. " TIMEOUT_CLK_UNIT         ,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "0,1"
bitfld.quad 0x00 0.--5. "                 TIMEOUT_CLK_FREQ         ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.quad 0x48++0x7
line.quad 0x00 "MMCSD0_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage."
hexmask.quad.byte 0x00 32.--39. 1. " VDD2_1P8V                ,Maximum Current for 1.8 V VDD2"
hexmask.quad.byte 0x00 16.--23. 1. "                VDD1_1P8V                ,Maximum Current for 1.8 V VDD1"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " VDD1_3P0V                ,Maximum Current for 3.0 V VDD1"
hexmask.quad.byte 0x00 0.--7. 1. "                VDD1_3P3V                ,Maximum Current for 3.3 V VDD1"
wgroup.word 0x50++0x1
line.word 0x00 "MMCSD0_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented, rather it is an address where the register can be written. Writing 1h: set each bit of the register Writing 0h: no effect By setting a bit in this register, the correspondent bit is set in the"
bitfld.word 0x00 7. "             CMD_NOT_ISS              ,Force Event for Command Not Issued by AUTO CMD12 Error 0h: Not Affected 1h: Command Not Issued By Auto CMD12 Error Status is set" "0,1"
bitfld.word 0x00 5. "                 RESP                     ,Force Event for AUTO CMD Response Error 0h: Not Affected 1h: Auto CMD Response Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " INDEX                    ,Force Event for AUTO CMD Index Error 0h: Not Affected 1h: Auto CMD Index Error Status is set" "0,1"
bitfld.word 0x00 3. "                 ENDBIT                   ,Force Event for AUTO CMD End Bit Error 0h: Not Affected 1h: Auto CMD End bit Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CRC                      ,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD CRC Error Status is set" "0,1"
bitfld.word 0x00 1. "                 TIMEOUT                  ,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD Timeout Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " ACMD_NOT_EXEC            ,Force Event for AUTO CMD12 Not Executed 0h: Not Affected 1h: Auto CMD12 Not Executed Status is set" "0,1"
wgroup.word 0x52++0x1
line.word 0x00 "MMCSD0_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented, rather it is an address where the register can be written. The register is not a physically implemented register. Rather, it is an address at which the register can be written. The effect of a write to this address will be reflected in the register if the corresponding bit of the register is set. Writing 1h: set each bit of the register Writing 0h: no effect"
bitfld.word 0x00 12.--15. "             VEND_SPEC                ,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. "                RESP                     ,Force Event for Response Error 0h: Not Affected 1h: Response Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 10. " TUNING                   ,Force Event for Tuning Error 0h: Not Affected 1h: Tuning Error Status is set" "0,1"
bitfld.word 0x00 9. "                 ADMA                     ,Force Event for ADMA Error 0h: Not Affected 1h: ADMA Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " AUTO_CMD                 ,Force Event for Auto CMD Error 0h: Not Affected 1h: Auto CMD Error Status is set" "0,1"
bitfld.word 0x00 7. "                 CURR_LIM                 ,Force Event for Current Limit Error 0h: Not Affected 1h: Current Limit Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " DAT_ENDBIT               ,Force Event for Data End Bit Error 0h: Not Affected 1h: Data End Bit Error Status is set" "0,1"
bitfld.word 0x00 5. "                 DAT_CRC                  ,Force Event for Data CRC Error 0h: Not Affected 1h: CRC Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DAT_TIMEOUT              ,Force Event for Data Timeout Error 0h: Not Affected 1h: Timeout Error Status is set" "0,1"
bitfld.word 0x00 3. "                 CMD_INDEX                ,Force Event for Command Index Error 0h: Not Affected 1h: Command Index Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 2. " CMD_ENDBIT               ,Force Event for Command End Bit Error 0h: Not Affected 1h: Command End Bit Error Status is set" "0,1"
bitfld.word 0x00 1. "                 CMD_CRC                  ,Force Event for Command CRC Error 0h: Not Affected 1h: Command CRC Error Status is set" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " CMD_TIMEOUT              ,Force Event for CMD Timeout Error 0h: Not Affected 1h: Command Timeout Error Status is set" "0,1"
rgroup.byte 0x54++0x0
line.byte 0x00 "MMCSD0_ADMA_ERR_STATUS,When the ADMA Error interrupt occur, this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor."
bitfld.byte 0x00 2. "               ADMA_LENGTH_ERR          ,ADMA Length Mismatch Error This error occurs in the following 2 cases. While the 0h: No Error 1h: Error" "0,1"
bitfld.byte 0x00 0.--1. "                 ADMA_ERR_STATE           ,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '2h' because ADMA never stops in this state. D01 - D00: ADMA Error State when error occurred Contents of SYS_SDR register 0h: ST_STOP (Stop DMA) Points to next of the error descriptor 1h: ST_FDS (Fetch Descriptor) Points to the error descriptor 2h: Never set this state (Not used) 3h: ST_TFR (Transfer Data) Points to the next of the error descriptor" "0,1,2,3"
group.quad 0x58++0x7
line.quad 0x00 "MMCSD0_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer."
hexmask.quad 0x00 0.--63. 1. " ADMA_ADDR                ,ADMA System Address The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this register and assumes it to be 0h. DMA in 64-bit addressing. The 64-bit addressing Host Driver uses all bits of this register and shall program Descriptor Table on 64-bit boundary and set 64-bit boundary address to this register. DMA2/3 ignores lower 3-bit of this register andassumes it to be 0h. If the This register holds byte address of executing command of the Descriptor table. At the start of ADMA2, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. This register is set by ADMA3. Host Driver is not necessary to set this register. The ADMA3 increments address of this register, which points to next line, when every time fetching a Descriptor line. When Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state. Register Value - Addressing Mode - 32-bit System Address Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address"
rgroup.word 0x60++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value. When the [15] PRESET_VALUE_ENA bit is set to 1h, SDCLK/RCLK Frequency Select and Clock Generator Select in the register, and Driver Strength Select in the register are automatically set based on the Selected Bus Speed Mode (see ). This means the Host Driver needs not set these fields when preset is enabled. Before starting the initialization sequence, the Host Driver needs to set a clock preset value to SDCLK/RCLK Frequency Select in the register. The [15] PRESET_VALUE_ENA bit can be set after initialization completed. shows the conditions to select one of preset value registers."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x62++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE1,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x64++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE2,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x66++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE3,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x68++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE4,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6A++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE5,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6C++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE6,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x6E++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE7,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x72++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE8,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
rgroup.word 0x74++0x1
line.word 0x00 "MMCSD0_PRESET_VALUE10,This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value."
bitfld.word 0x00 14.--15. "             DRIVER_STRENGTH_SEL      ,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is Selected 3h: Driver Type B is Selected" "0,1,2,3"
bitfld.word 0x00 10. "                 CLOCK_GENSEL             ,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1"
textline "                                                 "
hexmask.word 0x00 0.--9. 1. " SDCLK_FRQSEL             ,SDCLK Frequency Select Value 10-bit preset value to set the"
group.quad 0x78++0x7
line.quad 0x00 "MMCSD0_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register."
hexmask.quad 0x00 0.--63. 1. " INTG_DESC_ADDR           ,ADMA3 Integrated Descriptor Address The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the next Descriptor address. The 32-bit addressing Host Driver uses lower 32-bit of this register and shall program Descriptor Table on 32-bit boundary. ADMA3 ignores lower 2-bit of this register and assumes it to be 0h. Writing to 07Bh starts ADMA3 data transfer. The 64-bit addressing Host Driver uses all 64-bit of this register and shall program Descriptor Table on 64-bit boundary. ADMA3 ignores lower 3-bit of this register and assumes it to be 0h. Writing to 07Fh starts ADMA3 data transfer. Register Value - Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address"
group.word 0x80++0x1
line.word 0x00 "MMCSD0_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block."
bitfld.word 0x00 12.--14. "             SDMA_BUF_BOUNDARY        ,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging, SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and requests the Host Driver to update the At the end of transfer, the Host Controller may issue or may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer Complete Interrupt is issued (see These bits shall be supported when the 0h: 4K bytes (Detects A11 carry out) 1h: 8K bytes (Detects A12 carry out) 2h: 16K Bytes (Detects A13 carry out) 3h: 32K Bytes (Detects A14 carry out) 4h: 64K bytes (Detects A15 carry out) 5h: 128K Bytes (Detects A16 carry out) 6h: 256K Bytes (Detects A17 carry out) 7h: 512K Bytes (Detects A18 carry out)" "0,1,2,3,4,5,6,7"
hexmask.word 0x00 0.--11. 1. "                 XFER_BLK_SIZE            ,UHS-II Block Size This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This bit field is effective when the 0000h - No data transfer 0001h - 1 Byte 0002h - 2 Bytes 0003h - 3 Bytes ... ... 01FFh - 511 Bytes 0200h - 512 Bytes ... ... 0800h - 2048 Bytes"
group.long 0x84++0x3
line.long 0x00 "MMCSD0_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks."
hexmask.long 0x00 0.--31. 1. "         XFER_BLK_COUNT           ,UHS-II Block Count This register is effective when the This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored. 00000000h: Stop Count 00000001h: 1 block 00000002h: 2 blocks ... ... FFFFFFFFh: 4G blocks - 1"
group.word 0x9C++0x1
line.word 0x00 "MMCSD0_UHS2_XFER_MODE,This register is used to control the operations of data transfers. On issuing a Command Packet, a Command Packet image is set to UHS-II Command Packet register (see - ) but Host Controller does not analyze the setting of UHS-II Command Packet register. Instead, Host Controller refers setting of this register to issue a Command Packet to make the control easy. Setting of these registers shall be correspondent."
bitfld.word 0x00 15. "             DUPLEX_SELECT            ,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver. 0h: Full Duplex Mode 1h: 2 Lane Half Duplex Mode" "0,1"
bitfld.word 0x00 14. "                 EBSY_WAIT                ,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer. If this bit is set to 1h, Host Controller waits receiving of EBSY packet and on receiving EBSY packet, the Setting of the 0h: Issue a command without busy 1h: Wait EBSY" "0,1"
textline "                                                 "
bitfld.word 0x00 8. " RESP_INTR_DIS            ,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits the 0h: Response Interrupt is enabled 1h: Response Interrupt is disabled" "0,1"
bitfld.word 0x00 7. "                 RESP_ERR_CHK_ENA         ,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, this bit is set to 0h and the 0h: Response Error Check is disabled 1h: Response Error Check is enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 6. " RESP_TYPE                ,Response Type R1/R5 When response error check is enabled, this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1"
bitfld.word 0x00 5. "                 BYTE_MODE                ,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when the 0h: Block Mode 1h: Byte Mode" "0,1"
textline "                                                 "
bitfld.word 0x00 4. " DATA_XFER_DIR            ,Data Transfer Direction This bit specifies direction of data transfer when the 0h: Read (Card to Host) 1h: Write (Host to Card)" "0,1"
bitfld.word 0x00 1. "                 BLK_CNT_ENA              ,Block Count Enable This bit specifies whether data transfer uses the 0h: Block Count Disabled 1h: Block Count Enabled" "0,1"
textline "                                                 "
bitfld.word 0x00 0. " DMA_ENA                  ,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the 0h: DMA is disabled 1h: DMA is enabled" "0,1"
group.word 0x9E++0x1
line.word 0x00 "MMCSD0_UHS2_COMMAND,This register is used to program the Command for host controller."
bitfld.word 0x00 8.--12. "             PKT_LENGTH               ,UHS-II Command Packet Length A command packet length, which is set in the UHS-II Command Packet register ( 00011b ? 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b ? 10101b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 6.--7. "                CMD_TYPE                 ,Command Type This field is used to distinguish a specific command like abort command. If this field is set to 0h, the UHS-II RES Packet is stored in UHS-II Response register ( 0h: Normal Command 1h: TRANS_ABORT CCMD 3h: CMD12 or SDIO Abort command 4h: Go Dormant Command" "0,1,2,3"
textline "                                                 "
bitfld.word 0x00 5. " DATA_PRESENT             ,Data Present This bit specifies whether the command is accompanied by data packet. 0h: No Data Present 1h: Data Present" "0,1"
bitfld.word 0x00 2. "                 SUB_COMMAND              ,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the 0h: Sub Command 1h: Main Command" "0,1"
group.byte 0xB4++0x0
line.byte 0x00 "MMCSD0_UHS2_MESSAGE_SELECT,This register is used to access internal buffer."
bitfld.byte 0x00 0.--1. "               MSG_SEL                  ,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the (assumed for debug usage). 0h: The latest MSG 1h: One MSG before 2h: Two MSGs before 3h: Three MSGs before" "0,1,2,3"
rgroup.long 0xB8++0x3
line.long 0x00 "MMCSD0_UHS2_MESSAGE,This register is used to access internal buffer."
hexmask.long.byte 0x00 24.--31. 1. "         MSG_BYTE3                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hexmask.long.byte 0x00 16.--23. 1. "                MSG_BYTE2                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " MSG_BYTE1                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hexmask.long.byte 0x00 0.--7. 1. "                MSG_BYTE0                ,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the"
hgroup.word 0xBC++0x1
hide.word 0x00 "MMCSD0_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device."
in
textline "                                                 "
group.byte 0xBE++0x0
line.byte 0x00 "MMCSD0_UHS2_DEVICE_SELECT,UHS-II Device Select Register."
bitfld.byte 0x00 7. "               INT_MSG_ENA              ,INT MSG Enable (Optional) This bit enables receipt of INT MSG. If this bit is set to 1h, receipt of INT MSG is informed by the Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0, INT MSG Interrupt is not supported by the Host Controller. In this case, the 0h: Disabled 1h: Enabled" "0,1"
bitfld.byte 0x00 0.--3. "                 DEV_SEL                  ,UHS-II Device Select Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the The number of devices implemented in the Host Controller is indicated by the 0h: Unselected (Default) 1h: INT MSG of Device ID 1 is selected 2h: INT MSG of Device ID 2 is selected ..... ..... Fh: INT MSG of Device ID 15 is selected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xBF++0x0
line.byte 0x00 "MMCSD0_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h."
hexmask.byte 0x00 0.--7. 1. "               DEV_INTR                 ,UHS II Device Interrupt This register is effective when the The number of the registers to hold INT MSGs is determined by the"
group.word 0xC0++0x1
line.word 0x00 "MMCSD0_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register."
bitfld.word 0x00 1. "             HOST_SDTRAN_RESET        ,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued, SD-TRAN Initialization sequence from CMD8 is required to use UHS-II mode. Assuming that bus power is maintained and CM-TRAN Initialization is not required. Host Controller requires to do followings: (1) SD Clock Enable is maintained (continue to provide RCLK). (2) All setting register is maintained. (3) Internal sequencers are reset to just after power on be able to issue a command. (4) All Interrupt Status, Status Enable and Signal Enable are cleared. (5) Data transfer is terminated and data in buffer is discarded. 0h: Not Affected 1h: Reset SD-TRAN" "0,1"
bitfld.word 0x00 0. "                 HOST_FULL_RESET          ,Host Full Reset On issuing FULL_RESET CCMD, Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to use UHS-II mode. Assuming that bus power is maintained. Host Controller requires to do followings: (1) SD Clock Enable is cleared (internal Clock is still synchronized). (2) All setting register is cleared. (3) Internal sequencers are reset to just after power on. (4) All Interrupt Status, Status Enable and Signal Enable are cleared. 0h: Not Affected 1h: Reset Host Controller" "0,1"
group.word 0xC2++0x1
line.word 0x00 "MMCSD0_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register."
bitfld.word 0x00 4.--7. "             DEADLOCK_TIMEOUT_CTR     ,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for Deadlock (in the Fh: Reserved Eh: TMCLK x 2 .... .... 1h: TMCLK x 2 0h: TMCLK x 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "                CMDRESP_TIMEOUT_CTR      ,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for CMD_RES (in the Fh: Reserved Eh: TMCLK x 2 .... .... 1h: TMCLK x 2 0h: TMCLK x 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xC4++0x3
hide.long 0x00 "MMCSD0_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts."
in
textline "                                                 "
group.long 0xC8++0x3
line.long 0x00 "MMCSD0_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields."
bitfld.long 0x00 27.--31. "         VENDOR_SPECFIC           ,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                DEADLOCK_TIMEOUT         ,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " CMD_RESP_TIMEOUT         ,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 15. "                 ADMA2_ADMA3              ,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,TID Error Setting this bit to 1h enables setting of TID Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Framing Error Setting this bit to 1h enables setting of Framing Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,CRC Error Setting this bit to 1h enables setting of CRC Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED            ,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RESP_PKT                 ,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Header Error Setting this bit to 1h enables setting of Header Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1"
group.long 0xCC++0x3
line.long 0x00 "MMCSD0_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals."
bitfld.long 0x00 27.--31. "         VENDOR_SPECFIC           ,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                DEADLOCK_TIMEOUT         ,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " CMD_RESP_TIMEOUT         ,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 15. "                 ADMA2_ADMA3              ,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED_SIG_ENA    ,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RESP_PKT                 ,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1"
rgroup.word 0xE0++0x1
line.word 0x00 "MMCSD0_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings."
hexmask.word 0x00 0.--15. 1. "             UHS2_SETTINGS_PTR        ,Pointer for UHS-II Settings Register"
rgroup.word 0xE2++0x1
line.word 0x00 "MMCSD0_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register."
hexmask.word 0x00 0.--15. 1. "             UHS2_CAPABILITIES_PTR    ,Pointer for UHS-II Capabilities Register"
rgroup.word 0xE4++0x1
line.word 0x00 "MMCSD0_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register."
hexmask.word 0x00 0.--15. 1. "             UHS2_TEST_PTR            ,Pointer for UHS-II Test Register"
rgroup.word 0xE6++0x1
line.word 0x00 "MMCSD0_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register."
hexmask.word 0x00 0.--15. 1. "             SHARED_BUS_CTRL_PTR      ,Pointer for Shared Bus Control Register"
rgroup.word 0xE8++0x1
line.word 0x00 "MMCSD0_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register."
hexmask.word 0x00 0.--15. 1. "             VENDOR_SPECFIC_PTR       ,Pointer for Vendor Specific Area"
group.long 0xF4++0x3
line.long 0x00 "MMCSD0_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter."
hexmask.long 0x00 0.--31. 1. "         DATA_TIMEOUT_CNT         ,Boot Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card. The value is in number of SD clock."
group.long 0xF8++0x3
line.long 0x00 "MMCSD0_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK, CMD11 Power Down Timer, Enhanced Strobe and eMMC Hardware Reset."
bitfld.long 0x00 16. "         AUTOGATE_SDCLK           ,Auto Gate SD CLK If this bit is set, SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device. 0h: Disable 1h: Enable" "0,1"
hexmask.long.word 0x00 2.--15. 1. "                 CMD11_PD_TIMER           ,CMD11 Power Down Timer Value"
textline "                                                 "
bitfld.long 0x00 1. " EMMC_HW_RESET            ,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set. 0h: De-sassert hardware reset pin 1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)" "0,1"
bitfld.long 0x00 0. "                 ENHANCED_STROBE          ,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller." "0,1"
rgroup.word 0xFC++0x1
line.word 0x00 "MMCSD0_SLOT_INT_STS,This register is used to read the interrupt signal for each slot."
hexmask.word.byte 0x00 0.--7. 1. "             INTR_SIG                 ,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot."
rgroup.word 0xFE++0x1
line.word 0x00 "MMCSD0_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number."
hexmask.word.byte 0x00 8.--15. 1. "             VEN_VER_NUM              ,Vendor Version Number The Vendor Version Number is set to 10h (1.0)"
hexmask.word.byte 0x00 0.--7. 1. "                SPEC_VER_NUM             ,Specification Version Number This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version. 0h: SD Host Controller Specification Version 1.00 1h: SD Host Controller Specification Version 2.00 Including the feature of the ADMA and Test Register 2h: SD Host Controller Specification Version 3.00 3h: SD Host Controller Specification Version 4.00 4h: SD Host Controller Specification Version 4.10 Others: Reserved"
group.long 0x100++0x3
line.long 0x00 "MMCSD0_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register."
bitfld.long 0x00 8.--13. "         NUMLANES                 ,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0h: 2 Lanes FD or 2L-HD 1h: Not Used 2h: 3 Lanes 2D1U-FD (Embedded) 3h: 3 Lanes 1D2U-FD (Embedded) 4h: 4 Lanes 2D2U-FD (Embedded) Others: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0. "                POWER_MODE               ,Power Mode This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode. 0h: Fast Mode 1h: Low Power Mode" "0,1"
group.long 0x104++0x3
line.long 0x00 "MMCSD0_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register."
bitfld.long 0x00 20.--23. "         N_LSS_DIR                ,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h: 8 x 16 LSS 1h: 8 x 1 LSS 2h: 8 x 2 LSS 3h: 8 x 3 LSS .... .... Fh: 8 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                N_LSS_SYN                ,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h - 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 15. " HIBERNATE_ENA            ,Hibernate Enable After checking card capability of Hibernate mode, if all devices support Hibernate mode, this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode, VDD1 Power may be off. 0h: Hibernate Disabled 1h: Hibernate Enabled" "0,1"
bitfld.long 0x00 6.--7. "                 SPEED_RANGE              ,Speed Range PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. 0h: Range A (Defalt) 1h: Range B 2h: Reserved 3h: Reserved" "0,1,2,3"
group.quad 0x108++0x7
line.quad 0x00 "MMCSD0_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register."
hexmask.quad.byte 0x00 32.--39. 1. " N_DATA_GAP               ,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS"
bitfld.quad 0x00 16.--17. "                RETRY_COUNT              ,Retry Count Data Burst retry count is set to this field. 00h: Retry Disabled 01h: 1 time 02h: 2 times 03h: 3 times" "0,1,2,3"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " HOST_NFCU                ,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field. The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended considering buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Blocks 03h: 3 Blocks .... .... FFh: 255 Blocks"
rgroup.long 0x110++0x3
line.long 0x00 "MMCSD0_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register."
bitfld.long 0x00 22.--23. "         CORECFG_UHS2_BUS_TOPLOGY ,Bus Topology This field indicates one of bus topologies configured by a Host system. 0h: P2P Connection 1h: Ring Connection 2h: HUB Connection 3h: HUB is Connected in Ring" "0,1,2,3"
bitfld.long 0x00 18.--21. "                 CORECFG_UHS2_MAX_DEVICES ,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller. 0h: Not used 1h: 1 Devices 2h: 2 Devices .... .... Fh: 15 Devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 16.--17. " DEVICE_TYPE              ,Removable/Embedded This field indicates device type configured by a Host system. 0h: Removable Card (P2P) 1h: Embedded Devices 2h: Embedded Devices + Removable Card 3h: Reserved" "0,1,2,3"
bitfld.long 0x00 14. "                 CFG_64BIT_ADDRESSING     ,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller. 0h: 32-bit Addressing is supported 1h: 32-bit and 64-bit Addressing is supported" "0,1"
textline "                                                 "
bitfld.long 0x00 8.--13. " NUM_LANES                ,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller. 0 mean not supported and 1 means supported. D08: 2L-HD D09: 2D1U-FD D10: 1D2U-FD D11: 2D2U-FD D12: Reserved D13: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--7. "                GAP                      ,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM. 0h: Not used 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x 15 mW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 0.--3. " DAP                      ,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD. 0h: 360 mW (Default) 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x 15 mW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x114++0x3
line.long 0x00 "MMCSD0_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register."
bitfld.long 0x00 20.--23. "         N_LSS_DIR                ,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                N_LSS_SYN                ,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 6.--7. " SPEED_RANGE              ,Speed Range This field indicates supported Speed Range by the Host Controller. 0h: Range A (Default) 1h: Range A and Range B 2h: Reserved 3h: Reserved" "0,1,2,3"
rgroup.quad 0x118++0x7
line.quad 0x00 "MMCSD0_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register."
hexmask.quad.byte 0x00 32.--39. 1. " N_DATA_GAP               ,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS"
hexmask.quad.word 0x00 20.--31. 1. "                MAX_BLK_LENGTH           ,Host Maximum Block Length This field indicates maximum block length by the Host Controller. 000h: Not Used 001h: 1 byte 002h: 2 bytes .... .... 200h: 512 bytes .... .... 800h: 2048 bytes 801h - FFFh: Not Used"
textline "                                                 "
hexmask.quad.byte 0x00 8.--15. 1. " N_FCU                    ,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Block 03h: 3 Block .... .... FFh: 255 Blocks"
wgroup.long 0x120++0x3
line.long 0x00 "MMCSD0_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented, rather it is an address where the register can be written."
bitfld.long 0x00 27.--31. "         VENDOR_SPECIFIC          ,Force Event for Vendor Specific Error 0h: Not Affected 1h: Vendor Specific Error Status is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 17. "                TIMEOUT_DEADLOCK         ,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in the 0h: Not affected 1h: Timeout for Deadlock Error status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " TIMEOUT_CMD_RES          ,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in the 0h: Not affected 1h: Timout for CMD_RES Status is set" "0,1"
bitfld.long 0x00 15. "                 ADMA                     ,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in the 0h: Not affected 1h: ADMA Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " EBSY                     ,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in the 0h: Not affected 1h: EBSY Error Status is set" "0,1"
bitfld.long 0x00 7. "                 UNRECOVERABLE            ,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in the 0h: Not affected 1h: Unrecoverable Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 5. " TID                      ,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in the 0h: Not affected 1h: TID Error Status is set" "0,1"
bitfld.long 0x00 4. "                 FRAMING                  ,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in the 0h: Not affected 1h: Framing Error Status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 3. " CRC                      ,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in the 0h: Not affected 1h: CRC Error Status is set" "0,1"
bitfld.long 0x00 2. "                 RETRY_EXPIRED            ,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in the 0h: Not affected 1h: Retry expired error status is set" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " RES_PKT                  ,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in the 0h: Not affected 1h: RES packet error status is set" "0,1"
bitfld.long 0x00 0. "                 HEADER                   ,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in the 0h: Not affected 1h: Header error status is set" "0,1"
rgroup.long 0x200++0x3
line.long 0x00 "MMCSD0_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE, in BCD format. The current version is rev 5.1. The following table describes the CQBASE+00h: Command Queueing Version."
bitfld.long 0x00 8.--11. "         EMMC_MAJOR_VER_NUM       ,eMMC Major Version Number (digit left of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "                EMMC_MINOR_VER_NUM       ,eMMC Minor Version Number (digit right of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 0.--3. " EMMC_VERSION_SUFFIX      ,eMMC Version Suffix (2nd digit right of decimal point), in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x204++0x3
line.long 0x00 "MMCSD0_CQ_CAPABILITIES,This register is reserved for capability indication."
bitfld.long 0x00 12.--15. "         CF_MUL                   ,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details ( Field Value Description: 0h: 0.001 MHz 1h: 0.01 MHz 2h: 0.1 MHz 3h: 1 MHz 4h: 10 MHz Other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "                CF_VAL                   ,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling. The clock frequency is calculated as ITCFVAL ? ITCFMUL. For example, to encode 19.2 MHz ITCFVAL shall be 192 ? 0.1 MHz = 19.2 MHz"
group.long 0x208++0x3
line.long 0x00 "MMCSD0_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time."
bitfld.long 0x00 12. "         DCMD_ENA                 ,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor, or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. Bit Value Description 0h: Task descriptor in slot #31 is a Data Transfer Task Descriptor 1h: Task descriptor in slot #31 is a DCMD Task Descriptor" "0,1"
bitfld.long 0x00 8. "                 TASK_DESC_SIZE           ,This bit indicates whether the task descriptor size is 128 bits or 64 bits. This bit can only be configured when the Bit Value Description 0h: Task descriptor size is 64 bits 1h: Task descriptor size is 128 bits" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " CQ_ENABLE                ,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE). When this bit is 0h, CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller. Before software writes 1h to this bit, software shall verify that the eMMC host controller is in idle state and there are no commands or data transfers ongoing. When software wants to exit command queueing mode, it shall clear all previous tasks if such exist before setting this bit to 0h." "0,1"
group.long 0x20C++0x3
line.long 0x00 "MMCSD0_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time."
bitfld.long 0x00 8. "         CLEAR_ALL_TASKS          ,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state (Halt bit is 1h). When software writes 1h, the value of the register is updated to 1h, and CQE shall reset the Software should poll on this bit until it is set to back 0 and may then resume normal operation, by clearing the Halt bit. CQE does not communicate to the device that the tasks were cleared. It is softwares responsibility to order the device to discard the tasks in its queue using CMDQ_TASK_MGMT command. Writing 0h to this register shall have no effect." "0,1"
bitfld.long 0x00 0. "                 HALT_BIT                 ,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example, issuing a Discard Task command (CMDQ_TASK_MGMT). When software writes 1h, CQE shall complete the ongoing task if such a task is in progress. Once the task is completed and CQE is in idle state, CQE shall not issue new commands and shall indicate so to software by setting this bit to 1h. Software may poll on this bit until it is set to 1h, and may only then send commands on the eMMC bus. In order to exit halt state (resume CQE activity), software shall clear this bit (write 0h). Writing 0h when the value is already 0h shall have no effect." "0,1"
hgroup.long 0x210++0x3
hide.long 0x00 "MMCSD0_CQ_INTR_STS,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event, only if the respective bit is set in the register."
in
textline "                                                 "
group.long 0x214++0x3
line.long 0x00 "MMCSD0_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register. When a bit is set (1h) and the corresponding interrupt condition is active, then the 300 bit in the register is asserted. Interrupt sources that are disabled (0h) are not indicated in the 301 register. This register is bit-index matched to the register."
bitfld.long 0x00 4. "         TASK_ERROR               ,1h: 0h:" "0,1"
bitfld.long 0x00 3. "                 TASK_CLEARED             ,1h: 0h:" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " RESP_ERR_DET             ,1h: 0h:" "0,1"
bitfld.long 0x00 1. "                 TASK_COMPLETE            ,1h: 0h:" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " HALT_COMPLETE            ,1h: 0h:" "0,1"
group.long 0x218++0x3
line.long 0x00 "MMCSD0_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the register is set, then an interrupt is generated. Interrupt sources 305 that are disabled (0h) are still indicated in the register. This register is bit-index matched 306 to the register."
bitfld.long 0x00 4. "         TASK_ERROR               ,When set and the" "0,1"
bitfld.long 0x00 3. "                 TASK_CLEARED             ,When set and the" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " RESP_ERR_DET             ,When set and the" "0,1"
bitfld.long 0x00 1. "                 TASK_COMPLETE            ,When set and the" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " HALT_COMPLETE            ,When set and the" "0,1"
group.long 0x21C++0x3
line.long 0x00 "MMCSD0_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature."
bitfld.long 0x00 31. "         CQINTCOALESC_ENABLE      ,When set to 0h by software, command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor. When set to 1h, the interrupt coalescing mechanism is enabled and coalesced interrupts are generated." "0,1"
bitfld.long 0x00 20. "                 IC_STATUS                ,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0). Bit Value Description 0h: No task completions have occurred since last counter reset (IC counter = 0) 1h: At least one task completion has been counted (IC counter > 0)" "0,1"
textline "                                                 "
bitfld.long 0x00 8.--12. " CTR_THRESHOLD            ,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT = 0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine. The counter stops counting when it reaches the value configured in ICCTH. The maximum allowed value is 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--6. 1. "                TIMEOUT_VAL              ,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts running when a data transfer task with INT = 0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field it generates an interrupt and stops. The timers unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field in the The minimum value is 1h (1024 clock periods) and the maximum value is 7Fh (127 ? 1024 clock periods). For example, a"
group.long 0x220++0x3
line.long 0x00 "MMCSD0_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory."
hexmask.long 0x00 0.--31. 1. "         CQTDLBA_LO               ,This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 ? (Task Descriptor size + Transfer Descriptor size) as configured by Host driver. This address shall be set on Byte1 KByte boundary. The lower 10 bits of this register shall be set to 0h by software and shall be ignored by CQE."
group.long 0x224++0x3
line.long 0x00 "MMCSD0_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory."
hexmask.long 0x00 0.--31. 1. "         CQTDLBA_HI               ,This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 ? (Task Descriptor size + Transfer Descriptor size) as configured by Host driver. This register is reserved when using 32-bit addressing mode."
group.long 0x228++0x3
line.long 0x00 "MMCSD0_CQ_TASK_DOOR_BELL,Using this register, software triggers CQE to process a new task."
hexmask.long 0x00 0.--31. 1. "         CQTDB_VAL                ,Software shall configure the Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. CQE always processes tasks in-order according to the order submitted to the list by the CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. The corresponding bit is cleared to 0h by CQE in one of the following events: (a) When a task execution is completed (with success or error) (b) The task is cleared using (c) All tasks are cleared using (d) CQE is disabled using Software may initiate multiple tasks at the same time (batch submission) by writing 1h to multiple bits of this register in the same transaction. In the case of batch submission: CQE shall process the tasks in order of the task index, starting with the lowest index. If one or more tasks in the batch are marked with QBR, the ordering of execution will be based on said processing order. Writing 0h by software shall have no impact on the hardware, and will not change the value of the register bit."
hgroup.long 0x22C++0x3
hide.long 0x00 "MMCSD0_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks."
in
textline "                                                 "
rgroup.long 0x230++0x3
line.long 0x00 "MMCSD0_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status."
hexmask.long 0x00 0.--31. 1. "         CQDQ_STS                 ,Every time the Host controller receives a queue status register (QSR) from the device, it updates this register with the response of status command (the device's queue status)."
rgroup.long 0x234++0x3
line.long 0x00 "MMCSD0_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device, awaiting execution."
hexmask.long 0x00 0.--31. 1. "         CQDP_TSKS                ,Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet. CQE shall set this bit after receiving a successful response for CMD45. CQE shall clear this bit after the task has completed execution. Software needs to read this register in the task-discard procedure, when the controller is halted, to determine if the task is queued in the device. If the task is queued, the driver sends a CMDQ_TASK_MGMT (CMD48) to the device ordering it to discard the task. Then software clears the task in the CQE. Only then the software orders CQE to resume its operation using"
group.long 0x238++0x3
line.long 0x00 "MMCSD0_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state."
hexmask.long 0x00 0.--31. 1. "         CQTCLR                   ,Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued. This bit can only be written when CQE is in Halt state as indicated in the When software writes 1h to a bit in this register, CQE updates the value to 1h, and starts clearing the data structures related to the task. CQE clears the bit fields (sets a value of 0h) in the Software should poll on the Writing to this register only clears the task in the CQE and does not have impact on the device. In order to discard the task in the device, host software shall send CMDQ_TASK _MGMT while CQE is still in Halt state. Host driver is not allowed to use this register to clear multiple tasks at the same time. Clearing multiple tasks can be done using Writing 0h to a register bit shall have no impact."
group.long 0x240++0x3
line.long 0x00 "MMCSD0_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent."
bitfld.long 0x00 16.--19. "         CMD_BLK_CNTR             ,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue. A value of n means CQE shall send status command on the CMD line, during the transfer of data block A value of 0h means that SEND_QUEUE_STATUS (CMD13) command shall not be sent during the transaction. Instead it will be sent only when the data lines are idle. A value of 1 means that STATUS command is to be sent during the last block of the transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "                CMD_IDLE_TIMER           ,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. When a SEND_QUEUE_STATUS response indicating that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. Timer units are clock periods of theclock whose frequency is specified in the Internal Timer Clock Frequency field in the The minimum value is 1h (1 clock period) and the maximum value is FFFFh (65535 clock periods). Default interval is: 4096 clock periods. For example, a"
group.long 0x244++0x3
line.long 0x00 "MMCSD0_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument."
hexmask.long.word 0x00 0.--15. 1. "         QUEUE_RCA                ,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command."
rgroup.long 0x248++0x3
line.long 0x00 "MMCSD0_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software."
hexmask.long 0x00 0.--31. 1. "         LAST_RESP                ,This register contains the response of the command generated by the last direct command (DCMD) task which was sent. CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31 of the"
rgroup.long 0x250++0x3
line.long 0x00 "MMCSD0_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt."
hexmask.long 0x00 0.--31. 1. "         CQRMEM                   ,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses. Bit Value Description (for any bit i): 1h: When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated 0h: When a R1/R1b response is received, bit i in the device status is ignored The reset value of this register is set to trigger an interrupt on all 'Error' type bits in the device status."
rgroup.long 0x254++0x3
line.long 0x00 "MMCSD0_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the register the task IDs and the command indices of the commands which were executed on the 343 command line and data lines when the error occurred. Software is expected to use this information in the error recovery procedure."
bitfld.long 0x00 31. "         DATERR_VALID             ,This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated, the bit is set to 1h. If a no data transfer is in progress when the error is detected/indicated, the bit is cleared to 0h." "0,1"
bitfld.long 0x00 24.--28. "                 DATERR_TASK_ID           ,This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 16.--21. " DATERR_CMD_INDEX         ,This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "                RESP_MODE_VALID          ,This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated, the bit is set to 1h. If a no command transaction is in progress when the error is detected/indicated, the bit is cleared to 0h." "0,1"
textline "                                                 "
bitfld.long 0x00 8.--12. " RESP_MODE_TASK_ID        ,This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "                RESP_MODE_CMD_INDEX      ,This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x258++0x3
line.long 0x00 "MMCSD0_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response."
bitfld.long 0x00 0.--5. "         LAST_CRI                 ,This field stores the index of the last received command response. CQE shall update the value every time a command response is received." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x25C++0x3
line.long 0x00 "MMCSD0_CQ_CMD_RESP_ARG,This register stores the index of the last received command response."
hexmask.long 0x00 0.--31. 1. "         LAST_CRA                 ,This field stores the argument of the last received command. CQE shall update the value every time a command response is received."
rgroup.long 0x260++0x3
line.long 0x00 "MMCSD0_CQ_ERROR_TASK_ID,CQ Error Task ID Register"
bitfld.long 0x00 0.--4. "         TERR_ID                  ,Task Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "MCU_FSS"
tree "MCU_FSS0_OSPI_ECC_AGGR"
tree "MCU_FSS0_OSPI1_ECC_AGGR"
base ad:0x47064000
width 30.
rgroup.long 0x0++0x3
line.long 0x00 "OSPI_ECC_REV,Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,bu" "0,1,2,3"
textline "                                       "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                       "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom version" "0,1,2,3"
textline "                                       "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "OSPI_ECC_VECTOR,ECC Vector Register."
in
textline "                                       "
rgroup.long 0xC++0x3
line.long 0x00 "OSPI_ECC_STAT,Miscellaneous status register."
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS        ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "OSPI_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR          ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "OSPI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0."
bitfld.long 0x00 0. " SRAM_PEND       ,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "OSPI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0."
bitfld.long 0x00 0. " SRAM_ENABLE_SET ,Interrupt Enable Set Register for sram_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "OSPI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0."
in
textline "                                       "
group.long 0x13C++0x3
line.long 0x00 "OSPI_ECC_DED_EOI_REG,EOI Register."
bitfld.long 0x00 0. " EOI_WR          ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "OSPI_ECC_DED_STATUS_REG0,Interrupt Status Register 0."
bitfld.long 0x00 0. " SRAM_PEND       ,Interrupt Pending Status for sram_pend." "0,1"
group.long 0x180++0x3
line.long 0x00 "OSPI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0."
bitfld.long 0x00 0. " SRAM_ENABLE_SET ,Interrupt Enable Set Register for sram_pend." "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "OSPI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0."
in
textline "                                       "
group.long 0x200++0x3
line.long 0x00 "OSPI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register."
bitfld.long 0x00 1. " TIMEOUT         ,Interrupt enable set for svbus timeout errors." "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors." "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "OSPI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register."
in
textline "                                       "
group.long 0x208++0x3
line.long 0x00 "OSPI_ECC_AGGR_STATUS_SET,AGGR interrupt status set register."
bitfld.long 0x00 2.--3. " TIMEOUT         ,Interrupt status set for svbus timeout errors." "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors." "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "OSPI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register."
bitfld.long 0x00 2.--3. " TIMEOUT         ,Interrupt status clear for svbus timeout errors." "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors." "0,1,2,3"
width 0x0B
tree.end
tree "MCU_FSS0_OSPI0_ECC_AGGR"
base ad:0x47068000
width 30.
rgroup.long 0x0++0x3
line.long 0x00 "OSPI_ECC_REV,Revision parameters."
bitfld.long 0x00 30.--31. " SCHEME          ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU               ,bu" "0,1,2,3"
textline "                                       "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID       ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                       "
bitfld.long 0x00 8.--10. " REVMAJ          ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM           ,Custom version" "0,1,2,3"
textline "                                       "
bitfld.long 0x00 0.--5. " REVMIN          ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "OSPI_ECC_VECTOR,ECC Vector Register."
in
textline "                                       "
rgroup.long 0xC++0x3
line.long 0x00 "OSPI_ECC_STAT,Miscellaneous status register."
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS        ,Indicates the number of RAMs serviced by the ECC aggregator."
group.long 0x3C++0x3
line.long 0x00 "OSPI_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR          ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "OSPI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0."
bitfld.long 0x00 0. " SRAM_PEND       ,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "OSPI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0."
bitfld.long 0x00 0. " SRAM_ENABLE_SET ,Interrupt Enable Set Register for sram_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "OSPI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0."
in
textline "                                       "
group.long 0x13C++0x3
line.long 0x00 "OSPI_ECC_DED_EOI_REG,EOI Register."
bitfld.long 0x00 0. " EOI_WR          ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "OSPI_ECC_DED_STATUS_REG0,Interrupt Status Register 0."
bitfld.long 0x00 0. " SRAM_PEND       ,Interrupt Pending Status for sram_pend." "0,1"
group.long 0x180++0x3
line.long 0x00 "OSPI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0."
bitfld.long 0x00 0. " SRAM_ENABLE_SET ,Interrupt Enable Set Register for sram_pend." "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "OSPI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0."
in
textline "                                       "
group.long 0x200++0x3
line.long 0x00 "OSPI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register."
bitfld.long 0x00 1. " TIMEOUT         ,Interrupt enable set for svbus timeout errors." "0,1"
bitfld.long 0x00 0. "     PARITY           ,Interrupt enable set for parity errors." "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "OSPI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register."
in
textline "                                       "
group.long 0x208++0x3
line.long 0x00 "OSPI_ECC_AGGR_STATUS_SET,AGGR interrupt status set register."
bitfld.long 0x00 2.--3. " TIMEOUT         ,Interrupt status set for svbus timeout errors." "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status set for parity errors." "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "OSPI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register."
bitfld.long 0x00 2.--3. " TIMEOUT         ,Interrupt status clear for svbus timeout errors." "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY           ,Interrupt status clear for parity errors." "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "MCU_FSS0_OSPI_SS_CFG"
tree "MCU_FSS0_OSPI0_SS_CFG"
base ad:0x47044000
width 11.
rgroup.long 0x0++0x3
line.long 0x00 "OSPI_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME              ," "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU     ,Business Unit:10 = Processors" "0,1,2,3"
textline "                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID           ,Module ID"
bitfld.long 0x00 11.--15. "  RTL    ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                    "
bitfld.long 0x00 8.--10. " MAJOR               ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM ,Custom" "0,1,2,3"
textline "                    "
bitfld.long 0x00 0.--5. " MINOR               ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "OSPI_CTRL,The Control Register contains general control bits for the OSPI."
bitfld.long 0x00 3. " PIPELINE_MODE_FLUSH ,1h = Flush Flash Controller FIFO by forcing data interface slave select signal low. 0h = Data interface slave select signal to Controller is 1." "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "OSPI_STAT,The Status register provide general status bits for the OSPI."
bitfld.long 0x00 1. " MEM_INIT_DONE       ,0h = Memory initialization is in progress, 1h = Memory intialization is done." "0,1"
wgroup.long 0x20++0x3
line.long 0x00 "OSPI_EOI,End of Interrupt Register Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long.byte 0x00 0.--7. 1. " EOI                 ,Write with bit position of targetted interrupt.(that is Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt."
width 0x0B
tree.end
tree "MCU_FSS0_OSPI1_SS_CFG"
base ad:0x47054000
width 11.
rgroup.long 0x0++0x3
line.long 0x00 "OSPI_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME              ," "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU     ,Business Unit:10 = Processors" "0,1,2,3"
textline "                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID           ,Module ID"
bitfld.long 0x00 11.--15. "  RTL    ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                    "
bitfld.long 0x00 8.--10. " MAJOR               ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM ,Custom" "0,1,2,3"
textline "                    "
bitfld.long 0x00 0.--5. " MINOR               ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "OSPI_CTRL,The Control Register contains general control bits for the OSPI."
bitfld.long 0x00 3. " PIPELINE_MODE_FLUSH ,1h = Flush Flash Controller FIFO by forcing data interface slave select signal low. 0h = Data interface slave select signal to Controller is 1." "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "OSPI_STAT,The Status register provide general status bits for the OSPI."
bitfld.long 0x00 1. " MEM_INIT_DONE       ,0h = Memory initialization is in progress, 1h = Memory intialization is done." "0,1"
wgroup.long 0x20++0x3
line.long 0x00 "OSPI_EOI,End of Interrupt Register Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long.byte 0x00 0.--7. 1. " EOI                 ,Write with bit position of targetted interrupt.(that is Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt."
width 0x0B
tree.end
tree.end
tree "MCU_FSS0_OSPI_CTRL"
tree "MCU_FSS0_OSPI0_CTRL"
base ad:0x47040000
width 40.
group.long 0x0++0x3
line.long 0x00 "OSPI_CONFIG_REG,OSPI Configuration Register This register contains basic configuration fields of the controller. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
bitfld.long 0x00 31. " IDLE_FLD                                ,Serial interface and low level SPI pipeline is IDLE." "0,1"
bitfld.long 0x00 30. "         DUAL_BYTE_OPCODE_EN_FLD                    ,Dual-byte Opcode Mode enable bit." "0,1"
textline "                                                 "
bitfld.long 0x00 29. " CRC_ENABLE_FLD                          ,CRC enable bit." "0,1"
bitfld.long 0x00 26.--28. "         CONFIG_RESV2_FLD                           ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 25. " PIPELINE_PHY_FLD                        ,Pipeline PHY Mode enable." "0,1"
bitfld.long 0x00 24. "         ENABLE_DTR_PROTOCOL_FLD                    ,Enable DTR Protocol." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " ENABLE_AHB_DECODER_FLD                  ,Enable AHB Decoder. 0h = Active slave is selected based on the OSPI_CONFIG_REG[13:10] PERIPH_CS_LINES_FLD. 1h = Active slave is selected based on actual data interface address (the partition is calculated with respect to bits OSPI_DEV_SIZE_CONFIG_REG[28:21])." "0,1"
bitfld.long 0x00 19.--22. "         MSTR_BAUD_DIV_FLD                          ,Master mode baud rate divisor (2 to 32)," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 18. " ENTER_XIP_MODE_IMM_FLD                  ,Enter XIP Mode immediately.0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value=1h = Operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode [as per the contents of its non-volatile configuration register]. The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred.Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited." "0,1"
bitfld.long 0x00 17. "         ENTER_XIP_MODE_FLD                         ,Enter XIP Mode on next READ.0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction.1h = If XIP is disabled, then setting to 1 will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " ENB_AHB_ADDR_REMAP_FLD                  ,Enable Data Interface Address Remapping [Direct Access Mode Only]" "0,1"
bitfld.long 0x00 15. "         ENB_DMA_IF_FLD                             ,Enable DMA Peripheral Interface." "0,1"
textline "                                                 "
bitfld.long 0x00 14. " WR_PROT_FLASH_FLD                       ,Write Protect Flash Pin." "0,1"
bitfld.long 0x00 10.--13. "         PERIPH_CS_LINES_FLD                        ,Peripheral Chip Select Lines.If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0, ss[3:0] are output thus:ss[3:0]xxx0 xx01 x011 0111 1111 N_SS_OUT[3:0]11101101 1011 0111 1111 [no peripheral selected] . else ss[3:0] directly drives N_SS_OUT[3:0] ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 9. " PERIPH_SEL_DEC_FLD                      ,Peripheral select decode.0h = only 1 of 4 selects N_SS_OUT[3:0] is active,1h = allow external 4-to-16 decode [N_SS_OUT = ss]" "0,1"
bitfld.long 0x00 8. "         ENB_LEGACY_IP_MODE_FLD                     ,Legacy IP Mode Enable.0h = Use Direct Access Controller/Indirect Access Controller 1h = Legacy Mode is enabled. In this mode, any write to the controller via the data interface is serialized and sent to the FLASH device. Any valid data read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, 4, 2 or 1 byte transfers are permitted and controlled." "0,1"
textline "                                                 "
bitfld.long 0x00 7. " ENB_DIR_ACC_CTLR_FLD                    ,Enable Direct Access Controller.0h = Disable the Direct Access Controller once current transfer of the data word is complete.1h = Enable the Direct Access Controller. When the Direct Access Controller and Indirect Access Controller are both disabled, all data requests are completed with an error response." "0,1"
bitfld.long 0x00 6. "         RESET_CFG_FLD                              ,RESET pin configuration.0h = RESET feature on DQ3 pin of the device 1h = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]." "0,1"
textline "                                                 "
bitfld.long 0x00 5. " RESET_PIN_FLD                           ,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature." "0,1"
bitfld.long 0x00 4. "         HOLD_PIN_FLD                               ,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature." "0,1"
textline "                                                 "
bitfld.long 0x00 3. " PHY_MODE_ENABLE_FLD                     ,PHY mode enable." "0,1"
bitfld.long 0x00 2. "         SEL_CLK_PHASE_FLD                          ,Select Clock Phase.Selects whether the clock is in an active or inactive phase outside the SPI word 0h = The SPI clock is active outside the word 1h = The SPI clock is inactive outside the word" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " SEL_CLK_POL_FLD                         ,Clock polarity outside SPI word.0h = The SPI clock is quiescent low 1h = The SPI clock is quiescent high" "0,1"
bitfld.long 0x00 0. "         ENB_SPI_FLD                                ,OSPI Enable.0h = Disable the OSPI, once current transfer of the data wordis complete.1h = Enable the OSPI, when this bit is set to 0, all output enables are inactive and all pins are set to input mode." "0,1"
group.long 0x4++0x3
line.long 0x00 "OSPI_DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register. This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " RD_INSTR_RESV5_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "         DUMMY_RD_CLK_CYCLES_FLD                    ,Dummy Read Clock Cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 21.--23. " RD_INSTR_RESV4_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20. "         MODE_BIT_ENABLE_FLD                        ,Mode Bit Enable." "0,1"
textline "                                                 "
bitfld.long 0x00 18.--19. " RD_INSTR_RESV3_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--17. "         DATA_XFER_TYPE_EXT_MODE_FLD                ,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Quad Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 14.--15. " RD_INSTR_RESV2_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         ADDR_XFER_TYPE_STD_MODE_FLD                ,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2, and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 11. " RD_INSTR_RESV1_FLD                      ,Reserved" "0,1"
bitfld.long 0x00 10. "         DDR_EN_FLD                                 ,DDR Enable." "0,1"
textline "                                                 "
bitfld.long 0x00 8.--9. " INSTR_TYPE_FLD                          ,Instruction Type.0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1h = Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2h = Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2, and DQ3] 3h = Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]]" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "         RD_OPCODE_NON_XIP_FLD                      ,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
group.long 0x8++0x3
line.long 0x00 "OSPI_DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register. This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " WR_INSTR_RESV4_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "         DUMMY_WR_CLK_CYCLES_FLD                    ,Dummy Write Clock Cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 18.--23. " WR_INSTR_RESV3_FLD                      ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--17. "        DATA_XFER_TYPE_EXT_MODE_FLD                ,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Quad Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 14.--15. " WR_INSTR_RESV2_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         ADDR_XFER_TYPE_STD_MODE_FLD                ,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2. and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 9.--11. " WR_INSTR_RESV1_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "         WEL_DIS_FLD                                ,WEL Disable." "0,1"
textline "                                                 "
hexmask.long.byte 0x00 0.--7. 1. " WR_OPCODE_FLD                           ,Write Opcode"
group.long 0xC++0x3
line.long 0x00 "OSPI_DEV_DELAY_REG,OSPI Device Delay Register. This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the OSPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock. This register should be setup while the controller is idle."
hexmask.long.byte 0x00 24.--31. 1. " D_NSS_FLD                               ,Clock Delay for Chip Select Deassert."
hexmask.long.byte 0x00 16.--23. 1. "        D_BTWN_FLD                                 ,Clock Delay for Chip Select Deactivation."
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " D_AFTER_FLD                             ,Clock Delay for Last Transaction Bit."
hexmask.long.byte 0x00 0.--7. 1. "        D_INIT_FLD                                 ,Clock Delay with N_SS_OUT."
group.long 0x10++0x3
line.long 0x00 "OSPI_RD_DATA_CAPTURE_REG,Read Data Capture Register. This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle."
hexmask.long.word 0x00 20.--31. 1. " RD_DATA_RESV3_FLD                       ,Reserved"
bitfld.long 0x00 16.--19. "      DDR_READ_DELAY_FLD                         ,DDR read delay." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
hexmask.long.byte 0x00 9.--15. 1. " RD_DATA_RESV2_FLD                       ,Reserved"
bitfld.long 0x00 8. "        DQS_ENABLE_FLD                             ,DQS enable bit." "0,1"
textline "                                                 "
bitfld.long 0x00 6.--7. " RD_DATA_RESV1_FLD                       ,Reserved" "0,1,2,3"
bitfld.long 0x00 5. "         SAMPLE_EDGE_SEL_FLD                        ,Sample edge selection." "0,1"
textline "                                                 "
bitfld.long 0x00 1.--4. " DELAY_FLD                               ,Read Delay." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        BYPASS_FLD                                 ,Bypass." "0,1"
group.long 0x14++0x3
line.long 0x00 "OSPI_DEV_SIZE_CONFIG_REG,Device Size Configuration Register. This register allows to define the memory organization of using Flash Devices. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " DEV_SIZE_RESV_FLD                       ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 27.--28. "         MEM_SIZE_ON_CS3_FLD                        ,Size of Flash Device connected to CS[3] pin:0h = size of 512Mb 1h = size of 1Gb2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 25.--26. " MEM_SIZE_ON_CS2_FLD                     ,Size of Flash Device connected to CS[2] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
bitfld.long 0x00 23.--24. "         MEM_SIZE_ON_CS1_FLD                        ,Size of Flash Device connected to CS[1] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 21.--22. " MEM_SIZE_ON_CS0_FLD                     ,Size of Flash Device connected to CS[0] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
bitfld.long 0x00 16.--20. "         BYTES_PER_SUBSECTOR_FLD                    ,Number of bytes per Block." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
hexmask.long.word 0x00 4.--15. 1. " BYTES_PER_DEVICE_PAGE_FLD               ,Number of bytes per device page."
bitfld.long 0x00 0.--3. "      NUM_ADDR_BYTES_FLD                         ,Number of address bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "OSPI_SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register."
hexmask.long.tbyte 0x00 8.--31. 1. " SRAM_PARTITION_RESV_FLD                 ,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "    ADDR_FLD                                   ,Indirect Read Partition Size."
group.long 0x1C++0x3
line.long 0x00 "OSPI_IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register. This register allowsto define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Indirect Trigger Address."
group.long 0x20++0x3
line.long 0x00 "OSPI_DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register. This register allows to define the parameters of DMA peripheral controller. This register should be setup while the controller is idle. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long.tbyte 0x00 12.--31. 1. " DMA_PERIPH_RESV2_FLD                    ,Reserved"
bitfld.long 0x00 8.--11. "    NUM_BURST_REQ_BYTES_FLD                    ,Number of Burst Bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 4.--7. " DMA_PERIPH_RESV1_FLD                    ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        NUM_SINGLE_REQ_BYTES_FLD                   ,Number of Single Bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x3
line.long 0x00 "OSPI_REMAP_ADDR_REG,Remap Address Register. This register allows to define the address offset for DAC accesses. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,This register is used to remap an incoming data address to a different address used by the FLASH device."
group.long 0x28++0x3
line.long 0x00 "OSPI_MODE_BIT_CONFIG_REG,Mode Bit Configuration Register. This register allows to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle."
hexmask.long.byte 0x00 24.--31. 1. " RX_CRC_DATA_LOW_FLD                     ,RX CRC data [lower]."
hexmask.long.byte 0x00 16.--23. 1. "        RX_CRC_DATA_UP_FLD                         ,RX CRC data [upper]."
textline "                                                 "
bitfld.long 0x00 15. " CRC_OUT_ENABLE_FLD                      ,CRC# output enable bit." "0,1"
bitfld.long 0x00 11.--14. "         MODE_BIT_RESV1_FLD                         ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 8.--10. " CHUNK_SIZE_FLD                          ,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MODE_FLD                                   ,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled."
rgroup.long 0x2C++0x3
line.long 0x00 "OSPI_SRAM_FILL_REG,SRAM Fill Register. This register keeps the values of current fill levels of both SRAM partitions."
hexmask.long.word 0x00 16.--31. 1. " SRAM_FILL_INDAC_WRITE_FLD               ,SRAM Fill Level [Indirect Write Partition]."
hexmask.long.word 0x00 0.--15. 1. "      SRAM_FILL_INDAC_READ_FLD                   ,SRAM Fill Level [Indirect Read Partition]."
group.long 0x30++0x3
line.long 0x00 "OSPI_TX_THRESH_REG,TX Threshold Register. This register allows to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle."
hexmask.long 0x00 5.--31. 1. " TX_THRESH_RESV_FLD                      ,Reserved"
bitfld.long 0x00 0.--4. "  LEVEL_FLD                                  ,Defines the level at which the small TX FIFO not full interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "OSPI_RX_THRESH_REG,RX Threshold Register. This register allows to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle."
hexmask.long 0x00 5.--31. 1. " RX_THRESH_RESV_FLD                      ,Reserved"
bitfld.long 0x00 0.--4. "  LEVEL_FLD                                  ,Defines the level at which the small RX FIFO not empty interrupt is generated." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x3
line.long 0x00 "OSPI_WRITE_COMPLETION_CTRL_REG,Write Completion Control Register. This register defines how the controller will poll the device following a write transfer."
hexmask.long.byte 0x00 24.--31. 1. " POLL_REP_DELAY_FLD                      ,Polling repetition delay."
hexmask.long.byte 0x00 16.--23. 1. "        POLL_COUNT_FLD                             ,Polling count."
textline "                                                 "
bitfld.long 0x00 15. " ENABLE_POLLING_EXP_FLD                  ,Enable polling expiration." "0,1"
bitfld.long 0x00 14. "         DISABLE_POLLING_FLD                        ,Disable polling." "0,1"
textline "                                                 "
bitfld.long 0x00 13. " POLLING_POLARITY_FLD                    ,Polling polarity." "0,1"
bitfld.long 0x00 11.--12. "         WR_COMP_CTRL_RESV1_FLD                     ,Reserved" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 8.--10. " POLLING_BIT_INDEX_FLD                   ,Polling bit index." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         OPCODE_FLD                                 ,Polling opcode."
group.long 0x3C++0x3
line.long 0x00 "OSPI_NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register. This register defines maximum number of poll cycles. If the expected value of the bit being polled is not gotten after number defined in this register, the auto-polling is done on the next phase."
hexmask.long 0x00 0.--31. 1. " NO_OF_POLLS_BEF_EXP_FLD                 ,Defines the numbers of poll cycles after which auto-polling phase terminates and polling expiration interrupt is generated."
hgroup.long 0x40++0x3
hide.long 0x00 "OSPI_IRQ_STATUS_REG,Interrupt Status Register. The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 through 10 are only valid when legacy SPI mode is active."
in
textline "                                                 "
group.long 0x44++0x3
line.long 0x00 "OSPI_IRQ_MASK_REG,Interrupt Mask Register. This register allows the user to mask/unmask particular interrupt sources. This register should be setup while the controller is idle. 0h = the interrupt for the corresponding interrupt status register bit is disabled. 1h = the interrupt for the corresponding interrupt status register bit is enabled."
hexmask.long.word 0x00 20.--31. 1. " IRQ_MASK_RESV_FLD                       ,Reserved"
bitfld.long 0x00 19. "      ECC_FAIL_MASK_FLD                          ,ECC failure Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 18. " TX_CRC_CHUNK_BRK_MASK_FLD               ,TX CRC chunk was broken Mask" "0,1"
bitfld.long 0x00 17. "         RX_CRC_DATA_VAL_MASK_FLD                   ,RX CRC data valid Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " RX_CRC_DATA_ERR_MASK_FLD                ,RX CRC data error Mask" "0,1"
bitfld.long 0x00 15. "         IRQ_MASK_RESV1_FLD                         ,Reserved" "0,1"
textline "                                                 "
bitfld.long 0x00 14. " STIG_REQ_MASK_FLD                       ,STIG request completion Mask" "0,1"
bitfld.long 0x00 13. "         POLL_EXP_INT_MASK_FLD                      ,Polling expiration detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 12. " INDRD_SRAM_FULL_MASK_FLD                ,Indirect Read Partition overflow mask" "0,1"
bitfld.long 0x00 11. "         RX_FIFO_FULL_MASK_FLD                      ,Small RX FIFO full Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 10. " RX_FIFO_NOT_EMPTY_MASK_FLD              ,Small RX FIFO not empty Mask" "0,1"
bitfld.long 0x00 9. "         TX_FIFO_FULL_MASK_FLD                      ,Small TX FIFO full Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " TX_FIFO_NOT_FULL_MASK_FLD               ,Small TX FIFO not full Mask" "0,1"
bitfld.long 0x00 7. "         RECV_OVERFLOW_MASK_FLD                     ,Receive Overflow Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 6. " INDIRECT_XFER_LEVEL_BREACH_MASK_FLD     ,Transfer Watermark Breach Mask" "0,1"
bitfld.long 0x00 5. "         ILLEGAL_ACCESS_DET_MASK_FLD                ,Illegal Access Detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 4. " PROT_WR_ATTEMPT_MASK_FLD                ,Protected Area Write Attempt Mask" "0,1"
bitfld.long 0x00 3. "         INDIRECT_READ_REJECT_MASK_FLD              ,Indirect Read Reject Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " INDIRECT_OP_DONE_MASK_FLD               ,Indirect Complete Mask" "0,1"
bitfld.long 0x00 1. "         UNDERFLOW_DET_MASK_FLD                     ,Underflow Detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " MODE_M_FAIL_MASK_FLD                    ,Mode M Failure Mask" "0,1"
group.long 0x50++0x3
line.long 0x00 "OSPI_LOWER_WR_PROT_REG,Lower Write Protection Register. This register allows to define lower boundary of the write protection area. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " SUBSECTOR_FLD                           ,Lower Block Number.The block number that defines the lower block in the range of blocks that is to be locked from writing."
group.long 0x54++0x3
line.long 0x00 "OSPI_UPPER_WR_PROT_REG,Upper Write Protection Register. This register allows to define upper boundary of the write protection area. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " SUBSECTOR_FLD                           ,Lower Block Number."
group.long 0x58++0x3
line.long 0x00 "OSPI_WR_PROT_CTRL_REG,Write Protection Control Register. This register allows to define the configuration of write protection settings. This register should be setup while the controller is idle."
hexmask.long 0x00 2.--31. 1. " WR_PROT_CTRL_RESV_FLD                   ,Reserved"
bitfld.long 0x00 1. "  ENB_FLD                                    ,Write Protection Enable Bit." "0,1"
textline "                                                 "
bitfld.long 0x00 0. " INV_FLD                                 ,Write Protection Inversion Bit." "0,1"
hgroup.long 0x60++0x3
hide.long 0x00 "OSPI_INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register. This register allows control of the Indirect Read Transfer logic."
in
textline "                                                 "
group.long 0x64++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register. This register allows to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long 0x00 0.--31. 1. " LEVEL_FLD                               ,Watermark Value."
group.long 0x68++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register. This register allows to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Start of Indirect Access."
group.long 0x6C++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register. This register allows to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,Indirect Number of Bytes."
hgroup.long 0x70++0x3
hide.long 0x00 "OSPI_INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register. This register allows control of the Indirect Write Transfer logic."
in
textline "                                                 "
group.long 0x74++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register. This register allows to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long 0x00 0.--31. 1. " LEVEL_FLD                               ,Watermark Value."
group.long 0x78++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register. This register allows to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is triggered."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Start of Indirect Access."
group.long 0x7C++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register. This register allows to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,Indirect Number of Bytes."
group.long 0x80++0x3
line.long 0x00 "OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register. This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer, there is no need to detect indirect trigger address boundaries by software. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 4.--31. 1. " IND_RANGE_RESV1_FLD                     ,Reserved"
bitfld.long 0x00 0.--3. "  IND_RANGE_WIDTH_FLD                        ,Indirect Range Width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C++0x3
line.long 0x00 "OSPI_FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register. This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank."
bitfld.long 0x00 29.--31. " FLASH_COMMAND_CTRL_MEM_RESV1_FLD        ,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 20.--28. 1. "         MEM_BANK_ADDR_FLD                          ,Memory Bank Address."
textline "                                                 "
bitfld.long 0x00 19. " FLASH_COMMAND_CTRL_MEM_RESV2_FLD        ,Reserved" "0,1"
bitfld.long 0x00 16.--18. "         NB_OF_STIG_READ_BYTES_FLD                  ,Number of STIG Memory Bank Read Bytes." "0,1,2,3,4,5,6,7"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " MEM_BANK_READ_DATA_FLD                  ,Memory Bank Read Data."
bitfld.long 0x00 2.--7. "        FLASH_COMMAND_CTRL_MEM_RESV3_FLD           ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                 "
bitfld.long 0x00 1. " MEM_BANK_REQ_IN_PROGRESS_FLD            ,Memory Bank data request in progress." "0,1"
bitfld.long 0x00 0. "         TRIGGER_MEM_BANK_REQ_FLD                   ,Trigger the Memory Bank data request." "0,1"
group.long 0x90++0x3
line.long 0x00 "OSPI_FLASH_CMD_CTRL_REG,Flash Command Control Register. This register controls SPI transactions generated by STIG. It allows to define corresponding SPI frame to particular command, triggering the transfer and polling for its completion."
hexmask.long.byte 0x00 24.--31. 1. " CMD_OPCODE_FLD                          ,Command Opcode."
bitfld.long 0x00 23. "        ENB_READ_DATA_FLD                          ,Read Data Enable. Set to 1 if the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires read data bytes to be received from the device." "0,1"
textline "                                                 "
bitfld.long 0x00 20.--22. " NUM_RD_DATA_BYTES_FLD                   ,Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19. "         ENB_COMD_ADDR_FLD                          ,Command Address Enable.Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field." "0,1"
textline "                                                 "
bitfld.long 0x00 18. " ENB_MODE_BIT_FLD                        ,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
bitfld.long 0x00 16.--17. "         NUM_ADDR_BYTES_FLD                         ,Number of Address Bytes. Set to the number of address bytes required [the address itself is programmed in the OSPI_FLASH_CMD_ADDR_REG. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD:0h = 1 address byte 1h = 2 address bytes 2h = 3 address bytes 3h = 4 address bytes" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 15. " ENB_WRITE_DATA_FLD                      ,Write Data Enable." "0,1"
bitfld.long 0x00 12.--14. "         NUM_WR_DATA_BYTES_FLD                      ,Number of Write Data Bytes." "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 7.--11. " NUM_DUMMY_CYCLES_FLD                    ,Number of Dummy cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--6. "        FLASH_CMD_CTRL_RESV1_FLD                   ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 2. " STIG_MEM_BANK_EN_FLD                    ,STIG Memory Bank enable bit." "0,1"
bitfld.long 0x00 1. "         CMD_EXEC_STATUS_FLD                        ,Command execution in progress." "0,1"
textline "                                                 "
bitfld.long 0x00 0. " CMD_EXEC_FLD                            ,Execute the command." "0,1"
group.long 0x94++0x3
line.long 0x00 "OSPI_FLASH_CMD_ADDR_REG,Flash Command Address Register. This register allows to define the address of the command using by the STIG controller. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Command Address."
rgroup.long 0xA0++0x3
line.long 0x00 "OSPI_FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower). This register keeps the last 4 bytes read by STIG SPI access."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Read Data (Lower)."
rgroup.long 0xA4++0x3
line.long 0x00 "OSPI_FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper). This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the register enables the controller to keep 8 last bytes read from the Flash Device using STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Read Data (Upper)."
group.long 0xA8++0x3
line.long 0x00 "OSPI_FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower). This register takes the first 4 bytes to be written by STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Write Data Lower Byte."
group.long 0xAC++0x3
line.long 0x00 "OSPI_FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper). This register takes the bytes ranging from 5 to 8 to be written by STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Write Data Upper Byte."
group.long 0xB0++0x3
line.long 0x00 "OSPI_POLLING_FLASH_STATUS_REG,Polling Flash Status Register. This register provides auto-polling data. It acts as the extension for the register where full status is not available and any action can be taken only relying on the indication of single bit being polled for."
hexmask.long.word 0x00 20.--31. 1. " DEVICE_STATUS_RSVD_FLD2                 ,Reserved"
bitfld.long 0x00 16.--19. "      DEVICE_STATUS_NB_DUMMY                     ,Number of dummy cycles for auto-polling." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
hexmask.long.byte 0x00 9.--15. 1. " DEVICE_STATUS_RSVD_FLD1                 ,Reserved"
bitfld.long 0x00 8. "        DEVICE_STATUS_VALID_FLD                    ,Device Status Valid." "0,1"
textline "                                                 "
hexmask.long.byte 0x00 0.--7. 1. " DEVICE_STATUS_FLD                       ,Defines actual Status Register of Device."
group.long 0xB4++0x3
line.long 0x00 "OSPI_PHY_CONFIGURATION_REG,PHY Configuration Register. This register defines the configuration of PHY Module and controls the internal DLL. This register should be setup while the controller is idle."
bitfld.long 0x00 31. " PHY_CONFIG_RESYNC_FLD                   ,Re-synchronisation DLL." "0,1"
bitfld.long 0x00 30. "         PHY_CONFIG_RESET_FLD                       ,DLL Reset." "0,1"
textline "                                                 "
bitfld.long 0x00 29. " PHY_CONFIG_RX_DLL_BYPASS_FLD            ,RX DLL Bypass." "0,1"
bitfld.long 0x00 23.--28. "         PHY_CONFIG_RESV2_FLD                       ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                 "
hexmask.long.byte 0x00 16.--22. 1. " PHY_CONFIG_TX_DLL_DELAY_FLD             ,TX DLL Delay."
hexmask.long.word 0x00 7.--15. 1. "        PHY_CONFIG_RESV1_FLD                       ,Reserved"
textline "                                                 "
hexmask.long.byte 0x00 0.--6. 1. " PHY_CONFIG_RX_DLL_DELAY_FLD             ,RX DLL Delay."
group.long 0xB8++0x3
line.long 0x00 "OSPI_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register. This register defines the configuration and control logic of DLL intended to work in DLL Master Mode."
hexmask.long.byte 0x00 25.--31. 1. " PHY_MASTER_CONTROL_RESV3_FLD            ,Reserved"
bitfld.long 0x00 24. "        PHY_MASTER_LOCK_MODE_FLD                   ,Determines if the master delay line locks on a full cycle or half cycle of delay. This bit need not be written by software. If DLL does not lock in full cycle, it will automatically try to lock in half cycle mode." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " PHY_MASTER_BYPASS_MODE_FLD              ,Controls the bypass mode of the master and slave DLLs.Master DLL is disabled with only 1 delay element in its delay line. The slave delay lines decode delays in absolute delay elements rather than as fractional delays.Delays are defined in" "0,1"
bitfld.long 0x00 20.--22. "         PHY_MASTER_PHASE_DETECT_SELECTOR_FLD       ,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 19. " PHY_MASTER_CONTROL_RESV2_FLD            ,Reserved" "0,1"
bitfld.long 0x00 16.--18. "         PHY_MASTER_NB_INDICATIONS_FLD              ,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7"
textline "                                                 "
hexmask.long.word 0x00 7.--15. 1. " PHY_MASTER_CONTROL_RESV1_FLD            ,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "      PHY_MASTER_INITIAL_DELAY_FLD               ,This value is the initial delay value for the Master DLL."
rgroup.long 0xBC++0x3
line.long 0x00 "OSPI_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower. This register allows to observe and debug DLL status."
hexmask.long.byte 0x00 24.--31. 1. " DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD   ,Holds the state of the cumulative lock incremental steps when the"
hexmask.long.byte 0x00 16.--23. 1. "        DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD      ,Holds the state of the cumulative lock decremental steps when the"
textline "                                                 "
bitfld.long 0x00 15. " DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD  ,This bit indicates that lock of loopback is done." "0,1"
hexmask.long.byte 0x00 8.--14. 1. "         DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD        ,DLL Lock Value."
textline "                                                 "
bitfld.long 0x00 3.--7. " DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD ,DLL Unlock Counter." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "        DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD         ,DLL Locked Mode." "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 0. " DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD       ,DLL Lock." "0,1"
rgroup.long 0xC0++0x3
line.long 0x00 "OSPI_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper. This register allows to observe and debug DLL status."
hexmask.long.word 0x00 23.--31. 1. " DLL_OBSERVABLE_UPPER_RESV2_FLD          ,Reserved"
hexmask.long.byte 0x00 16.--22. 1. "      DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD ,TX DLL decoder output."
textline "                                                 "
hexmask.long.word 0x00 7.--15. 1. " DLL_OBSERVABLE_UPPER_RESV1_FLD          ,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "      DLL_OBSERVABLE_UPPER_RX_DECODER_OUTPUT_FLD ,RX DLL decoder output."
group.long 0xE0++0x3
line.long 0x00 "OSPI_OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit."
hexmask.long.byte 0x00 24.--31. 1. " EXT_READ_OPCODE_FLD                     ,Supplement byte of any Read Opcoded defined in the"
hexmask.long.byte 0x00 16.--23. 1. "        EXT_WRITE_OPCODE_FLD                       ,Supplement byte of any Write Opcode defined in the"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " EXT_POLL_OPCODE_FLD                     ,Supplement byte of any Polling Opcode defined in the"
hexmask.long.byte 0x00 0.--7. 1. "        EXT_STIG_OPCODE_FLD                        ,Supplement byte of any STIG Opcode defined in the"
group.long 0xE4++0x3
line.long 0x00 "OSPI_OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit."
hexmask.long.byte 0x00 24.--31. 1. " WEL_OPCODE_FLD                          ,WEL Opcode byte 1."
hexmask.long.byte 0x00 16.--23. 1. "        EXT_WEL_OPCODE_FLD                         ,WEL Opcode byte 2 (Optional)."
textline "                                                 "
hexmask.long.word 0x00 0.--15. 1. " OPCODE_EXT_UPPER_RESV1_FLD              ,Reserved"
rgroup.long 0xFC++0x3
line.long 0x00 "OSPI_MODULE_ID_REG,Module ID Register. This register provides the IP release number and the configuration data."
hexmask.long.byte 0x00 24.--31. 1. " FIX_PATCH_FLD                           ,Fix/path number related to revision described by 3 LSBs of this register"
hexmask.long.word 0x00 8.--23. 1. "        MODULE_ID_FLD                              ,Module/Revision ID number"
textline "                                                 "
bitfld.long 0x00 2.--7. " MODULE_ID_RESV_FLD                      ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "        CONF_FLD                                   ,Configuration ID number:0h = OCTAL + PHY Configuration 1h = OCTAL Configuration 2h = QUAD + PHY Configuration 3h = QUAD Configuration" "0,1,2,3"
width 0x0B
tree.end
tree "MCU_FSS0_OSPI1_CTRL"
base ad:0x47050000
width 40.
group.long 0x0++0x3
line.long 0x00 "OSPI_CONFIG_REG,OSPI Configuration Register This register contains basic configuration fields of the controller. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
bitfld.long 0x00 31. " IDLE_FLD                                ,Serial interface and low level SPI pipeline is IDLE." "0,1"
bitfld.long 0x00 30. "         DUAL_BYTE_OPCODE_EN_FLD                    ,Dual-byte Opcode Mode enable bit." "0,1"
textline "                                                 "
bitfld.long 0x00 29. " CRC_ENABLE_FLD                          ,CRC enable bit." "0,1"
bitfld.long 0x00 26.--28. "         CONFIG_RESV2_FLD                           ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 25. " PIPELINE_PHY_FLD                        ,Pipeline PHY Mode enable." "0,1"
bitfld.long 0x00 24. "         ENABLE_DTR_PROTOCOL_FLD                    ,Enable DTR Protocol." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " ENABLE_AHB_DECODER_FLD                  ,Enable AHB Decoder. 0h = Active slave is selected based on the OSPI_CONFIG_REG[13:10] PERIPH_CS_LINES_FLD. 1h = Active slave is selected based on actual data interface address (the partition is calculated with respect to bits OSPI_DEV_SIZE_CONFIG_REG[28:21])." "0,1"
bitfld.long 0x00 19.--22. "         MSTR_BAUD_DIV_FLD                          ,Master mode baud rate divisor (2 to 32)," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 18. " ENTER_XIP_MODE_IMM_FLD                  ,Enter XIP Mode immediately.0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value=1h = Operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode [as per the contents of its non-volatile configuration register]. The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred.Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited." "0,1"
bitfld.long 0x00 17. "         ENTER_XIP_MODE_FLD                         ,Enter XIP Mode on next READ.0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction.1h = If XIP is disabled, then setting to 1 will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " ENB_AHB_ADDR_REMAP_FLD                  ,Enable Data Interface Address Remapping [Direct Access Mode Only]" "0,1"
bitfld.long 0x00 15. "         ENB_DMA_IF_FLD                             ,Enable DMA Peripheral Interface." "0,1"
textline "                                                 "
bitfld.long 0x00 14. " WR_PROT_FLASH_FLD                       ,Write Protect Flash Pin." "0,1"
bitfld.long 0x00 10.--13. "         PERIPH_CS_LINES_FLD                        ,Peripheral Chip Select Lines.If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0, ss[3:0] are output thus:ss[3:0]xxx0 xx01 x011 0111 1111 N_SS_OUT[3:0]11101101 1011 0111 1111 [no peripheral selected] . else ss[3:0] directly drives N_SS_OUT[3:0] ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 9. " PERIPH_SEL_DEC_FLD                      ,Peripheral select decode.0h = only 1 of 4 selects N_SS_OUT[3:0] is active,1h = allow external 4-to-16 decode [N_SS_OUT = ss]" "0,1"
bitfld.long 0x00 8. "         ENB_LEGACY_IP_MODE_FLD                     ,Legacy IP Mode Enable.0h = Use Direct Access Controller/Indirect Access Controller 1h = Legacy Mode is enabled. In this mode, any write to the controller via the data interface is serialized and sent to the FLASH device. Any valid data read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, 4, 2 or 1 byte transfers are permitted and controlled." "0,1"
textline "                                                 "
bitfld.long 0x00 7. " ENB_DIR_ACC_CTLR_FLD                    ,Enable Direct Access Controller.0h = Disable the Direct Access Controller once current transfer of the data word is complete.1h = Enable the Direct Access Controller. When the Direct Access Controller and Indirect Access Controller are both disabled, all data requests are completed with an error response." "0,1"
bitfld.long 0x00 6. "         RESET_CFG_FLD                              ,RESET pin configuration.0h = RESET feature on DQ3 pin of the device 1h = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]." "0,1"
textline "                                                 "
bitfld.long 0x00 5. " RESET_PIN_FLD                           ,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature." "0,1"
bitfld.long 0x00 4. "         HOLD_PIN_FLD                               ,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature." "0,1"
textline "                                                 "
bitfld.long 0x00 3. " PHY_MODE_ENABLE_FLD                     ,PHY mode enable." "0,1"
bitfld.long 0x00 2. "         SEL_CLK_PHASE_FLD                          ,Select Clock Phase.Selects whether the clock is in an active or inactive phase outside the SPI word 0h = The SPI clock is active outside the word 1h = The SPI clock is inactive outside the word" "0,1"
textline "                                                 "
bitfld.long 0x00 1. " SEL_CLK_POL_FLD                         ,Clock polarity outside SPI word.0h = The SPI clock is quiescent low 1h = The SPI clock is quiescent high" "0,1"
bitfld.long 0x00 0. "         ENB_SPI_FLD                                ,OSPI Enable.0h = Disable the OSPI, once current transfer of the data wordis complete.1h = Enable the OSPI, when this bit is set to 0, all output enables are inactive and all pins are set to input mode." "0,1"
group.long 0x4++0x3
line.long 0x00 "OSPI_DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register. This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " RD_INSTR_RESV5_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "         DUMMY_RD_CLK_CYCLES_FLD                    ,Dummy Read Clock Cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 21.--23. " RD_INSTR_RESV4_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20. "         MODE_BIT_ENABLE_FLD                        ,Mode Bit Enable." "0,1"
textline "                                                 "
bitfld.long 0x00 18.--19. " RD_INSTR_RESV3_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--17. "         DATA_XFER_TYPE_EXT_MODE_FLD                ,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Quad Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 14.--15. " RD_INSTR_RESV2_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         ADDR_XFER_TYPE_STD_MODE_FLD                ,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2, and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 11. " RD_INSTR_RESV1_FLD                      ,Reserved" "0,1"
bitfld.long 0x00 10. "         DDR_EN_FLD                                 ,DDR Enable." "0,1"
textline "                                                 "
bitfld.long 0x00 8.--9. " INSTR_TYPE_FLD                          ,Instruction Type.0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1h = Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2h = Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2, and DQ3] 3h = Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]]" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "         RD_OPCODE_NON_XIP_FLD                      ,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
group.long 0x8++0x3
line.long 0x00 "OSPI_DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register. This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " WR_INSTR_RESV4_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--28. "         DUMMY_WR_CLK_CYCLES_FLD                    ,Dummy Write Clock Cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
bitfld.long 0x00 18.--23. " WR_INSTR_RESV3_FLD                      ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--17. "        DATA_XFER_TYPE_EXT_MODE_FLD                ,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Quad Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 14.--15. " WR_INSTR_RESV2_FLD                      ,Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "         ADDR_XFER_TYPE_STD_MODE_FLD                ,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2. and DQ3 3h = Addresses can be shifted to the device on DQ[7:0]" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 9.--11. " WR_INSTR_RESV1_FLD                      ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "         WEL_DIS_FLD                                ,WEL Disable." "0,1"
textline "                                                 "
hexmask.long.byte 0x00 0.--7. 1. " WR_OPCODE_FLD                           ,Write Opcode"
group.long 0xC++0x3
line.long 0x00 "OSPI_DEV_DELAY_REG,OSPI Device Delay Register. This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the OSPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock. This register should be setup while the controller is idle."
hexmask.long.byte 0x00 24.--31. 1. " D_NSS_FLD                               ,Clock Delay for Chip Select Deassert."
hexmask.long.byte 0x00 16.--23. 1. "        D_BTWN_FLD                                 ,Clock Delay for Chip Select Deactivation."
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " D_AFTER_FLD                             ,Clock Delay for Last Transaction Bit."
hexmask.long.byte 0x00 0.--7. 1. "        D_INIT_FLD                                 ,Clock Delay with N_SS_OUT."
group.long 0x10++0x3
line.long 0x00 "OSPI_RD_DATA_CAPTURE_REG,Read Data Capture Register. This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle."
hexmask.long.word 0x00 20.--31. 1. " RD_DATA_RESV3_FLD                       ,Reserved"
bitfld.long 0x00 16.--19. "      DDR_READ_DELAY_FLD                         ,DDR read delay." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
hexmask.long.byte 0x00 9.--15. 1. " RD_DATA_RESV2_FLD                       ,Reserved"
bitfld.long 0x00 8. "        DQS_ENABLE_FLD                             ,DQS enable bit." "0,1"
textline "                                                 "
bitfld.long 0x00 6.--7. " RD_DATA_RESV1_FLD                       ,Reserved" "0,1,2,3"
bitfld.long 0x00 5. "         SAMPLE_EDGE_SEL_FLD                        ,Sample edge selection." "0,1"
textline "                                                 "
bitfld.long 0x00 1.--4. " DELAY_FLD                               ,Read Delay." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        BYPASS_FLD                                 ,Bypass." "0,1"
group.long 0x14++0x3
line.long 0x00 "OSPI_DEV_SIZE_CONFIG_REG,Device Size Configuration Register. This register allows to define the memory organization of using Flash Devices. This register should be setup while the controller is idle."
bitfld.long 0x00 29.--31. " DEV_SIZE_RESV_FLD                       ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 27.--28. "         MEM_SIZE_ON_CS3_FLD                        ,Size of Flash Device connected to CS[3] pin:0h = size of 512Mb 1h = size of 1Gb2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 25.--26. " MEM_SIZE_ON_CS2_FLD                     ,Size of Flash Device connected to CS[2] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
bitfld.long 0x00 23.--24. "         MEM_SIZE_ON_CS1_FLD                        ,Size of Flash Device connected to CS[1] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 21.--22. " MEM_SIZE_ON_CS0_FLD                     ,Size of Flash Device connected to CS[0] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3"
bitfld.long 0x00 16.--20. "         BYTES_PER_SUBSECTOR_FLD                    ,Number of bytes per Block." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                 "
hexmask.long.word 0x00 4.--15. 1. " BYTES_PER_DEVICE_PAGE_FLD               ,Number of bytes per device page."
bitfld.long 0x00 0.--3. "      NUM_ADDR_BYTES_FLD                         ,Number of address bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "OSPI_SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register."
hexmask.long.tbyte 0x00 8.--31. 1. " SRAM_PARTITION_RESV_FLD                 ,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "    ADDR_FLD                                   ,Indirect Read Partition Size."
group.long 0x1C++0x3
line.long 0x00 "OSPI_IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register. This register allowsto define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Indirect Trigger Address."
group.long 0x20++0x3
line.long 0x00 "OSPI_DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register. This register allows to define the parameters of DMA peripheral controller. This register should be setup while the controller is idle. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long.tbyte 0x00 12.--31. 1. " DMA_PERIPH_RESV2_FLD                    ,Reserved"
bitfld.long 0x00 8.--11. "    NUM_BURST_REQ_BYTES_FLD                    ,Number of Burst Bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 4.--7. " DMA_PERIPH_RESV1_FLD                    ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        NUM_SINGLE_REQ_BYTES_FLD                   ,Number of Single Bytes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x3
line.long 0x00 "OSPI_REMAP_ADDR_REG,Remap Address Register. This register allows to define the address offset for DAC accesses. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,This register is used to remap an incoming data address to a different address used by the FLASH device."
group.long 0x28++0x3
line.long 0x00 "OSPI_MODE_BIT_CONFIG_REG,Mode Bit Configuration Register. This register allows to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle."
hexmask.long.byte 0x00 24.--31. 1. " RX_CRC_DATA_LOW_FLD                     ,RX CRC data [lower]."
hexmask.long.byte 0x00 16.--23. 1. "        RX_CRC_DATA_UP_FLD                         ,RX CRC data [upper]."
textline "                                                 "
bitfld.long 0x00 15. " CRC_OUT_ENABLE_FLD                      ,CRC# output enable bit." "0,1"
bitfld.long 0x00 11.--14. "         MODE_BIT_RESV1_FLD                         ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 8.--10. " CHUNK_SIZE_FLD                          ,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MODE_FLD                                   ,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled."
rgroup.long 0x2C++0x3
line.long 0x00 "OSPI_SRAM_FILL_REG,SRAM Fill Register. This register keeps the values of current fill levels of both SRAM partitions."
hexmask.long.word 0x00 16.--31. 1. " SRAM_FILL_INDAC_WRITE_FLD               ,SRAM Fill Level [Indirect Write Partition]."
hexmask.long.word 0x00 0.--15. 1. "      SRAM_FILL_INDAC_READ_FLD                   ,SRAM Fill Level [Indirect Read Partition]."
group.long 0x30++0x3
line.long 0x00 "OSPI_TX_THRESH_REG,TX Threshold Register. This register allows to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle."
hexmask.long 0x00 5.--31. 1. " TX_THRESH_RESV_FLD                      ,Reserved"
bitfld.long 0x00 0.--4. "  LEVEL_FLD                                  ,Defines the level at which the small TX FIFO not full interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "OSPI_RX_THRESH_REG,RX Threshold Register. This register allows to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle."
hexmask.long 0x00 5.--31. 1. " RX_THRESH_RESV_FLD                      ,Reserved"
bitfld.long 0x00 0.--4. "  LEVEL_FLD                                  ,Defines the level at which the small RX FIFO not empty interrupt is generated." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x3
line.long 0x00 "OSPI_WRITE_COMPLETION_CTRL_REG,Write Completion Control Register. This register defines how the controller will poll the device following a write transfer."
hexmask.long.byte 0x00 24.--31. 1. " POLL_REP_DELAY_FLD                      ,Polling repetition delay."
hexmask.long.byte 0x00 16.--23. 1. "        POLL_COUNT_FLD                             ,Polling count."
textline "                                                 "
bitfld.long 0x00 15. " ENABLE_POLLING_EXP_FLD                  ,Enable polling expiration." "0,1"
bitfld.long 0x00 14. "         DISABLE_POLLING_FLD                        ,Disable polling." "0,1"
textline "                                                 "
bitfld.long 0x00 13. " POLLING_POLARITY_FLD                    ,Polling polarity." "0,1"
bitfld.long 0x00 11.--12. "         WR_COMP_CTRL_RESV1_FLD                     ,Reserved" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 8.--10. " POLLING_BIT_INDEX_FLD                   ,Polling bit index." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         OPCODE_FLD                                 ,Polling opcode."
group.long 0x3C++0x3
line.long 0x00 "OSPI_NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register. This register defines maximum number of poll cycles. If the expected value of the bit being polled is not gotten after number defined in this register, the auto-polling is done on the next phase."
hexmask.long 0x00 0.--31. 1. " NO_OF_POLLS_BEF_EXP_FLD                 ,Defines the numbers of poll cycles after which auto-polling phase terminates and polling expiration interrupt is generated."
hgroup.long 0x40++0x3
hide.long 0x00 "OSPI_IRQ_STATUS_REG,Interrupt Status Register. The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 through 10 are only valid when legacy SPI mode is active."
in
textline "                                                 "
group.long 0x44++0x3
line.long 0x00 "OSPI_IRQ_MASK_REG,Interrupt Mask Register. This register allows the user to mask/unmask particular interrupt sources. This register should be setup while the controller is idle. 0h = the interrupt for the corresponding interrupt status register bit is disabled. 1h = the interrupt for the corresponding interrupt status register bit is enabled."
hexmask.long.word 0x00 20.--31. 1. " IRQ_MASK_RESV_FLD                       ,Reserved"
bitfld.long 0x00 19. "      ECC_FAIL_MASK_FLD                          ,ECC failure Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 18. " TX_CRC_CHUNK_BRK_MASK_FLD               ,TX CRC chunk was broken Mask" "0,1"
bitfld.long 0x00 17. "         RX_CRC_DATA_VAL_MASK_FLD                   ,RX CRC data valid Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 16. " RX_CRC_DATA_ERR_MASK_FLD                ,RX CRC data error Mask" "0,1"
bitfld.long 0x00 15. "         IRQ_MASK_RESV1_FLD                         ,Reserved" "0,1"
textline "                                                 "
bitfld.long 0x00 14. " STIG_REQ_MASK_FLD                       ,STIG request completion Mask" "0,1"
bitfld.long 0x00 13. "         POLL_EXP_INT_MASK_FLD                      ,Polling expiration detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 12. " INDRD_SRAM_FULL_MASK_FLD                ,Indirect Read Partition overflow mask" "0,1"
bitfld.long 0x00 11. "         RX_FIFO_FULL_MASK_FLD                      ,Small RX FIFO full Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 10. " RX_FIFO_NOT_EMPTY_MASK_FLD              ,Small RX FIFO not empty Mask" "0,1"
bitfld.long 0x00 9. "         TX_FIFO_FULL_MASK_FLD                      ,Small TX FIFO full Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 8. " TX_FIFO_NOT_FULL_MASK_FLD               ,Small TX FIFO not full Mask" "0,1"
bitfld.long 0x00 7. "         RECV_OVERFLOW_MASK_FLD                     ,Receive Overflow Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 6. " INDIRECT_XFER_LEVEL_BREACH_MASK_FLD     ,Transfer Watermark Breach Mask" "0,1"
bitfld.long 0x00 5. "         ILLEGAL_ACCESS_DET_MASK_FLD                ,Illegal Access Detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 4. " PROT_WR_ATTEMPT_MASK_FLD                ,Protected Area Write Attempt Mask" "0,1"
bitfld.long 0x00 3. "         INDIRECT_READ_REJECT_MASK_FLD              ,Indirect Read Reject Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 2. " INDIRECT_OP_DONE_MASK_FLD               ,Indirect Complete Mask" "0,1"
bitfld.long 0x00 1. "         UNDERFLOW_DET_MASK_FLD                     ,Underflow Detected Mask" "0,1"
textline "                                                 "
bitfld.long 0x00 0. " MODE_M_FAIL_MASK_FLD                    ,Mode M Failure Mask" "0,1"
group.long 0x50++0x3
line.long 0x00 "OSPI_LOWER_WR_PROT_REG,Lower Write Protection Register. This register allows to define lower boundary of the write protection area. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " SUBSECTOR_FLD                           ,Lower Block Number.The block number that defines the lower block in the range of blocks that is to be locked from writing."
group.long 0x54++0x3
line.long 0x00 "OSPI_UPPER_WR_PROT_REG,Upper Write Protection Register. This register allows to define upper boundary of the write protection area. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " SUBSECTOR_FLD                           ,Lower Block Number."
group.long 0x58++0x3
line.long 0x00 "OSPI_WR_PROT_CTRL_REG,Write Protection Control Register. This register allows to define the configuration of write protection settings. This register should be setup while the controller is idle."
hexmask.long 0x00 2.--31. 1. " WR_PROT_CTRL_RESV_FLD                   ,Reserved"
bitfld.long 0x00 1. "  ENB_FLD                                    ,Write Protection Enable Bit." "0,1"
textline "                                                 "
bitfld.long 0x00 0. " INV_FLD                                 ,Write Protection Inversion Bit." "0,1"
hgroup.long 0x60++0x3
hide.long 0x00 "OSPI_INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register. This register allows control of the Indirect Read Transfer logic."
in
textline "                                                 "
group.long 0x64++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register. This register allows to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long 0x00 0.--31. 1. " LEVEL_FLD                               ,Watermark Value."
group.long 0x68++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register. This register allows to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Start of Indirect Access."
group.long 0x6C++0x3
line.long 0x00 "OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register. This register allows to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,Indirect Number of Bytes."
hgroup.long 0x70++0x3
hide.long 0x00 "OSPI_INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register. This register allows control of the Indirect Write Transfer logic."
in
textline "                                                 "
group.long 0x74++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register. This register allows to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered. Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see , OSPI Not Supported Features."
hexmask.long 0x00 0.--31. 1. " LEVEL_FLD                               ,Watermark Value."
group.long 0x78++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register. This register allows to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is triggered."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Start of Indirect Access."
group.long 0x7C++0x3
line.long 0x00 "OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register. This register allows to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 0.--31. 1. " VALUE_FLD                               ,Indirect Number of Bytes."
group.long 0x80++0x3
line.long 0x00 "OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register. This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer, there is no need to detect indirect trigger address boundaries by software. This register should be setup before an indirect read transfer is triggered."
hexmask.long 0x00 4.--31. 1. " IND_RANGE_RESV1_FLD                     ,Reserved"
bitfld.long 0x00 0.--3. "  IND_RANGE_WIDTH_FLD                        ,Indirect Range Width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C++0x3
line.long 0x00 "OSPI_FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register. This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank."
bitfld.long 0x00 29.--31. " FLASH_COMMAND_CTRL_MEM_RESV1_FLD        ,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 20.--28. 1. "         MEM_BANK_ADDR_FLD                          ,Memory Bank Address."
textline "                                                 "
bitfld.long 0x00 19. " FLASH_COMMAND_CTRL_MEM_RESV2_FLD        ,Reserved" "0,1"
bitfld.long 0x00 16.--18. "         NB_OF_STIG_READ_BYTES_FLD                  ,Number of STIG Memory Bank Read Bytes." "0,1,2,3,4,5,6,7"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " MEM_BANK_READ_DATA_FLD                  ,Memory Bank Read Data."
bitfld.long 0x00 2.--7. "        FLASH_COMMAND_CTRL_MEM_RESV3_FLD           ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                 "
bitfld.long 0x00 1. " MEM_BANK_REQ_IN_PROGRESS_FLD            ,Memory Bank data request in progress." "0,1"
bitfld.long 0x00 0. "         TRIGGER_MEM_BANK_REQ_FLD                   ,Trigger the Memory Bank data request." "0,1"
group.long 0x90++0x3
line.long 0x00 "OSPI_FLASH_CMD_CTRL_REG,Flash Command Control Register. This register controls SPI transactions generated by STIG. It allows to define corresponding SPI frame to particular command, triggering the transfer and polling for its completion."
hexmask.long.byte 0x00 24.--31. 1. " CMD_OPCODE_FLD                          ,Command Opcode."
bitfld.long 0x00 23. "        ENB_READ_DATA_FLD                          ,Read Data Enable. Set to 1 if the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires read data bytes to be received from the device." "0,1"
textline "                                                 "
bitfld.long 0x00 20.--22. " NUM_RD_DATA_BYTES_FLD                   ,Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19. "         ENB_COMD_ADDR_FLD                          ,Command Address Enable.Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field." "0,1"
textline "                                                 "
bitfld.long 0x00 18. " ENB_MODE_BIT_FLD                        ,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
bitfld.long 0x00 16.--17. "         NUM_ADDR_BYTES_FLD                         ,Number of Address Bytes. Set to the number of address bytes required [the address itself is programmed in the OSPI_FLASH_CMD_ADDR_REG. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD:0h = 1 address byte 1h = 2 address bytes 2h = 3 address bytes 3h = 4 address bytes" "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 15. " ENB_WRITE_DATA_FLD                      ,Write Data Enable." "0,1"
bitfld.long 0x00 12.--14. "         NUM_WR_DATA_BYTES_FLD                      ,Number of Write Data Bytes." "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 7.--11. " NUM_DUMMY_CYCLES_FLD                    ,Number of Dummy cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--6. "        FLASH_CMD_CTRL_RESV1_FLD                   ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
bitfld.long 0x00 2. " STIG_MEM_BANK_EN_FLD                    ,STIG Memory Bank enable bit." "0,1"
bitfld.long 0x00 1. "         CMD_EXEC_STATUS_FLD                        ,Command execution in progress." "0,1"
textline "                                                 "
bitfld.long 0x00 0. " CMD_EXEC_FLD                            ,Execute the command." "0,1"
group.long 0x94++0x3
line.long 0x00 "OSPI_FLASH_CMD_ADDR_REG,Flash Command Address Register. This register allows to define the address of the command using by the STIG controller. This register should be setup while the controller is idle."
hexmask.long 0x00 0.--31. 1. " ADDR_FLD                                ,Command Address."
rgroup.long 0xA0++0x3
line.long 0x00 "OSPI_FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower). This register keeps the last 4 bytes read by STIG SPI access."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Read Data (Lower)."
rgroup.long 0xA4++0x3
line.long 0x00 "OSPI_FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper). This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the register enables the controller to keep 8 last bytes read from the Flash Device using STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Read Data (Upper)."
group.long 0xA8++0x3
line.long 0x00 "OSPI_FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower). This register takes the first 4 bytes to be written by STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Write Data Lower Byte."
group.long 0xAC++0x3
line.long 0x00 "OSPI_FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper). This register takes the bytes ranging from 5 to 8 to be written by STIG."
hexmask.long 0x00 0.--31. 1. " DATA_FLD                                ,Command Write Data Upper Byte."
group.long 0xB0++0x3
line.long 0x00 "OSPI_POLLING_FLASH_STATUS_REG,Polling Flash Status Register. This register provides auto-polling data. It acts as the extension for the register where full status is not available and any action can be taken only relying on the indication of single bit being polled for."
hexmask.long.word 0x00 20.--31. 1. " DEVICE_STATUS_RSVD_FLD2                 ,Reserved"
bitfld.long 0x00 16.--19. "      DEVICE_STATUS_NB_DUMMY                     ,Number of dummy cycles for auto-polling." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                 "
hexmask.long.byte 0x00 9.--15. 1. " DEVICE_STATUS_RSVD_FLD1                 ,Reserved"
bitfld.long 0x00 8. "        DEVICE_STATUS_VALID_FLD                    ,Device Status Valid." "0,1"
textline "                                                 "
hexmask.long.byte 0x00 0.--7. 1. " DEVICE_STATUS_FLD                       ,Defines actual Status Register of Device."
group.long 0xB4++0x3
line.long 0x00 "OSPI_PHY_CONFIGURATION_REG,PHY Configuration Register. This register defines the configuration of PHY Module and controls the internal DLL. This register should be setup while the controller is idle."
bitfld.long 0x00 31. " PHY_CONFIG_RESYNC_FLD                   ,Re-synchronisation DLL." "0,1"
bitfld.long 0x00 30. "         PHY_CONFIG_RESET_FLD                       ,DLL Reset." "0,1"
textline "                                                 "
bitfld.long 0x00 29. " PHY_CONFIG_RX_DLL_BYPASS_FLD            ,RX DLL Bypass." "0,1"
bitfld.long 0x00 23.--28. "         PHY_CONFIG_RESV2_FLD                       ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                 "
hexmask.long.byte 0x00 16.--22. 1. " PHY_CONFIG_TX_DLL_DELAY_FLD             ,TX DLL Delay."
hexmask.long.word 0x00 7.--15. 1. "        PHY_CONFIG_RESV1_FLD                       ,Reserved"
textline "                                                 "
hexmask.long.byte 0x00 0.--6. 1. " PHY_CONFIG_RX_DLL_DELAY_FLD             ,RX DLL Delay."
group.long 0xB8++0x3
line.long 0x00 "OSPI_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register. This register defines the configuration and control logic of DLL intended to work in DLL Master Mode."
hexmask.long.byte 0x00 25.--31. 1. " PHY_MASTER_CONTROL_RESV3_FLD            ,Reserved"
bitfld.long 0x00 24. "        PHY_MASTER_LOCK_MODE_FLD                   ,Determines if the master delay line locks on a full cycle or half cycle of delay. This bit need not be written by software. If DLL does not lock in full cycle, it will automatically try to lock in half cycle mode." "0,1"
textline "                                                 "
bitfld.long 0x00 23. " PHY_MASTER_BYPASS_MODE_FLD              ,Controls the bypass mode of the master and slave DLLs.Master DLL is disabled with only 1 delay element in its delay line. The slave delay lines decode delays in absolute delay elements rather than as fractional delays.Delays are defined in" "0,1"
bitfld.long 0x00 20.--22. "         PHY_MASTER_PHASE_DETECT_SELECTOR_FLD       ,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7"
textline "                                                 "
bitfld.long 0x00 19. " PHY_MASTER_CONTROL_RESV2_FLD            ,Reserved" "0,1"
bitfld.long 0x00 16.--18. "         PHY_MASTER_NB_INDICATIONS_FLD              ,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7"
textline "                                                 "
hexmask.long.word 0x00 7.--15. 1. " PHY_MASTER_CONTROL_RESV1_FLD            ,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "      PHY_MASTER_INITIAL_DELAY_FLD               ,This value is the initial delay value for the Master DLL."
rgroup.long 0xBC++0x3
line.long 0x00 "OSPI_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower. This register allows to observe and debug DLL status."
hexmask.long.byte 0x00 24.--31. 1. " DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD   ,Holds the state of the cumulative lock incremental steps when the"
hexmask.long.byte 0x00 16.--23. 1. "        DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD      ,Holds the state of the cumulative lock decremental steps when the"
textline "                                                 "
bitfld.long 0x00 15. " DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD  ,This bit indicates that lock of loopback is done." "0,1"
hexmask.long.byte 0x00 8.--14. 1. "         DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD        ,DLL Lock Value."
textline "                                                 "
bitfld.long 0x00 3.--7. " DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD ,DLL Unlock Counter." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--2. "        DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD         ,DLL Locked Mode." "0,1,2,3"
textline "                                                 "
bitfld.long 0x00 0. " DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD       ,DLL Lock." "0,1"
rgroup.long 0xC0++0x3
line.long 0x00 "OSPI_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper. This register allows to observe and debug DLL status."
hexmask.long.word 0x00 23.--31. 1. " DLL_OBSERVABLE_UPPER_RESV2_FLD          ,Reserved"
hexmask.long.byte 0x00 16.--22. 1. "      DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD ,TX DLL decoder output."
textline "                                                 "
hexmask.long.word 0x00 7.--15. 1. " DLL_OBSERVABLE_UPPER_RESV1_FLD          ,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "      DLL_OBSERVABLE_UPPER_RX_DECODER_OUTPUT_FLD ,RX DLL decoder output."
group.long 0xE0++0x3
line.long 0x00 "OSPI_OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit."
hexmask.long.byte 0x00 24.--31. 1. " EXT_READ_OPCODE_FLD                     ,Supplement byte of any Read Opcoded defined in the"
hexmask.long.byte 0x00 16.--23. 1. "        EXT_WRITE_OPCODE_FLD                       ,Supplement byte of any Write Opcode defined in the"
textline "                                                 "
hexmask.long.byte 0x00 8.--15. 1. " EXT_POLL_OPCODE_FLD                     ,Supplement byte of any Polling Opcode defined in the"
hexmask.long.byte 0x00 0.--7. 1. "        EXT_STIG_OPCODE_FLD                        ,Supplement byte of any STIG Opcode defined in the"
group.long 0xE4++0x3
line.long 0x00 "OSPI_OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit."
hexmask.long.byte 0x00 24.--31. 1. " WEL_OPCODE_FLD                          ,WEL Opcode byte 1."
hexmask.long.byte 0x00 16.--23. 1. "        EXT_WEL_OPCODE_FLD                         ,WEL Opcode byte 2 (Optional)."
textline "                                                 "
hexmask.long.word 0x00 0.--15. 1. " OPCODE_EXT_UPPER_RESV1_FLD              ,Reserved"
rgroup.long 0xFC++0x3
line.long 0x00 "OSPI_MODULE_ID_REG,Module ID Register. This register provides the IP release number and the configuration data."
hexmask.long.byte 0x00 24.--31. 1. " FIX_PATCH_FLD                           ,Fix/path number related to revision described by 3 LSBs of this register"
hexmask.long.word 0x00 8.--23. 1. "        MODULE_ID_FLD                              ,Module/Revision ID number"
textline "                                                 "
bitfld.long 0x00 2.--7. " MODULE_ID_RESV_FLD                      ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "        CONF_FLD                                   ,Configuration ID number:0h = OCTAL + PHY Configuration 1h = OCTAL Configuration 2h = QUAD + PHY Configuration 3h = QUAD Configuration" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree.end
tree "PCIE_CORE_EP"
tree "PCIE_DAT"
tree "PCIE0_DAT"
base ad:0x5500000
width 53.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_RC_PID,Peripheral Version and ID Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                                 ,Module ID of the Peripheral"
bitfld.long 0x00 11.--15. "      RTL                                     ,RTL Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 8.--10. " MAJOR                                 ,Major Revision Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                  ,Custom Code" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 0.--5. " MINOR                                 ,Minor Revision Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "PCIE_RC_CMD_STATUS,Command Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. " RSVD11                                ,Reserved"
bitfld.long 0x00 7. "    RX_LANE_FLIP_EN                         ,Set to enable manual reversal for RX lanes. This drives the rx_lane_flip_en input of the PCIe core" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " TX_LANE_FLIP_EN                       ,Set to enable manual reversal for TX lanes. This drives the tx_lane_flip_en input of the PCIe core" "0,1"
bitfld.long 0x00 5. "         DBI_CS2                                 ,Set to enable writing to BAR mask registers that are overlaid on BAR registers." "0,1"
textline "                                                              "
bitfld.long 0x00 4. " APP_RETRY_EN                          ,Application Request Retry Enable. Setting this bit will enable all incoming PCIe transactions to be returned with a retry response. This feature can be used if initialization can take longer than PCIe stipulated time frame." "0,1"
bitfld.long 0x00 1.--3. "         RSVD10                                  ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " LTSSM_EN                              ,Link Training Enable. Setting this bit will enable LTSSM in PCI Express Core and link negotiation with link partner will begin." "0,1"
group.long 0x14++0x3
line.long 0x00 "PCIE_RC_RSTCMD,Reset Command and Status Register"
bitfld.long 0x00 29.--31. " RSVD21                                ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "         FLR_PF_ACTIVE                           ,Function-level reset for physical function active. 1 - FLR for Physical function 0 is active" "0,1"
textline "                                                              "
hexmask.long 0x00 1.--27. 1. " RSVD20                                ,Reserved"
bitfld.long 0x00 0. "  INIT_RST                                ,Write one to initiate a downstream hot reset sequence on downstream" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_RC_PTMCFG,PTM Config register"
hexmask.long.tbyte 0x00 14.--31. 1. " RSVD32                                ,Reserved"
bitfld.long 0x00 8.--13. "    PTM_CLK_SEL                             ,Select ptm_local_clk bit input to CPTS. 0 will select ptm_local_clk[0], 1 will select ptm_local_clk[1] ... 63 will select ptm_local_clk[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVD30                                ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_CONTEXT_VALID                       ,'1' indicates PTM context is valid-EP only" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_MANUAL_UPDATE                     ,Write '1' to enable PTM transaction.EP only. EP will initiate one PTM transaction when this field is updated. Always reads '0'" "0,1"
bitfld.long 0x00 0. "         PTM_AUTO_UPDATE                         ,Write '1' to enable PTM auto-update-EP only. EP will automatically initiate PTM transaction every 10ms" "0,1"
group.long 0x20++0x3
line.long 0x00 "PCIE_RC_PMCMD,Power Management Command Register"
hexmask.long 0x00 2.--31. 1. " RSVD40                                ,Reserved"
bitfld.long 0x00 1. "  PM_XMT_TURNOFF                          ,Write one to transmit a PM_TURNOFF message. Reads zero. Applicable in RC mode only." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_XMT_PE                             ,Write one to transmit a PM_PME message for Physical Function 0. Reads zero. Applicable to EP mode only." "0,1"
group.long 0x50++0x3
line.long 0x00 "PCIE_RC_IRQ_EOI,End of Interrupt Register"
hexmask.long 0x00 5.--31. 1. " RSVD60                                ,Reserved"
bitfld.long 0x00 0.--3. "  EOI                                     ,EOI for interrupts. Write to indicate end-of-interrupt for the respective interrupt. EOI value has to be the following as indicated below to toggle the interrupts in the various interrupt registers EOI = 0 for LEGACY_A_IRQ, EOI = 1 for LEGACY_B_IRQ, EOI = 2 for LEGACY_C_IRQ, EOI = 3 for LEGACY_D_IRQ, EOI = 4 for MMR0_IRQ, EOI = 5 for MMR1_IRQ, EOI = 6 for MMR2_IRQ, EOI = 7 for MMR3_IRQ, EOI = 8 for MMR4_IRQ, EOI = 9 for MMR5_IRQ, EOI = 10 for MMR6_IRQ, EOI = 11 for MMR7_IRQ, EOI = 12 for ERR_IRQ, EOI = 13 for PMRST_IRQ, EOI = 14 for PTM_IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "PCIE_RC_MMR_IRQ,Memory Mapped Interrupt IRQ Register"
hexmask.long 0x00 0.--30. 1. " MMR_IRQ                               ,This register is not used in RC mode."
group.long 0x64++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_SET,Legacy Interrupt Request Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD70                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_SET_0                        ,Write one to generate assert legacy PCI interrupt message for Physical Function0. On read, a one indicates currently asserted interrupt." "0,1"
hgroup.long 0x68++0x3
hide.long 0x00 "PCIE_RC_LEGACY_IRQ_CLR,Legacy Interrupt Request Clear Register"
in
textline "                                                              "
rgroup.long 0x6C++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_STATUS,Legacy Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD90                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_STATUS_0                     ,Indicates whether legacy PCI interrupt for physical function 0 is asserted or not" "0,1"
group.long 0x70++0x3
line.long 0x00 "PCIE_RC_GPR0,General Purpose 0 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC0                              ,Generic Info field 0"
group.long 0x74++0x3
line.long 0x00 "PCIE_RC_GPR1,General Purpose 1 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC1                              ,Generic Info field 1"
group.long 0x78++0x3
line.long 0x00 "PCIE_RC_GPR2,General Purpose 2 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC2                              ,Generic Info field 2"
group.long 0x7C++0x3
line.long 0x00 "PCIE_RC_GPR3,General Purpose 3 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC3                              ,Generic Info field 3"
group.long 0x100++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS_RAW,MMR 0 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD100                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (24, 16, 8, 0) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x104++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS,MMR 0 Interrupt Status Register"
in
textline "                                                              "
group.long 0x108++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_SET,MMR 0 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD111                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (24, 16, 8, 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x10C++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_CLR,MMR 0 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x110++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS_RAW,MMR 1 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD120                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (25, 17, 9, 1) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x114++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS,MMR 1 Interrupt Status Register"
in
textline "                                                              "
group.long 0x118++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_SET,MMR 1 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD122                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (25, 17, 9, 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x11C++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_CLR,MMR 1 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x120++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS_RAW,MMR 2 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD130                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (26, 18, 10, 2) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x124++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS,MMR 2 Interrupt Status Register"
in
textline "                                                              "
group.long 0x128++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_SET,MMR 2 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD132                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (26, 18, 10, 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x12C++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_CLR,MMR 2 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x130++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS_RAW,MMR 3 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD140                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (27, 19, 11, 3) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x134++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS,MMR 3 Interrupt Status Register"
in
textline "                                                              "
group.long 0x138++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_SET,MMR 3 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD142                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (27, 19, 11, 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x13C++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_CLR,MMR 3 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x140++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS_RAW,MMR 4 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD150                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (28, 20, 12, 4) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x144++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS,MMR 4 Interrupt Status Register"
in
textline "                                                              "
group.long 0x148++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_SET,MMR 4 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD152                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (28, 20, 12, 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x14C++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_CLR,MMR 4 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x150++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS_RAW,MMR 5 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD160                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (29, 21, 13, 5) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x154++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS,MMR 5 Interrupt Status Register"
in
textline "                                                              "
group.long 0x158++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_SET,MMR 5 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD162                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (29, 21, 13, 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x15C++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_CLR,MMR 5 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x160++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS_RAW,MMR 6 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD170                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (30, 22, 14, 6) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x164++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS,MMR 6 Interrupt Status Register"
in
textline "                                                              "
group.long 0x168++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_SET,MMR 6 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD172                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (30, 22, 14, 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x16C++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_CLR,MMR 6 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x170++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS_RAW,MMR 7 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD180                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_STATUS_RAW                     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x174++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS,MMR 7 Interrupt Status Register"
in
textline "                                                              "
group.long 0x178++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_SET,MMR 7 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD182                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (31, 23, 15, 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x17C++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_CLR,MMR 7 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x180++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS_RAW,Legacy A Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD200                               ,Reserved"
bitfld.long 0x00 0. "  INTA_RAW                                ,Legacy Interrupt A raw status. RC mode only" "0,1"
hgroup.long 0x184++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS,Legacy A Raw Interrupt Status Register"
in
textline "                                                              "
group.long 0x188++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_SET,Legacy A Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD220                               ,Reserved"
bitfld.long 0x00 0. "  INTA_EN_SET                             ,Legacy Interrupt A enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x18C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_CLR,Legacy A Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x190++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS_RAW,Legacy B Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD300                               ,Reserved"
bitfld.long 0x00 0. "  INTB_RAW                                ,Legacy Interrupt B raw status. RC mode only" "0,1"
hgroup.long 0x194++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS,Legacy B Interrupt Status Register"
in
textline "                                                              "
group.long 0x198++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_SET,Legacy B Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD320                               ,Reserved"
bitfld.long 0x00 0. "  INTB_EN_SET                             ,Legacy Interrupt B enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x19C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_CLR,Legacy B Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1A0++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS_RAW,Legacy C Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD400                               ,Reserved"
bitfld.long 0x00 0. "  INTC_RAW                                ,Legacy Interrupt C raw status. RC mode only" "0,1"
hgroup.long 0x1A4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS,Legacy C Interrupt Status Register"
in
textline "                                                              "
group.long 0x1A8++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_SET,Legacy C Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD420                               ,Reserved"
bitfld.long 0x00 0. "  INTC_EN_SET                             ,Legacy Interrupt C enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1AC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_CLR,Legacy C Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1B0++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS_RAW,Legacy D Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD500                               ,Reserved"
bitfld.long 0x00 0. "  INTD_RAW                                ,Legacy Interrupt D raw status. RC mode only" "0,1"
hgroup.long 0x1B4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS,Legacy D Interrupt Status Register"
in
textline "                                                              "
group.long 0x1B8++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_SET,Legacy D Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD520                               ,Reserved"
bitfld.long 0x00 0. "  INTD_EN_SET                             ,Legacy Interrupt D enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1BC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_CLR,Legacy D Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1C0++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status Register"
hexmask.long 0x00 5.--31. 1. " RSVD600                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_RAW                             ,AER MSI error raw status. This interrupt is generated due to the assertion of the cfg_aer_rc_err_int or the cfg_aer_err_msi output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_RAW                          ,Correctable error raw status. This interrupt is generated due to the assertion of the radm_correctable_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_RAW                        ,Nonfatal error raw status. This interrupt is generated due to the assertion of the radm_nonfatal_err output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_RAW                         ,Fatal error raw status. This interrupt is generated due to the assertion of the radm_fatal_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_RAW                             ,System Error (FATAL, NONFATAL or CORRECTABLE error) raw status. This interrupt is generated due to the assertion of the cfg_sys_err_rc output of the PCIe controller core." "0,1"
hgroup.long 0x1C4++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_STATUS,"
in
textline "                                                              "
group.long 0x1C8++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_SET,"
hexmask.long 0x00 5.--31. 1. " RSVD620                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_EN_SET                          ,AER MSI error interrupt enable. Set to enable. On read, one/zero means enabled/disabled respectively" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_EN_SET                       ,Correctable error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_EN_SET                     ,Nonfatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_EN_SET                      ,Fatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_EN_SET                          ,System Error (FATAL, NONFATAL or CORRECTABLE error) interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1CC++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_CLR,"
in
textline "                                                              "
group.long 0x1D0++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD700                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_RAW                         ,Link Request Reset interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_RAW                            ,Power Management PME message received interrupt raw status" "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_RAW                           ,Power Management ACK received interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_RAW                        ,Power Management Turnoff message received raw status" "0,1"
hgroup.long 0x1D4++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS,Power Management and Reset Interrupt Status Register"
in
textline "                                                              "
group.long 0x1D8++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_SET,Power Management and Reset Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD720                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_EN_SET                      ,Link Request Reset interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_EN_SET                         ,Power Management PME message received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_EN_SET                        ,Power Management ACK received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_EN_SET                     ,Power Management Turnoff message received enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1DC++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1E0++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_STATUS_RAW,Precision Time Measurement Raw Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD800                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_RAW                     ,Precision Time Measurement interrupt raw status" "0,1"
hgroup.long 0x1E4++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_STATUS,Precision Time Measurement Status Register"
in
textline "                                                              "
group.long 0x1E8++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_SET,Precision Time Measurement Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD820                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_EN_SET                  ,Precision Time Measurement interrupt enable set. Write one to set" "0,1"
hgroup.long 0x1EC++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_CLR,Precision Time Measurement Enable Clear Register"
in
textline "                                                              "
rgroup.long 0x1000++0x3
line.long 0x00 "PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID                             ,Device ID - Vendor Assigned Device Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      VENDOR_ID                               ,Vendor ID - PCI-SIG assigned Manufacturer Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1004++0x3
hide.long 0x00 "PCIE_RC_TYPE1_STATUS_COMMAND_REG,Command and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1008++0x3
line.long 0x00 "PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE                       ,Base Class Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SUBCLASS_CODE                           ,Subclass Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTERFACE                     ,Class Code Programming Interface For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        REVISION_ID                             ,Vendor chosen Revision ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x100C++0x3
line.long 0x00 "PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST, Header Type, Cache Line Size, and Master Latency Timer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BIST                                  ,Optional for BIST support For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 23. "        MULTI_FUNC                              ,Specifies whether device is multifunction For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE                           ,Specifies Header Type For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "        LATENCY_MASTER_TIMER                    ,Primary Latency Timer Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE                       ,Cache Line Size field Has no effect on PCIe device behavior For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1018++0x3
line.long 0x00 "PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary, Secondary, Subordinate Bus Numbers and Latency Timer Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER                         ,Latency Timer Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 16.--23. 1. "        SUB_BUS                                 ,Subordinate Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS                               ,Secondary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 0.--7. 1. "        PRIM_BUS                                ,Primary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x101C++0x3
hide.long 0x00 "PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1020++0x3
line.long 0x00 "PCIE_RC_MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " MEM_LIMIT                             ,Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 16.--19. "      MEM_LIMIT_RESERV                        ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " MEM_BASE                              ,Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 0.--3. "      MEM_BASE_RESERV                         ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x3
line.long 0x00 "PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Base and Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PREF_MEM_LIMIT                        ,Prefetchable Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 17.--19. "      PREF_RESERV1                            ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE                 ,Prefetchable Memory Limit Decode For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 4.--15. 1. "         PREF_MEM_BASE                           ,Prefetchable Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 1.--3. " PREF_RESERV                           ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PREF_MEM_DECODE                         ,Prefetchable Memory Decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
rgroup.long 0x1028++0x3
line.long 0x00 "PCIE_RC_PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_BASE_UPPER                   ,Prefetchable Memory Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x102C++0x3
line.long 0x00 "PCIE_RC_PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_LIMIT_UPPER                  ,Prefetchable Memory Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1030++0x3
line.long 0x00 "PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " IO_LIMIT_UPPER                        ,Prefetchable I/O Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
hexmask.long.word 0x00 0.--15. 1. "      IO_BASE_UPPER                           ,Prefetchable I/O Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1034++0x3
line.long 0x00 "PCIE_RC_TYPE1_CAP_PTR_REG,Capability Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "    CAP_POINTER                             ,Pointer to first item in the PCI Capability Structure For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x1038++0x3
line.long 0x00 "PCIE_RC_TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register. For a description of this standard PCIe register, see the PCI Express Specification. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address."
hexmask.long.tbyte 0x00 11.--31. 1. " EXP_ROM_BASE_ADDRESS                  ,Expansion ROM BAR and Mask Register For a description of this standard PCIe register, see the PCI Express Specification The mask for this ROM BAR exists [if implemented] as a shadow register at this address The assertion of CS2 [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] is required to write to the second register at this address Note: The access attributes of this field are as follows: - Dbi: R/W"
hexmask.long.word 0x00 1.--10. 1. "    RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " ROM_BAR_ENABLE                        ,Expansion ROM Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x103C++0x3
line.long 0x00 "PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 23.--31. 1. " BRIDGE_CTRL_RESERV                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22. "      SBR                                     ,Secondary Bus Hot Reset For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 21. " MSTR_ABORT_MODE                       ,Master Abort Mode Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 20. "         VGA_16B_DEC                             ,VGA 16 bit decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " VGA_EN                                ,VGA Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
bitfld.long 0x00 18. "         ISA_EN                                  ,ISA Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " SERR_EN                               ,System Error Response Enable from Secondary to Primary For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         PERE                                    ,Parity Error Response Enable Controls Logging of Poisoned TLPs For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " INT_PIN                               ,PCI Compatible Interrupt Pin Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        INT_LINE                                ,PCI Compatible Interrupt Line Routing Register Field For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1040++0x3
line.long 0x00 "PCIE_RC_CAP_ID_NXT_PTR_REG,Power Management Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " PME_SUPPORT                           ,Power Management Event Support For a description of this standard PCIe register field, see the PCI Express Specification The read value from this field is the write value && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where D1_SUPPORT and D2_SUPPORT are fields in this register The reset value PME_SUPPORT_n && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where PME_SUPPORT_n is a configuration parameter Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        D2_SUPPORT                              ,D2 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " D1_SUPPORT                            ,D1 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 22.--24. "         AUX_CURR                                ,Auxiliary Current Requirements For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 21. " DSI                                   ,Device Specific Initialization Bit For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         PME_CLK                                 ,PCI Clock Requirement For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16.--18. " PM_SPEC_VER                           ,Power Management Spec Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "         PM_NEXT_POINTER                         ,Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID                             ,Power Management Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x1044++0x3
hide.long 0x00 "PCIE_RC_CON_STATUS_REG,Power Management Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1050++0x3
line.long 0x00 "PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID, Next Pointer, Capability/Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        PCI_MSI_EXT_DATA_EN                     ,Extended Message Data Enable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_EXT_DATA_CAP ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP                  ,Extended Message Data Capable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         PCI_PVM_SUPPORT                         ,MSI Per Vector Masking Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP               ,MSI 64-bit Address Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 20.--22. "         PCI_MSI_MULTIPLE_MSG_EN                 ,MSI Multiple Message Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP              ,MSI Multiple Message Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         PCI_MSI_ENABLE                          ,MSI Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSI_CAP_NEXT_OFFSET               ,MSI Capability Next Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSI_CAP_ID                          ,MSI Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1054++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_04H_REG,MSI Message Lower Address Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " PCI_MSI_CAP_OFF_04H                   ,MSI Message Lower Address Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 0.--1. "  RSVDP_0                                 ,Reserved for future use" "0,1,2,3"
group.long 0x1058++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_08H_REG,For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0AH                   ,For a 32 bit MSI Message, this field contains Ext MSI Data For 64-bit it contains upper 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_08H                     ,For a 32-bit MSI Message, this field contains Data For 64-bit it contains lower 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R"
group.long 0x105C++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_0CH_REG,For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0EH                   ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the upper Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: [!MSI_64_EN && MSI_PVM_EN_VALUE] ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_0CH                     ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the lower Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR MSI_PVM_EN ? R/W : R"
group.long 0x1060++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_10H                   ,Used for MSI when Vector Masking Capable For 32-bit contains Pending Bits For 64-bit, contains Mask Bits For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R"
rgroup.long 0x1064++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_14H_REG,Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_14H                   ,Used for MSI 64-bit messaging when Vector Masking Capable Contains Pending Bits For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1070++0x3
line.long 0x00 "PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities, ID, Next Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         RSVD                                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM                      ,PCIE Interrupt Message Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "        PCIE_SLOT_IMP                           ,PCIe Slot Implemented Valid For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE                    ,PCIE Device/PortType For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PCIE_CAP_REG                            ,PCIE Capability Version Number For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR                     ,PCIE Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCIE_CAP_ID                             ,PCIE Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1074++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES_REG,Device Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      PCIE_CAP_ROLE_BASED_ERR_REPORT          ,Role-based Error Reporting Implemented For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 6.--14. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "      PCIE_CAP_EXT_TAG_SUPP                   ,Extended Tag Field Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT         ,Phantom Functions Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 0.--2. "         PCIE_CAP_MAX_PAYLOAD_SIZE               ,Max Payload Size Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hgroup.long 0x1078++0x3
hide.long 0x00 "PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x107C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES_REG,Link Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM                     ,Port Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE          ,ASPM Optionality Compliance For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 21. "         PCIE_CAP_LINK_BW_NOT_CAP                ,Link Bandwidth Notification Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP           ,Data Link Layer Link Active Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 19. "         PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP      ,Surprise Down Error Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN              ,Clock Power Management For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 15.--17. "         PCIE_CAP_L1_EXIT_LATENCY                ,L1 Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY             ,LOs Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--11. "         PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT   ,Level of ASPM [Active State Power Management] Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH               ,Maximum Link Width For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. "        PCIE_CAP_MAX_LINK_SPEED                 ,Maximum Link Speed For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1080++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1084++0x3
line.long 0x00 "PCIE_RC_SLOT_CAPABILITIES_REG,Slot Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM                 ,Physical Slot Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 18. "      PCIE_CAP_NO_CMD_CPL_SUPPORT             ,No Command Completed Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK        ,Electromechanical Interlock Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 15.--16. "         PCIE_CAP_SLOT_POWER_LIMIT_SCALE         ,Slot Power Limit Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE       ,Slot Power Limit Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 6. "        PCIE_CAP_HOT_PLUG_CAPABLE               ,Hot Plug Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE            ,Hot Plug Surprise possible For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_POWER_INDICATOR                ,Power Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR          ,Attention Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_MRL_SENSOR                     ,MRL Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER             ,Power Controller Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_ATTENTION_INDICATOR_BUTTON     ,Attention Button Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
hgroup.long 0x1088++0x3
hide.long 0x00 "PCIE_RC_SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x108C++0x3
line.long 0x00 "PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      PCIE_CAP_CRS_SW_VISIBILITY              ,CRS Software Visibility Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W [Sticky] else R [Sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 5.--15. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 4. "      PCIE_CAP_CRS_SW_VISIBILITY_EN           ,Configuration Request Retry Status [CRS] Software Visibility Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REGPCIE_CAP_CRS_SW_VISIBILITY ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN                   ,PME Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN        ,System Error on Fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN  ,System Error on Non-fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN         ,System Error on Correctable Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1090++0x3
hide.long 0x00 "PCIE_RC_ROOT_STATUS_REG,Root Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1094++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--30. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 18.--19. "        PCIE_CAP_OBFF_SUPPORT                   ,[OBFF] Optimized Buffer Flush/fill Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT      ,10-Bit Tag Requester Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
bitfld.long 0x00 16. "         PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT       ,10-Bit Tag Completer Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPPORT_1          ,TPH Completer Supported Bit 1 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 12. "         PCIE_CAP_TPH_CMPLT_SUPPORT_0            ,TPH Completer Supported Bit 0 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP                     ,LTR Mechanism Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 10. "         PCIE_CAP_NO_RO_EN_PR2PR_PAR             ,No Relaxed Ordering Enabled PR-PR Passing For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP             ,128 Bit CAS Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 8. "         PCIE_CAP_64_ATOMIC_CPL_SUPP             ,64 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP           ,32 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 6. "         PCIE_CAP_ATOMIC_ROUTING_SUPP            ,Atomic Operation Routing Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT          ,ARI Forwarding Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT    ,Completion Timeout Disable Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE            ,Completion Timeout Ranges Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1098++0x3
line.long 0x00 "PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS       ,ARI Forwarding Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE            ,Completion Timeout Disable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VALUE            ,Completion Timeout Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x109C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES2_REG,Link Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 25.--30. " RSVDP_25                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 9.--22. 1. "        RSVDP_9                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT           ,Cross Link Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR      ,Supported Link Speeds Vector For a description of this standard PCIe register field, see the PCI Express Specification This field has a default of [PCIE_CAP_MAX_LINK_SPEED == 0100] ? 0001111 : [PCIE_CAP_MAX_LINK_SPEED == 0011] ? 0000111 : [PCIE_CAP_MAX_LINK_SPEED == 0010] ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the PCIE_RC_LINK_CAPABILITIES_REG register"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
hgroup.long 0x10A0++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x10B0++0x3
line.long 0x00 "PCIE_RC_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID, Next Pointer, Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " PCI_MSIX_ENABLE                       ,MSI-X Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 30. "         PCI_MSIX_FUNCTION_MASK                  ,Function Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--26. 1. "         PCI_MSIX_TABLE_SIZE                     ,MSI-X Table Size For a description of this standard PCIe register field, see the PCI Express Specification SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' [PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG] To write this common value, you must perform a DBI_CS2 write [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] while accessing the PCI_MSIX_TABLE_SIZE field in the PF"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSIX_CAP_NEXT_OFFSET              ,MSI-X Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSIX_CAP_ID                         ,MSI-X Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x10B4++0x3
line.long 0x00 "PCIE_RC_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_TABLE_OFFSET                 ,MSI-X Table Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_BIR                            ,MSI-X Table Bar Indicator Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x10B8++0x3
line.long 0x00 "PCIE_RC_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_PBA_OFFSET                   ,MSI-X PBA Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_PBA                            ,MSI-X PBA BIR For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x1100++0x3
line.long 0x00 "PCIE_RC_AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " CAP_ID                                ,AER Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1104++0x3
hide.long 0x00 "PCIE_RC_UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1108++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_MASK               ,TLP Prefix Blocked Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK        ,AtomicOp Egress Block Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_MASK                     ,Uncorrectable Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_MASK                ,Unsupported Request Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_MASK                         ,ECRC Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_MASK                       ,Malformed TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK                 ,Receiver Overflow Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_MASK                    ,Unexpected Completion Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK                  ,Completer Abort Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_MASK                  ,Completion Timeout Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK                  ,Flow Control Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_MASK                       ,Poisoned TLP Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_MASK                  ,Surprise Down Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK                  ,Data Link Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110C++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_SEVERITY           ,TLP Prefix Blocked Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY    ,AtomicOp Egress Blocked Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_SEVERITY                 ,Uncorrectable Internal Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_SEVERITY            ,Unsupported Request Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_SEVERITY                     ,ECRC Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_SEVERITY                   ,Malformed TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_SEVERITY             ,Receiver Overflow Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_SEVERITY                ,Unexpected Completion Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_SEVERITY              ,Completer Abort Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_SEVERITY              ,Completion Timeout Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_SEVERITY              ,Flow Control Protocol Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_SEVERITY                   ,Poisoned TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_SVRITY                ,Surprise Down Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_SEVERITY              ,Data Link Protocol Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1110++0x3
hide.long 0x00 "PCIE_RC_CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1114++0x3
line.long 0x00 "PCIE_RC_CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      HEADER_LOG_OVERFLOW_MASK                ,Header Log Overflow Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14. " CORRECTED_INT_ERR_MASK                ,Corrected Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 13. "         ADVISORY_NON_FATAL_ERR_MASK             ,Advisory Non-Fatal Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RPL_TIMER_TIMEOUT_MASK                ,Replay Timer Timeout Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 9.--11. "         RSVDP_9                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8. " REPLAY_NO_ROLEOVER_MASK               ,REPLAY_NUM Rollover Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 7. "         BAD_DLLP_MASK                           ,Bad DLLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " BAD_TLP_MASK                          ,Bad TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 1.--5. "         RSVDP_1                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 0. " RX_ERR_MASK                           ,Receiver Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
group.long 0x1118++0x3
line.long 0x00 "PCIE_RC_ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10. "    MULTIPLE_HEADER_EN                      ,Multiple Header Recording Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " MULTIPLE_HEADER_CAP                   ,Multiple Header Recording Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         ECRC_CHECK_EN                           ,ECRC Check Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " ECRC_CHECK_CAP                        ,ECRC Check Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 6. "         ECRC_GEN_EN                             ,ECRC Generation Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " ECRC_GEN_CAP                          ,ECRC Generation Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--4. "         FIRST_ERR_POINTER                       ,First Error Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x111C++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FIRST_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FIRST_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1120++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SECOND_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SECOND_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        SECOND_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1124++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        THIRD_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " THIRD_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        THIRD_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1128++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FOURTH_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FOURTH_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
group.long 0x112C++0x3
line.long 0x00 "PCIE_RC_ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " RSVDP_3                               ,Reserved for future use"
bitfld.long 0x00 2. "  FATAL_ERR_REPORTING_EN                  ,Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN            ,Non-Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         CORR_ERR_REPORTING_EN                   ,Correctable Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1130++0x3
hide.long 0x00 "PCIE_RC_ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1134++0x3
line.long 0x00 "PCIE_RC_ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID         ,Source of Fatal/Non-Fatal Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      ERR_COR_SOURCE_ID                       ,Source of Correctable Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1138++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE         ,Byte 3 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_1_THIRD_BYTE            ,Byte 2 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE         ,Byte 1 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_1_FIRST_BYTE            ,Byte 0 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x113C++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_2_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_2_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1140++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_3_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_3_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1144++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_4_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_4_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1148++0x3
line.long 0x00 "PCIE_RC_VC_BASE,VC Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " VC_NEXT_OFFSET                        ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      VC_CAP_VERSION                          ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " VC_PCIE_EXTENDED_CAP_ID               ,VC Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x114C++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_1,Port VC Capability Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10.--11. "    VC_PORT_ARBI_TBL_ENTRY_SIZE             ,Port Arbitration Table Entry Size For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 8.--9. " VC_REFERENCE_CLOCK                    ,Reference Clock For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
bitfld.long 0x00 7. "         RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " VC_LOW_PRI_EXT_VC_CNT                 ,Low Priority Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RSVDP_3                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--2. " VC_EXT_VC_CNT                         ,Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
rgroup.long 0x1150++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_2,Port VC Capability Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_ARBI_TABLE_OFFSET                  ,VC Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.tbyte 0x00 4.--23. 1. "        RSVDP_4                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0.--3. " VC_ARBI_CAP                           ,VC Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1154++0x3
line.long 0x00 "PCIE_RC_VC_STATUS_CONTROL_REG,Port VC Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      VC_ARBI_TABLE_STATUS                    ,VC Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " RSVDP_4                               ,Reserved for future use"
bitfld.long 0x00 1.--3. "      VC_ARBI_SELECT                          ,VC Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " VC_LOAD_VC_ARBI_TABLE                 ,Requests Hardware to Load VC Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1158++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC0,VC Resource Capability Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC0                ,Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC0                  ,Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC0               ,Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC0                    ,Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x115C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC0,VC Resource Control Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC0                         ,VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC                              ,VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--23. "         RSVDP_18                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 17. " VC_PORT_ARBI_SELECT_VC0               ,Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC0             ,Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC0_BIT1                      ,Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC0                         ,Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1160++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC0,VC Resource Status Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC0                     ,VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC0         ,Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1164++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC1,VC Resource Capability Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC1                ,VC1 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC1                  ,VC1 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC1               ,VC1 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC1                    ,VC1 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1168++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC1,VC Resource Control Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC1                         ,VC1 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC1                             ,VC1 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC1               ,VC1 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC1             ,VC1 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC1_BIT1                      ,VC1 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC1                         ,VC1 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x116C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC1,VC Resource Status Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC1                     ,VC1 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC1         ,VC1 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1170++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC2,VC Resource Capability Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC2                ,VC2 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC2                  ,VC2 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC2               ,VC2 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC2                    ,VC2 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1174++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC2,VC Resource Control Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC2                         ,VC2 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC2                             ,VC2 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC2               ,VC2 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC2             ,VC2 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC2_BIT1                      ,VC2 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC2                         ,VC2 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1178++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC2,VC Resource Status Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC2                     ,VC2 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC2         ,VC2 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x117C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC3,VC Resource Capability Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC3                ,VC3 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC3                  ,VC3 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC3               ,VC3 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC3                    ,VC3 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1180++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC3,VC Resource Control Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC3                         ,VC3 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC3                             ,VC3 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC3               ,VC3 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC3             ,VC3 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC3_BIT1                      ,VC3 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC3                         ,VC3 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1184++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC3,VC Resource Status Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC3                     ,VC3 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC3         ,VC3 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1198++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,Secondary PCI Express Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x119C++0x3
line.long 0x00 "PCIE_RC_LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  EQ_REQ_INT_EN                           ,Link Equalization Request Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PERFORM_EQ                            ,Perform Equalization For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
hgroup.long 0x11A0++0x3
hide.long 0x00 "PCIE_RC_LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x11A4++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 28.--30. "         USP_RX_PRESET_HINT1                     ,Upstream Port 80 GT/s Receiver Preset Hint 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 24.--27. " USP_TX_PRESET1                        ,Upstream Port 80 GT/s Transmitter Preset 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1                   ,Downstream Port 80 GT/s Receiver Preset Hint 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         DSP_TX_PRESET1                          ,Downstream Port 80 GT/s Transmitter Preset 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 15. " RSVDP_15                              ,Reserved for future use" "0,1"
bitfld.long 0x00 12.--14. "         USP_RX_PRESET_HINT0                     ,Upstream Port 80 GT/s Receiver Preset Hint 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--11. " USP_TX_PRESET0                        ,Upstream Port 80 GT/s Transmitter Preset 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0                   ,Downstream Port 80 GT/s Receiver Preset Hint 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         DSP_TX_PRESET0                          ,Downstream Port 80 GT/s Transmitter Preset 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x11A8++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,L1SUB Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x11AC++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAPABILITY_REG,L1 Substates Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 19.--23. "        PWR_ON_VALUE_SUPPORT                    ,Port T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 18. " RSVDP_18                              ,Reserved for future use" "0,1"
bitfld.long 0x00 16.--17. "         PWR_ON_SCALE_SUPPORT                    ,Port T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " COMM_MODE_SUPPORT                     ,Port Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 5.--7. "        RSVDP_5                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 4. " L1_PMSUB_SUPPORT                      ,L1 PM Substates ECN Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 3. "         L1_1_ASPM_SUPPORT                       ,ASPM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT                     ,ASPM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_SUPPORT                      ,PCI-PM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_SUPPORT                    ,PCI-PM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x11B0++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 29.--31. " L1_2_TH_SCA                           ,LTR L12 Threshold Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "         RSVDP_26                                ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 16.--25. 1. " L1_2_TH_VAL                           ,LTR L12 Threshold Value For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "      T_COMMON_MODE                           ,Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
textline "                                                              "
bitfld.long 0x00 4.--7. " RSVDP_4                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        L1_1_ASPM_EN                            ,ASPM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_EN                          ,ASPM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_EN                           ,PCI-PM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_EN                         ,PCI-PM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
group.long 0x11B4++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 3.--7. "    T_POWER_ON_VALUE                        ,T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 0.--1. "         T_POWER_ON_SCALE                        ,T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
rgroup.long 0x11B8++0x3
line.long 0x00 "PCIE_RC_PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PTM_NEXT_OFFSET                       ,Precision Time Measurement PCI Express Extended Capability Next Offset For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_CAP_VERSION                         ,Precision Time Measurement PCI Express Extended Capability Version For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_CAP_ID                            ,Precision Time Measurement PCI Express Extended Capability ID For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11BC++0x3
line.long 0x00 "PCIE_RC_PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      PTM_CLK_GRAN                            ,PTM Local Clock Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVDP_3                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_ROOT_CAPABLE                        ,PTM Root Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_RES_CAPABLE                       ,PTM Responder Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 0. "         PTM_REQ_CAPABLE                         ,PTM Requester Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
group.long 0x11C0++0x3
line.long 0x00 "PCIE_RC_PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      EFF_GRAN                                ,PTM Effective Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT"
textline "                                                              "
bitfld.long 0x00 2.--7. " RSVDP_2                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        ROOT_SELECT                             ,PTM Root Select When set this Time Source is the PTM Root For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_ENABLE                            ,PTM Enable When set, this function is permitted to participate in the PTM mechanism For a description of this standard PCIe register, see the PCI Express Specification" "0,1"
rgroup.long 0x11C4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC)."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_EXT_CAP_NEXT_OFFS             ,Precision Time Measurement Responder VSEC Next Pointer Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_EXT_CAP_VER                     ,Precision Time Measurement Responder VSEC Version Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_EXT_CAP_ID                    ,Precision Time Measurement Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11C8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. ."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_VSEC_LENGTH                   ,PTM Responder VSEC Length Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_VSEC_REV                        ,PTM Responder VSEC Revision Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_VSEC_ID                       ,PTM Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11CC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CONTROL_OFF,PTM Responder Control Register. ."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  PTM_RES_CCONTEXT_VALID                  ,PTM Responder Control Context Valid - PTM Local Timing is valid This bit is set over the DBI A speed change or aux_clk_active will set this bit low Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x11D0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_STATUS_OFF,PTM Responder Status Register. ."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  PTM_RES_REQUEST_RECEIVED                ,PTM 1st Request Received - PTM Responder has received the first PTM Request Message Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder, if the context is valid If the context is invalid a Response message will be sent instead Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_RES_CONTEXT_VALID                 ,PTM Responder Status Context Valid - PTM Local Timing Context is Valid Value set from upstream port Requester in a Switch Shadows the same in the control register in all other products Note: This register field is sticky" "0,1"
rgroup.long 0x11D4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_LSB                     ,PTM Responder Local Clock LSB - Lower 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11D8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_MSB                     ,PTM Responder Local Clock MSB - Upper 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11DC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_LSB                        ,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_MSB                        ,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_LSB                       ,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_MSB                       ,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11EC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_LSB                        ,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_MSB                        ,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_LSB                       ,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_MSB                       ,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
group.long 0x11FC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_TX_LATENCY                      ,PTM Responder TX Latency - Responder Transmit path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1200++0x3
line.long 0x00 "PCIE_RC_PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_RX_LATENCY                      ,PTM Responder RX Latency - Responder Receive path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1700++0x3
line.long 0x00 "PCIE_RC_ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register."
hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT                     ,Replay Timer Limit The replay timer expires when it reaches this limit The controller initiates a replay upon reception of a NAK or when the replay timer expires You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 30 specification If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
hexmask.long.word 0x00 0.--15. 1. "      ROUND_TRIP_LATENCY_TIME_LIMIT           ,Ack Latency Timer Limit The Ack latency timer expires when it reaches this limit You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 30 specification The limit must reflect the round trip latency from requester to completer If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_ACK_NAK field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
group.long 0x1704++0x3
line.long 0x00 "PCIE_RC_VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register."
hexmask.long 0x00 0.--31. 1. " VENDOR_SPEC_DLLP                      ,Vendor Specific DLLP Register Used to send a specific PCI Express DLLP Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of"
hgroup.long 0x1708++0x3
hide.long 0x00 "PCIE_RC_PORT_FORCE_OFF,Port Force Link Register."
in
textline "                                                              "
group.long 0x170C++0x3
line.long 0x00 "PCIE_RC_ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         ENTER_ASPM                              ,ASPM L1 Entry Control - 1: Core enters ASPM L1 after a period in which it has been idle - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " L1_ENTRANCE_LATENCY                   ,L1 Entrance Latency Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         L0S_ENTRANCE_LATENCY                    ,L0s Entrance Latency Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 16.--23. 1. " COMMON_CLK_N_FTS                      ,Common Clock N_FTS This is the N_FTS when common clock is used The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 This field is only writable [sticky] when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 8.--15. 1. "        ACK_N_FTS                               ,N_FTS The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " ACK_FREQ                              ,Ack Frequency The controller accumulates the number of pending ACKs specified here [up to 255] before sending an ACK DLLP - 0: Indicates that this Ack frequency control feature is turned off The controller schedules a low-priority ACK DLLP for every TLP that it receives - 1- 255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs It might schedule the ACK before receiving this number of TLPs, but never later For a typical system, you do not have to modify the default setting Note: This register field is sticky"
hgroup.long 0x1710++0x3
hide.long 0x00 "PCIE_RC_PORT_LINK_CTRL_OFF,Port Link Control Register."
in
textline "                                                              "
group.long 0x1714++0x3
line.long 0x00 "PCIE_RC_LANE_SKEW_OFF,Lane Skew Register."
bitfld.long 0x00 31. " DISABLE_LANE_TO_LANE_DESKEW           ,Disable Lane-to-Lane Deskew Causes the controller to disable the internal Lane-to-Lane deskew logic Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         IMPLEMENT_NUM_LANES                     ,Implementation-specific Number of Lanes Set the implementation-specific number of lanes Allowed values are: - 4'b 0000: 1 lane - 4'b 0001: 2 lanes - 4'b 0011: 4 lanes - 4'b 0111: 8 lanes - 4'b 1111: 16 lanes The number of lanes to be used when in Loopback Master The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field The controller will transition from LoopbackEntry to LoopbackActive after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 26. " LANE_SKEW_OFF_26                      ,Reserved Read/Write regsiter for future use Note: This register field is sticky" "0,1"
bitfld.long 0x00 25. "         ACK_NAK_DISABLE                         ,Ack/Nak Disable Prevents the controller from sending ACK and NAK DLLPs Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " FLOW_CTRL_DISABLE                     ,Flow Control Disable Prevents the controller from sending FC DLLPs Note: This register field is sticky" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. "         INSERT_LANE_SKEW                        ,Insert Lane Skew for Transmit [not supported for x16] Optional feature that causes the controller to insert skew between Lanes for test purposes There are three bits per Lane The value is in units of one symbol time For example, the value 010b for a Lane forces a skew of two symbol times for that Lane The maximum skew value for any Lane is 5 symbol times Note: This register field is sticky"
group.long 0x1718++0x3
line.long 0x00 "PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 29.--30. "         FAST_LINK_SCALING_FACTOR                ,Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field inPCIE_RC_PORT_LINK_CTRL_OFF is set to '1' - 0: Scaling Factor is 1024 [1ms is 1us] - 1: Scaling Factor is 256 [1ms is 4us] - 2: Scaling Factor is 64 [1ms is 16us] - 3: Scaling Factor is 16 [1ms is 64us] Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0' Not used for M-PCIe Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--28. " UPDATE_FREQ_TIMER                     ,UPDATE_FREQ_TIMER is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19.--23. "        TIMER_MOD_ACK_NAK                       ,Ack Latency Timer Modifier Increases the timer value for the Ack latency timer in increments of 64 clock cycles A value of '0' represents no modification to the timer value For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 14.--18. " TIMER_MOD_REPLAY_TIMER                ,Replay Timer Limit Modifier Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed A value of '0' represents no modification to the timer limit For more details, see the REPLAY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RSVDP_8                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MAX_FUNC_NUM                          ,Maximum function number that can be used in a request Configuration requests targeted at function numbers above this value are returned with UR [unsupported request] Note: This register field is sticky"
group.long 0x171C++0x3
line.long 0x00 "PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long.word 0x00 16.--31. 1. " MASK_RADM_1                           ,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD 0: For RADM RC filter to not allow CFG transaction being received 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD 0: For RADM RC filter to not allow IO transaction being received 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP 0: Drop MSG TLP [except for Vendor MSG]. Send decoded message on the SII. 1: Do not Drop MSG [except for Vendor MSG]. Send message TLPs to your application on TRGT1 and send decoded message on the SII. The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG = 1, then the default of this bit is '0' [drop message TLPs]. This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 [or AXI bridge master], as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. 0: Discard completions with ECRC errors 1: Allow completions with ECRC errors to be passed up Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD 0: Discard TLPs with ECRC errors 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH 0: Enforce Req Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Req Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_c? 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR 0: Treat locked Read TLPs as UR for EP; Supported for RC 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR 0: Treat CFG type1 TLPs as UR for EP; Supported for RC 1: Treat CFG type1 TLPs as Supported for EP; UR for RC When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests, if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR 0: Treat out-of-bar TLPs as UR 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS 0: Treat poisoned request TLPs as UR 1: Do not treat poisoned request TLPs as UR The native controller always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH 0: Treat Function MisMatched TLPs as UR 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky."
bitfld.long 0x00 15. "      DISABLE_FC_WD_TIMER                     ,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1"
textline "                                                              "
bitfld.long 0x00 11.--14. " EIDLE_TIMER                           ,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "        SKP_INT_VAL                             ,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register [in a 250 MHz controller], then the controller actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 [because one clock tick = two symbol times in this case]. Note: This value is not used at Gen3 speed. The skip interval is hardcoded to 370 blocks For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows: 2K_PPM_DISABLED = 1: 1280/CX_NB 2K_PPM_DISABLED = 0: 228/CX_NB You need to set this field again, if necessary, when 2K_PPM_DISABLED is changed. Note: This register field is sticky."
group.long 0x1720++0x3
line.long 0x00 "PCIE_RC_FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long 0x00 0.--31. 1. " MASK_RADM_2                           ,Filter Mask 2. This field modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
group.long 0x1724++0x3
line.long 0x00 "PCIE_RC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  OB_RD_SPLIT_BURST_EN                    ,Enable AMBA Multiple Outbound Decomposed NP SubRequests This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device [or switch] is reordering completions that have different tags Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x1728++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG0_OFF,Debug Register 0"
hexmask.long 0x00 0.--31. 1. " DEB_REG_0                             ,The value on cxpl_debug_info[31:0]"
rgroup.long 0x172C++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG1_OFF,Debug Register 1"
hexmask.long 0x00 0.--31. 1. " DEB_REG_1                             ,The value on cxpl_debug_info[63:32]"
rgroup.long 0x1730++0x3
line.long 0x00 "PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_P_HEADER_FC_CREDIT                   ,Transmit Posted Header FC Credits The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_P_DATA_FC_CREDIT                   ,Transmit Posted Data FC Credits The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1734++0x3
line.long 0x00 "PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_NP_HEADER_FC_CREDIT                  ,Transmit Non-Posted Header FC Credits The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_NP_DATA_FC_CREDIT                  ,Transmit Non-Posted Data FC Credits The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1738++0x3
line.long 0x00 "PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_CPL_HEADER_FC_CREDIT                 ,Transmit Completion Header FC Credits The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_CPL_DATA_FC_CREDIT                 ,Transmit Completion Data FC Credits The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
hgroup.long 0x173C++0x3
hide.long 0x00 "PCIE_RC_QUEUE_STATUS_OFF,Queue Status"
in
textline "                                                              "
rgroup.long 0x1740++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3                       ,WRR Weight for VC3 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_2                         ,WRR Weight for VC2 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1                       ,WRR Weight for VC1 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_0                         ,WRR Weight for VC0 Note: The access attributes of this field are as follows: - Dbi: R"
rgroup.long 0x1744++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_7                       ,WRR Weight for VC7 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_6                         ,WRR Weight for VC6 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_5                       ,WRR Weight for VC5 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_4                         ,WRR Weight for VC4 Note: The access attributes of this field are as follows: - Dbi: R"
group.long 0x1748++0x3
line.long 0x00 "PCIE_RC_VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control."
bitfld.long 0x00 31. " VC_ORDERING_RX_Q                      ,VC Ordering for Receive Queues Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         TLP_TYPE_ORDERING_VC0                   ,TLP Type Ordering for VC0 Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE                      ,VC0 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_P_HDR_SCALE                         ,VC0 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_P_TLP_Q_MODE                      ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_P_HEADER_CREDIT                     ,VC0 Posted Header Credits The number of initial posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CREDIT                     ,VC0 Posted Data Credits The number of initial posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x174C++0x3
line.long 0x00 "PCIE_RC_VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_NP_DATA_SCALE                     ,VC0 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_NP_HDR_SCALE                        ,VC0 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_NP_HEADER_CREDIT                    ,VC0 Non-Posted Header Credits The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_NP_DATA_CREDIT                    ,VC0 Non-Posted Data Credits The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1750++0x3
line.long 0x00 "PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_CPL_DATA_SCALE                    ,VC0 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_CPL_HDR_SCALE                       ,VC0 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_CPL_HEADER_CREDIT                   ,VC0 Completion Header Credits The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_CPL_DATA_CREDIT                   ,VC0 Completion Data Credits The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1754++0x3
line.long 0x00 "PCIE_RC_VC1_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC1                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC1_P_DATA_SCALE                        ,VC1 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC1_P_HDR_SCALE                       ,VC1 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC1_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC1_P_HEADER_CREDIT                   ,VC1 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC1_P_DATA_CREDIT                       ,VC1 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1758++0x3
line.long 0x00 "PCIE_RC_VC1_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_NP_DATA_SCALE                     ,VC1 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_NP_HDR_SCALE                        ,VC1 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x175C++0x3
line.long 0x00 "PCIE_RC_VC1_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_CPL_DATA_SCALE                    ,VC1 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_CPL_HDR_SCALE                       ,VC1 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1760++0x3
line.long 0x00 "PCIE_RC_VC2_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC2                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC2_P_DATA_SCALE                        ,VC2 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC2_P_HDR_SCALE                       ,VC2 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC2_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC2_P_HEADER_CREDIT                   ,VC2 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC2_P_DATA_CREDIT                       ,VC2 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1764++0x3
line.long 0x00 "PCIE_RC_VC2_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_NP_DATA_SCALE                     ,VC2 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_NP_HDR_SCALE                        ,VC2 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1768++0x3
line.long 0x00 "PCIE_RC_VC2_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_CPL_DATA_SCALE                    ,VC2 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_CPL_HDR_SCALE                       ,VC2 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x176C++0x3
line.long 0x00 "PCIE_RC_VC3_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC3                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC3_P_DATA_SCALE                        ,VC3 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC3_P_HDR_SCALE                       ,VC3 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC3_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC3_P_HEADER_CREDIT                   ,VC3 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC3_P_DATA_CREDIT                       ,VC3 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1770++0x3
line.long 0x00 "PCIE_RC_VC3_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_NP_DATA_SCALE                     ,VC3 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_NP_HDR_SCALE                        ,VC3 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1774++0x3
line.long 0x00 "PCIE_RC_VC3_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_CPL_DATA_SCALE                    ,VC3 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_CPL_HDR_SCALE                       ,VC3 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x180C++0x3
line.long 0x00 "PCIE_RC_GEN2_CTRL_OFF,Link Width and Speed Change Control Register."
hexmask.long.word 0x00 22.--31. 1. " RSVDP_22                              ,Reserved for future use"
bitfld.long 0x00 21. "      GEN1_EI_INFERENCE                       ,Electrical Idle Inference Mode at Gen1 Rate Programmable mode to determine inferred electrical idle [EI] in RecoverySpeed or LoopbackActive [as slave] state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking for a '0' on RxValid If the PHY fails to deassert the RxValid signal in RecoverySpeed or LoopbackActive [because of corrupted EIOS for example], then EI cannot be inferred successfully in the controller by just detecting the condition RxValid= 0 - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " SEL_DEEMPHASIS                        ,Used to set the de-emphasis level for upstream ports This bit selects the level of de-emphasis the link operates at - 0: -6 dB - 1: -35 dB This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         CONFIG_TX_COMP_RX                       ,Config Tx Compliance Receive Bit When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert [equal to '1'] This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE                  ,Config PHY Tx Swing Controls the PHY transmitter voltage swing level The controller drives the mac_phy_txswing output from this register bit field - 0: Full Swing - 1: Low Swing This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 17. "         DIRECT_SPEED_CHANGE                     ,Directed Speed Change Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed When the speed change occurs, the controller will clear the contents of this field and a read to this field by your software will return a '0' To manually initiate the speed change: - Write to PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to '1', then the speed change is initiated automatically after link up, and the controller clears the contents of this field If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register [LINK_CONTROL2_LINK_STATUS2_OFF PCIE_CAP_TARGET_LINK_SPEED] through the DBI before link up This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN                ,Enable Auto flipping of the lanes You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 13.--15. "         PRE_DET_LANE                            ,Predetermined Lane for Auto Flip This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect Allowed values are: - 3'b 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/ 2-1 or CX_NL/ 4-1 or CX_NL/ 8-1, depending on which lane is detected - 3'b 001: Connect logical Lane0 to physical lane 1 - 3'b 010: Connect logical Lane0 to physical lane 3 - 3'b 011: Connect logical Lane0 to physical lane 7 - 3'b 100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state Note: This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--12. " NUM_OF_LANES                          ,Predetermined Number of Lanes Defines the number of lanes which are connected and not bad Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver Indicates the number of lanes to check for exit from Electrical Idle in PollingActive and L2Idle It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured This value is referred to as the 'Predetermined Number of Lanes' in section 42621 of the PCI Express Base 30 Specification, revision 10 Encoding is as follows: - 0x 01: 1 lane - 0x 02: 2 lanes - 0x 03: 3 lanes - When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes You must also change the value in the 'Link Mode Enable' field of PCIE_RC_PORT_LINK_CTRL_OFF The value in this register is normally the same as the encoded value in PCIE_RC_PORT_LINK_CTRL_OFF If you find that one of your used lanes is bad then you must reduce the value in this register This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "        FAST_TRAINING_SEQ                       ,Sets the Number of Fast Training Sequences [N_FTS] that the controller advertises as its N_FTS during Gen2 or Gen3 link training This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state Do not set N_FTS to zero doing so can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky"
rgroup.long 0x1810++0x3
line.long 0x00 "PCIE_RC_PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins."
hexmask.long 0x00 0.--31. 1. " PHY_STATUS                            ,PHY Status Data received directly from the phy_cfg_status bus These is a GPIO register reflecting the values on the static phy_cfg_status input signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband status signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x1814++0x3
line.long 0x00 "PCIE_RC_PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins."
hexmask.long 0x00 0.--31. 1. " PHY_CONTROL                           ,PHY Control Data sent directly to the cfg_phy_control bus These is a GPIO register driving the values on the static cfg_phy_control output signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband control signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x181C++0x3
line.long 0x00 "PCIE_RC_TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register."
bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX                      ,The number of the PF Function on which the Target Values are set This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "        TARGET_MAP_ROM                          ,Target Value for the ROM page of the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--5. " TARGET_MAP_PF                         ,Target Values for each BAR on the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1820++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_ADDR                         ,Integrated MSI Reception Module Address System specified address for MSI memory write transaction termination Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register and also to see if it satisfies the definition of an MSI interrupt request When these conditions are satisfied the Memory Write request is marked as an MSI request Note: This register field is sticky"
group.long 0x1824++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_UPPER_ADDR                   ,Integrated MSI Reception Module Upper Address System specified upper address for MSI memory write transaction termination Allows functions to support a 64-bit MSI address Note: This register field is sticky"
group.long 0x1828++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x182C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1830++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1834++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1838++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x183C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1840++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1844++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1848++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x184C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1850++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1854++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1858++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x185C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1860++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1864++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1868++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x186C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1870++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1874++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1878++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x187C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1880++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1884++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1888++0x3
line.long 0x00 "PCIE_RC_MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register."
hexmask.long 0x00 0.--31. 1. " MSI_GPIO_REG                          ,MSI GPIO Register The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky"
group.long 0x188C++0x3
line.long 0x00 "PCIE_RC_CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register. Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g output will always be set to '1'."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  RADM_CLK_GATING_EN                      ,Enable Radm clock gating feature - 0: Disable - 1: Enable[default]" "0,1"
group.long 0x1890++0x3
line.long 0x00 "PCIE_RC_GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The 'Directed Speed Change' field in the 'Link Width and Speed Change Control Register' is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the 'Directed Speed Change' field is set to '1' and (2) the 'Target Link Speed' field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "        GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE        ,Eq InvalidRequest and RxEqEval Different Time Assertion Disable Disable the assertion of Eq InvalidRequest and RxEqEval at different time Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19.--20. " RSVDP_19                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 18. "         GEN3_DC_BALANCE_DISABLE                 ,DC Balance Disable Disable DC Balance feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE           ,DLLP Transmission Delay Disable Disable delay transmission of DLLPs before equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         GEN3_EQUALIZATION_DISABLE               ,Equalization Disable Disable equalization feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14.--15. " RSVDP_14                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 13. "         RXEQ_RGRDLESS_RXTS                      ,When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RXEQ_PH01_EN                          ,Rx Equalization Phase 0/Phase 1 Hold Enable When this bit is set the upstream port holds phase 0 [the downstream port holds phase 1] for 10ms Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY This bit is used during Virtex-7 Gen3 equalization The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/ 3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/ 1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
bitfld.long 0x00 11. "         EQ_REDO                                 ,Equalization Redo Disable Disable autonomous mechanism for requesting to redo the equalization process Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 10. " EQ_EIEOS_CNT                          ,Equalization EIEOS Count Reset Disable Disable requesting reset of EIEOS count during equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         EQ_PHASE_2_3                            ,Equalization Phase 2 and Phase 3 Disable This applies to downstream ports only Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3               ,Disable Scrambler for Gen3 and Gen4 Data Rate The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller [for example within the PHY] Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL                   ,Gen3 Receiver Impedance ZRX-DC Not Compliant Receivers that operate at 80 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 25 GT/s [40-60 Ohms] must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled - 0: The receiver complies with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher - 1: The receiver does not comply with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates Note: This register field is sticky" "0,1"
group.long 0x18A8++0x3
line.long 0x00 "PCIE_RC_GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP ,Request controller to send back-to-back EIEOS in RecoveryRcvrLock state until presets to coefficients mapping is complete - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " GEN3_EQ_PSET_REQ_AS_COEF              ,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field Do not use Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         GEN3_EQ_FOM_INC_INITIAL_EVAL            ,Include Initial FOM Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC                  ,Preset Request Vector Requesting of Presets during the initial part of the EQ Master Phase Encoding scheme is as follows: Bit [15:0] =0x 0: No preset is requested and evaluated in EQ Master Phase Bit [i] = 1: 'Preset=i' is requested and evaluated in EQ Master Phase - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx 1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: You must ensure 24 ms timeout does not occur in presets requests in EQ master phase, ie, you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky"
bitfld.long 0x00 7. "      RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " GEN3_LOWER_RATE_EQ_REDO_ENABLE        ,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
bitfld.long 0x00 5. "         GEN3_EQ_EVAL_2MS_DISABLE                ,Phase2_3 2 ms Timeout Disable Determine behavior in Phase2 for USP [Phase3 if DSP] when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE             ,Behavior After 24 ms Timeout [when optimal settings are not found] For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationPhase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the 'Link Status Register 2' For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationRcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the 'Link Status Register 2' Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode EQ requests for Figure Of Merit mode complete before 24 ms timeout Please see GEN3_EQ_PSET_REQ_VEC Register for more Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         GEN3_EQ_FB_MODE                         ,Feedback Mode - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - : Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18B4++0x3
line.long 0x00 "PCIE_RC_ORDER_RULE_CTRL_OFF,Order Rule Control Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      CPL_PASS_P                              ,Completion Passing Posted Ordering Rule Control Determines if CPL can pass halted P queue - 0: CPL can not pass P [recommended] - 1: CPL can pass P"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P                             ,Non-Posted Passing Posted Ordering Rule Control Determines if NP can pass halted P queue - 0 : NP can not pass P [recommended] - 1 : NP can pass P"
group.long 0x18B8++0x3
line.long 0x00 "PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register."
bitfld.long 0x00 31. " PIPE_LOOPBACK                         ,PIPE Loopback Enable Indicates RMMI Loopback if M-PCIe Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " RXSTATUS_VALUE                        ,RXSTATUS_VALUE is an internally reserved field Do not use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--23. "         RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " RXSTATUS_LANE                         ,RXSTATUS_LANE is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        LPBK_RXVALID                            ,LPBK_RXVALID is an internally reserved field Do not use Note: This register field is sticky"
group.long 0x18BC++0x3
line.long 0x00 "PCIE_RC_MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register."
hexmask.long 0x00 6.--31. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "  ARI_DEVICE_NUMBER                       ,When ARI is enabled, enables use of the device ID Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " RSVDP_4                               ,Reserved for future use" "0,1"
bitfld.long 0x00 3. "         SIMPLIFIED_REPLAY_TIMER                 ,Enables Simplified Replay Timer [Gen4] Simplified Replay Timer Values are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b Must not be changed while link is in use Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " UR_CA_MASK_4_TRGT1                    ,This field only applies to request TLPs [with UR filtering status] that you have chosen to forward to the application [when you set DEFAULT_TARGET in this register] - When you set this field to '1', the core suppresses error logging, Error Message generation, and CPL generation [for non-posted requests] - You should set this if you have set the Default Target port logic register to '1' Default is CX_MASK_UR_CA_4_TRGT1 configuration parameter Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         DEFAULT_TARGET                          ,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller - 0: The controller drops all incoming I/O or MEM requests [after corresponding error reporting] A completion with UR status will be generated for non-posted requests - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET configuration parameter Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " DBI_RO_WR_EN                          ,Write to RO Registers Using DBI When you set this field to '1', then some RO and HwInit bits are writable from the local application through the DBI Note: This register field is sticky" "0,1"
group.long 0x18C0++0x3
line.long 0x00 "PCIE_RC_MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 7. "    UPCONFIGURE_SUPPORT                     ,Upconfigure Support The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in ConfigurationComplete state This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " DIRECT_LINK_WIDTH_CHANGE              ,Directed Link Width Change The controller always moves to Configuration state through Recovery state when this bit is set to '1' - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in" "0,1"
bitfld.long 0x00 0.--5. "         TARGET_LINK_WIDTH                       ,Target Link Width Values correspond to: - 6'b 000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state - 6'b 000001: x 1 - 6'b 000010: x 2 - 6'b 000100: x 4 - 6'b 001000: x 8 - 6'b 010000: x 16 - 6'b 100000: x32 This field is reserved [fixed to '0'] for M-PCIe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18C4++0x3
line.long 0x00 "PCIE_RC_PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default."
hexmask.long.tbyte 0x00 11.--31. 1. " RSVDP_11                              ,Reserved for future use"
bitfld.long 0x00 10. "    L1_CLK_SEL                              ,L1 Clock control bit - 1: Controller does not request aux_clk switch and core_clk gating in L 1 - 0: Controller requests aux_clk switch and core_clk gating in L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " L1_NOWAIT_P1                          ,L1 entry control bit - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L 1 - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1 Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         L1SUB_EXIT_MODE                         ,L1 Exit Control Using phy_mac_pclkack_n - 1: Core exits L1 without waiting for the PHY to assert phy_mac_pclkack_n - 0: Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " RSVDP_7                               ,Reserved for future use" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         RXSTANDBY_CONTROL                       ,Rxstandby Control Bits 05 determine if the controller asserts the RxStandby signal [mac_phy_rxstandby] in the indicated condition Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP 2 - [4]: RxL0sIdle - [5]: EI Infer in L 0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
hgroup.long 0x18C8++0x3
hide.long 0x00 "PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason. Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire."
in
textline "                                                              "
group.long 0x18CC++0x3
line.long 0x00 "PCIE_RC_LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register."
hexmask.long.byte 0x00 24.--31. 1. " RSVD_I_8                              ,This is an internally reserved field Do not use Note: This register field is sticky"
hexmask.long.tbyte 0x00 1.--23. 1. "        RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " AUTO_FLUSH_EN                         ,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge The flushing process is initiated if any of the following events occur: - Hot reset request A downstream port [DSP] can 'hot reset' an upstream port [USP] by sending two consecutive TS1 ordered sets with the hot reset bit asserted - Warm [Soft] reset request Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst= 0 - Link down reset request A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge Note: This register field is sticky" "0,1"
group.long 0x18D0++0x3
line.long 0x00 "PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 10.--15. "      AMBA_ERROR_RESPONSE_MAP                 ,AXI Slave Response Error Map Allows you to selectively map the errors received from the PCIe completion [for non-posted requests] to the AXI slave responses, slv_rresp or slv_bresp The recommended setting is SLVERR CRS is always mapped to OKAY - [0] -- 0: UR [unsupported request] -> DECERR -- 1: UR [unsupported request] -> SLVERR - [1] -- 0: CRS [configuration retry status] -> DECERR -- 1: CRS [configuration retry status] -> SLVERR - [2] -- 0: CA [completer abort] -> DECERR -- 1: CA [completer abort] -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops [processes internally but not passed to your application] a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface It waits for a timeout and then signals 'Completion Timeout' to the slave interface The controller sets the AXI slave read databus to 0xFFFF for all error responses Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 5.--9. " RSVDP_5                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--4. "        AMBA_ERROR_RESPONSE_CRS                 ,CRS Slave Error Response Mapping Determines the AXI slave response for CRS completions AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " AMBA_ERROR_RESPONSE_VENDORID          ,Vendor ID Non-existent Slave Error Response Mapping Determines the AXI slave response for errors on reads to non-existent Vendor ID register AHB: - 0: OKAY [with FFFF data] The controller ignores the setting in the bit when bit 0 of this register is '0' - 1: ERROR AXI: - 0: OKAY [with FFFF data] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " AMBA_ERROR_RESPONSE_GLOBAL            ,Global Slave Error Response Mapping Determines the AXI slave response for all error scenarios on non-posted requests AHB: - 0: OKAY [with FFFF data for non-posted requests] and ignore the setting in bit [2] of this register - 1: ERROR for normal link [data] accesses and look at bit [2] for other scenarios AXI: - 0: OKAY [with FFFF data for non-posted requests] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] The error response mapping is not applicable to Non-existent Vendor ID register reads Note: This register field is sticky" "0,1"
group.long 0x18D4++0x3
line.long 0x00 "PCIE_RC_AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a 'flush' timer. The timeout value of the timer is set by this register. The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests."
hexmask.long.tbyte 0x00 9.--31. 1. " RSVDP_9                               ,Reserved for future use"
bitfld.long 0x00 8. "    LINK_TIMEOUT_ENABLE_DEFAULT             ,Disable Flush You can disable the flush feature by setting this field to '1' Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " LINK_TIMEOUT_PERIOD_DEFAULT           ,Timeout Value [ms] The timer will timeout and then flush the bridge TX request queues after this amount of time The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests The timer is clocked by core_clk For an M-PCIe configuration: - Time unit of this field is 4 ms - Margin of error for RateA clock is < 1% - Margin of error for RateB clock is between 16% and 17% Note: This register field is sticky"
group.long 0x18D8++0x3
line.long 0x00 "PCIE_RC_AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control."
hexmask.long 0x00 5.--31. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 3.--4. "  AX_MSTR_ORDR_P_EVENT_SEL                ,AXI Master Posted Ordering Event Selector This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, 'NP must not pass P' at the AXI Master Interface The AXI protocol does not support ordering between channels Therefore, NP reads can pass P on your AXI bus fabric This can result in an ordering violation when the read overtakes a P that is going to the same address Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination It does this by waiting for the all of the write responses on the B channel This can affect the performance of the master read channel For scenarios where the interconnect serializes the AXI master 'AW', 'W' and 'AR' channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave [default] - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master - 11: Reserved Note 2: This setting will not affect: - MSI interrupt catcher and P data ordering This is always driven by the B'last event - DMA read engine TLP ordering This is always driven by the B'last event - NP write transactions which are always serialized with P write transactions" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 1. "         AX_SNP_EN                               ,AXI Serialize Non-Posted Requests Enable This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
group.long 0x18E0++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1"
hexmask.long 0x00 2.--31. 1. " CFG_MEMTYPE_BOUNDARY_LOW_ADDR         ,Boundary Lower Address For Memory Type Bits [31:0] of dword-aligned address of the boundary for Memory type The two lower address LSBs are '00' Addresses up to but not including this value are in the lower address space region addresses equal or greater than this value are in the upper address space region Note: This register field is sticky"
bitfld.long 0x00 1. "  RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE                     ,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral upper = Memory - 1: lower = Memory type upper = Peripheral Note: This register field is sticky" "0,1"
group.long 0x18E4++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2"
hexmask.long 0x00 0.--31. 1. " CFG_MEMTYPE_BOUNDARY_HIGH_ADDR        ,Boundary Upper Address For Memory Type Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type Note: This register field is sticky"
group.long 0x18E8++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3"
bitfld.long 0x00 27.--30. " CFG_MSTR_AWCACHE_VALUE                ,Master Write CACHE Signal Value Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1' Note: not applicable to message requests for message requests the value of mstr_awcache is always '0000' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--22. "        CFG_MSTR_ARCACHE_VALUE                  ,Master Read CACHE Signal Value Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 11.--14. " CFG_MSTR_AWCACHE_MODE                 ,Master Write CACHE Signal Behavior Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always '0000' regardless of the value of this bit Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--6. "        CFG_MSTR_ARCACHE_MODE                   ,Master Read CACHE Signal Behavior Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18F0++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the and registers."
hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW              ,Lower 20 bits of the programmable AXI address for Messages Note: This register field is sticky"
group.long 0x18F4++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to."
hexmask.long 0x00 0.--31. 1. " CFG_AXIMSTR_MSG_ADDR_HIGH             ,Upper 32 bits of the programmable AXI address for Messages Note: This register field is sticky"
rgroup.long 0x18F8++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_NUMBER                        ,Version Number"
rgroup.long 0x18FC++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_TYPE                          ,Version Type"
group.long 0x1940++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 2.--31. 1. " MSIX_ADDRESS_MATCH_LOW                ,MSI-X Address Match Low Address Note: This register field is sticky"
bitfld.long 0x00 0. "  MSIX_ADDRESS_MATCH_EN                   ,MSI-X Match Enable Enable the MSI-X Address Match feature when the AXI bridge is present Note: This register field is sticky" "0,1"
group.long 0x1944++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 0.--31. 1. " MSIX_ADDRESS_MATCH_HIGH               ,MSI-X Address Match High Address Note: This register field is sticky"
group.long 0x1948++0x3
line.long 0x00 "PCIE_RC_MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. - For AXI configurations: when your local application writes (MWr) to the address defined in , the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs."
bitfld.long 0x00 24.--28. " MSIX_DOORBELL_PF                      ,MSIX Doorbell Physical Function This register determines the Physical Function for the MSI-X transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--23. 1. "        MSIX_DOORBELL_VF                        ,MSIX Doorbell Virtual Function This register determines the Virtual Function for the MSI-X transaction"
textline "                                                              "
bitfld.long 0x00 15. " MSIX_DOORBELL_VF_ACTIVE               ,MSIX Doorbell Virtual Function Active This register determines whether a Virtual Function is used to generate the MSI-X transaction" "0,1"
bitfld.long 0x00 12.--14. "         MSIX_DOORBELL_TC                        ,MSIX Doorbell Traffic Class This register determines which traffic class to generate the MSI-X transaction with" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 0.--10. 1. " MSIX_DOORBELL_VECTOR                  ,MSI-X Doorbell Vector This register determines which vector to generate the MSI-X transaction for"
group.long 0x194C++0x3
line.long 0x00 "PCIE_RC_MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests."
bitfld.long 0x00 25. " MSIX_RAM_CTRL_DBG_PBA                 ,MSIX PBA RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the PBA Use can also use the dbg_pba input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         MSIX_RAM_CTRL_DBG_TABLE                 ,MSIX Table RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the Table Use can also use the dbg_table input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " MSIX_RAM_CTRL_BYPASS                  ,MSIX RAM Control Bypass The bypass field, when set, disables the internal generation of low power signals for both RAMs It is up to the application to ensure the RAMs are in the proper power state before trying to access them Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         MSIX_RAM_CTRL_PBA_SD                    ,MSIX PBA RAM Shut Down Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " MSIX_RAM_CTRL_PBA_DS                  ,MSIX PBA RAM Deep Sleep Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         MSIX_RAM_CTRL_TABLE_SD                  ,MSIX Table RAM Shut Down Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " MSIX_RAM_CTRL_TABLE_DS                ,MSIX Table RAM Deep Sleep Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
group.long 0x1B40++0x3
line.long 0x00 "PCIE_RC_AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register."
hexmask.long.tbyte 0x00 10.--31. 1. " RSVDP_10                              ,Reserved for future use"
hexmask.long.word 0x00 0.--9. 1. "    AUX_CLK_FREQ                            ,The aux_clk frequency in MHz This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted If the actual frequency [f] of aux_clk does not exactly match the programmed frequency [f_prog], then there is an error in the time counted by the controller that can be expressed in percentage as: err% = [f_prog/f-1]*100 For example if f=25 MHz and f_prog=3 MHz, then err% =[3/ 25-1]* 100 =20%, meaning that the time counted by the controller on aux_clk will be 20 0reater than the time in us programmed in the corresponding time register [for example T_POWER_ON] Note: This register field is sticky"
group.long 0x1B44++0x3
line.long 0x00 "PCIE_RC_L1_SUBSTATES_OFF,L1 Substates Timing Register."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 6.--7. "    L1SUB_T_PCLKACK                         ,Max delay [in 1us units] between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n If the PHY does not respond within this time the request is aborted Range is 03 Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2.--5. " L1SUB_T_L1_2                          ,Duration [in 1us units] of L12 Range is 015 Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        L1SUB_T_POWER_OFF                       ,Duration [in 1us units] of L12Entry Range is 03 Note: This register field is sticky" "0,1,2,3"
group.long 0x6000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x600C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x610C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x620C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x630C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x640C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x650C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x660C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x670C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x680C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x690C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x700C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x710C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x720C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x730C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x740C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x750C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x760C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x770C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x780C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x790C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
width 0x0B
tree.end
tree "PCIE1_DAT"
base ad:0x5600000
width 53.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_RC_PID,Peripheral Version and ID Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                                 ,Module ID of the Peripheral"
bitfld.long 0x00 11.--15. "      RTL                                     ,RTL Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 8.--10. " MAJOR                                 ,Major Revision Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                  ,Custom Code" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 0.--5. " MINOR                                 ,Minor Revision Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "PCIE_RC_CMD_STATUS,Command Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. " RSVD11                                ,Reserved"
bitfld.long 0x00 7. "    RX_LANE_FLIP_EN                         ,Set to enable manual reversal for RX lanes. This drives the rx_lane_flip_en input of the PCIe core" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " TX_LANE_FLIP_EN                       ,Set to enable manual reversal for TX lanes. This drives the tx_lane_flip_en input of the PCIe core" "0,1"
bitfld.long 0x00 5. "         DBI_CS2                                 ,Set to enable writing to BAR mask registers that are overlaid on BAR registers." "0,1"
textline "                                                              "
bitfld.long 0x00 4. " APP_RETRY_EN                          ,Application Request Retry Enable. Setting this bit will enable all incoming PCIe transactions to be returned with a retry response. This feature can be used if initialization can take longer than PCIe stipulated time frame." "0,1"
bitfld.long 0x00 1.--3. "         RSVD10                                  ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " LTSSM_EN                              ,Link Training Enable. Setting this bit will enable LTSSM in PCI Express Core and link negotiation with link partner will begin." "0,1"
group.long 0x14++0x3
line.long 0x00 "PCIE_RC_RSTCMD,Reset Command and Status Register"
bitfld.long 0x00 29.--31. " RSVD21                                ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "         FLR_PF_ACTIVE                           ,Function-level reset for physical function active. 1 - FLR for Physical function 0 is active" "0,1"
textline "                                                              "
hexmask.long 0x00 1.--27. 1. " RSVD20                                ,Reserved"
bitfld.long 0x00 0. "  INIT_RST                                ,Write one to initiate a downstream hot reset sequence on downstream" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_RC_PTMCFG,PTM Config register"
hexmask.long.tbyte 0x00 14.--31. 1. " RSVD32                                ,Reserved"
bitfld.long 0x00 8.--13. "    PTM_CLK_SEL                             ,Select ptm_local_clk bit input to CPTS. 0 will select ptm_local_clk[0], 1 will select ptm_local_clk[1] ... 63 will select ptm_local_clk[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVD30                                ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_CONTEXT_VALID                       ,'1' indicates PTM context is valid-EP only" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_MANUAL_UPDATE                     ,Write '1' to enable PTM transaction.EP only. EP will initiate one PTM transaction when this field is updated. Always reads '0'" "0,1"
bitfld.long 0x00 0. "         PTM_AUTO_UPDATE                         ,Write '1' to enable PTM auto-update-EP only. EP will automatically initiate PTM transaction every 10ms" "0,1"
group.long 0x20++0x3
line.long 0x00 "PCIE_RC_PMCMD,Power Management Command Register"
hexmask.long 0x00 2.--31. 1. " RSVD40                                ,Reserved"
bitfld.long 0x00 1. "  PM_XMT_TURNOFF                          ,Write one to transmit a PM_TURNOFF message. Reads zero. Applicable in RC mode only." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_XMT_PE                             ,Write one to transmit a PM_PME message for Physical Function 0. Reads zero. Applicable to EP mode only." "0,1"
group.long 0x50++0x3
line.long 0x00 "PCIE_RC_IRQ_EOI,End of Interrupt Register"
hexmask.long 0x00 5.--31. 1. " RSVD60                                ,Reserved"
bitfld.long 0x00 0.--3. "  EOI                                     ,EOI for interrupts. Write to indicate end-of-interrupt for the respective interrupt. EOI value has to be the following as indicated below to toggle the interrupts in the various interrupt registers EOI = 0 for LEGACY_A_IRQ, EOI = 1 for LEGACY_B_IRQ, EOI = 2 for LEGACY_C_IRQ, EOI = 3 for LEGACY_D_IRQ, EOI = 4 for MMR0_IRQ, EOI = 5 for MMR1_IRQ, EOI = 6 for MMR2_IRQ, EOI = 7 for MMR3_IRQ, EOI = 8 for MMR4_IRQ, EOI = 9 for MMR5_IRQ, EOI = 10 for MMR6_IRQ, EOI = 11 for MMR7_IRQ, EOI = 12 for ERR_IRQ, EOI = 13 for PMRST_IRQ, EOI = 14 for PTM_IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "PCIE_RC_MMR_IRQ,Memory Mapped Interrupt IRQ Register"
hexmask.long 0x00 0.--30. 1. " MMR_IRQ                               ,This register is not used in RC mode."
group.long 0x64++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_SET,Legacy Interrupt Request Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD70                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_SET_0                        ,Write one to generate assert legacy PCI interrupt message for Physical Function0. On read, a one indicates currently asserted interrupt." "0,1"
hgroup.long 0x68++0x3
hide.long 0x00 "PCIE_RC_LEGACY_IRQ_CLR,Legacy Interrupt Request Clear Register"
in
textline "                                                              "
rgroup.long 0x6C++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_STATUS,Legacy Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD90                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_STATUS_0                     ,Indicates whether legacy PCI interrupt for physical function 0 is asserted or not" "0,1"
group.long 0x70++0x3
line.long 0x00 "PCIE_RC_GPR0,General Purpose 0 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC0                              ,Generic Info field 0"
group.long 0x74++0x3
line.long 0x00 "PCIE_RC_GPR1,General Purpose 1 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC1                              ,Generic Info field 1"
group.long 0x78++0x3
line.long 0x00 "PCIE_RC_GPR2,General Purpose 2 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC2                              ,Generic Info field 2"
group.long 0x7C++0x3
line.long 0x00 "PCIE_RC_GPR3,General Purpose 3 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC3                              ,Generic Info field 3"
group.long 0x100++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS_RAW,MMR 0 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD100                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (24, 16, 8, 0) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x104++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS,MMR 0 Interrupt Status Register"
in
textline "                                                              "
group.long 0x108++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_SET,MMR 0 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD111                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (24, 16, 8, 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x10C++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_CLR,MMR 0 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x110++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS_RAW,MMR 1 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD120                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (25, 17, 9, 1) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x114++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS,MMR 1 Interrupt Status Register"
in
textline "                                                              "
group.long 0x118++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_SET,MMR 1 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD122                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (25, 17, 9, 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x11C++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_CLR,MMR 1 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x120++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS_RAW,MMR 2 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD130                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (26, 18, 10, 2) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x124++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS,MMR 2 Interrupt Status Register"
in
textline "                                                              "
group.long 0x128++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_SET,MMR 2 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD132                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (26, 18, 10, 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x12C++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_CLR,MMR 2 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x130++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS_RAW,MMR 3 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD140                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (27, 19, 11, 3) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x134++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS,MMR 3 Interrupt Status Register"
in
textline "                                                              "
group.long 0x138++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_SET,MMR 3 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD142                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (27, 19, 11, 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x13C++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_CLR,MMR 3 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x140++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS_RAW,MMR 4 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD150                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (28, 20, 12, 4) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x144++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS,MMR 4 Interrupt Status Register"
in
textline "                                                              "
group.long 0x148++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_SET,MMR 4 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD152                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (28, 20, 12, 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x14C++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_CLR,MMR 4 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x150++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS_RAW,MMR 5 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD160                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (29, 21, 13, 5) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x154++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS,MMR 5 Interrupt Status Register"
in
textline "                                                              "
group.long 0x158++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_SET,MMR 5 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD162                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (29, 21, 13, 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x15C++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_CLR,MMR 5 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x160++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS_RAW,MMR 6 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD170                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (30, 22, 14, 6) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x164++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS,MMR 6 Interrupt Status Register"
in
textline "                                                              "
group.long 0x168++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_SET,MMR 6 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD172                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (30, 22, 14, 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x16C++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_CLR,MMR 6 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x170++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS_RAW,MMR 7 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD180                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_STATUS_RAW                     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x174++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS,MMR 7 Interrupt Status Register"
in
textline "                                                              "
group.long 0x178++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_SET,MMR 7 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD182                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (31, 23, 15, 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x17C++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_CLR,MMR 7 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x180++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS_RAW,Legacy A Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD200                               ,Reserved"
bitfld.long 0x00 0. "  INTA_RAW                                ,Legacy Interrupt A raw status. RC mode only" "0,1"
hgroup.long 0x184++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS,Legacy A Raw Interrupt Status Register"
in
textline "                                                              "
group.long 0x188++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_SET,Legacy A Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD220                               ,Reserved"
bitfld.long 0x00 0. "  INTA_EN_SET                             ,Legacy Interrupt A enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x18C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_CLR,Legacy A Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x190++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS_RAW,Legacy B Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD300                               ,Reserved"
bitfld.long 0x00 0. "  INTB_RAW                                ,Legacy Interrupt B raw status. RC mode only" "0,1"
hgroup.long 0x194++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS,Legacy B Interrupt Status Register"
in
textline "                                                              "
group.long 0x198++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_SET,Legacy B Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD320                               ,Reserved"
bitfld.long 0x00 0. "  INTB_EN_SET                             ,Legacy Interrupt B enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x19C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_CLR,Legacy B Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1A0++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS_RAW,Legacy C Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD400                               ,Reserved"
bitfld.long 0x00 0. "  INTC_RAW                                ,Legacy Interrupt C raw status. RC mode only" "0,1"
hgroup.long 0x1A4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS,Legacy C Interrupt Status Register"
in
textline "                                                              "
group.long 0x1A8++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_SET,Legacy C Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD420                               ,Reserved"
bitfld.long 0x00 0. "  INTC_EN_SET                             ,Legacy Interrupt C enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1AC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_CLR,Legacy C Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1B0++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS_RAW,Legacy D Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD500                               ,Reserved"
bitfld.long 0x00 0. "  INTD_RAW                                ,Legacy Interrupt D raw status. RC mode only" "0,1"
hgroup.long 0x1B4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS,Legacy D Interrupt Status Register"
in
textline "                                                              "
group.long 0x1B8++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_SET,Legacy D Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD520                               ,Reserved"
bitfld.long 0x00 0. "  INTD_EN_SET                             ,Legacy Interrupt D enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1BC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_CLR,Legacy D Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1C0++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status Register"
hexmask.long 0x00 5.--31. 1. " RSVD600                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_RAW                             ,AER MSI error raw status. This interrupt is generated due to the assertion of the cfg_aer_rc_err_int or the cfg_aer_err_msi output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_RAW                          ,Correctable error raw status. This interrupt is generated due to the assertion of the radm_correctable_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_RAW                        ,Nonfatal error raw status. This interrupt is generated due to the assertion of the radm_nonfatal_err output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_RAW                         ,Fatal error raw status. This interrupt is generated due to the assertion of the radm_fatal_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_RAW                             ,System Error (FATAL, NONFATAL or CORRECTABLE error) raw status. This interrupt is generated due to the assertion of the cfg_sys_err_rc output of the PCIe controller core." "0,1"
hgroup.long 0x1C4++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_STATUS,"
in
textline "                                                              "
group.long 0x1C8++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_SET,"
hexmask.long 0x00 5.--31. 1. " RSVD620                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_EN_SET                          ,AER MSI error interrupt enable. Set to enable. On read, one/zero means enabled/disabled respectively" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_EN_SET                       ,Correctable error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_EN_SET                     ,Nonfatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_EN_SET                      ,Fatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_EN_SET                          ,System Error (FATAL, NONFATAL or CORRECTABLE error) interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1CC++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_CLR,"
in
textline "                                                              "
group.long 0x1D0++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD700                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_RAW                         ,Link Request Reset interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_RAW                            ,Power Management PME message received interrupt raw status" "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_RAW                           ,Power Management ACK received interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_RAW                        ,Power Management Turnoff message received raw status" "0,1"
hgroup.long 0x1D4++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS,Power Management and Reset Interrupt Status Register"
in
textline "                                                              "
group.long 0x1D8++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_SET,Power Management and Reset Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD720                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_EN_SET                      ,Link Request Reset interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_EN_SET                         ,Power Management PME message received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_EN_SET                        ,Power Management ACK received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_EN_SET                     ,Power Management Turnoff message received enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1DC++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1E0++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_STATUS_RAW,Precision Time Measurement Raw Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD800                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_RAW                     ,Precision Time Measurement interrupt raw status" "0,1"
hgroup.long 0x1E4++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_STATUS,Precision Time Measurement Status Register"
in
textline "                                                              "
group.long 0x1E8++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_SET,Precision Time Measurement Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD820                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_EN_SET                  ,Precision Time Measurement interrupt enable set. Write one to set" "0,1"
hgroup.long 0x1EC++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_CLR,Precision Time Measurement Enable Clear Register"
in
textline "                                                              "
rgroup.long 0x1000++0x3
line.long 0x00 "PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID                             ,Device ID - Vendor Assigned Device Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      VENDOR_ID                               ,Vendor ID - PCI-SIG assigned Manufacturer Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1004++0x3
hide.long 0x00 "PCIE_RC_TYPE1_STATUS_COMMAND_REG,Command and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1008++0x3
line.long 0x00 "PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE                       ,Base Class Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SUBCLASS_CODE                           ,Subclass Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTERFACE                     ,Class Code Programming Interface For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        REVISION_ID                             ,Vendor chosen Revision ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x100C++0x3
line.long 0x00 "PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST, Header Type, Cache Line Size, and Master Latency Timer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BIST                                  ,Optional for BIST support For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 23. "        MULTI_FUNC                              ,Specifies whether device is multifunction For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE                           ,Specifies Header Type For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "        LATENCY_MASTER_TIMER                    ,Primary Latency Timer Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE                       ,Cache Line Size field Has no effect on PCIe device behavior For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1018++0x3
line.long 0x00 "PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary, Secondary, Subordinate Bus Numbers and Latency Timer Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER                         ,Latency Timer Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 16.--23. 1. "        SUB_BUS                                 ,Subordinate Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS                               ,Secondary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 0.--7. 1. "        PRIM_BUS                                ,Primary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x101C++0x3
hide.long 0x00 "PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1020++0x3
line.long 0x00 "PCIE_RC_MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " MEM_LIMIT                             ,Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 16.--19. "      MEM_LIMIT_RESERV                        ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " MEM_BASE                              ,Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 0.--3. "      MEM_BASE_RESERV                         ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x3
line.long 0x00 "PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Base and Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PREF_MEM_LIMIT                        ,Prefetchable Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 17.--19. "      PREF_RESERV1                            ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE                 ,Prefetchable Memory Limit Decode For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 4.--15. 1. "         PREF_MEM_BASE                           ,Prefetchable Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 1.--3. " PREF_RESERV                           ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PREF_MEM_DECODE                         ,Prefetchable Memory Decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
rgroup.long 0x1028++0x3
line.long 0x00 "PCIE_RC_PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_BASE_UPPER                   ,Prefetchable Memory Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x102C++0x3
line.long 0x00 "PCIE_RC_PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_LIMIT_UPPER                  ,Prefetchable Memory Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1030++0x3
line.long 0x00 "PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " IO_LIMIT_UPPER                        ,Prefetchable I/O Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
hexmask.long.word 0x00 0.--15. 1. "      IO_BASE_UPPER                           ,Prefetchable I/O Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1034++0x3
line.long 0x00 "PCIE_RC_TYPE1_CAP_PTR_REG,Capability Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "    CAP_POINTER                             ,Pointer to first item in the PCI Capability Structure For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x1038++0x3
line.long 0x00 "PCIE_RC_TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register. For a description of this standard PCIe register, see the PCI Express Specification. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address."
hexmask.long.tbyte 0x00 11.--31. 1. " EXP_ROM_BASE_ADDRESS                  ,Expansion ROM BAR and Mask Register For a description of this standard PCIe register, see the PCI Express Specification The mask for this ROM BAR exists [if implemented] as a shadow register at this address The assertion of CS2 [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] is required to write to the second register at this address Note: The access attributes of this field are as follows: - Dbi: R/W"
hexmask.long.word 0x00 1.--10. 1. "    RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " ROM_BAR_ENABLE                        ,Expansion ROM Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x103C++0x3
line.long 0x00 "PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 23.--31. 1. " BRIDGE_CTRL_RESERV                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22. "      SBR                                     ,Secondary Bus Hot Reset For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 21. " MSTR_ABORT_MODE                       ,Master Abort Mode Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 20. "         VGA_16B_DEC                             ,VGA 16 bit decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " VGA_EN                                ,VGA Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
bitfld.long 0x00 18. "         ISA_EN                                  ,ISA Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " SERR_EN                               ,System Error Response Enable from Secondary to Primary For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         PERE                                    ,Parity Error Response Enable Controls Logging of Poisoned TLPs For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " INT_PIN                               ,PCI Compatible Interrupt Pin Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        INT_LINE                                ,PCI Compatible Interrupt Line Routing Register Field For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1040++0x3
line.long 0x00 "PCIE_RC_CAP_ID_NXT_PTR_REG,Power Management Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " PME_SUPPORT                           ,Power Management Event Support For a description of this standard PCIe register field, see the PCI Express Specification The read value from this field is the write value && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where D1_SUPPORT and D2_SUPPORT are fields in this register The reset value PME_SUPPORT_n && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where PME_SUPPORT_n is a configuration parameter Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        D2_SUPPORT                              ,D2 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " D1_SUPPORT                            ,D1 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 22.--24. "         AUX_CURR                                ,Auxiliary Current Requirements For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 21. " DSI                                   ,Device Specific Initialization Bit For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         PME_CLK                                 ,PCI Clock Requirement For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16.--18. " PM_SPEC_VER                           ,Power Management Spec Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "         PM_NEXT_POINTER                         ,Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID                             ,Power Management Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x1044++0x3
hide.long 0x00 "PCIE_RC_CON_STATUS_REG,Power Management Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1050++0x3
line.long 0x00 "PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID, Next Pointer, Capability/Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        PCI_MSI_EXT_DATA_EN                     ,Extended Message Data Enable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_EXT_DATA_CAP ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP                  ,Extended Message Data Capable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         PCI_PVM_SUPPORT                         ,MSI Per Vector Masking Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP               ,MSI 64-bit Address Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 20.--22. "         PCI_MSI_MULTIPLE_MSG_EN                 ,MSI Multiple Message Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP              ,MSI Multiple Message Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         PCI_MSI_ENABLE                          ,MSI Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSI_CAP_NEXT_OFFSET               ,MSI Capability Next Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSI_CAP_ID                          ,MSI Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1054++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_04H_REG,MSI Message Lower Address Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " PCI_MSI_CAP_OFF_04H                   ,MSI Message Lower Address Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 0.--1. "  RSVDP_0                                 ,Reserved for future use" "0,1,2,3"
group.long 0x1058++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_08H_REG,For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0AH                   ,For a 32 bit MSI Message, this field contains Ext MSI Data For 64-bit it contains upper 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_08H                     ,For a 32-bit MSI Message, this field contains Data For 64-bit it contains lower 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R"
group.long 0x105C++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_0CH_REG,For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0EH                   ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the upper Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: [!MSI_64_EN && MSI_PVM_EN_VALUE] ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_0CH                     ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the lower Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR MSI_PVM_EN ? R/W : R"
group.long 0x1060++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_10H                   ,Used for MSI when Vector Masking Capable For 32-bit contains Pending Bits For 64-bit, contains Mask Bits For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R"
rgroup.long 0x1064++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_14H_REG,Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_14H                   ,Used for MSI 64-bit messaging when Vector Masking Capable Contains Pending Bits For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1070++0x3
line.long 0x00 "PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities, ID, Next Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         RSVD                                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM                      ,PCIE Interrupt Message Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "        PCIE_SLOT_IMP                           ,PCIe Slot Implemented Valid For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE                    ,PCIE Device/PortType For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PCIE_CAP_REG                            ,PCIE Capability Version Number For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR                     ,PCIE Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCIE_CAP_ID                             ,PCIE Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1074++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES_REG,Device Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      PCIE_CAP_ROLE_BASED_ERR_REPORT          ,Role-based Error Reporting Implemented For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 6.--14. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "      PCIE_CAP_EXT_TAG_SUPP                   ,Extended Tag Field Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT         ,Phantom Functions Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 0.--2. "         PCIE_CAP_MAX_PAYLOAD_SIZE               ,Max Payload Size Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hgroup.long 0x1078++0x3
hide.long 0x00 "PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x107C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES_REG,Link Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM                     ,Port Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE          ,ASPM Optionality Compliance For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 21. "         PCIE_CAP_LINK_BW_NOT_CAP                ,Link Bandwidth Notification Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP           ,Data Link Layer Link Active Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 19. "         PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP      ,Surprise Down Error Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN              ,Clock Power Management For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 15.--17. "         PCIE_CAP_L1_EXIT_LATENCY                ,L1 Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY             ,LOs Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--11. "         PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT   ,Level of ASPM [Active State Power Management] Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH               ,Maximum Link Width For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. "        PCIE_CAP_MAX_LINK_SPEED                 ,Maximum Link Speed For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1080++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1084++0x3
line.long 0x00 "PCIE_RC_SLOT_CAPABILITIES_REG,Slot Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM                 ,Physical Slot Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 18. "      PCIE_CAP_NO_CMD_CPL_SUPPORT             ,No Command Completed Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK        ,Electromechanical Interlock Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 15.--16. "         PCIE_CAP_SLOT_POWER_LIMIT_SCALE         ,Slot Power Limit Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE       ,Slot Power Limit Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 6. "        PCIE_CAP_HOT_PLUG_CAPABLE               ,Hot Plug Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE            ,Hot Plug Surprise possible For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_POWER_INDICATOR                ,Power Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR          ,Attention Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_MRL_SENSOR                     ,MRL Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER             ,Power Controller Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_ATTENTION_INDICATOR_BUTTON     ,Attention Button Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
hgroup.long 0x1088++0x3
hide.long 0x00 "PCIE_RC_SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x108C++0x3
line.long 0x00 "PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      PCIE_CAP_CRS_SW_VISIBILITY              ,CRS Software Visibility Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W [Sticky] else R [Sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 5.--15. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 4. "      PCIE_CAP_CRS_SW_VISIBILITY_EN           ,Configuration Request Retry Status [CRS] Software Visibility Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REGPCIE_CAP_CRS_SW_VISIBILITY ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN                   ,PME Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN        ,System Error on Fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN  ,System Error on Non-fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN         ,System Error on Correctable Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1090++0x3
hide.long 0x00 "PCIE_RC_ROOT_STATUS_REG,Root Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1094++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--30. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 18.--19. "        PCIE_CAP_OBFF_SUPPORT                   ,[OBFF] Optimized Buffer Flush/fill Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT      ,10-Bit Tag Requester Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
bitfld.long 0x00 16. "         PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT       ,10-Bit Tag Completer Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPPORT_1          ,TPH Completer Supported Bit 1 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 12. "         PCIE_CAP_TPH_CMPLT_SUPPORT_0            ,TPH Completer Supported Bit 0 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP                     ,LTR Mechanism Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 10. "         PCIE_CAP_NO_RO_EN_PR2PR_PAR             ,No Relaxed Ordering Enabled PR-PR Passing For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP             ,128 Bit CAS Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 8. "         PCIE_CAP_64_ATOMIC_CPL_SUPP             ,64 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP           ,32 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 6. "         PCIE_CAP_ATOMIC_ROUTING_SUPP            ,Atomic Operation Routing Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT          ,ARI Forwarding Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT    ,Completion Timeout Disable Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE            ,Completion Timeout Ranges Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1098++0x3
line.long 0x00 "PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS       ,ARI Forwarding Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE            ,Completion Timeout Disable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VALUE            ,Completion Timeout Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x109C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES2_REG,Link Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 25.--30. " RSVDP_25                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 9.--22. 1. "        RSVDP_9                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT           ,Cross Link Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR      ,Supported Link Speeds Vector For a description of this standard PCIe register field, see the PCI Express Specification This field has a default of [PCIE_CAP_MAX_LINK_SPEED == 0100] ? 0001111 : [PCIE_CAP_MAX_LINK_SPEED == 0011] ? 0000111 : [PCIE_CAP_MAX_LINK_SPEED == 0010] ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the PCIE_RC_LINK_CAPABILITIES_REG register"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
hgroup.long 0x10A0++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x10B0++0x3
line.long 0x00 "PCIE_RC_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID, Next Pointer, Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " PCI_MSIX_ENABLE                       ,MSI-X Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 30. "         PCI_MSIX_FUNCTION_MASK                  ,Function Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--26. 1. "         PCI_MSIX_TABLE_SIZE                     ,MSI-X Table Size For a description of this standard PCIe register field, see the PCI Express Specification SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' [PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG] To write this common value, you must perform a DBI_CS2 write [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] while accessing the PCI_MSIX_TABLE_SIZE field in the PF"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSIX_CAP_NEXT_OFFSET              ,MSI-X Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSIX_CAP_ID                         ,MSI-X Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x10B4++0x3
line.long 0x00 "PCIE_RC_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_TABLE_OFFSET                 ,MSI-X Table Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_BIR                            ,MSI-X Table Bar Indicator Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x10B8++0x3
line.long 0x00 "PCIE_RC_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_PBA_OFFSET                   ,MSI-X PBA Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_PBA                            ,MSI-X PBA BIR For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x1100++0x3
line.long 0x00 "PCIE_RC_AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " CAP_ID                                ,AER Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1104++0x3
hide.long 0x00 "PCIE_RC_UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1108++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_MASK               ,TLP Prefix Blocked Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK        ,AtomicOp Egress Block Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_MASK                     ,Uncorrectable Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_MASK                ,Unsupported Request Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_MASK                         ,ECRC Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_MASK                       ,Malformed TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK                 ,Receiver Overflow Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_MASK                    ,Unexpected Completion Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK                  ,Completer Abort Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_MASK                  ,Completion Timeout Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK                  ,Flow Control Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_MASK                       ,Poisoned TLP Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_MASK                  ,Surprise Down Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK                  ,Data Link Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110C++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_SEVERITY           ,TLP Prefix Blocked Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY    ,AtomicOp Egress Blocked Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_SEVERITY                 ,Uncorrectable Internal Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_SEVERITY            ,Unsupported Request Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_SEVERITY                     ,ECRC Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_SEVERITY                   ,Malformed TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_SEVERITY             ,Receiver Overflow Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_SEVERITY                ,Unexpected Completion Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_SEVERITY              ,Completer Abort Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_SEVERITY              ,Completion Timeout Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_SEVERITY              ,Flow Control Protocol Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_SEVERITY                   ,Poisoned TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_SVRITY                ,Surprise Down Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_SEVERITY              ,Data Link Protocol Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1110++0x3
hide.long 0x00 "PCIE_RC_CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1114++0x3
line.long 0x00 "PCIE_RC_CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      HEADER_LOG_OVERFLOW_MASK                ,Header Log Overflow Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14. " CORRECTED_INT_ERR_MASK                ,Corrected Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 13. "         ADVISORY_NON_FATAL_ERR_MASK             ,Advisory Non-Fatal Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RPL_TIMER_TIMEOUT_MASK                ,Replay Timer Timeout Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 9.--11. "         RSVDP_9                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8. " REPLAY_NO_ROLEOVER_MASK               ,REPLAY_NUM Rollover Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 7. "         BAD_DLLP_MASK                           ,Bad DLLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " BAD_TLP_MASK                          ,Bad TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 1.--5. "         RSVDP_1                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 0. " RX_ERR_MASK                           ,Receiver Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
group.long 0x1118++0x3
line.long 0x00 "PCIE_RC_ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10. "    MULTIPLE_HEADER_EN                      ,Multiple Header Recording Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " MULTIPLE_HEADER_CAP                   ,Multiple Header Recording Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         ECRC_CHECK_EN                           ,ECRC Check Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " ECRC_CHECK_CAP                        ,ECRC Check Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 6. "         ECRC_GEN_EN                             ,ECRC Generation Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " ECRC_GEN_CAP                          ,ECRC Generation Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--4. "         FIRST_ERR_POINTER                       ,First Error Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x111C++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FIRST_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FIRST_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1120++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SECOND_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SECOND_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        SECOND_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1124++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        THIRD_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " THIRD_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        THIRD_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1128++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FOURTH_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FOURTH_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
group.long 0x112C++0x3
line.long 0x00 "PCIE_RC_ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " RSVDP_3                               ,Reserved for future use"
bitfld.long 0x00 2. "  FATAL_ERR_REPORTING_EN                  ,Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN            ,Non-Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         CORR_ERR_REPORTING_EN                   ,Correctable Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1130++0x3
hide.long 0x00 "PCIE_RC_ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1134++0x3
line.long 0x00 "PCIE_RC_ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID         ,Source of Fatal/Non-Fatal Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      ERR_COR_SOURCE_ID                       ,Source of Correctable Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1138++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE         ,Byte 3 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_1_THIRD_BYTE            ,Byte 2 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE         ,Byte 1 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_1_FIRST_BYTE            ,Byte 0 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x113C++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_2_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_2_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1140++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_3_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_3_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1144++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_4_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_4_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1148++0x3
line.long 0x00 "PCIE_RC_VC_BASE,VC Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " VC_NEXT_OFFSET                        ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      VC_CAP_VERSION                          ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " VC_PCIE_EXTENDED_CAP_ID               ,VC Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x114C++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_1,Port VC Capability Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10.--11. "    VC_PORT_ARBI_TBL_ENTRY_SIZE             ,Port Arbitration Table Entry Size For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 8.--9. " VC_REFERENCE_CLOCK                    ,Reference Clock For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
bitfld.long 0x00 7. "         RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " VC_LOW_PRI_EXT_VC_CNT                 ,Low Priority Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RSVDP_3                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--2. " VC_EXT_VC_CNT                         ,Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
rgroup.long 0x1150++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_2,Port VC Capability Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_ARBI_TABLE_OFFSET                  ,VC Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.tbyte 0x00 4.--23. 1. "        RSVDP_4                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0.--3. " VC_ARBI_CAP                           ,VC Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1154++0x3
line.long 0x00 "PCIE_RC_VC_STATUS_CONTROL_REG,Port VC Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      VC_ARBI_TABLE_STATUS                    ,VC Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " RSVDP_4                               ,Reserved for future use"
bitfld.long 0x00 1.--3. "      VC_ARBI_SELECT                          ,VC Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " VC_LOAD_VC_ARBI_TABLE                 ,Requests Hardware to Load VC Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1158++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC0,VC Resource Capability Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC0                ,Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC0                  ,Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC0               ,Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC0                    ,Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x115C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC0,VC Resource Control Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC0                         ,VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC                              ,VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--23. "         RSVDP_18                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 17. " VC_PORT_ARBI_SELECT_VC0               ,Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC0             ,Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC0_BIT1                      ,Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC0                         ,Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1160++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC0,VC Resource Status Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC0                     ,VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC0         ,Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1164++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC1,VC Resource Capability Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC1                ,VC1 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC1                  ,VC1 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC1               ,VC1 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC1                    ,VC1 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1168++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC1,VC Resource Control Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC1                         ,VC1 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC1                             ,VC1 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC1               ,VC1 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC1             ,VC1 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC1_BIT1                      ,VC1 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC1                         ,VC1 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x116C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC1,VC Resource Status Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC1                     ,VC1 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC1         ,VC1 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1170++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC2,VC Resource Capability Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC2                ,VC2 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC2                  ,VC2 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC2               ,VC2 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC2                    ,VC2 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1174++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC2,VC Resource Control Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC2                         ,VC2 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC2                             ,VC2 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC2               ,VC2 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC2             ,VC2 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC2_BIT1                      ,VC2 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC2                         ,VC2 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1178++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC2,VC Resource Status Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC2                     ,VC2 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC2         ,VC2 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x117C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC3,VC Resource Capability Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC3                ,VC3 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC3                  ,VC3 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC3               ,VC3 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC3                    ,VC3 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1180++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC3,VC Resource Control Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC3                         ,VC3 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC3                             ,VC3 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC3               ,VC3 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC3             ,VC3 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC3_BIT1                      ,VC3 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC3                         ,VC3 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1184++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC3,VC Resource Status Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC3                     ,VC3 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC3         ,VC3 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1198++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,Secondary PCI Express Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x119C++0x3
line.long 0x00 "PCIE_RC_LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  EQ_REQ_INT_EN                           ,Link Equalization Request Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PERFORM_EQ                            ,Perform Equalization For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
hgroup.long 0x11A0++0x3
hide.long 0x00 "PCIE_RC_LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x11A4++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 28.--30. "         USP_RX_PRESET_HINT1                     ,Upstream Port 80 GT/s Receiver Preset Hint 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 24.--27. " USP_TX_PRESET1                        ,Upstream Port 80 GT/s Transmitter Preset 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1                   ,Downstream Port 80 GT/s Receiver Preset Hint 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         DSP_TX_PRESET1                          ,Downstream Port 80 GT/s Transmitter Preset 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 15. " RSVDP_15                              ,Reserved for future use" "0,1"
bitfld.long 0x00 12.--14. "         USP_RX_PRESET_HINT0                     ,Upstream Port 80 GT/s Receiver Preset Hint 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--11. " USP_TX_PRESET0                        ,Upstream Port 80 GT/s Transmitter Preset 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0                   ,Downstream Port 80 GT/s Receiver Preset Hint 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         DSP_TX_PRESET0                          ,Downstream Port 80 GT/s Transmitter Preset 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x11A8++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,L1SUB Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x11AC++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAPABILITY_REG,L1 Substates Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 19.--23. "        PWR_ON_VALUE_SUPPORT                    ,Port T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 18. " RSVDP_18                              ,Reserved for future use" "0,1"
bitfld.long 0x00 16.--17. "         PWR_ON_SCALE_SUPPORT                    ,Port T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " COMM_MODE_SUPPORT                     ,Port Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 5.--7. "        RSVDP_5                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 4. " L1_PMSUB_SUPPORT                      ,L1 PM Substates ECN Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 3. "         L1_1_ASPM_SUPPORT                       ,ASPM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT                     ,ASPM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_SUPPORT                      ,PCI-PM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_SUPPORT                    ,PCI-PM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x11B0++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 29.--31. " L1_2_TH_SCA                           ,LTR L12 Threshold Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "         RSVDP_26                                ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 16.--25. 1. " L1_2_TH_VAL                           ,LTR L12 Threshold Value For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "      T_COMMON_MODE                           ,Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
textline "                                                              "
bitfld.long 0x00 4.--7. " RSVDP_4                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        L1_1_ASPM_EN                            ,ASPM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_EN                          ,ASPM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_EN                           ,PCI-PM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_EN                         ,PCI-PM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
group.long 0x11B4++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 3.--7. "    T_POWER_ON_VALUE                        ,T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 0.--1. "         T_POWER_ON_SCALE                        ,T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
rgroup.long 0x11B8++0x3
line.long 0x00 "PCIE_RC_PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PTM_NEXT_OFFSET                       ,Precision Time Measurement PCI Express Extended Capability Next Offset For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_CAP_VERSION                         ,Precision Time Measurement PCI Express Extended Capability Version For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_CAP_ID                            ,Precision Time Measurement PCI Express Extended Capability ID For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11BC++0x3
line.long 0x00 "PCIE_RC_PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      PTM_CLK_GRAN                            ,PTM Local Clock Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVDP_3                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_ROOT_CAPABLE                        ,PTM Root Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_RES_CAPABLE                       ,PTM Responder Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 0. "         PTM_REQ_CAPABLE                         ,PTM Requester Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
group.long 0x11C0++0x3
line.long 0x00 "PCIE_RC_PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      EFF_GRAN                                ,PTM Effective Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT"
textline "                                                              "
bitfld.long 0x00 2.--7. " RSVDP_2                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        ROOT_SELECT                             ,PTM Root Select When set this Time Source is the PTM Root For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_ENABLE                            ,PTM Enable When set, this function is permitted to participate in the PTM mechanism For a description of this standard PCIe register, see the PCI Express Specification" "0,1"
rgroup.long 0x11C4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC)."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_EXT_CAP_NEXT_OFFS             ,Precision Time Measurement Responder VSEC Next Pointer Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_EXT_CAP_VER                     ,Precision Time Measurement Responder VSEC Version Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_EXT_CAP_ID                    ,Precision Time Measurement Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11C8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. ."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_VSEC_LENGTH                   ,PTM Responder VSEC Length Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_VSEC_REV                        ,PTM Responder VSEC Revision Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_VSEC_ID                       ,PTM Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11CC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CONTROL_OFF,PTM Responder Control Register. ."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  PTM_RES_CCONTEXT_VALID                  ,PTM Responder Control Context Valid - PTM Local Timing is valid This bit is set over the DBI A speed change or aux_clk_active will set this bit low Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x11D0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_STATUS_OFF,PTM Responder Status Register. ."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  PTM_RES_REQUEST_RECEIVED                ,PTM 1st Request Received - PTM Responder has received the first PTM Request Message Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder, if the context is valid If the context is invalid a Response message will be sent instead Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_RES_CONTEXT_VALID                 ,PTM Responder Status Context Valid - PTM Local Timing Context is Valid Value set from upstream port Requester in a Switch Shadows the same in the control register in all other products Note: This register field is sticky" "0,1"
rgroup.long 0x11D4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_LSB                     ,PTM Responder Local Clock LSB - Lower 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11D8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_MSB                     ,PTM Responder Local Clock MSB - Upper 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11DC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_LSB                        ,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_MSB                        ,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_LSB                       ,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_MSB                       ,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11EC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_LSB                        ,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_MSB                        ,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_LSB                       ,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_MSB                       ,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
group.long 0x11FC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_TX_LATENCY                      ,PTM Responder TX Latency - Responder Transmit path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1200++0x3
line.long 0x00 "PCIE_RC_PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_RX_LATENCY                      ,PTM Responder RX Latency - Responder Receive path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1700++0x3
line.long 0x00 "PCIE_RC_ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register."
hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT                     ,Replay Timer Limit The replay timer expires when it reaches this limit The controller initiates a replay upon reception of a NAK or when the replay timer expires You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 30 specification If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
hexmask.long.word 0x00 0.--15. 1. "      ROUND_TRIP_LATENCY_TIME_LIMIT           ,Ack Latency Timer Limit The Ack latency timer expires when it reaches this limit You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 30 specification The limit must reflect the round trip latency from requester to completer If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_ACK_NAK field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
group.long 0x1704++0x3
line.long 0x00 "PCIE_RC_VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register."
hexmask.long 0x00 0.--31. 1. " VENDOR_SPEC_DLLP                      ,Vendor Specific DLLP Register Used to send a specific PCI Express DLLP Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of"
hgroup.long 0x1708++0x3
hide.long 0x00 "PCIE_RC_PORT_FORCE_OFF,Port Force Link Register."
in
textline "                                                              "
group.long 0x170C++0x3
line.long 0x00 "PCIE_RC_ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         ENTER_ASPM                              ,ASPM L1 Entry Control - 1: Core enters ASPM L1 after a period in which it has been idle - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " L1_ENTRANCE_LATENCY                   ,L1 Entrance Latency Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         L0S_ENTRANCE_LATENCY                    ,L0s Entrance Latency Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 16.--23. 1. " COMMON_CLK_N_FTS                      ,Common Clock N_FTS This is the N_FTS when common clock is used The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 This field is only writable [sticky] when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 8.--15. 1. "        ACK_N_FTS                               ,N_FTS The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " ACK_FREQ                              ,Ack Frequency The controller accumulates the number of pending ACKs specified here [up to 255] before sending an ACK DLLP - 0: Indicates that this Ack frequency control feature is turned off The controller schedules a low-priority ACK DLLP for every TLP that it receives - 1- 255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs It might schedule the ACK before receiving this number of TLPs, but never later For a typical system, you do not have to modify the default setting Note: This register field is sticky"
hgroup.long 0x1710++0x3
hide.long 0x00 "PCIE_RC_PORT_LINK_CTRL_OFF,Port Link Control Register."
in
textline "                                                              "
group.long 0x1714++0x3
line.long 0x00 "PCIE_RC_LANE_SKEW_OFF,Lane Skew Register."
bitfld.long 0x00 31. " DISABLE_LANE_TO_LANE_DESKEW           ,Disable Lane-to-Lane Deskew Causes the controller to disable the internal Lane-to-Lane deskew logic Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         IMPLEMENT_NUM_LANES                     ,Implementation-specific Number of Lanes Set the implementation-specific number of lanes Allowed values are: - 4'b 0000: 1 lane - 4'b 0001: 2 lanes - 4'b 0011: 4 lanes - 4'b 0111: 8 lanes - 4'b 1111: 16 lanes The number of lanes to be used when in Loopback Master The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field The controller will transition from LoopbackEntry to LoopbackActive after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 26. " LANE_SKEW_OFF_26                      ,Reserved Read/Write regsiter for future use Note: This register field is sticky" "0,1"
bitfld.long 0x00 25. "         ACK_NAK_DISABLE                         ,Ack/Nak Disable Prevents the controller from sending ACK and NAK DLLPs Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " FLOW_CTRL_DISABLE                     ,Flow Control Disable Prevents the controller from sending FC DLLPs Note: This register field is sticky" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. "         INSERT_LANE_SKEW                        ,Insert Lane Skew for Transmit [not supported for x16] Optional feature that causes the controller to insert skew between Lanes for test purposes There are three bits per Lane The value is in units of one symbol time For example, the value 010b for a Lane forces a skew of two symbol times for that Lane The maximum skew value for any Lane is 5 symbol times Note: This register field is sticky"
group.long 0x1718++0x3
line.long 0x00 "PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 29.--30. "         FAST_LINK_SCALING_FACTOR                ,Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field inPCIE_RC_PORT_LINK_CTRL_OFF is set to '1' - 0: Scaling Factor is 1024 [1ms is 1us] - 1: Scaling Factor is 256 [1ms is 4us] - 2: Scaling Factor is 64 [1ms is 16us] - 3: Scaling Factor is 16 [1ms is 64us] Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0' Not used for M-PCIe Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--28. " UPDATE_FREQ_TIMER                     ,UPDATE_FREQ_TIMER is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19.--23. "        TIMER_MOD_ACK_NAK                       ,Ack Latency Timer Modifier Increases the timer value for the Ack latency timer in increments of 64 clock cycles A value of '0' represents no modification to the timer value For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 14.--18. " TIMER_MOD_REPLAY_TIMER                ,Replay Timer Limit Modifier Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed A value of '0' represents no modification to the timer limit For more details, see the REPLAY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RSVDP_8                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MAX_FUNC_NUM                          ,Maximum function number that can be used in a request Configuration requests targeted at function numbers above this value are returned with UR [unsupported request] Note: This register field is sticky"
group.long 0x171C++0x3
line.long 0x00 "PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long.word 0x00 16.--31. 1. " MASK_RADM_1                           ,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD 0: For RADM RC filter to not allow CFG transaction being received 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD 0: For RADM RC filter to not allow IO transaction being received 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP 0: Drop MSG TLP [except for Vendor MSG]. Send decoded message on the SII. 1: Do not Drop MSG [except for Vendor MSG]. Send message TLPs to your application on TRGT1 and send decoded message on the SII. The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG = 1, then the default of this bit is '0' [drop message TLPs]. This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 [or AXI bridge master], as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. 0: Discard completions with ECRC errors 1: Allow completions with ECRC errors to be passed up Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD 0: Discard TLPs with ECRC errors 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH 0: Enforce Req Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Req Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_c? 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR 0: Treat locked Read TLPs as UR for EP; Supported for RC 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR 0: Treat CFG type1 TLPs as UR for EP; Supported for RC 1: Treat CFG type1 TLPs as Supported for EP; UR for RC When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests, if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR 0: Treat out-of-bar TLPs as UR 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS 0: Treat poisoned request TLPs as UR 1: Do not treat poisoned request TLPs as UR The native controller always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH 0: Treat Function MisMatched TLPs as UR 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky."
bitfld.long 0x00 15. "      DISABLE_FC_WD_TIMER                     ,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1"
textline "                                                              "
bitfld.long 0x00 11.--14. " EIDLE_TIMER                           ,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "        SKP_INT_VAL                             ,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register [in a 250 MHz controller], then the controller actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 [because one clock tick = two symbol times in this case]. Note: This value is not used at Gen3 speed. The skip interval is hardcoded to 370 blocks For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows: 2K_PPM_DISABLED = 1: 1280/CX_NB 2K_PPM_DISABLED = 0: 228/CX_NB You need to set this field again, if necessary, when 2K_PPM_DISABLED is changed. Note: This register field is sticky."
group.long 0x1720++0x3
line.long 0x00 "PCIE_RC_FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long 0x00 0.--31. 1. " MASK_RADM_2                           ,Filter Mask 2. This field modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
group.long 0x1724++0x3
line.long 0x00 "PCIE_RC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  OB_RD_SPLIT_BURST_EN                    ,Enable AMBA Multiple Outbound Decomposed NP SubRequests This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device [or switch] is reordering completions that have different tags Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x1728++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG0_OFF,Debug Register 0"
hexmask.long 0x00 0.--31. 1. " DEB_REG_0                             ,The value on cxpl_debug_info[31:0]"
rgroup.long 0x172C++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG1_OFF,Debug Register 1"
hexmask.long 0x00 0.--31. 1. " DEB_REG_1                             ,The value on cxpl_debug_info[63:32]"
rgroup.long 0x1730++0x3
line.long 0x00 "PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_P_HEADER_FC_CREDIT                   ,Transmit Posted Header FC Credits The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_P_DATA_FC_CREDIT                   ,Transmit Posted Data FC Credits The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1734++0x3
line.long 0x00 "PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_NP_HEADER_FC_CREDIT                  ,Transmit Non-Posted Header FC Credits The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_NP_DATA_FC_CREDIT                  ,Transmit Non-Posted Data FC Credits The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1738++0x3
line.long 0x00 "PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_CPL_HEADER_FC_CREDIT                 ,Transmit Completion Header FC Credits The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_CPL_DATA_FC_CREDIT                 ,Transmit Completion Data FC Credits The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
hgroup.long 0x173C++0x3
hide.long 0x00 "PCIE_RC_QUEUE_STATUS_OFF,Queue Status"
in
textline "                                                              "
rgroup.long 0x1740++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3                       ,WRR Weight for VC3 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_2                         ,WRR Weight for VC2 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1                       ,WRR Weight for VC1 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_0                         ,WRR Weight for VC0 Note: The access attributes of this field are as follows: - Dbi: R"
rgroup.long 0x1744++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_7                       ,WRR Weight for VC7 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_6                         ,WRR Weight for VC6 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_5                       ,WRR Weight for VC5 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_4                         ,WRR Weight for VC4 Note: The access attributes of this field are as follows: - Dbi: R"
group.long 0x1748++0x3
line.long 0x00 "PCIE_RC_VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control."
bitfld.long 0x00 31. " VC_ORDERING_RX_Q                      ,VC Ordering for Receive Queues Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         TLP_TYPE_ORDERING_VC0                   ,TLP Type Ordering for VC0 Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE                      ,VC0 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_P_HDR_SCALE                         ,VC0 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_P_TLP_Q_MODE                      ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_P_HEADER_CREDIT                     ,VC0 Posted Header Credits The number of initial posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CREDIT                     ,VC0 Posted Data Credits The number of initial posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x174C++0x3
line.long 0x00 "PCIE_RC_VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_NP_DATA_SCALE                     ,VC0 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_NP_HDR_SCALE                        ,VC0 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_NP_HEADER_CREDIT                    ,VC0 Non-Posted Header Credits The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_NP_DATA_CREDIT                    ,VC0 Non-Posted Data Credits The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1750++0x3
line.long 0x00 "PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_CPL_DATA_SCALE                    ,VC0 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_CPL_HDR_SCALE                       ,VC0 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_CPL_HEADER_CREDIT                   ,VC0 Completion Header Credits The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_CPL_DATA_CREDIT                   ,VC0 Completion Data Credits The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1754++0x3
line.long 0x00 "PCIE_RC_VC1_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC1                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC1_P_DATA_SCALE                        ,VC1 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC1_P_HDR_SCALE                       ,VC1 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC1_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC1_P_HEADER_CREDIT                   ,VC1 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC1_P_DATA_CREDIT                       ,VC1 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1758++0x3
line.long 0x00 "PCIE_RC_VC1_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_NP_DATA_SCALE                     ,VC1 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_NP_HDR_SCALE                        ,VC1 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x175C++0x3
line.long 0x00 "PCIE_RC_VC1_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_CPL_DATA_SCALE                    ,VC1 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_CPL_HDR_SCALE                       ,VC1 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1760++0x3
line.long 0x00 "PCIE_RC_VC2_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC2                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC2_P_DATA_SCALE                        ,VC2 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC2_P_HDR_SCALE                       ,VC2 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC2_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC2_P_HEADER_CREDIT                   ,VC2 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC2_P_DATA_CREDIT                       ,VC2 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1764++0x3
line.long 0x00 "PCIE_RC_VC2_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_NP_DATA_SCALE                     ,VC2 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_NP_HDR_SCALE                        ,VC2 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1768++0x3
line.long 0x00 "PCIE_RC_VC2_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_CPL_DATA_SCALE                    ,VC2 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_CPL_HDR_SCALE                       ,VC2 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x176C++0x3
line.long 0x00 "PCIE_RC_VC3_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC3                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC3_P_DATA_SCALE                        ,VC3 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC3_P_HDR_SCALE                       ,VC3 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC3_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC3_P_HEADER_CREDIT                   ,VC3 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC3_P_DATA_CREDIT                       ,VC3 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1770++0x3
line.long 0x00 "PCIE_RC_VC3_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_NP_DATA_SCALE                     ,VC3 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_NP_HDR_SCALE                        ,VC3 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1774++0x3
line.long 0x00 "PCIE_RC_VC3_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_CPL_DATA_SCALE                    ,VC3 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_CPL_HDR_SCALE                       ,VC3 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x180C++0x3
line.long 0x00 "PCIE_RC_GEN2_CTRL_OFF,Link Width and Speed Change Control Register."
hexmask.long.word 0x00 22.--31. 1. " RSVDP_22                              ,Reserved for future use"
bitfld.long 0x00 21. "      GEN1_EI_INFERENCE                       ,Electrical Idle Inference Mode at Gen1 Rate Programmable mode to determine inferred electrical idle [EI] in RecoverySpeed or LoopbackActive [as slave] state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking for a '0' on RxValid If the PHY fails to deassert the RxValid signal in RecoverySpeed or LoopbackActive [because of corrupted EIOS for example], then EI cannot be inferred successfully in the controller by just detecting the condition RxValid= 0 - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " SEL_DEEMPHASIS                        ,Used to set the de-emphasis level for upstream ports This bit selects the level of de-emphasis the link operates at - 0: -6 dB - 1: -35 dB This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         CONFIG_TX_COMP_RX                       ,Config Tx Compliance Receive Bit When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert [equal to '1'] This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE                  ,Config PHY Tx Swing Controls the PHY transmitter voltage swing level The controller drives the mac_phy_txswing output from this register bit field - 0: Full Swing - 1: Low Swing This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 17. "         DIRECT_SPEED_CHANGE                     ,Directed Speed Change Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed When the speed change occurs, the controller will clear the contents of this field and a read to this field by your software will return a '0' To manually initiate the speed change: - Write to PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to '1', then the speed change is initiated automatically after link up, and the controller clears the contents of this field If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register [LINK_CONTROL2_LINK_STATUS2_OFF PCIE_CAP_TARGET_LINK_SPEED] through the DBI before link up This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN                ,Enable Auto flipping of the lanes You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 13.--15. "         PRE_DET_LANE                            ,Predetermined Lane for Auto Flip This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect Allowed values are: - 3'b 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/ 2-1 or CX_NL/ 4-1 or CX_NL/ 8-1, depending on which lane is detected - 3'b 001: Connect logical Lane0 to physical lane 1 - 3'b 010: Connect logical Lane0 to physical lane 3 - 3'b 011: Connect logical Lane0 to physical lane 7 - 3'b 100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state Note: This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--12. " NUM_OF_LANES                          ,Predetermined Number of Lanes Defines the number of lanes which are connected and not bad Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver Indicates the number of lanes to check for exit from Electrical Idle in PollingActive and L2Idle It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured This value is referred to as the 'Predetermined Number of Lanes' in section 42621 of the PCI Express Base 30 Specification, revision 10 Encoding is as follows: - 0x 01: 1 lane - 0x 02: 2 lanes - 0x 03: 3 lanes - When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes You must also change the value in the 'Link Mode Enable' field of PCIE_RC_PORT_LINK_CTRL_OFF The value in this register is normally the same as the encoded value in PCIE_RC_PORT_LINK_CTRL_OFF If you find that one of your used lanes is bad then you must reduce the value in this register This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "        FAST_TRAINING_SEQ                       ,Sets the Number of Fast Training Sequences [N_FTS] that the controller advertises as its N_FTS during Gen2 or Gen3 link training This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state Do not set N_FTS to zero doing so can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky"
rgroup.long 0x1810++0x3
line.long 0x00 "PCIE_RC_PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins."
hexmask.long 0x00 0.--31. 1. " PHY_STATUS                            ,PHY Status Data received directly from the phy_cfg_status bus These is a GPIO register reflecting the values on the static phy_cfg_status input signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband status signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x1814++0x3
line.long 0x00 "PCIE_RC_PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins."
hexmask.long 0x00 0.--31. 1. " PHY_CONTROL                           ,PHY Control Data sent directly to the cfg_phy_control bus These is a GPIO register driving the values on the static cfg_phy_control output signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband control signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x181C++0x3
line.long 0x00 "PCIE_RC_TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register."
bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX                      ,The number of the PF Function on which the Target Values are set This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "        TARGET_MAP_ROM                          ,Target Value for the ROM page of the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--5. " TARGET_MAP_PF                         ,Target Values for each BAR on the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1820++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_ADDR                         ,Integrated MSI Reception Module Address System specified address for MSI memory write transaction termination Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register and also to see if it satisfies the definition of an MSI interrupt request When these conditions are satisfied the Memory Write request is marked as an MSI request Note: This register field is sticky"
group.long 0x1824++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_UPPER_ADDR                   ,Integrated MSI Reception Module Upper Address System specified upper address for MSI memory write transaction termination Allows functions to support a 64-bit MSI address Note: This register field is sticky"
group.long 0x1828++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x182C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1830++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1834++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1838++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x183C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1840++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1844++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1848++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x184C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1850++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1854++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1858++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x185C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1860++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1864++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1868++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x186C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1870++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1874++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1878++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x187C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1880++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1884++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1888++0x3
line.long 0x00 "PCIE_RC_MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register."
hexmask.long 0x00 0.--31. 1. " MSI_GPIO_REG                          ,MSI GPIO Register The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky"
group.long 0x188C++0x3
line.long 0x00 "PCIE_RC_CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register. Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g output will always be set to '1'."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  RADM_CLK_GATING_EN                      ,Enable Radm clock gating feature - 0: Disable - 1: Enable[default]" "0,1"
group.long 0x1890++0x3
line.long 0x00 "PCIE_RC_GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The 'Directed Speed Change' field in the 'Link Width and Speed Change Control Register' is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the 'Directed Speed Change' field is set to '1' and (2) the 'Target Link Speed' field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "        GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE        ,Eq InvalidRequest and RxEqEval Different Time Assertion Disable Disable the assertion of Eq InvalidRequest and RxEqEval at different time Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19.--20. " RSVDP_19                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 18. "         GEN3_DC_BALANCE_DISABLE                 ,DC Balance Disable Disable DC Balance feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE           ,DLLP Transmission Delay Disable Disable delay transmission of DLLPs before equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         GEN3_EQUALIZATION_DISABLE               ,Equalization Disable Disable equalization feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14.--15. " RSVDP_14                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 13. "         RXEQ_RGRDLESS_RXTS                      ,When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RXEQ_PH01_EN                          ,Rx Equalization Phase 0/Phase 1 Hold Enable When this bit is set the upstream port holds phase 0 [the downstream port holds phase 1] for 10ms Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY This bit is used during Virtex-7 Gen3 equalization The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/ 3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/ 1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
bitfld.long 0x00 11. "         EQ_REDO                                 ,Equalization Redo Disable Disable autonomous mechanism for requesting to redo the equalization process Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 10. " EQ_EIEOS_CNT                          ,Equalization EIEOS Count Reset Disable Disable requesting reset of EIEOS count during equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         EQ_PHASE_2_3                            ,Equalization Phase 2 and Phase 3 Disable This applies to downstream ports only Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3               ,Disable Scrambler for Gen3 and Gen4 Data Rate The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller [for example within the PHY] Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL                   ,Gen3 Receiver Impedance ZRX-DC Not Compliant Receivers that operate at 80 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 25 GT/s [40-60 Ohms] must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled - 0: The receiver complies with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher - 1: The receiver does not comply with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates Note: This register field is sticky" "0,1"
group.long 0x18A8++0x3
line.long 0x00 "PCIE_RC_GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP ,Request controller to send back-to-back EIEOS in RecoveryRcvrLock state until presets to coefficients mapping is complete - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " GEN3_EQ_PSET_REQ_AS_COEF              ,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field Do not use Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         GEN3_EQ_FOM_INC_INITIAL_EVAL            ,Include Initial FOM Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC                  ,Preset Request Vector Requesting of Presets during the initial part of the EQ Master Phase Encoding scheme is as follows: Bit [15:0] =0x 0: No preset is requested and evaluated in EQ Master Phase Bit [i] = 1: 'Preset=i' is requested and evaluated in EQ Master Phase - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx 1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: You must ensure 24 ms timeout does not occur in presets requests in EQ master phase, ie, you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky"
bitfld.long 0x00 7. "      RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " GEN3_LOWER_RATE_EQ_REDO_ENABLE        ,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
bitfld.long 0x00 5. "         GEN3_EQ_EVAL_2MS_DISABLE                ,Phase2_3 2 ms Timeout Disable Determine behavior in Phase2 for USP [Phase3 if DSP] when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE             ,Behavior After 24 ms Timeout [when optimal settings are not found] For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationPhase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the 'Link Status Register 2' For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationRcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the 'Link Status Register 2' Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode EQ requests for Figure Of Merit mode complete before 24 ms timeout Please see GEN3_EQ_PSET_REQ_VEC Register for more Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         GEN3_EQ_FB_MODE                         ,Feedback Mode - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - : Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18B4++0x3
line.long 0x00 "PCIE_RC_ORDER_RULE_CTRL_OFF,Order Rule Control Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      CPL_PASS_P                              ,Completion Passing Posted Ordering Rule Control Determines if CPL can pass halted P queue - 0: CPL can not pass P [recommended] - 1: CPL can pass P"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P                             ,Non-Posted Passing Posted Ordering Rule Control Determines if NP can pass halted P queue - 0 : NP can not pass P [recommended] - 1 : NP can pass P"
group.long 0x18B8++0x3
line.long 0x00 "PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register."
bitfld.long 0x00 31. " PIPE_LOOPBACK                         ,PIPE Loopback Enable Indicates RMMI Loopback if M-PCIe Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " RXSTATUS_VALUE                        ,RXSTATUS_VALUE is an internally reserved field Do not use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--23. "         RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " RXSTATUS_LANE                         ,RXSTATUS_LANE is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        LPBK_RXVALID                            ,LPBK_RXVALID is an internally reserved field Do not use Note: This register field is sticky"
group.long 0x18BC++0x3
line.long 0x00 "PCIE_RC_MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register."
hexmask.long 0x00 6.--31. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "  ARI_DEVICE_NUMBER                       ,When ARI is enabled, enables use of the device ID Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " RSVDP_4                               ,Reserved for future use" "0,1"
bitfld.long 0x00 3. "         SIMPLIFIED_REPLAY_TIMER                 ,Enables Simplified Replay Timer [Gen4] Simplified Replay Timer Values are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b Must not be changed while link is in use Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " UR_CA_MASK_4_TRGT1                    ,This field only applies to request TLPs [with UR filtering status] that you have chosen to forward to the application [when you set DEFAULT_TARGET in this register] - When you set this field to '1', the core suppresses error logging, Error Message generation, and CPL generation [for non-posted requests] - You should set this if you have set the Default Target port logic register to '1' Default is CX_MASK_UR_CA_4_TRGT1 configuration parameter Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         DEFAULT_TARGET                          ,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller - 0: The controller drops all incoming I/O or MEM requests [after corresponding error reporting] A completion with UR status will be generated for non-posted requests - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET configuration parameter Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " DBI_RO_WR_EN                          ,Write to RO Registers Using DBI When you set this field to '1', then some RO and HwInit bits are writable from the local application through the DBI Note: This register field is sticky" "0,1"
group.long 0x18C0++0x3
line.long 0x00 "PCIE_RC_MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 7. "    UPCONFIGURE_SUPPORT                     ,Upconfigure Support The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in ConfigurationComplete state This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " DIRECT_LINK_WIDTH_CHANGE              ,Directed Link Width Change The controller always moves to Configuration state through Recovery state when this bit is set to '1' - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in" "0,1"
bitfld.long 0x00 0.--5. "         TARGET_LINK_WIDTH                       ,Target Link Width Values correspond to: - 6'b 000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state - 6'b 000001: x 1 - 6'b 000010: x 2 - 6'b 000100: x 4 - 6'b 001000: x 8 - 6'b 010000: x 16 - 6'b 100000: x32 This field is reserved [fixed to '0'] for M-PCIe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18C4++0x3
line.long 0x00 "PCIE_RC_PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default."
hexmask.long.tbyte 0x00 11.--31. 1. " RSVDP_11                              ,Reserved for future use"
bitfld.long 0x00 10. "    L1_CLK_SEL                              ,L1 Clock control bit - 1: Controller does not request aux_clk switch and core_clk gating in L 1 - 0: Controller requests aux_clk switch and core_clk gating in L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " L1_NOWAIT_P1                          ,L1 entry control bit - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L 1 - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1 Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         L1SUB_EXIT_MODE                         ,L1 Exit Control Using phy_mac_pclkack_n - 1: Core exits L1 without waiting for the PHY to assert phy_mac_pclkack_n - 0: Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " RSVDP_7                               ,Reserved for future use" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         RXSTANDBY_CONTROL                       ,Rxstandby Control Bits 05 determine if the controller asserts the RxStandby signal [mac_phy_rxstandby] in the indicated condition Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP 2 - [4]: RxL0sIdle - [5]: EI Infer in L 0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
hgroup.long 0x18C8++0x3
hide.long 0x00 "PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason. Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire."
in
textline "                                                              "
group.long 0x18CC++0x3
line.long 0x00 "PCIE_RC_LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register."
hexmask.long.byte 0x00 24.--31. 1. " RSVD_I_8                              ,This is an internally reserved field Do not use Note: This register field is sticky"
hexmask.long.tbyte 0x00 1.--23. 1. "        RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " AUTO_FLUSH_EN                         ,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge The flushing process is initiated if any of the following events occur: - Hot reset request A downstream port [DSP] can 'hot reset' an upstream port [USP] by sending two consecutive TS1 ordered sets with the hot reset bit asserted - Warm [Soft] reset request Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst= 0 - Link down reset request A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge Note: This register field is sticky" "0,1"
group.long 0x18D0++0x3
line.long 0x00 "PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 10.--15. "      AMBA_ERROR_RESPONSE_MAP                 ,AXI Slave Response Error Map Allows you to selectively map the errors received from the PCIe completion [for non-posted requests] to the AXI slave responses, slv_rresp or slv_bresp The recommended setting is SLVERR CRS is always mapped to OKAY - [0] -- 0: UR [unsupported request] -> DECERR -- 1: UR [unsupported request] -> SLVERR - [1] -- 0: CRS [configuration retry status] -> DECERR -- 1: CRS [configuration retry status] -> SLVERR - [2] -- 0: CA [completer abort] -> DECERR -- 1: CA [completer abort] -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops [processes internally but not passed to your application] a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface It waits for a timeout and then signals 'Completion Timeout' to the slave interface The controller sets the AXI slave read databus to 0xFFFF for all error responses Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 5.--9. " RSVDP_5                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--4. "        AMBA_ERROR_RESPONSE_CRS                 ,CRS Slave Error Response Mapping Determines the AXI slave response for CRS completions AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " AMBA_ERROR_RESPONSE_VENDORID          ,Vendor ID Non-existent Slave Error Response Mapping Determines the AXI slave response for errors on reads to non-existent Vendor ID register AHB: - 0: OKAY [with FFFF data] The controller ignores the setting in the bit when bit 0 of this register is '0' - 1: ERROR AXI: - 0: OKAY [with FFFF data] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " AMBA_ERROR_RESPONSE_GLOBAL            ,Global Slave Error Response Mapping Determines the AXI slave response for all error scenarios on non-posted requests AHB: - 0: OKAY [with FFFF data for non-posted requests] and ignore the setting in bit [2] of this register - 1: ERROR for normal link [data] accesses and look at bit [2] for other scenarios AXI: - 0: OKAY [with FFFF data for non-posted requests] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] The error response mapping is not applicable to Non-existent Vendor ID register reads Note: This register field is sticky" "0,1"
group.long 0x18D4++0x3
line.long 0x00 "PCIE_RC_AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a 'flush' timer. The timeout value of the timer is set by this register. The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests."
hexmask.long.tbyte 0x00 9.--31. 1. " RSVDP_9                               ,Reserved for future use"
bitfld.long 0x00 8. "    LINK_TIMEOUT_ENABLE_DEFAULT             ,Disable Flush You can disable the flush feature by setting this field to '1' Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " LINK_TIMEOUT_PERIOD_DEFAULT           ,Timeout Value [ms] The timer will timeout and then flush the bridge TX request queues after this amount of time The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests The timer is clocked by core_clk For an M-PCIe configuration: - Time unit of this field is 4 ms - Margin of error for RateA clock is < 1% - Margin of error for RateB clock is between 16% and 17% Note: This register field is sticky"
group.long 0x18D8++0x3
line.long 0x00 "PCIE_RC_AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control."
hexmask.long 0x00 5.--31. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 3.--4. "  AX_MSTR_ORDR_P_EVENT_SEL                ,AXI Master Posted Ordering Event Selector This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, 'NP must not pass P' at the AXI Master Interface The AXI protocol does not support ordering between channels Therefore, NP reads can pass P on your AXI bus fabric This can result in an ordering violation when the read overtakes a P that is going to the same address Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination It does this by waiting for the all of the write responses on the B channel This can affect the performance of the master read channel For scenarios where the interconnect serializes the AXI master 'AW', 'W' and 'AR' channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave [default] - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master - 11: Reserved Note 2: This setting will not affect: - MSI interrupt catcher and P data ordering This is always driven by the B'last event - DMA read engine TLP ordering This is always driven by the B'last event - NP write transactions which are always serialized with P write transactions" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 1. "         AX_SNP_EN                               ,AXI Serialize Non-Posted Requests Enable This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
group.long 0x18E0++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1"
hexmask.long 0x00 2.--31. 1. " CFG_MEMTYPE_BOUNDARY_LOW_ADDR         ,Boundary Lower Address For Memory Type Bits [31:0] of dword-aligned address of the boundary for Memory type The two lower address LSBs are '00' Addresses up to but not including this value are in the lower address space region addresses equal or greater than this value are in the upper address space region Note: This register field is sticky"
bitfld.long 0x00 1. "  RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE                     ,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral upper = Memory - 1: lower = Memory type upper = Peripheral Note: This register field is sticky" "0,1"
group.long 0x18E4++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2"
hexmask.long 0x00 0.--31. 1. " CFG_MEMTYPE_BOUNDARY_HIGH_ADDR        ,Boundary Upper Address For Memory Type Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type Note: This register field is sticky"
group.long 0x18E8++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3"
bitfld.long 0x00 27.--30. " CFG_MSTR_AWCACHE_VALUE                ,Master Write CACHE Signal Value Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1' Note: not applicable to message requests for message requests the value of mstr_awcache is always '0000' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--22. "        CFG_MSTR_ARCACHE_VALUE                  ,Master Read CACHE Signal Value Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 11.--14. " CFG_MSTR_AWCACHE_MODE                 ,Master Write CACHE Signal Behavior Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always '0000' regardless of the value of this bit Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--6. "        CFG_MSTR_ARCACHE_MODE                   ,Master Read CACHE Signal Behavior Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18F0++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the and registers."
hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW              ,Lower 20 bits of the programmable AXI address for Messages Note: This register field is sticky"
group.long 0x18F4++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to."
hexmask.long 0x00 0.--31. 1. " CFG_AXIMSTR_MSG_ADDR_HIGH             ,Upper 32 bits of the programmable AXI address for Messages Note: This register field is sticky"
rgroup.long 0x18F8++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_NUMBER                        ,Version Number"
rgroup.long 0x18FC++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_TYPE                          ,Version Type"
group.long 0x1940++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 2.--31. 1. " MSIX_ADDRESS_MATCH_LOW                ,MSI-X Address Match Low Address Note: This register field is sticky"
bitfld.long 0x00 0. "  MSIX_ADDRESS_MATCH_EN                   ,MSI-X Match Enable Enable the MSI-X Address Match feature when the AXI bridge is present Note: This register field is sticky" "0,1"
group.long 0x1944++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 0.--31. 1. " MSIX_ADDRESS_MATCH_HIGH               ,MSI-X Address Match High Address Note: This register field is sticky"
group.long 0x1948++0x3
line.long 0x00 "PCIE_RC_MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. - For AXI configurations: when your local application writes (MWr) to the address defined in , the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs."
bitfld.long 0x00 24.--28. " MSIX_DOORBELL_PF                      ,MSIX Doorbell Physical Function This register determines the Physical Function for the MSI-X transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--23. 1. "        MSIX_DOORBELL_VF                        ,MSIX Doorbell Virtual Function This register determines the Virtual Function for the MSI-X transaction"
textline "                                                              "
bitfld.long 0x00 15. " MSIX_DOORBELL_VF_ACTIVE               ,MSIX Doorbell Virtual Function Active This register determines whether a Virtual Function is used to generate the MSI-X transaction" "0,1"
bitfld.long 0x00 12.--14. "         MSIX_DOORBELL_TC                        ,MSIX Doorbell Traffic Class This register determines which traffic class to generate the MSI-X transaction with" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 0.--10. 1. " MSIX_DOORBELL_VECTOR                  ,MSI-X Doorbell Vector This register determines which vector to generate the MSI-X transaction for"
group.long 0x194C++0x3
line.long 0x00 "PCIE_RC_MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests."
bitfld.long 0x00 25. " MSIX_RAM_CTRL_DBG_PBA                 ,MSIX PBA RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the PBA Use can also use the dbg_pba input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         MSIX_RAM_CTRL_DBG_TABLE                 ,MSIX Table RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the Table Use can also use the dbg_table input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " MSIX_RAM_CTRL_BYPASS                  ,MSIX RAM Control Bypass The bypass field, when set, disables the internal generation of low power signals for both RAMs It is up to the application to ensure the RAMs are in the proper power state before trying to access them Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         MSIX_RAM_CTRL_PBA_SD                    ,MSIX PBA RAM Shut Down Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " MSIX_RAM_CTRL_PBA_DS                  ,MSIX PBA RAM Deep Sleep Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         MSIX_RAM_CTRL_TABLE_SD                  ,MSIX Table RAM Shut Down Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " MSIX_RAM_CTRL_TABLE_DS                ,MSIX Table RAM Deep Sleep Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
group.long 0x1B40++0x3
line.long 0x00 "PCIE_RC_AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register."
hexmask.long.tbyte 0x00 10.--31. 1. " RSVDP_10                              ,Reserved for future use"
hexmask.long.word 0x00 0.--9. 1. "    AUX_CLK_FREQ                            ,The aux_clk frequency in MHz This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted If the actual frequency [f] of aux_clk does not exactly match the programmed frequency [f_prog], then there is an error in the time counted by the controller that can be expressed in percentage as: err% = [f_prog/f-1]*100 For example if f=25 MHz and f_prog=3 MHz, then err% =[3/ 25-1]* 100 =20%, meaning that the time counted by the controller on aux_clk will be 20 0reater than the time in us programmed in the corresponding time register [for example T_POWER_ON] Note: This register field is sticky"
group.long 0x1B44++0x3
line.long 0x00 "PCIE_RC_L1_SUBSTATES_OFF,L1 Substates Timing Register."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 6.--7. "    L1SUB_T_PCLKACK                         ,Max delay [in 1us units] between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n If the PHY does not respond within this time the request is aborted Range is 03 Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2.--5. " L1SUB_T_L1_2                          ,Duration [in 1us units] of L12 Range is 015 Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        L1SUB_T_POWER_OFF                       ,Duration [in 1us units] of L12Entry Range is 03 Note: This register field is sticky" "0,1,2,3"
group.long 0x6000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x600C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x610C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x620C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x630C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x640C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x650C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x660C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x670C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x680C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x690C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x700C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x710C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x720C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x730C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x740C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x750C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x760C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x770C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x780C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x790C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
width 0x0B
tree.end
tree.end
tree.end
tree "PCIE_CORE_RC"
tree "PCIE_DAT"
tree "PCIE0_DAT"
base ad:0x5500000
width 53.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_RC_PID,Peripheral Version and ID Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                                 ,Module ID of the Peripheral"
bitfld.long 0x00 11.--15. "      RTL                                     ,RTL Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 8.--10. " MAJOR                                 ,Major Revision Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                  ,Custom Code" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 0.--5. " MINOR                                 ,Minor Revision Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "PCIE_RC_CMD_STATUS,Command Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. " RSVD11                                ,Reserved"
bitfld.long 0x00 7. "    RX_LANE_FLIP_EN                         ,Set to enable manual reversal for RX lanes. This drives the rx_lane_flip_en input of the PCIe core" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " TX_LANE_FLIP_EN                       ,Set to enable manual reversal for TX lanes. This drives the tx_lane_flip_en input of the PCIe core" "0,1"
bitfld.long 0x00 5. "         DBI_CS2                                 ,Set to enable writing to BAR mask registers that are overlaid on BAR registers." "0,1"
textline "                                                              "
bitfld.long 0x00 4. " APP_RETRY_EN                          ,Application Request Retry Enable. Setting this bit will enable all incoming PCIe transactions to be returned with a retry response. This feature can be used if initialization can take longer than PCIe stipulated time frame." "0,1"
bitfld.long 0x00 1.--3. "         RSVD10                                  ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " LTSSM_EN                              ,Link Training Enable. Setting this bit will enable LTSSM in PCI Express Core and link negotiation with link partner will begin." "0,1"
group.long 0x14++0x3
line.long 0x00 "PCIE_RC_RSTCMD,Reset Command and Status Register"
bitfld.long 0x00 29.--31. " RSVD21                                ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "         FLR_PF_ACTIVE                           ,Function-level reset for physical function active. 1 - FLR for Physical function 0 is active" "0,1"
textline "                                                              "
hexmask.long 0x00 1.--27. 1. " RSVD20                                ,Reserved"
bitfld.long 0x00 0. "  INIT_RST                                ,Write one to initiate a downstream hot reset sequence on downstream" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_RC_PTMCFG,PTM Config register"
hexmask.long.tbyte 0x00 14.--31. 1. " RSVD32                                ,Reserved"
bitfld.long 0x00 8.--13. "    PTM_CLK_SEL                             ,Select ptm_local_clk bit input to CPTS. 0 will select ptm_local_clk[0], 1 will select ptm_local_clk[1] ... 63 will select ptm_local_clk[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVD30                                ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_CONTEXT_VALID                       ,'1' indicates PTM context is valid-EP only" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_MANUAL_UPDATE                     ,Write '1' to enable PTM transaction.EP only. EP will initiate one PTM transaction when this field is updated. Always reads '0'" "0,1"
bitfld.long 0x00 0. "         PTM_AUTO_UPDATE                         ,Write '1' to enable PTM auto-update-EP only. EP will automatically initiate PTM transaction every 10ms" "0,1"
group.long 0x20++0x3
line.long 0x00 "PCIE_RC_PMCMD,Power Management Command Register"
hexmask.long 0x00 2.--31. 1. " RSVD40                                ,Reserved"
bitfld.long 0x00 1. "  PM_XMT_TURNOFF                          ,Write one to transmit a PM_TURNOFF message. Reads zero. Applicable in RC mode only." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_XMT_PE                             ,Write one to transmit a PM_PME message for Physical Function 0. Reads zero. Applicable to EP mode only." "0,1"
group.long 0x50++0x3
line.long 0x00 "PCIE_RC_IRQ_EOI,End of Interrupt Register"
hexmask.long 0x00 5.--31. 1. " RSVD60                                ,Reserved"
bitfld.long 0x00 0.--3. "  EOI                                     ,EOI for interrupts. Write to indicate end-of-interrupt for the respective interrupt. EOI value has to be the following as indicated below to toggle the interrupts in the various interrupt registers EOI = 0 for LEGACY_A_IRQ, EOI = 1 for LEGACY_B_IRQ, EOI = 2 for LEGACY_C_IRQ, EOI = 3 for LEGACY_D_IRQ, EOI = 4 for MMR0_IRQ, EOI = 5 for MMR1_IRQ, EOI = 6 for MMR2_IRQ, EOI = 7 for MMR3_IRQ, EOI = 8 for MMR4_IRQ, EOI = 9 for MMR5_IRQ, EOI = 10 for MMR6_IRQ, EOI = 11 for MMR7_IRQ, EOI = 12 for ERR_IRQ, EOI = 13 for PMRST_IRQ, EOI = 14 for PTM_IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "PCIE_RC_MMR_IRQ,Memory Mapped Interrupt IRQ Register"
hexmask.long 0x00 0.--30. 1. " MMR_IRQ                               ,This register is not used in RC mode."
group.long 0x64++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_SET,Legacy Interrupt Request Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD70                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_SET_0                        ,Write one to generate assert legacy PCI interrupt message for Physical Function0. On read, a one indicates currently asserted interrupt." "0,1"
hgroup.long 0x68++0x3
hide.long 0x00 "PCIE_RC_LEGACY_IRQ_CLR,Legacy Interrupt Request Clear Register"
in
textline "                                                              "
rgroup.long 0x6C++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_STATUS,Legacy Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD90                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_STATUS_0                     ,Indicates whether legacy PCI interrupt for physical function 0 is asserted or not" "0,1"
group.long 0x70++0x3
line.long 0x00 "PCIE_RC_GPR0,General Purpose 0 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC0                              ,Generic Info field 0"
group.long 0x74++0x3
line.long 0x00 "PCIE_RC_GPR1,General Purpose 1 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC1                              ,Generic Info field 1"
group.long 0x78++0x3
line.long 0x00 "PCIE_RC_GPR2,General Purpose 2 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC2                              ,Generic Info field 2"
group.long 0x7C++0x3
line.long 0x00 "PCIE_RC_GPR3,General Purpose 3 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC3                              ,Generic Info field 3"
group.long 0x100++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS_RAW,MMR 0 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD100                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (24, 16, 8, 0) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x104++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS,MMR 0 Interrupt Status Register"
in
textline "                                                              "
group.long 0x108++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_SET,MMR 0 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD111                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (24, 16, 8, 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x10C++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_CLR,MMR 0 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x110++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS_RAW,MMR 1 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD120                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (25, 17, 9, 1) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x114++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS,MMR 1 Interrupt Status Register"
in
textline "                                                              "
group.long 0x118++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_SET,MMR 1 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD122                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (25, 17, 9, 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x11C++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_CLR,MMR 1 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x120++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS_RAW,MMR 2 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD130                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (26, 18, 10, 2) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x124++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS,MMR 2 Interrupt Status Register"
in
textline "                                                              "
group.long 0x128++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_SET,MMR 2 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD132                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (26, 18, 10, 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x12C++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_CLR,MMR 2 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x130++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS_RAW,MMR 3 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD140                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (27, 19, 11, 3) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x134++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS,MMR 3 Interrupt Status Register"
in
textline "                                                              "
group.long 0x138++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_SET,MMR 3 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD142                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (27, 19, 11, 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x13C++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_CLR,MMR 3 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x140++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS_RAW,MMR 4 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD150                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (28, 20, 12, 4) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x144++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS,MMR 4 Interrupt Status Register"
in
textline "                                                              "
group.long 0x148++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_SET,MMR 4 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD152                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (28, 20, 12, 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x14C++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_CLR,MMR 4 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x150++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS_RAW,MMR 5 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD160                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (29, 21, 13, 5) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x154++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS,MMR 5 Interrupt Status Register"
in
textline "                                                              "
group.long 0x158++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_SET,MMR 5 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD162                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (29, 21, 13, 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x15C++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_CLR,MMR 5 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x160++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS_RAW,MMR 6 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD170                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (30, 22, 14, 6) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x164++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS,MMR 6 Interrupt Status Register"
in
textline "                                                              "
group.long 0x168++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_SET,MMR 6 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD172                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (30, 22, 14, 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x16C++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_CLR,MMR 6 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x170++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS_RAW,MMR 7 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD180                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_STATUS_RAW                     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x174++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS,MMR 7 Interrupt Status Register"
in
textline "                                                              "
group.long 0x178++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_SET,MMR 7 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD182                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (31, 23, 15, 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x17C++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_CLR,MMR 7 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x180++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS_RAW,Legacy A Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD200                               ,Reserved"
bitfld.long 0x00 0. "  INTA_RAW                                ,Legacy Interrupt A raw status. RC mode only" "0,1"
hgroup.long 0x184++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS,Legacy A Raw Interrupt Status Register"
in
textline "                                                              "
group.long 0x188++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_SET,Legacy A Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD220                               ,Reserved"
bitfld.long 0x00 0. "  INTA_EN_SET                             ,Legacy Interrupt A enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x18C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_CLR,Legacy A Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x190++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS_RAW,Legacy B Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD300                               ,Reserved"
bitfld.long 0x00 0. "  INTB_RAW                                ,Legacy Interrupt B raw status. RC mode only" "0,1"
hgroup.long 0x194++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS,Legacy B Interrupt Status Register"
in
textline "                                                              "
group.long 0x198++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_SET,Legacy B Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD320                               ,Reserved"
bitfld.long 0x00 0. "  INTB_EN_SET                             ,Legacy Interrupt B enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x19C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_CLR,Legacy B Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1A0++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS_RAW,Legacy C Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD400                               ,Reserved"
bitfld.long 0x00 0. "  INTC_RAW                                ,Legacy Interrupt C raw status. RC mode only" "0,1"
hgroup.long 0x1A4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS,Legacy C Interrupt Status Register"
in
textline "                                                              "
group.long 0x1A8++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_SET,Legacy C Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD420                               ,Reserved"
bitfld.long 0x00 0. "  INTC_EN_SET                             ,Legacy Interrupt C enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1AC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_CLR,Legacy C Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1B0++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS_RAW,Legacy D Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD500                               ,Reserved"
bitfld.long 0x00 0. "  INTD_RAW                                ,Legacy Interrupt D raw status. RC mode only" "0,1"
hgroup.long 0x1B4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS,Legacy D Interrupt Status Register"
in
textline "                                                              "
group.long 0x1B8++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_SET,Legacy D Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD520                               ,Reserved"
bitfld.long 0x00 0. "  INTD_EN_SET                             ,Legacy Interrupt D enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1BC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_CLR,Legacy D Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1C0++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status Register"
hexmask.long 0x00 5.--31. 1. " RSVD600                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_RAW                             ,AER MSI error raw status. This interrupt is generated due to the assertion of the cfg_aer_rc_err_int or the cfg_aer_err_msi output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_RAW                          ,Correctable error raw status. This interrupt is generated due to the assertion of the radm_correctable_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_RAW                        ,Nonfatal error raw status. This interrupt is generated due to the assertion of the radm_nonfatal_err output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_RAW                         ,Fatal error raw status. This interrupt is generated due to the assertion of the radm_fatal_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_RAW                             ,System Error (FATAL, NONFATAL or CORRECTABLE error) raw status. This interrupt is generated due to the assertion of the cfg_sys_err_rc output of the PCIe controller core." "0,1"
hgroup.long 0x1C4++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_STATUS,"
in
textline "                                                              "
group.long 0x1C8++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_SET,"
hexmask.long 0x00 5.--31. 1. " RSVD620                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_EN_SET                          ,AER MSI error interrupt enable. Set to enable. On read, one/zero means enabled/disabled respectively" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_EN_SET                       ,Correctable error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_EN_SET                     ,Nonfatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_EN_SET                      ,Fatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_EN_SET                          ,System Error (FATAL, NONFATAL or CORRECTABLE error) interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1CC++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_CLR,"
in
textline "                                                              "
group.long 0x1D0++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD700                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_RAW                         ,Link Request Reset interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_RAW                            ,Power Management PME message received interrupt raw status" "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_RAW                           ,Power Management ACK received interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_RAW                        ,Power Management Turnoff message received raw status" "0,1"
hgroup.long 0x1D4++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS,Power Management and Reset Interrupt Status Register"
in
textline "                                                              "
group.long 0x1D8++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_SET,Power Management and Reset Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD720                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_EN_SET                      ,Link Request Reset interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_EN_SET                         ,Power Management PME message received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_EN_SET                        ,Power Management ACK received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_EN_SET                     ,Power Management Turnoff message received enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1DC++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1E0++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_STATUS_RAW,Precision Time Measurement Raw Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD800                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_RAW                     ,Precision Time Measurement interrupt raw status" "0,1"
hgroup.long 0x1E4++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_STATUS,Precision Time Measurement Status Register"
in
textline "                                                              "
group.long 0x1E8++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_SET,Precision Time Measurement Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD820                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_EN_SET                  ,Precision Time Measurement interrupt enable set. Write one to set" "0,1"
hgroup.long 0x1EC++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_CLR,Precision Time Measurement Enable Clear Register"
in
textline "                                                              "
rgroup.long 0x1000++0x3
line.long 0x00 "PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID                             ,Device ID - Vendor Assigned Device Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      VENDOR_ID                               ,Vendor ID - PCI-SIG assigned Manufacturer Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1004++0x3
hide.long 0x00 "PCIE_RC_TYPE1_STATUS_COMMAND_REG,Command and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1008++0x3
line.long 0x00 "PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE                       ,Base Class Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SUBCLASS_CODE                           ,Subclass Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTERFACE                     ,Class Code Programming Interface For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        REVISION_ID                             ,Vendor chosen Revision ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x100C++0x3
line.long 0x00 "PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST, Header Type, Cache Line Size, and Master Latency Timer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BIST                                  ,Optional for BIST support For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 23. "        MULTI_FUNC                              ,Specifies whether device is multifunction For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE                           ,Specifies Header Type For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "        LATENCY_MASTER_TIMER                    ,Primary Latency Timer Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE                       ,Cache Line Size field Has no effect on PCIe device behavior For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1018++0x3
line.long 0x00 "PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary, Secondary, Subordinate Bus Numbers and Latency Timer Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER                         ,Latency Timer Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 16.--23. 1. "        SUB_BUS                                 ,Subordinate Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS                               ,Secondary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 0.--7. 1. "        PRIM_BUS                                ,Primary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x101C++0x3
hide.long 0x00 "PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1020++0x3
line.long 0x00 "PCIE_RC_MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " MEM_LIMIT                             ,Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 16.--19. "      MEM_LIMIT_RESERV                        ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " MEM_BASE                              ,Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 0.--3. "      MEM_BASE_RESERV                         ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x3
line.long 0x00 "PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Base and Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PREF_MEM_LIMIT                        ,Prefetchable Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 17.--19. "      PREF_RESERV1                            ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE                 ,Prefetchable Memory Limit Decode For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 4.--15. 1. "         PREF_MEM_BASE                           ,Prefetchable Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 1.--3. " PREF_RESERV                           ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PREF_MEM_DECODE                         ,Prefetchable Memory Decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
rgroup.long 0x1028++0x3
line.long 0x00 "PCIE_RC_PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_BASE_UPPER                   ,Prefetchable Memory Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x102C++0x3
line.long 0x00 "PCIE_RC_PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_LIMIT_UPPER                  ,Prefetchable Memory Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1030++0x3
line.long 0x00 "PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " IO_LIMIT_UPPER                        ,Prefetchable I/O Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
hexmask.long.word 0x00 0.--15. 1. "      IO_BASE_UPPER                           ,Prefetchable I/O Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1034++0x3
line.long 0x00 "PCIE_RC_TYPE1_CAP_PTR_REG,Capability Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "    CAP_POINTER                             ,Pointer to first item in the PCI Capability Structure For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x1038++0x3
line.long 0x00 "PCIE_RC_TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register. For a description of this standard PCIe register, see the PCI Express Specification. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address."
hexmask.long.tbyte 0x00 11.--31. 1. " EXP_ROM_BASE_ADDRESS                  ,Expansion ROM BAR and Mask Register For a description of this standard PCIe register, see the PCI Express Specification The mask for this ROM BAR exists [if implemented] as a shadow register at this address The assertion of CS2 [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] is required to write to the second register at this address Note: The access attributes of this field are as follows: - Dbi: R/W"
hexmask.long.word 0x00 1.--10. 1. "    RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " ROM_BAR_ENABLE                        ,Expansion ROM Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x103C++0x3
line.long 0x00 "PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 23.--31. 1. " BRIDGE_CTRL_RESERV                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22. "      SBR                                     ,Secondary Bus Hot Reset For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 21. " MSTR_ABORT_MODE                       ,Master Abort Mode Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 20. "         VGA_16B_DEC                             ,VGA 16 bit decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " VGA_EN                                ,VGA Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
bitfld.long 0x00 18. "         ISA_EN                                  ,ISA Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " SERR_EN                               ,System Error Response Enable from Secondary to Primary For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         PERE                                    ,Parity Error Response Enable Controls Logging of Poisoned TLPs For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " INT_PIN                               ,PCI Compatible Interrupt Pin Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        INT_LINE                                ,PCI Compatible Interrupt Line Routing Register Field For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1040++0x3
line.long 0x00 "PCIE_RC_CAP_ID_NXT_PTR_REG,Power Management Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " PME_SUPPORT                           ,Power Management Event Support For a description of this standard PCIe register field, see the PCI Express Specification The read value from this field is the write value && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where D1_SUPPORT and D2_SUPPORT are fields in this register The reset value PME_SUPPORT_n && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where PME_SUPPORT_n is a configuration parameter Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        D2_SUPPORT                              ,D2 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " D1_SUPPORT                            ,D1 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 22.--24. "         AUX_CURR                                ,Auxiliary Current Requirements For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 21. " DSI                                   ,Device Specific Initialization Bit For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         PME_CLK                                 ,PCI Clock Requirement For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16.--18. " PM_SPEC_VER                           ,Power Management Spec Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "         PM_NEXT_POINTER                         ,Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID                             ,Power Management Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x1044++0x3
hide.long 0x00 "PCIE_RC_CON_STATUS_REG,Power Management Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1050++0x3
line.long 0x00 "PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID, Next Pointer, Capability/Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        PCI_MSI_EXT_DATA_EN                     ,Extended Message Data Enable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_EXT_DATA_CAP ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP                  ,Extended Message Data Capable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         PCI_PVM_SUPPORT                         ,MSI Per Vector Masking Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP               ,MSI 64-bit Address Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 20.--22. "         PCI_MSI_MULTIPLE_MSG_EN                 ,MSI Multiple Message Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP              ,MSI Multiple Message Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         PCI_MSI_ENABLE                          ,MSI Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSI_CAP_NEXT_OFFSET               ,MSI Capability Next Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSI_CAP_ID                          ,MSI Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1054++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_04H_REG,MSI Message Lower Address Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " PCI_MSI_CAP_OFF_04H                   ,MSI Message Lower Address Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 0.--1. "  RSVDP_0                                 ,Reserved for future use" "0,1,2,3"
group.long 0x1058++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_08H_REG,For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0AH                   ,For a 32 bit MSI Message, this field contains Ext MSI Data For 64-bit it contains upper 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_08H                     ,For a 32-bit MSI Message, this field contains Data For 64-bit it contains lower 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R"
group.long 0x105C++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_0CH_REG,For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0EH                   ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the upper Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: [!MSI_64_EN && MSI_PVM_EN_VALUE] ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_0CH                     ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the lower Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR MSI_PVM_EN ? R/W : R"
group.long 0x1060++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_10H                   ,Used for MSI when Vector Masking Capable For 32-bit contains Pending Bits For 64-bit, contains Mask Bits For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R"
rgroup.long 0x1064++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_14H_REG,Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_14H                   ,Used for MSI 64-bit messaging when Vector Masking Capable Contains Pending Bits For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1070++0x3
line.long 0x00 "PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities, ID, Next Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         RSVD                                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM                      ,PCIE Interrupt Message Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "        PCIE_SLOT_IMP                           ,PCIe Slot Implemented Valid For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE                    ,PCIE Device/PortType For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PCIE_CAP_REG                            ,PCIE Capability Version Number For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR                     ,PCIE Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCIE_CAP_ID                             ,PCIE Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1074++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES_REG,Device Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      PCIE_CAP_ROLE_BASED_ERR_REPORT          ,Role-based Error Reporting Implemented For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 6.--14. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "      PCIE_CAP_EXT_TAG_SUPP                   ,Extended Tag Field Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT         ,Phantom Functions Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 0.--2. "         PCIE_CAP_MAX_PAYLOAD_SIZE               ,Max Payload Size Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hgroup.long 0x1078++0x3
hide.long 0x00 "PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x107C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES_REG,Link Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM                     ,Port Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE          ,ASPM Optionality Compliance For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 21. "         PCIE_CAP_LINK_BW_NOT_CAP                ,Link Bandwidth Notification Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP           ,Data Link Layer Link Active Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 19. "         PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP      ,Surprise Down Error Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN              ,Clock Power Management For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 15.--17. "         PCIE_CAP_L1_EXIT_LATENCY                ,L1 Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY             ,LOs Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--11. "         PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT   ,Level of ASPM [Active State Power Management] Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH               ,Maximum Link Width For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. "        PCIE_CAP_MAX_LINK_SPEED                 ,Maximum Link Speed For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1080++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1084++0x3
line.long 0x00 "PCIE_RC_SLOT_CAPABILITIES_REG,Slot Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM                 ,Physical Slot Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 18. "      PCIE_CAP_NO_CMD_CPL_SUPPORT             ,No Command Completed Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK        ,Electromechanical Interlock Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 15.--16. "         PCIE_CAP_SLOT_POWER_LIMIT_SCALE         ,Slot Power Limit Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE       ,Slot Power Limit Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 6. "        PCIE_CAP_HOT_PLUG_CAPABLE               ,Hot Plug Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE            ,Hot Plug Surprise possible For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_POWER_INDICATOR                ,Power Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR          ,Attention Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_MRL_SENSOR                     ,MRL Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER             ,Power Controller Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_ATTENTION_INDICATOR_BUTTON     ,Attention Button Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
hgroup.long 0x1088++0x3
hide.long 0x00 "PCIE_RC_SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x108C++0x3
line.long 0x00 "PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      PCIE_CAP_CRS_SW_VISIBILITY              ,CRS Software Visibility Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W [Sticky] else R [Sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 5.--15. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 4. "      PCIE_CAP_CRS_SW_VISIBILITY_EN           ,Configuration Request Retry Status [CRS] Software Visibility Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REGPCIE_CAP_CRS_SW_VISIBILITY ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN                   ,PME Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN        ,System Error on Fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN  ,System Error on Non-fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN         ,System Error on Correctable Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1090++0x3
hide.long 0x00 "PCIE_RC_ROOT_STATUS_REG,Root Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1094++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--30. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 18.--19. "        PCIE_CAP_OBFF_SUPPORT                   ,[OBFF] Optimized Buffer Flush/fill Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT      ,10-Bit Tag Requester Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
bitfld.long 0x00 16. "         PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT       ,10-Bit Tag Completer Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPPORT_1          ,TPH Completer Supported Bit 1 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 12. "         PCIE_CAP_TPH_CMPLT_SUPPORT_0            ,TPH Completer Supported Bit 0 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP                     ,LTR Mechanism Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 10. "         PCIE_CAP_NO_RO_EN_PR2PR_PAR             ,No Relaxed Ordering Enabled PR-PR Passing For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP             ,128 Bit CAS Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 8. "         PCIE_CAP_64_ATOMIC_CPL_SUPP             ,64 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP           ,32 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 6. "         PCIE_CAP_ATOMIC_ROUTING_SUPP            ,Atomic Operation Routing Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT          ,ARI Forwarding Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT    ,Completion Timeout Disable Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE            ,Completion Timeout Ranges Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1098++0x3
line.long 0x00 "PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS       ,ARI Forwarding Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE            ,Completion Timeout Disable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VALUE            ,Completion Timeout Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x109C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES2_REG,Link Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 25.--30. " RSVDP_25                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 9.--22. 1. "        RSVDP_9                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT           ,Cross Link Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR      ,Supported Link Speeds Vector For a description of this standard PCIe register field, see the PCI Express Specification This field has a default of [PCIE_CAP_MAX_LINK_SPEED == 0100] ? 0001111 : [PCIE_CAP_MAX_LINK_SPEED == 0011] ? 0000111 : [PCIE_CAP_MAX_LINK_SPEED == 0010] ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the PCIE_RC_LINK_CAPABILITIES_REG register"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
hgroup.long 0x10A0++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x10B0++0x3
line.long 0x00 "PCIE_RC_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID, Next Pointer, Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " PCI_MSIX_ENABLE                       ,MSI-X Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 30. "         PCI_MSIX_FUNCTION_MASK                  ,Function Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--26. 1. "         PCI_MSIX_TABLE_SIZE                     ,MSI-X Table Size For a description of this standard PCIe register field, see the PCI Express Specification SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' [PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG] To write this common value, you must perform a DBI_CS2 write [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] while accessing the PCI_MSIX_TABLE_SIZE field in the PF"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSIX_CAP_NEXT_OFFSET              ,MSI-X Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSIX_CAP_ID                         ,MSI-X Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x10B4++0x3
line.long 0x00 "PCIE_RC_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_TABLE_OFFSET                 ,MSI-X Table Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_BIR                            ,MSI-X Table Bar Indicator Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x10B8++0x3
line.long 0x00 "PCIE_RC_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_PBA_OFFSET                   ,MSI-X PBA Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_PBA                            ,MSI-X PBA BIR For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x1100++0x3
line.long 0x00 "PCIE_RC_AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " CAP_ID                                ,AER Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1104++0x3
hide.long 0x00 "PCIE_RC_UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1108++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_MASK               ,TLP Prefix Blocked Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK        ,AtomicOp Egress Block Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_MASK                     ,Uncorrectable Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_MASK                ,Unsupported Request Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_MASK                         ,ECRC Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_MASK                       ,Malformed TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK                 ,Receiver Overflow Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_MASK                    ,Unexpected Completion Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK                  ,Completer Abort Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_MASK                  ,Completion Timeout Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK                  ,Flow Control Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_MASK                       ,Poisoned TLP Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_MASK                  ,Surprise Down Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK                  ,Data Link Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110C++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_SEVERITY           ,TLP Prefix Blocked Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY    ,AtomicOp Egress Blocked Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_SEVERITY                 ,Uncorrectable Internal Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_SEVERITY            ,Unsupported Request Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_SEVERITY                     ,ECRC Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_SEVERITY                   ,Malformed TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_SEVERITY             ,Receiver Overflow Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_SEVERITY                ,Unexpected Completion Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_SEVERITY              ,Completer Abort Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_SEVERITY              ,Completion Timeout Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_SEVERITY              ,Flow Control Protocol Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_SEVERITY                   ,Poisoned TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_SVRITY                ,Surprise Down Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_SEVERITY              ,Data Link Protocol Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1110++0x3
hide.long 0x00 "PCIE_RC_CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1114++0x3
line.long 0x00 "PCIE_RC_CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      HEADER_LOG_OVERFLOW_MASK                ,Header Log Overflow Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14. " CORRECTED_INT_ERR_MASK                ,Corrected Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 13. "         ADVISORY_NON_FATAL_ERR_MASK             ,Advisory Non-Fatal Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RPL_TIMER_TIMEOUT_MASK                ,Replay Timer Timeout Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 9.--11. "         RSVDP_9                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8. " REPLAY_NO_ROLEOVER_MASK               ,REPLAY_NUM Rollover Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 7. "         BAD_DLLP_MASK                           ,Bad DLLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " BAD_TLP_MASK                          ,Bad TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 1.--5. "         RSVDP_1                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 0. " RX_ERR_MASK                           ,Receiver Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
group.long 0x1118++0x3
line.long 0x00 "PCIE_RC_ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10. "    MULTIPLE_HEADER_EN                      ,Multiple Header Recording Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " MULTIPLE_HEADER_CAP                   ,Multiple Header Recording Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         ECRC_CHECK_EN                           ,ECRC Check Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " ECRC_CHECK_CAP                        ,ECRC Check Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 6. "         ECRC_GEN_EN                             ,ECRC Generation Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " ECRC_GEN_CAP                          ,ECRC Generation Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--4. "         FIRST_ERR_POINTER                       ,First Error Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x111C++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FIRST_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FIRST_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1120++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SECOND_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SECOND_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        SECOND_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1124++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        THIRD_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " THIRD_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        THIRD_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1128++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FOURTH_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FOURTH_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
group.long 0x112C++0x3
line.long 0x00 "PCIE_RC_ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " RSVDP_3                               ,Reserved for future use"
bitfld.long 0x00 2. "  FATAL_ERR_REPORTING_EN                  ,Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN            ,Non-Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         CORR_ERR_REPORTING_EN                   ,Correctable Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1130++0x3
hide.long 0x00 "PCIE_RC_ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1134++0x3
line.long 0x00 "PCIE_RC_ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID         ,Source of Fatal/Non-Fatal Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      ERR_COR_SOURCE_ID                       ,Source of Correctable Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1138++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE         ,Byte 3 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_1_THIRD_BYTE            ,Byte 2 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE         ,Byte 1 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_1_FIRST_BYTE            ,Byte 0 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x113C++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_2_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_2_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1140++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_3_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_3_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1144++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_4_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_4_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1148++0x3
line.long 0x00 "PCIE_RC_VC_BASE,VC Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " VC_NEXT_OFFSET                        ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      VC_CAP_VERSION                          ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " VC_PCIE_EXTENDED_CAP_ID               ,VC Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x114C++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_1,Port VC Capability Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10.--11. "    VC_PORT_ARBI_TBL_ENTRY_SIZE             ,Port Arbitration Table Entry Size For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 8.--9. " VC_REFERENCE_CLOCK                    ,Reference Clock For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
bitfld.long 0x00 7. "         RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " VC_LOW_PRI_EXT_VC_CNT                 ,Low Priority Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RSVDP_3                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--2. " VC_EXT_VC_CNT                         ,Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
rgroup.long 0x1150++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_2,Port VC Capability Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_ARBI_TABLE_OFFSET                  ,VC Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.tbyte 0x00 4.--23. 1. "        RSVDP_4                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0.--3. " VC_ARBI_CAP                           ,VC Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1154++0x3
line.long 0x00 "PCIE_RC_VC_STATUS_CONTROL_REG,Port VC Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      VC_ARBI_TABLE_STATUS                    ,VC Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " RSVDP_4                               ,Reserved for future use"
bitfld.long 0x00 1.--3. "      VC_ARBI_SELECT                          ,VC Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " VC_LOAD_VC_ARBI_TABLE                 ,Requests Hardware to Load VC Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1158++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC0,VC Resource Capability Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC0                ,Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC0                  ,Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC0               ,Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC0                    ,Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x115C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC0,VC Resource Control Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC0                         ,VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC                              ,VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--23. "         RSVDP_18                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 17. " VC_PORT_ARBI_SELECT_VC0               ,Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC0             ,Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC0_BIT1                      ,Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC0                         ,Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1160++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC0,VC Resource Status Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC0                     ,VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC0         ,Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1164++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC1,VC Resource Capability Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC1                ,VC1 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC1                  ,VC1 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC1               ,VC1 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC1                    ,VC1 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1168++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC1,VC Resource Control Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC1                         ,VC1 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC1                             ,VC1 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC1               ,VC1 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC1             ,VC1 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC1_BIT1                      ,VC1 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC1                         ,VC1 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x116C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC1,VC Resource Status Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC1                     ,VC1 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC1         ,VC1 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1170++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC2,VC Resource Capability Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC2                ,VC2 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC2                  ,VC2 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC2               ,VC2 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC2                    ,VC2 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1174++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC2,VC Resource Control Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC2                         ,VC2 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC2                             ,VC2 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC2               ,VC2 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC2             ,VC2 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC2_BIT1                      ,VC2 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC2                         ,VC2 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1178++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC2,VC Resource Status Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC2                     ,VC2 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC2         ,VC2 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x117C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC3,VC Resource Capability Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC3                ,VC3 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC3                  ,VC3 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC3               ,VC3 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC3                    ,VC3 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1180++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC3,VC Resource Control Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC3                         ,VC3 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC3                             ,VC3 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC3               ,VC3 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC3             ,VC3 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC3_BIT1                      ,VC3 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC3                         ,VC3 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1184++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC3,VC Resource Status Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC3                     ,VC3 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC3         ,VC3 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1198++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,Secondary PCI Express Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x119C++0x3
line.long 0x00 "PCIE_RC_LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  EQ_REQ_INT_EN                           ,Link Equalization Request Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PERFORM_EQ                            ,Perform Equalization For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
hgroup.long 0x11A0++0x3
hide.long 0x00 "PCIE_RC_LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x11A4++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 28.--30. "         USP_RX_PRESET_HINT1                     ,Upstream Port 80 GT/s Receiver Preset Hint 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 24.--27. " USP_TX_PRESET1                        ,Upstream Port 80 GT/s Transmitter Preset 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1                   ,Downstream Port 80 GT/s Receiver Preset Hint 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         DSP_TX_PRESET1                          ,Downstream Port 80 GT/s Transmitter Preset 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 15. " RSVDP_15                              ,Reserved for future use" "0,1"
bitfld.long 0x00 12.--14. "         USP_RX_PRESET_HINT0                     ,Upstream Port 80 GT/s Receiver Preset Hint 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--11. " USP_TX_PRESET0                        ,Upstream Port 80 GT/s Transmitter Preset 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0                   ,Downstream Port 80 GT/s Receiver Preset Hint 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         DSP_TX_PRESET0                          ,Downstream Port 80 GT/s Transmitter Preset 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x11A8++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,L1SUB Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x11AC++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAPABILITY_REG,L1 Substates Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 19.--23. "        PWR_ON_VALUE_SUPPORT                    ,Port T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 18. " RSVDP_18                              ,Reserved for future use" "0,1"
bitfld.long 0x00 16.--17. "         PWR_ON_SCALE_SUPPORT                    ,Port T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " COMM_MODE_SUPPORT                     ,Port Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 5.--7. "        RSVDP_5                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 4. " L1_PMSUB_SUPPORT                      ,L1 PM Substates ECN Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 3. "         L1_1_ASPM_SUPPORT                       ,ASPM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT                     ,ASPM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_SUPPORT                      ,PCI-PM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_SUPPORT                    ,PCI-PM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x11B0++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 29.--31. " L1_2_TH_SCA                           ,LTR L12 Threshold Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "         RSVDP_26                                ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 16.--25. 1. " L1_2_TH_VAL                           ,LTR L12 Threshold Value For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "      T_COMMON_MODE                           ,Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
textline "                                                              "
bitfld.long 0x00 4.--7. " RSVDP_4                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        L1_1_ASPM_EN                            ,ASPM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_EN                          ,ASPM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_EN                           ,PCI-PM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_EN                         ,PCI-PM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
group.long 0x11B4++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 3.--7. "    T_POWER_ON_VALUE                        ,T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 0.--1. "         T_POWER_ON_SCALE                        ,T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
rgroup.long 0x11B8++0x3
line.long 0x00 "PCIE_RC_PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PTM_NEXT_OFFSET                       ,Precision Time Measurement PCI Express Extended Capability Next Offset For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_CAP_VERSION                         ,Precision Time Measurement PCI Express Extended Capability Version For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_CAP_ID                            ,Precision Time Measurement PCI Express Extended Capability ID For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11BC++0x3
line.long 0x00 "PCIE_RC_PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      PTM_CLK_GRAN                            ,PTM Local Clock Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVDP_3                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_ROOT_CAPABLE                        ,PTM Root Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_RES_CAPABLE                       ,PTM Responder Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 0. "         PTM_REQ_CAPABLE                         ,PTM Requester Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
group.long 0x11C0++0x3
line.long 0x00 "PCIE_RC_PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      EFF_GRAN                                ,PTM Effective Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT"
textline "                                                              "
bitfld.long 0x00 2.--7. " RSVDP_2                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        ROOT_SELECT                             ,PTM Root Select When set this Time Source is the PTM Root For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_ENABLE                            ,PTM Enable When set, this function is permitted to participate in the PTM mechanism For a description of this standard PCIe register, see the PCI Express Specification" "0,1"
rgroup.long 0x11C4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC)."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_EXT_CAP_NEXT_OFFS             ,Precision Time Measurement Responder VSEC Next Pointer Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_EXT_CAP_VER                     ,Precision Time Measurement Responder VSEC Version Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_EXT_CAP_ID                    ,Precision Time Measurement Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11C8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. ."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_VSEC_LENGTH                   ,PTM Responder VSEC Length Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_VSEC_REV                        ,PTM Responder VSEC Revision Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_VSEC_ID                       ,PTM Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11CC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CONTROL_OFF,PTM Responder Control Register. ."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  PTM_RES_CCONTEXT_VALID                  ,PTM Responder Control Context Valid - PTM Local Timing is valid This bit is set over the DBI A speed change or aux_clk_active will set this bit low Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x11D0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_STATUS_OFF,PTM Responder Status Register. ."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  PTM_RES_REQUEST_RECEIVED                ,PTM 1st Request Received - PTM Responder has received the first PTM Request Message Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder, if the context is valid If the context is invalid a Response message will be sent instead Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_RES_CONTEXT_VALID                 ,PTM Responder Status Context Valid - PTM Local Timing Context is Valid Value set from upstream port Requester in a Switch Shadows the same in the control register in all other products Note: This register field is sticky" "0,1"
rgroup.long 0x11D4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_LSB                     ,PTM Responder Local Clock LSB - Lower 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11D8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_MSB                     ,PTM Responder Local Clock MSB - Upper 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11DC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_LSB                        ,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_MSB                        ,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_LSB                       ,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_MSB                       ,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11EC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_LSB                        ,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_MSB                        ,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_LSB                       ,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_MSB                       ,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
group.long 0x11FC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_TX_LATENCY                      ,PTM Responder TX Latency - Responder Transmit path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1200++0x3
line.long 0x00 "PCIE_RC_PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_RX_LATENCY                      ,PTM Responder RX Latency - Responder Receive path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1700++0x3
line.long 0x00 "PCIE_RC_ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register."
hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT                     ,Replay Timer Limit The replay timer expires when it reaches this limit The controller initiates a replay upon reception of a NAK or when the replay timer expires You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 30 specification If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
hexmask.long.word 0x00 0.--15. 1. "      ROUND_TRIP_LATENCY_TIME_LIMIT           ,Ack Latency Timer Limit The Ack latency timer expires when it reaches this limit You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 30 specification The limit must reflect the round trip latency from requester to completer If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_ACK_NAK field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
group.long 0x1704++0x3
line.long 0x00 "PCIE_RC_VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register."
hexmask.long 0x00 0.--31. 1. " VENDOR_SPEC_DLLP                      ,Vendor Specific DLLP Register Used to send a specific PCI Express DLLP Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of"
hgroup.long 0x1708++0x3
hide.long 0x00 "PCIE_RC_PORT_FORCE_OFF,Port Force Link Register."
in
textline "                                                              "
group.long 0x170C++0x3
line.long 0x00 "PCIE_RC_ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         ENTER_ASPM                              ,ASPM L1 Entry Control - 1: Core enters ASPM L1 after a period in which it has been idle - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " L1_ENTRANCE_LATENCY                   ,L1 Entrance Latency Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         L0S_ENTRANCE_LATENCY                    ,L0s Entrance Latency Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 16.--23. 1. " COMMON_CLK_N_FTS                      ,Common Clock N_FTS This is the N_FTS when common clock is used The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 This field is only writable [sticky] when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 8.--15. 1. "        ACK_N_FTS                               ,N_FTS The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " ACK_FREQ                              ,Ack Frequency The controller accumulates the number of pending ACKs specified here [up to 255] before sending an ACK DLLP - 0: Indicates that this Ack frequency control feature is turned off The controller schedules a low-priority ACK DLLP for every TLP that it receives - 1- 255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs It might schedule the ACK before receiving this number of TLPs, but never later For a typical system, you do not have to modify the default setting Note: This register field is sticky"
hgroup.long 0x1710++0x3
hide.long 0x00 "PCIE_RC_PORT_LINK_CTRL_OFF,Port Link Control Register."
in
textline "                                                              "
group.long 0x1714++0x3
line.long 0x00 "PCIE_RC_LANE_SKEW_OFF,Lane Skew Register."
bitfld.long 0x00 31. " DISABLE_LANE_TO_LANE_DESKEW           ,Disable Lane-to-Lane Deskew Causes the controller to disable the internal Lane-to-Lane deskew logic Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         IMPLEMENT_NUM_LANES                     ,Implementation-specific Number of Lanes Set the implementation-specific number of lanes Allowed values are: - 4'b 0000: 1 lane - 4'b 0001: 2 lanes - 4'b 0011: 4 lanes - 4'b 0111: 8 lanes - 4'b 1111: 16 lanes The number of lanes to be used when in Loopback Master The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field The controller will transition from LoopbackEntry to LoopbackActive after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 26. " LANE_SKEW_OFF_26                      ,Reserved Read/Write regsiter for future use Note: This register field is sticky" "0,1"
bitfld.long 0x00 25. "         ACK_NAK_DISABLE                         ,Ack/Nak Disable Prevents the controller from sending ACK and NAK DLLPs Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " FLOW_CTRL_DISABLE                     ,Flow Control Disable Prevents the controller from sending FC DLLPs Note: This register field is sticky" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. "         INSERT_LANE_SKEW                        ,Insert Lane Skew for Transmit [not supported for x16] Optional feature that causes the controller to insert skew between Lanes for test purposes There are three bits per Lane The value is in units of one symbol time For example, the value 010b for a Lane forces a skew of two symbol times for that Lane The maximum skew value for any Lane is 5 symbol times Note: This register field is sticky"
group.long 0x1718++0x3
line.long 0x00 "PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 29.--30. "         FAST_LINK_SCALING_FACTOR                ,Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field inPCIE_RC_PORT_LINK_CTRL_OFF is set to '1' - 0: Scaling Factor is 1024 [1ms is 1us] - 1: Scaling Factor is 256 [1ms is 4us] - 2: Scaling Factor is 64 [1ms is 16us] - 3: Scaling Factor is 16 [1ms is 64us] Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0' Not used for M-PCIe Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--28. " UPDATE_FREQ_TIMER                     ,UPDATE_FREQ_TIMER is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19.--23. "        TIMER_MOD_ACK_NAK                       ,Ack Latency Timer Modifier Increases the timer value for the Ack latency timer in increments of 64 clock cycles A value of '0' represents no modification to the timer value For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 14.--18. " TIMER_MOD_REPLAY_TIMER                ,Replay Timer Limit Modifier Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed A value of '0' represents no modification to the timer limit For more details, see the REPLAY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RSVDP_8                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MAX_FUNC_NUM                          ,Maximum function number that can be used in a request Configuration requests targeted at function numbers above this value are returned with UR [unsupported request] Note: This register field is sticky"
group.long 0x171C++0x3
line.long 0x00 "PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long.word 0x00 16.--31. 1. " MASK_RADM_1                           ,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD 0: For RADM RC filter to not allow CFG transaction being received 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD 0: For RADM RC filter to not allow IO transaction being received 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP 0: Drop MSG TLP [except for Vendor MSG]. Send decoded message on the SII. 1: Do not Drop MSG [except for Vendor MSG]. Send message TLPs to your application on TRGT1 and send decoded message on the SII. The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG = 1, then the default of this bit is '0' [drop message TLPs]. This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 [or AXI bridge master], as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. 0: Discard completions with ECRC errors 1: Allow completions with ECRC errors to be passed up Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD 0: Discard TLPs with ECRC errors 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH 0: Enforce Req Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Req Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_c? 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR 0: Treat locked Read TLPs as UR for EP; Supported for RC 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR 0: Treat CFG type1 TLPs as UR for EP; Supported for RC 1: Treat CFG type1 TLPs as Supported for EP; UR for RC When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests, if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR 0: Treat out-of-bar TLPs as UR 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS 0: Treat poisoned request TLPs as UR 1: Do not treat poisoned request TLPs as UR The native controller always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH 0: Treat Function MisMatched TLPs as UR 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky."
bitfld.long 0x00 15. "      DISABLE_FC_WD_TIMER                     ,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1"
textline "                                                              "
bitfld.long 0x00 11.--14. " EIDLE_TIMER                           ,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "        SKP_INT_VAL                             ,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register [in a 250 MHz controller], then the controller actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 [because one clock tick = two symbol times in this case]. Note: This value is not used at Gen3 speed. The skip interval is hardcoded to 370 blocks For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows: 2K_PPM_DISABLED = 1: 1280/CX_NB 2K_PPM_DISABLED = 0: 228/CX_NB You need to set this field again, if necessary, when 2K_PPM_DISABLED is changed. Note: This register field is sticky."
group.long 0x1720++0x3
line.long 0x00 "PCIE_RC_FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long 0x00 0.--31. 1. " MASK_RADM_2                           ,Filter Mask 2. This field modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
group.long 0x1724++0x3
line.long 0x00 "PCIE_RC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  OB_RD_SPLIT_BURST_EN                    ,Enable AMBA Multiple Outbound Decomposed NP SubRequests This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device [or switch] is reordering completions that have different tags Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x1728++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG0_OFF,Debug Register 0"
hexmask.long 0x00 0.--31. 1. " DEB_REG_0                             ,The value on cxpl_debug_info[31:0]"
rgroup.long 0x172C++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG1_OFF,Debug Register 1"
hexmask.long 0x00 0.--31. 1. " DEB_REG_1                             ,The value on cxpl_debug_info[63:32]"
rgroup.long 0x1730++0x3
line.long 0x00 "PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_P_HEADER_FC_CREDIT                   ,Transmit Posted Header FC Credits The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_P_DATA_FC_CREDIT                   ,Transmit Posted Data FC Credits The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1734++0x3
line.long 0x00 "PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_NP_HEADER_FC_CREDIT                  ,Transmit Non-Posted Header FC Credits The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_NP_DATA_FC_CREDIT                  ,Transmit Non-Posted Data FC Credits The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1738++0x3
line.long 0x00 "PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_CPL_HEADER_FC_CREDIT                 ,Transmit Completion Header FC Credits The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_CPL_DATA_FC_CREDIT                 ,Transmit Completion Data FC Credits The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
hgroup.long 0x173C++0x3
hide.long 0x00 "PCIE_RC_QUEUE_STATUS_OFF,Queue Status"
in
textline "                                                              "
rgroup.long 0x1740++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3                       ,WRR Weight for VC3 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_2                         ,WRR Weight for VC2 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1                       ,WRR Weight for VC1 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_0                         ,WRR Weight for VC0 Note: The access attributes of this field are as follows: - Dbi: R"
rgroup.long 0x1744++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_7                       ,WRR Weight for VC7 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_6                         ,WRR Weight for VC6 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_5                       ,WRR Weight for VC5 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_4                         ,WRR Weight for VC4 Note: The access attributes of this field are as follows: - Dbi: R"
group.long 0x1748++0x3
line.long 0x00 "PCIE_RC_VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control."
bitfld.long 0x00 31. " VC_ORDERING_RX_Q                      ,VC Ordering for Receive Queues Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         TLP_TYPE_ORDERING_VC0                   ,TLP Type Ordering for VC0 Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE                      ,VC0 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_P_HDR_SCALE                         ,VC0 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_P_TLP_Q_MODE                      ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_P_HEADER_CREDIT                     ,VC0 Posted Header Credits The number of initial posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CREDIT                     ,VC0 Posted Data Credits The number of initial posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x174C++0x3
line.long 0x00 "PCIE_RC_VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_NP_DATA_SCALE                     ,VC0 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_NP_HDR_SCALE                        ,VC0 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_NP_HEADER_CREDIT                    ,VC0 Non-Posted Header Credits The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_NP_DATA_CREDIT                    ,VC0 Non-Posted Data Credits The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1750++0x3
line.long 0x00 "PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_CPL_DATA_SCALE                    ,VC0 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_CPL_HDR_SCALE                       ,VC0 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_CPL_HEADER_CREDIT                   ,VC0 Completion Header Credits The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_CPL_DATA_CREDIT                   ,VC0 Completion Data Credits The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1754++0x3
line.long 0x00 "PCIE_RC_VC1_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC1                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC1_P_DATA_SCALE                        ,VC1 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC1_P_HDR_SCALE                       ,VC1 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC1_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC1_P_HEADER_CREDIT                   ,VC1 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC1_P_DATA_CREDIT                       ,VC1 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1758++0x3
line.long 0x00 "PCIE_RC_VC1_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_NP_DATA_SCALE                     ,VC1 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_NP_HDR_SCALE                        ,VC1 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x175C++0x3
line.long 0x00 "PCIE_RC_VC1_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_CPL_DATA_SCALE                    ,VC1 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_CPL_HDR_SCALE                       ,VC1 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1760++0x3
line.long 0x00 "PCIE_RC_VC2_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC2                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC2_P_DATA_SCALE                        ,VC2 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC2_P_HDR_SCALE                       ,VC2 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC2_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC2_P_HEADER_CREDIT                   ,VC2 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC2_P_DATA_CREDIT                       ,VC2 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1764++0x3
line.long 0x00 "PCIE_RC_VC2_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_NP_DATA_SCALE                     ,VC2 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_NP_HDR_SCALE                        ,VC2 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1768++0x3
line.long 0x00 "PCIE_RC_VC2_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_CPL_DATA_SCALE                    ,VC2 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_CPL_HDR_SCALE                       ,VC2 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x176C++0x3
line.long 0x00 "PCIE_RC_VC3_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC3                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC3_P_DATA_SCALE                        ,VC3 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC3_P_HDR_SCALE                       ,VC3 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC3_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC3_P_HEADER_CREDIT                   ,VC3 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC3_P_DATA_CREDIT                       ,VC3 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1770++0x3
line.long 0x00 "PCIE_RC_VC3_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_NP_DATA_SCALE                     ,VC3 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_NP_HDR_SCALE                        ,VC3 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1774++0x3
line.long 0x00 "PCIE_RC_VC3_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_CPL_DATA_SCALE                    ,VC3 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_CPL_HDR_SCALE                       ,VC3 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x180C++0x3
line.long 0x00 "PCIE_RC_GEN2_CTRL_OFF,Link Width and Speed Change Control Register."
hexmask.long.word 0x00 22.--31. 1. " RSVDP_22                              ,Reserved for future use"
bitfld.long 0x00 21. "      GEN1_EI_INFERENCE                       ,Electrical Idle Inference Mode at Gen1 Rate Programmable mode to determine inferred electrical idle [EI] in RecoverySpeed or LoopbackActive [as slave] state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking for a '0' on RxValid If the PHY fails to deassert the RxValid signal in RecoverySpeed or LoopbackActive [because of corrupted EIOS for example], then EI cannot be inferred successfully in the controller by just detecting the condition RxValid= 0 - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " SEL_DEEMPHASIS                        ,Used to set the de-emphasis level for upstream ports This bit selects the level of de-emphasis the link operates at - 0: -6 dB - 1: -35 dB This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         CONFIG_TX_COMP_RX                       ,Config Tx Compliance Receive Bit When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert [equal to '1'] This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE                  ,Config PHY Tx Swing Controls the PHY transmitter voltage swing level The controller drives the mac_phy_txswing output from this register bit field - 0: Full Swing - 1: Low Swing This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 17. "         DIRECT_SPEED_CHANGE                     ,Directed Speed Change Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed When the speed change occurs, the controller will clear the contents of this field and a read to this field by your software will return a '0' To manually initiate the speed change: - Write to PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to '1', then the speed change is initiated automatically after link up, and the controller clears the contents of this field If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register [LINK_CONTROL2_LINK_STATUS2_OFF PCIE_CAP_TARGET_LINK_SPEED] through the DBI before link up This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN                ,Enable Auto flipping of the lanes You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 13.--15. "         PRE_DET_LANE                            ,Predetermined Lane for Auto Flip This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect Allowed values are: - 3'b 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/ 2-1 or CX_NL/ 4-1 or CX_NL/ 8-1, depending on which lane is detected - 3'b 001: Connect logical Lane0 to physical lane 1 - 3'b 010: Connect logical Lane0 to physical lane 3 - 3'b 011: Connect logical Lane0 to physical lane 7 - 3'b 100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state Note: This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--12. " NUM_OF_LANES                          ,Predetermined Number of Lanes Defines the number of lanes which are connected and not bad Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver Indicates the number of lanes to check for exit from Electrical Idle in PollingActive and L2Idle It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured This value is referred to as the 'Predetermined Number of Lanes' in section 42621 of the PCI Express Base 30 Specification, revision 10 Encoding is as follows: - 0x 01: 1 lane - 0x 02: 2 lanes - 0x 03: 3 lanes - When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes You must also change the value in the 'Link Mode Enable' field of PCIE_RC_PORT_LINK_CTRL_OFF The value in this register is normally the same as the encoded value in PCIE_RC_PORT_LINK_CTRL_OFF If you find that one of your used lanes is bad then you must reduce the value in this register This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "        FAST_TRAINING_SEQ                       ,Sets the Number of Fast Training Sequences [N_FTS] that the controller advertises as its N_FTS during Gen2 or Gen3 link training This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state Do not set N_FTS to zero doing so can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky"
rgroup.long 0x1810++0x3
line.long 0x00 "PCIE_RC_PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins."
hexmask.long 0x00 0.--31. 1. " PHY_STATUS                            ,PHY Status Data received directly from the phy_cfg_status bus These is a GPIO register reflecting the values on the static phy_cfg_status input signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband status signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x1814++0x3
line.long 0x00 "PCIE_RC_PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins."
hexmask.long 0x00 0.--31. 1. " PHY_CONTROL                           ,PHY Control Data sent directly to the cfg_phy_control bus These is a GPIO register driving the values on the static cfg_phy_control output signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband control signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x181C++0x3
line.long 0x00 "PCIE_RC_TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register."
bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX                      ,The number of the PF Function on which the Target Values are set This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "        TARGET_MAP_ROM                          ,Target Value for the ROM page of the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--5. " TARGET_MAP_PF                         ,Target Values for each BAR on the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1820++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_ADDR                         ,Integrated MSI Reception Module Address System specified address for MSI memory write transaction termination Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register and also to see if it satisfies the definition of an MSI interrupt request When these conditions are satisfied the Memory Write request is marked as an MSI request Note: This register field is sticky"
group.long 0x1824++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_UPPER_ADDR                   ,Integrated MSI Reception Module Upper Address System specified upper address for MSI memory write transaction termination Allows functions to support a 64-bit MSI address Note: This register field is sticky"
group.long 0x1828++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x182C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1830++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1834++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1838++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x183C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1840++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1844++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1848++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x184C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1850++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1854++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1858++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x185C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1860++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1864++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1868++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x186C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1870++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1874++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1878++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x187C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1880++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1884++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1888++0x3
line.long 0x00 "PCIE_RC_MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register."
hexmask.long 0x00 0.--31. 1. " MSI_GPIO_REG                          ,MSI GPIO Register The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky"
group.long 0x188C++0x3
line.long 0x00 "PCIE_RC_CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register. Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g output will always be set to '1'."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  RADM_CLK_GATING_EN                      ,Enable Radm clock gating feature - 0: Disable - 1: Enable[default]" "0,1"
group.long 0x1890++0x3
line.long 0x00 "PCIE_RC_GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The 'Directed Speed Change' field in the 'Link Width and Speed Change Control Register' is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the 'Directed Speed Change' field is set to '1' and (2) the 'Target Link Speed' field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "        GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE        ,Eq InvalidRequest and RxEqEval Different Time Assertion Disable Disable the assertion of Eq InvalidRequest and RxEqEval at different time Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19.--20. " RSVDP_19                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 18. "         GEN3_DC_BALANCE_DISABLE                 ,DC Balance Disable Disable DC Balance feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE           ,DLLP Transmission Delay Disable Disable delay transmission of DLLPs before equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         GEN3_EQUALIZATION_DISABLE               ,Equalization Disable Disable equalization feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14.--15. " RSVDP_14                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 13. "         RXEQ_RGRDLESS_RXTS                      ,When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RXEQ_PH01_EN                          ,Rx Equalization Phase 0/Phase 1 Hold Enable When this bit is set the upstream port holds phase 0 [the downstream port holds phase 1] for 10ms Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY This bit is used during Virtex-7 Gen3 equalization The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/ 3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/ 1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
bitfld.long 0x00 11. "         EQ_REDO                                 ,Equalization Redo Disable Disable autonomous mechanism for requesting to redo the equalization process Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 10. " EQ_EIEOS_CNT                          ,Equalization EIEOS Count Reset Disable Disable requesting reset of EIEOS count during equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         EQ_PHASE_2_3                            ,Equalization Phase 2 and Phase 3 Disable This applies to downstream ports only Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3               ,Disable Scrambler for Gen3 and Gen4 Data Rate The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller [for example within the PHY] Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL                   ,Gen3 Receiver Impedance ZRX-DC Not Compliant Receivers that operate at 80 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 25 GT/s [40-60 Ohms] must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled - 0: The receiver complies with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher - 1: The receiver does not comply with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates Note: This register field is sticky" "0,1"
group.long 0x18A8++0x3
line.long 0x00 "PCIE_RC_GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP ,Request controller to send back-to-back EIEOS in RecoveryRcvrLock state until presets to coefficients mapping is complete - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " GEN3_EQ_PSET_REQ_AS_COEF              ,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field Do not use Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         GEN3_EQ_FOM_INC_INITIAL_EVAL            ,Include Initial FOM Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC                  ,Preset Request Vector Requesting of Presets during the initial part of the EQ Master Phase Encoding scheme is as follows: Bit [15:0] =0x 0: No preset is requested and evaluated in EQ Master Phase Bit [i] = 1: 'Preset=i' is requested and evaluated in EQ Master Phase - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx 1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: You must ensure 24 ms timeout does not occur in presets requests in EQ master phase, ie, you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky"
bitfld.long 0x00 7. "      RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " GEN3_LOWER_RATE_EQ_REDO_ENABLE        ,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
bitfld.long 0x00 5. "         GEN3_EQ_EVAL_2MS_DISABLE                ,Phase2_3 2 ms Timeout Disable Determine behavior in Phase2 for USP [Phase3 if DSP] when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE             ,Behavior After 24 ms Timeout [when optimal settings are not found] For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationPhase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the 'Link Status Register 2' For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationRcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the 'Link Status Register 2' Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode EQ requests for Figure Of Merit mode complete before 24 ms timeout Please see GEN3_EQ_PSET_REQ_VEC Register for more Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         GEN3_EQ_FB_MODE                         ,Feedback Mode - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - : Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18B4++0x3
line.long 0x00 "PCIE_RC_ORDER_RULE_CTRL_OFF,Order Rule Control Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      CPL_PASS_P                              ,Completion Passing Posted Ordering Rule Control Determines if CPL can pass halted P queue - 0: CPL can not pass P [recommended] - 1: CPL can pass P"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P                             ,Non-Posted Passing Posted Ordering Rule Control Determines if NP can pass halted P queue - 0 : NP can not pass P [recommended] - 1 : NP can pass P"
group.long 0x18B8++0x3
line.long 0x00 "PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register."
bitfld.long 0x00 31. " PIPE_LOOPBACK                         ,PIPE Loopback Enable Indicates RMMI Loopback if M-PCIe Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " RXSTATUS_VALUE                        ,RXSTATUS_VALUE is an internally reserved field Do not use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--23. "         RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " RXSTATUS_LANE                         ,RXSTATUS_LANE is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        LPBK_RXVALID                            ,LPBK_RXVALID is an internally reserved field Do not use Note: This register field is sticky"
group.long 0x18BC++0x3
line.long 0x00 "PCIE_RC_MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register."
hexmask.long 0x00 6.--31. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "  ARI_DEVICE_NUMBER                       ,When ARI is enabled, enables use of the device ID Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " RSVDP_4                               ,Reserved for future use" "0,1"
bitfld.long 0x00 3. "         SIMPLIFIED_REPLAY_TIMER                 ,Enables Simplified Replay Timer [Gen4] Simplified Replay Timer Values are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b Must not be changed while link is in use Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " UR_CA_MASK_4_TRGT1                    ,This field only applies to request TLPs [with UR filtering status] that you have chosen to forward to the application [when you set DEFAULT_TARGET in this register] - When you set this field to '1', the core suppresses error logging, Error Message generation, and CPL generation [for non-posted requests] - You should set this if you have set the Default Target port logic register to '1' Default is CX_MASK_UR_CA_4_TRGT1 configuration parameter Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         DEFAULT_TARGET                          ,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller - 0: The controller drops all incoming I/O or MEM requests [after corresponding error reporting] A completion with UR status will be generated for non-posted requests - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET configuration parameter Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " DBI_RO_WR_EN                          ,Write to RO Registers Using DBI When you set this field to '1', then some RO and HwInit bits are writable from the local application through the DBI Note: This register field is sticky" "0,1"
group.long 0x18C0++0x3
line.long 0x00 "PCIE_RC_MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 7. "    UPCONFIGURE_SUPPORT                     ,Upconfigure Support The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in ConfigurationComplete state This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " DIRECT_LINK_WIDTH_CHANGE              ,Directed Link Width Change The controller always moves to Configuration state through Recovery state when this bit is set to '1' - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in" "0,1"
bitfld.long 0x00 0.--5. "         TARGET_LINK_WIDTH                       ,Target Link Width Values correspond to: - 6'b 000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state - 6'b 000001: x 1 - 6'b 000010: x 2 - 6'b 000100: x 4 - 6'b 001000: x 8 - 6'b 010000: x 16 - 6'b 100000: x32 This field is reserved [fixed to '0'] for M-PCIe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18C4++0x3
line.long 0x00 "PCIE_RC_PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default."
hexmask.long.tbyte 0x00 11.--31. 1. " RSVDP_11                              ,Reserved for future use"
bitfld.long 0x00 10. "    L1_CLK_SEL                              ,L1 Clock control bit - 1: Controller does not request aux_clk switch and core_clk gating in L 1 - 0: Controller requests aux_clk switch and core_clk gating in L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " L1_NOWAIT_P1                          ,L1 entry control bit - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L 1 - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1 Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         L1SUB_EXIT_MODE                         ,L1 Exit Control Using phy_mac_pclkack_n - 1: Core exits L1 without waiting for the PHY to assert phy_mac_pclkack_n - 0: Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " RSVDP_7                               ,Reserved for future use" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         RXSTANDBY_CONTROL                       ,Rxstandby Control Bits 05 determine if the controller asserts the RxStandby signal [mac_phy_rxstandby] in the indicated condition Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP 2 - [4]: RxL0sIdle - [5]: EI Infer in L 0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
hgroup.long 0x18C8++0x3
hide.long 0x00 "PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason. Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire."
in
textline "                                                              "
group.long 0x18CC++0x3
line.long 0x00 "PCIE_RC_LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register."
hexmask.long.byte 0x00 24.--31. 1. " RSVD_I_8                              ,This is an internally reserved field Do not use Note: This register field is sticky"
hexmask.long.tbyte 0x00 1.--23. 1. "        RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " AUTO_FLUSH_EN                         ,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge The flushing process is initiated if any of the following events occur: - Hot reset request A downstream port [DSP] can 'hot reset' an upstream port [USP] by sending two consecutive TS1 ordered sets with the hot reset bit asserted - Warm [Soft] reset request Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst= 0 - Link down reset request A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge Note: This register field is sticky" "0,1"
group.long 0x18D0++0x3
line.long 0x00 "PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 10.--15. "      AMBA_ERROR_RESPONSE_MAP                 ,AXI Slave Response Error Map Allows you to selectively map the errors received from the PCIe completion [for non-posted requests] to the AXI slave responses, slv_rresp or slv_bresp The recommended setting is SLVERR CRS is always mapped to OKAY - [0] -- 0: UR [unsupported request] -> DECERR -- 1: UR [unsupported request] -> SLVERR - [1] -- 0: CRS [configuration retry status] -> DECERR -- 1: CRS [configuration retry status] -> SLVERR - [2] -- 0: CA [completer abort] -> DECERR -- 1: CA [completer abort] -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops [processes internally but not passed to your application] a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface It waits for a timeout and then signals 'Completion Timeout' to the slave interface The controller sets the AXI slave read databus to 0xFFFF for all error responses Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 5.--9. " RSVDP_5                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--4. "        AMBA_ERROR_RESPONSE_CRS                 ,CRS Slave Error Response Mapping Determines the AXI slave response for CRS completions AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " AMBA_ERROR_RESPONSE_VENDORID          ,Vendor ID Non-existent Slave Error Response Mapping Determines the AXI slave response for errors on reads to non-existent Vendor ID register AHB: - 0: OKAY [with FFFF data] The controller ignores the setting in the bit when bit 0 of this register is '0' - 1: ERROR AXI: - 0: OKAY [with FFFF data] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " AMBA_ERROR_RESPONSE_GLOBAL            ,Global Slave Error Response Mapping Determines the AXI slave response for all error scenarios on non-posted requests AHB: - 0: OKAY [with FFFF data for non-posted requests] and ignore the setting in bit [2] of this register - 1: ERROR for normal link [data] accesses and look at bit [2] for other scenarios AXI: - 0: OKAY [with FFFF data for non-posted requests] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] The error response mapping is not applicable to Non-existent Vendor ID register reads Note: This register field is sticky" "0,1"
group.long 0x18D4++0x3
line.long 0x00 "PCIE_RC_AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a 'flush' timer. The timeout value of the timer is set by this register. The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests."
hexmask.long.tbyte 0x00 9.--31. 1. " RSVDP_9                               ,Reserved for future use"
bitfld.long 0x00 8. "    LINK_TIMEOUT_ENABLE_DEFAULT             ,Disable Flush You can disable the flush feature by setting this field to '1' Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " LINK_TIMEOUT_PERIOD_DEFAULT           ,Timeout Value [ms] The timer will timeout and then flush the bridge TX request queues after this amount of time The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests The timer is clocked by core_clk For an M-PCIe configuration: - Time unit of this field is 4 ms - Margin of error for RateA clock is < 1% - Margin of error for RateB clock is between 16% and 17% Note: This register field is sticky"
group.long 0x18D8++0x3
line.long 0x00 "PCIE_RC_AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control."
hexmask.long 0x00 5.--31. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 3.--4. "  AX_MSTR_ORDR_P_EVENT_SEL                ,AXI Master Posted Ordering Event Selector This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, 'NP must not pass P' at the AXI Master Interface The AXI protocol does not support ordering between channels Therefore, NP reads can pass P on your AXI bus fabric This can result in an ordering violation when the read overtakes a P that is going to the same address Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination It does this by waiting for the all of the write responses on the B channel This can affect the performance of the master read channel For scenarios where the interconnect serializes the AXI master 'AW', 'W' and 'AR' channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave [default] - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master - 11: Reserved Note 2: This setting will not affect: - MSI interrupt catcher and P data ordering This is always driven by the B'last event - DMA read engine TLP ordering This is always driven by the B'last event - NP write transactions which are always serialized with P write transactions" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 1. "         AX_SNP_EN                               ,AXI Serialize Non-Posted Requests Enable This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
group.long 0x18E0++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1"
hexmask.long 0x00 2.--31. 1. " CFG_MEMTYPE_BOUNDARY_LOW_ADDR         ,Boundary Lower Address For Memory Type Bits [31:0] of dword-aligned address of the boundary for Memory type The two lower address LSBs are '00' Addresses up to but not including this value are in the lower address space region addresses equal or greater than this value are in the upper address space region Note: This register field is sticky"
bitfld.long 0x00 1. "  RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE                     ,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral upper = Memory - 1: lower = Memory type upper = Peripheral Note: This register field is sticky" "0,1"
group.long 0x18E4++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2"
hexmask.long 0x00 0.--31. 1. " CFG_MEMTYPE_BOUNDARY_HIGH_ADDR        ,Boundary Upper Address For Memory Type Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type Note: This register field is sticky"
group.long 0x18E8++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3"
bitfld.long 0x00 27.--30. " CFG_MSTR_AWCACHE_VALUE                ,Master Write CACHE Signal Value Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1' Note: not applicable to message requests for message requests the value of mstr_awcache is always '0000' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--22. "        CFG_MSTR_ARCACHE_VALUE                  ,Master Read CACHE Signal Value Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 11.--14. " CFG_MSTR_AWCACHE_MODE                 ,Master Write CACHE Signal Behavior Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always '0000' regardless of the value of this bit Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--6. "        CFG_MSTR_ARCACHE_MODE                   ,Master Read CACHE Signal Behavior Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18F0++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the and registers."
hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW              ,Lower 20 bits of the programmable AXI address for Messages Note: This register field is sticky"
group.long 0x18F4++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to."
hexmask.long 0x00 0.--31. 1. " CFG_AXIMSTR_MSG_ADDR_HIGH             ,Upper 32 bits of the programmable AXI address for Messages Note: This register field is sticky"
rgroup.long 0x18F8++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_NUMBER                        ,Version Number"
rgroup.long 0x18FC++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_TYPE                          ,Version Type"
group.long 0x1940++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 2.--31. 1. " MSIX_ADDRESS_MATCH_LOW                ,MSI-X Address Match Low Address Note: This register field is sticky"
bitfld.long 0x00 0. "  MSIX_ADDRESS_MATCH_EN                   ,MSI-X Match Enable Enable the MSI-X Address Match feature when the AXI bridge is present Note: This register field is sticky" "0,1"
group.long 0x1944++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 0.--31. 1. " MSIX_ADDRESS_MATCH_HIGH               ,MSI-X Address Match High Address Note: This register field is sticky"
group.long 0x1948++0x3
line.long 0x00 "PCIE_RC_MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. - For AXI configurations: when your local application writes (MWr) to the address defined in , the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs."
bitfld.long 0x00 24.--28. " MSIX_DOORBELL_PF                      ,MSIX Doorbell Physical Function This register determines the Physical Function for the MSI-X transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--23. 1. "        MSIX_DOORBELL_VF                        ,MSIX Doorbell Virtual Function This register determines the Virtual Function for the MSI-X transaction"
textline "                                                              "
bitfld.long 0x00 15. " MSIX_DOORBELL_VF_ACTIVE               ,MSIX Doorbell Virtual Function Active This register determines whether a Virtual Function is used to generate the MSI-X transaction" "0,1"
bitfld.long 0x00 12.--14. "         MSIX_DOORBELL_TC                        ,MSIX Doorbell Traffic Class This register determines which traffic class to generate the MSI-X transaction with" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 0.--10. 1. " MSIX_DOORBELL_VECTOR                  ,MSI-X Doorbell Vector This register determines which vector to generate the MSI-X transaction for"
group.long 0x194C++0x3
line.long 0x00 "PCIE_RC_MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests."
bitfld.long 0x00 25. " MSIX_RAM_CTRL_DBG_PBA                 ,MSIX PBA RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the PBA Use can also use the dbg_pba input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         MSIX_RAM_CTRL_DBG_TABLE                 ,MSIX Table RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the Table Use can also use the dbg_table input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " MSIX_RAM_CTRL_BYPASS                  ,MSIX RAM Control Bypass The bypass field, when set, disables the internal generation of low power signals for both RAMs It is up to the application to ensure the RAMs are in the proper power state before trying to access them Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         MSIX_RAM_CTRL_PBA_SD                    ,MSIX PBA RAM Shut Down Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " MSIX_RAM_CTRL_PBA_DS                  ,MSIX PBA RAM Deep Sleep Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         MSIX_RAM_CTRL_TABLE_SD                  ,MSIX Table RAM Shut Down Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " MSIX_RAM_CTRL_TABLE_DS                ,MSIX Table RAM Deep Sleep Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
group.long 0x1B40++0x3
line.long 0x00 "PCIE_RC_AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register."
hexmask.long.tbyte 0x00 10.--31. 1. " RSVDP_10                              ,Reserved for future use"
hexmask.long.word 0x00 0.--9. 1. "    AUX_CLK_FREQ                            ,The aux_clk frequency in MHz This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted If the actual frequency [f] of aux_clk does not exactly match the programmed frequency [f_prog], then there is an error in the time counted by the controller that can be expressed in percentage as: err% = [f_prog/f-1]*100 For example if f=25 MHz and f_prog=3 MHz, then err% =[3/ 25-1]* 100 =20%, meaning that the time counted by the controller on aux_clk will be 20 0reater than the time in us programmed in the corresponding time register [for example T_POWER_ON] Note: This register field is sticky"
group.long 0x1B44++0x3
line.long 0x00 "PCIE_RC_L1_SUBSTATES_OFF,L1 Substates Timing Register."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 6.--7. "    L1SUB_T_PCLKACK                         ,Max delay [in 1us units] between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n If the PHY does not respond within this time the request is aborted Range is 03 Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2.--5. " L1SUB_T_L1_2                          ,Duration [in 1us units] of L12 Range is 015 Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        L1SUB_T_POWER_OFF                       ,Duration [in 1us units] of L12Entry Range is 03 Note: This register field is sticky" "0,1,2,3"
group.long 0x6000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x600C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x610C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x620C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x630C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x640C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x650C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x660C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x670C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x680C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x690C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x700C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x710C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x720C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x730C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x740C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x750C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x760C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x770C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x780C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x790C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
width 0x0B
tree.end
tree "PCIE1_DAT"
base ad:0x5600000
width 53.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_RC_PID,Peripheral Version and ID Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                                 ,Module ID of the Peripheral"
bitfld.long 0x00 11.--15. "      RTL                                     ,RTL Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 8.--10. " MAJOR                                 ,Major Revision Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM                                  ,Custom Code" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 0.--5. " MINOR                                 ,Minor Revision Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "PCIE_RC_CMD_STATUS,Command Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. " RSVD11                                ,Reserved"
bitfld.long 0x00 7. "    RX_LANE_FLIP_EN                         ,Set to enable manual reversal for RX lanes. This drives the rx_lane_flip_en input of the PCIe core" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " TX_LANE_FLIP_EN                       ,Set to enable manual reversal for TX lanes. This drives the tx_lane_flip_en input of the PCIe core" "0,1"
bitfld.long 0x00 5. "         DBI_CS2                                 ,Set to enable writing to BAR mask registers that are overlaid on BAR registers." "0,1"
textline "                                                              "
bitfld.long 0x00 4. " APP_RETRY_EN                          ,Application Request Retry Enable. Setting this bit will enable all incoming PCIe transactions to be returned with a retry response. This feature can be used if initialization can take longer than PCIe stipulated time frame." "0,1"
bitfld.long 0x00 1.--3. "         RSVD10                                  ,Reserved" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " LTSSM_EN                              ,Link Training Enable. Setting this bit will enable LTSSM in PCI Express Core and link negotiation with link partner will begin." "0,1"
group.long 0x14++0x3
line.long 0x00 "PCIE_RC_RSTCMD,Reset Command and Status Register"
bitfld.long 0x00 29.--31. " RSVD21                                ,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "         FLR_PF_ACTIVE                           ,Function-level reset for physical function active. 1 - FLR for Physical function 0 is active" "0,1"
textline "                                                              "
hexmask.long 0x00 1.--27. 1. " RSVD20                                ,Reserved"
bitfld.long 0x00 0. "  INIT_RST                                ,Write one to initiate a downstream hot reset sequence on downstream" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_RC_PTMCFG,PTM Config register"
hexmask.long.tbyte 0x00 14.--31. 1. " RSVD32                                ,Reserved"
bitfld.long 0x00 8.--13. "    PTM_CLK_SEL                             ,Select ptm_local_clk bit input to CPTS. 0 will select ptm_local_clk[0], 1 will select ptm_local_clk[1] ... 63 will select ptm_local_clk[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVD30                                ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_CONTEXT_VALID                       ,'1' indicates PTM context is valid-EP only" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_MANUAL_UPDATE                     ,Write '1' to enable PTM transaction.EP only. EP will initiate one PTM transaction when this field is updated. Always reads '0'" "0,1"
bitfld.long 0x00 0. "         PTM_AUTO_UPDATE                         ,Write '1' to enable PTM auto-update-EP only. EP will automatically initiate PTM transaction every 10ms" "0,1"
group.long 0x20++0x3
line.long 0x00 "PCIE_RC_PMCMD,Power Management Command Register"
hexmask.long 0x00 2.--31. 1. " RSVD40                                ,Reserved"
bitfld.long 0x00 1. "  PM_XMT_TURNOFF                          ,Write one to transmit a PM_TURNOFF message. Reads zero. Applicable in RC mode only." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_XMT_PE                             ,Write one to transmit a PM_PME message for Physical Function 0. Reads zero. Applicable to EP mode only." "0,1"
group.long 0x50++0x3
line.long 0x00 "PCIE_RC_IRQ_EOI,End of Interrupt Register"
hexmask.long 0x00 5.--31. 1. " RSVD60                                ,Reserved"
bitfld.long 0x00 0.--3. "  EOI                                     ,EOI for interrupts. Write to indicate end-of-interrupt for the respective interrupt. EOI value has to be the following as indicated below to toggle the interrupts in the various interrupt registers EOI = 0 for LEGACY_A_IRQ, EOI = 1 for LEGACY_B_IRQ, EOI = 2 for LEGACY_C_IRQ, EOI = 3 for LEGACY_D_IRQ, EOI = 4 for MMR0_IRQ, EOI = 5 for MMR1_IRQ, EOI = 6 for MMR2_IRQ, EOI = 7 for MMR3_IRQ, EOI = 8 for MMR4_IRQ, EOI = 9 for MMR5_IRQ, EOI = 10 for MMR6_IRQ, EOI = 11 for MMR7_IRQ, EOI = 12 for ERR_IRQ, EOI = 13 for PMRST_IRQ, EOI = 14 for PTM_IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x3
line.long 0x00 "PCIE_RC_MMR_IRQ,Memory Mapped Interrupt IRQ Register"
hexmask.long 0x00 0.--30. 1. " MMR_IRQ                               ,This register is not used in RC mode."
group.long 0x64++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_SET,Legacy Interrupt Request Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD70                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_SET_0                        ,Write one to generate assert legacy PCI interrupt message for Physical Function0. On read, a one indicates currently asserted interrupt." "0,1"
hgroup.long 0x68++0x3
hide.long 0x00 "PCIE_RC_LEGACY_IRQ_CLR,Legacy Interrupt Request Clear Register"
in
textline "                                                              "
rgroup.long 0x6C++0x3
line.long 0x00 "PCIE_RC_LEGACY_IRQ_STATUS,Legacy Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD90                                ,Reserved"
bitfld.long 0x00 0. "  LEGACY_IRQ_STATUS_0                     ,Indicates whether legacy PCI interrupt for physical function 0 is asserted or not" "0,1"
group.long 0x70++0x3
line.long 0x00 "PCIE_RC_GPR0,General Purpose 0 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC0                              ,Generic Info field 0"
group.long 0x74++0x3
line.long 0x00 "PCIE_RC_GPR1,General Purpose 1 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC1                              ,Generic Info field 1"
group.long 0x78++0x3
line.long 0x00 "PCIE_RC_GPR2,General Purpose 2 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC2                              ,Generic Info field 2"
group.long 0x7C++0x3
line.long 0x00 "PCIE_RC_GPR3,General Purpose 3 Register"
hexmask.long 0x00 0.--31. 1. " GENERIC3                              ,Generic Info field 3"
group.long 0x100++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS_RAW,MMR 0 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD100                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (24, 16, 8, 0) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x104++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_STATUS,MMR 0 Interrupt Status Register"
in
textline "                                                              "
group.long 0x108++0x3
line.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_SET,MMR 0 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD111                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR0_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (24, 16, 8, 0) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x10C++0x3
hide.long 0x00 "PCIE_RC_MMR0_IRQ_ENABLE_CLR,MMR 0 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x110++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS_RAW,MMR 1 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD120                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (25, 17, 9, 1) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x114++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_STATUS,MMR 1 Interrupt Status Register"
in
textline "                                                              "
group.long 0x118++0x3
line.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_SET,MMR 1 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD122                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR1_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (25, 17, 9, 1) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x11C++0x3
hide.long 0x00 "PCIE_RC_MMR1_IRQ_ENABLE_CLR,MMR 1 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x120++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS_RAW,MMR 2 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD130                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (26, 18, 10, 2) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x124++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_STATUS,MMR 2 Interrupt Status Register"
in
textline "                                                              "
group.long 0x128++0x3
line.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_SET,MMR 2 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD132                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR2_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (26, 18, 10, 2) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x12C++0x3
hide.long 0x00 "PCIE_RC_MMR2_IRQ_ENABLE_CLR,MMR 2 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x130++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS_RAW,MMR 3 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD140                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (27, 19, 11, 3) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x134++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_STATUS,MMR 3 Interrupt Status Register"
in
textline "                                                              "
group.long 0x138++0x3
line.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_SET,MMR 3 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD142                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR3_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (27, 19, 11, 3) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x13C++0x3
hide.long 0x00 "PCIE_RC_MMR3_IRQ_ENABLE_CLR,MMR 3 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x140++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS_RAW,MMR 4 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD150                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (28, 20, 12, 4) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x144++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_STATUS,MMR 4 Interrupt Status Register"
in
textline "                                                              "
group.long 0x148++0x3
line.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_SET,MMR 4 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD152                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR4_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (28, 20, 12, 4) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x14C++0x3
hide.long 0x00 "PCIE_RC_MMR4_IRQ_ENABLE_CLR,MMR 4 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x150++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS_RAW,MMR 5 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD160                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (29, 21, 13, 5) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x154++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_STATUS,MMR 5 Interrupt Status Register"
in
textline "                                                              "
group.long 0x158++0x3
line.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_SET,MMR 5 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD162                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR5_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (29, 21, 13, 5) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x15C++0x3
hide.long 0x00 "PCIE_RC_MMR5_IRQ_ENABLE_CLR,MMR 5 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x160++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS_RAW,MMR 6 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD170                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_STATUS_RAW                     ,Each bit indicates raw status of MMR vectors (30, 22, 14, 6) associated with the bit. Typically, writes to this register are only done for debug purposes." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x164++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_STATUS,MMR 6 Interrupt Status Register"
in
textline "                                                              "
group.long 0x168++0x3
line.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_SET,MMR 6 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD172                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR6_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (30, 22, 14, 6) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x16C++0x3
hide.long 0x00 "PCIE_RC_MMR6_IRQ_ENABLE_CLR,MMR 6 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x170++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS_RAW,MMR 7 Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD180                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_STATUS_RAW                     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x174++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_STATUS,MMR 7 Interrupt Status Register"
in
textline "                                                              "
group.long 0x178++0x3
line.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_SET,MMR 7 Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD182                               ,Reserved"
bitfld.long 0x00 0.--3. "  MMR7_IRQ_EN_SET                         ,Each bit, when written to, enables the MMR interrupt (31, 23, 15, 7) associated with the bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x17C++0x3
hide.long 0x00 "PCIE_RC_MMR7_IRQ_ENABLE_CLR,MMR 7 Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x180++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS_RAW,Legacy A Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD200                               ,Reserved"
bitfld.long 0x00 0. "  INTA_RAW                                ,Legacy Interrupt A raw status. RC mode only" "0,1"
hgroup.long 0x184++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_STATUS,Legacy A Raw Interrupt Status Register"
in
textline "                                                              "
group.long 0x188++0x3
line.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_SET,Legacy A Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD220                               ,Reserved"
bitfld.long 0x00 0. "  INTA_EN_SET                             ,Legacy Interrupt A enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x18C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_A_IRQ_ENABLE_CLR,Legacy A Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x190++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS_RAW,Legacy B Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD300                               ,Reserved"
bitfld.long 0x00 0. "  INTB_RAW                                ,Legacy Interrupt B raw status. RC mode only" "0,1"
hgroup.long 0x194++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_STATUS,Legacy B Interrupt Status Register"
in
textline "                                                              "
group.long 0x198++0x3
line.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_SET,Legacy B Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD320                               ,Reserved"
bitfld.long 0x00 0. "  INTB_EN_SET                             ,Legacy Interrupt B enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x19C++0x3
hide.long 0x00 "PCIE_RC_LEGACY_B_IRQ_ENABLE_CLR,Legacy B Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1A0++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS_RAW,Legacy C Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD400                               ,Reserved"
bitfld.long 0x00 0. "  INTC_RAW                                ,Legacy Interrupt C raw status. RC mode only" "0,1"
hgroup.long 0x1A4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_STATUS,Legacy C Interrupt Status Register"
in
textline "                                                              "
group.long 0x1A8++0x3
line.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_SET,Legacy C Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD420                               ,Reserved"
bitfld.long 0x00 0. "  INTC_EN_SET                             ,Legacy Interrupt C enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1AC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_C_IRQ_ENABLE_CLR,Legacy C Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1B0++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS_RAW,Legacy D Raw Interrupt Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD500                               ,Reserved"
bitfld.long 0x00 0. "  INTD_RAW                                ,Legacy Interrupt D raw status. RC mode only" "0,1"
hgroup.long 0x1B4++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_STATUS,Legacy D Interrupt Status Register"
in
textline "                                                              "
group.long 0x1B8++0x3
line.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_SET,Legacy D Interrupt Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD520                               ,Reserved"
bitfld.long 0x00 0. "  INTD_EN_SET                             ,Legacy Interrupt D enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1BC++0x3
hide.long 0x00 "PCIE_RC_LEGACY_D_IRQ_ENABLE_CLR,Legacy D Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1C0++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status Register"
hexmask.long 0x00 5.--31. 1. " RSVD600                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_RAW                             ,AER MSI error raw status. This interrupt is generated due to the assertion of the cfg_aer_rc_err_int or the cfg_aer_err_msi output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_RAW                          ,Correctable error raw status. This interrupt is generated due to the assertion of the radm_correctable_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_RAW                        ,Nonfatal error raw status. This interrupt is generated due to the assertion of the radm_nonfatal_err output of the PCIe controller core." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_RAW                         ,Fatal error raw status. This interrupt is generated due to the assertion of the radm_fatal_err output of the PCIe controller core." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_RAW                             ,System Error (FATAL, NONFATAL or CORRECTABLE error) raw status. This interrupt is generated due to the assertion of the cfg_sys_err_rc output of the PCIe controller core." "0,1"
hgroup.long 0x1C4++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_STATUS,"
in
textline "                                                              "
group.long 0x1C8++0x3
line.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_SET,"
hexmask.long 0x00 5.--31. 1. " RSVD620                               ,Reserved"
bitfld.long 0x00 4. "  ERR_AER_EN_SET                          ,AER MSI error interrupt enable. Set to enable. On read, one/zero means enabled/disabled respectively" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " ERR_CORR_EN_SET                       ,Correctable error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 2. "         ERR_NONFATAL_EN_SET                     ,Nonfatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 1. " ERR_FATAL_EN_SET                      ,Fatal error interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 0. "         ERR_SYS_EN_SET                          ,System Error (FATAL, NONFATAL or CORRECTABLE error) interrupt enable. Set to enable the interrupt. On read, one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1CC++0x3
hide.long 0x00 "PCIE_RC_ERR_IRQ_ENABLE_CLR,"
in
textline "                                                              "
group.long 0x1D0++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Raw Status Register"
hexmask.long 0x00 4.--31. 1. " RSVD700                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_RAW                         ,Link Request Reset interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_RAW                            ,Power Management PME message received interrupt raw status" "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_RAW                           ,Power Management ACK received interrupt raw status" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_RAW                        ,Power Management Turnoff message received raw status" "0,1"
hgroup.long 0x1D4++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_STATUS,Power Management and Reset Interrupt Status Register"
in
textline "                                                              "
group.long 0x1D8++0x3
line.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_SET,Power Management and Reset Interrupt Enable Set Register"
hexmask.long 0x00 4.--31. 1. " RSVD720                               ,Reserved"
bitfld.long 0x00 3. "  LNK_RST_REQ_EN_SET                      ,Link Request Reset interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 2. " PM_PME_EN_SET                         ,Power Management PME message received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
bitfld.long 0x00 1. "         PM_TO_ACK_EN_SET                        ,Power Management ACK received interrupt enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PM_TURNOFF_EN_SET                     ,Power Management Turnoff message received enable. Set to enable the interrupt. Read one/zero means interrupt is enabled/disabled." "0,1"
hgroup.long 0x1DC++0x3
hide.long 0x00 "PCIE_RC_PMRST_IRQ_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear Register"
in
textline "                                                              "
group.long 0x1E0++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_STATUS_RAW,Precision Time Measurement Raw Status Register"
hexmask.long 0x00 1.--31. 1. " RSVD800                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_RAW                     ,Precision Time Measurement interrupt raw status" "0,1"
hgroup.long 0x1E4++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_STATUS,Precision Time Measurement Status Register"
in
textline "                                                              "
group.long 0x1E8++0x3
line.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_SET,Precision Time Measurement Enable Set Register"
hexmask.long 0x00 1.--31. 1. " RSVD820                               ,Reserved"
bitfld.long 0x00 0. "  PTM_CLK_UPDATED_EN_SET                  ,Precision Time Measurement interrupt enable set. Write one to set" "0,1"
hgroup.long 0x1EC++0x3
hide.long 0x00 "PCIE_RC_PTM_IRQ_ENABLE_CLR,Precision Time Measurement Enable Clear Register"
in
textline "                                                              "
rgroup.long 0x1000++0x3
line.long 0x00 "PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID                             ,Device ID - Vendor Assigned Device Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      VENDOR_ID                               ,Vendor ID - PCI-SIG assigned Manufacturer Identifier For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1004++0x3
hide.long 0x00 "PCIE_RC_TYPE1_STATUS_COMMAND_REG,Command and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1008++0x3
line.long 0x00 "PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS_CODE                       ,Base Class Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SUBCLASS_CODE                           ,Subclass Code to represent Device Type For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PROGRAM_INTERFACE                     ,Class Code Programming Interface For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        REVISION_ID                             ,Vendor chosen Revision ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x100C++0x3
line.long 0x00 "PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST, Header Type, Cache Line Size, and Master Latency Timer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " BIST                                  ,Optional for BIST support For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 23. "        MULTI_FUNC                              ,Specifies whether device is multifunction For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE                           ,Specifies Header Type For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "        LATENCY_MASTER_TIMER                    ,Primary Latency Timer Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE                       ,Cache Line Size field Has no effect on PCIe device behavior For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1018++0x3
line.long 0x00 "PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Primary, Secondary, Subordinate Bus Numbers and Latency Timer Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SEC_LAT_TIMER                         ,Latency Timer Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 16.--23. 1. "        SUB_BUS                                 ,Subordinate Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS                               ,Secondary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 0.--7. 1. "        PRIM_BUS                                ,Primary Bus Number Not used in PCI-Express For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x101C++0x3
hide.long 0x00 "PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status and I/O Base and Limit Registers. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1020++0x3
line.long 0x00 "PCIE_RC_MEM_LIMIT_MEM_BASE_REG,Memory Base and Memory Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " MEM_LIMIT                             ,Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 16.--19. "      MEM_LIMIT_RESERV                        ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " MEM_BASE                              ,Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 0.--3. "      MEM_BASE_RESERV                         ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x3
line.long 0x00 "PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Base and Limit Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PREF_MEM_LIMIT                        ,Prefetchable Memory Limit Address For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 17.--19. "      PREF_RESERV1                            ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 16. " PREF_MEM_LIMIT_DECODE                 ,Prefetchable Memory Limit Decode For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 4.--15. 1. "         PREF_MEM_BASE                           ,Prefetchable Memory Base Address For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 1.--3. " PREF_RESERV                           ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PREF_MEM_DECODE                         ,Prefetchable Memory Decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
rgroup.long 0x1028++0x3
line.long 0x00 "PCIE_RC_PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_BASE_UPPER                   ,Prefetchable Memory Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x102C++0x3
line.long 0x00 "PCIE_RC_PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PREF_MEM_LIMIT_UPPER                  ,Prefetchable Memory Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1030++0x3
line.long 0x00 "PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Base and Limit Upper 16 Bits Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " IO_LIMIT_UPPER                        ,Prefetchable I/O Limit Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
hexmask.long.word 0x00 0.--15. 1. "      IO_BASE_UPPER                           ,Prefetchable I/O Base Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
rgroup.long 0x1034++0x3
line.long 0x00 "PCIE_RC_TYPE1_CAP_PTR_REG,Capability Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "    CAP_POINTER                             ,Pointer to first item in the PCI Capability Structure For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x1038++0x3
line.long 0x00 "PCIE_RC_TYPE1_EXP_ROM_BASE_REG,Expansion ROM BAR and Mask Register. For a description of this standard PCIe register, see the PCI Express Specification. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address."
hexmask.long.tbyte 0x00 11.--31. 1. " EXP_ROM_BASE_ADDRESS                  ,Expansion ROM BAR and Mask Register For a description of this standard PCIe register, see the PCI Express Specification The mask for this ROM BAR exists [if implemented] as a shadow register at this address The assertion of CS2 [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] is required to write to the second register at this address Note: The access attributes of this field are as follows: - Dbi: R/W"
hexmask.long.word 0x00 1.--10. 1. "    RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " ROM_BAR_ENABLE                        ,Expansion ROM Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x103C++0x3
line.long 0x00 "PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Interrupt Line and Pin and Bridge Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 23.--31. 1. " BRIDGE_CTRL_RESERV                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22. "      SBR                                     ,Secondary Bus Hot Reset For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 21. " MSTR_ABORT_MODE                       ,Master Abort Mode Does not apply to PCI Express For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 20. "         VGA_16B_DEC                             ,VGA 16 bit decode For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " VGA_EN                                ,VGA Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
bitfld.long 0x00 18. "         ISA_EN                                  ,ISA Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " SERR_EN                               ,System Error Response Enable from Secondary to Primary For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         PERE                                    ,Parity Error Response Enable Controls Logging of Poisoned TLPs For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " INT_PIN                               ,PCI Compatible Interrupt Pin Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        INT_LINE                                ,PCI Compatible Interrupt Line Routing Register Field For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1040++0x3
line.long 0x00 "PCIE_RC_CAP_ID_NXT_PTR_REG,Power Management Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " PME_SUPPORT                           ,Power Management Event Support For a description of this standard PCIe register field, see the PCI Express Specification The read value from this field is the write value && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where D1_SUPPORT and D2_SUPPORT are fields in this register The reset value PME_SUPPORT_n && [sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1], where PME_SUPPORT_n is a configuration parameter Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        D2_SUPPORT                              ,D2 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " D1_SUPPORT                            ,D1 State Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 22.--24. "         AUX_CURR                                ,Auxiliary Current Requirements For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 21. " DSI                                   ,Device Specific Initialization Bit For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         PME_CLK                                 ,PCI Clock Requirement For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16.--18. " PM_SPEC_VER                           ,Power Management Spec Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "         PM_NEXT_POINTER                         ,Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " PM_CAP_ID                             ,Power Management Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
hgroup.long 0x1044++0x3
hide.long 0x00 "PCIE_RC_CON_STATUS_REG,Power Management Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1050++0x3
line.long 0x00 "PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID, Next Pointer, Capability/Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        PCI_MSI_EXT_DATA_EN                     ,Extended Message Data Enable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_EXT_DATA_CAP ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " PCI_MSI_EXT_DATA_CAP                  ,Extended Message Data Capable For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         PCI_PVM_SUPPORT                         ,MSI Per Vector Masking Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 23. " PCI_MSI_64_BIT_ADDR_CAP               ,MSI 64-bit Address Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
bitfld.long 0x00 20.--22. "         PCI_MSI_MULTIPLE_MSG_EN                 ,MSI Multiple Message Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 17.--19. " PCI_MSI_MULTIPLE_MSG_CAP              ,MSI Multiple Message Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         PCI_MSI_ENABLE                          ,MSI Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSI_CAP_NEXT_OFFSET               ,MSI Capability Next Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSI_CAP_ID                          ,MSI Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1054++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_04H_REG,MSI Message Lower Address Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " PCI_MSI_CAP_OFF_04H                   ,MSI Message Lower Address Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 0.--1. "  RSVDP_0                                 ,Reserved for future use" "0,1,2,3"
group.long 0x1058++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_08H_REG,For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0AH                   ,For a 32 bit MSI Message, this field contains Ext MSI Data For 64-bit it contains upper 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_08H                     ,For a 32-bit MSI Message, this field contains Data For 64-bit it contains lower 16 bits of the Upper Address For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R"
group.long 0x105C++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_0CH_REG,For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " PCI_MSI_CAP_OFF_0EH                   ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the upper Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: [!MSI_64_EN && MSI_PVM_EN_VALUE] ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO"
hexmask.long.word 0x00 0.--15. 1. "      PCI_MSI_CAP_OFF_0CH                     ,For a 64-bit MSI Message, this field contains Data For 32-bit, it contains the lower Mask Bits if PVM is enabled For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP OR MSI_PVM_EN ? R/W : R"
group.long 0x1060++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_10H_REG,Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_10H                   ,Used for MSI when Vector Masking Capable For 32-bit contains Pending Bits For 64-bit, contains Mask Bits For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R"
rgroup.long 0x1064++0x3
line.long 0x00 "PCIE_RC_MSI_CAP_OFF_14H_REG,Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 0.--31. 1. " PCI_MSI_CAP_OFF_14H                   ,Used for MSI 64-bit messaging when Vector Masking Capable Contains Pending Bits For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1070++0x3
line.long 0x00 "PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities, ID, Next Pointer Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         RSVD                                    ,Reserved For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 25.--29. " PCIE_INT_MSG_NUM                      ,PCIE Interrupt Message Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "        PCIE_SLOT_IMP                           ,PCIe Slot Implemented Valid For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--23. " PCIE_DEV_PORT_TYPE                    ,PCIE Device/PortType For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        PCIE_CAP_REG                            ,PCIE Capability Version Number For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCIE_CAP_NEXT_PTR                     ,PCIE Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCIE_CAP_ID                             ,PCIE Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x1074++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES_REG,Device Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      PCIE_CAP_ROLE_BASED_ERR_REPORT          ,Role-based Error Reporting Implemented For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 6.--14. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "      PCIE_CAP_EXT_TAG_SUPP                   ,Extended Tag Field Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 3.--4. " PCIE_CAP_PHANTOM_FUNC_SUPPORT         ,Phantom Functions Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 0.--2. "         PCIE_CAP_MAX_PAYLOAD_SIZE               ,Max Payload Size Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hgroup.long 0x1078++0x3
hide.long 0x00 "PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x107C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES_REG,Link Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " PCIE_CAP_PORT_NUM                     ,Port Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " PCIE_CAP_ASPM_OPT_COMPLIANCE          ,ASPM Optionality Compliance For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 21. "         PCIE_CAP_LINK_BW_NOT_CAP                ,Link Bandwidth Notification Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " PCIE_CAP_DLL_ACTIVE_REP_CAP           ,Data Link Layer Link Active Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 19. "         PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP      ,Surprise Down Error Reporting Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " PCIE_CAP_CLOCK_POWER_MAN              ,Clock Power Management For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 15.--17. "         PCIE_CAP_L1_EXIT_LATENCY                ,L1 Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 12.--14. " PCIE_CAP_L0S_EXIT_LATENCY             ,LOs Exit Latency For a description of this standard PCIe register field, see the PCI Express Specification There are two each of these register fields, this one and a shadow one at the same address The Common Clock bit [PCIE_CAP_COMMON_CLK_CONFIG] of the Link Control Register [" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--11. "         PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT   ,Level of ASPM [Active State Power Management] Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 4.--9. " PCIE_CAP_MAX_LINK_WIDTH               ,Maximum Link Width For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. "        PCIE_CAP_MAX_LINK_SPEED                 ,Maximum Link Speed For a description of this standard PCIe register field, see the PCI Express Specification In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1080++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL_LINK_STATUS_REG,Link Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1084++0x3
line.long 0x00 "PCIE_RC_SLOT_CAPABILITIES_REG,Slot Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 19.--31. 1. " PCIE_CAP_PHY_SLOT_NUM                 ,Physical Slot Number For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 18. "      PCIE_CAP_NO_CMD_CPL_SUPPORT             ,No Command Completed Support For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP_ELECTROMECH_INTERLOCK        ,Electromechanical Interlock Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 15.--16. "         PCIE_CAP_SLOT_POWER_LIMIT_SCALE         ,Slot Power Limit Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 7.--14. 1. " PCIE_CAP_SLOT_POWER_LIMIT_VALUE       ,Slot Power Limit Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R"
bitfld.long 0x00 6. "        PCIE_CAP_HOT_PLUG_CAPABLE               ,Hot Plug Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_HOT_PLUG_SURPRISE            ,Hot Plug Surprise possible For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_POWER_INDICATOR                ,Power Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_ATTENTION_INDICATOR          ,Attention Indicator Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_MRL_SENSOR                     ,MRL Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_POWER_CONTROLLER             ,Power Controller Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_ATTENTION_INDICATOR_BUTTON     ,Attention Button Present For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R" "0,1"
hgroup.long 0x1088++0x3
hide.long 0x00 "PCIE_RC_SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x108C++0x3
line.long 0x00 "PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      PCIE_CAP_CRS_SW_VISIBILITY              ,CRS Software Visibility Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W [Sticky] else R [Sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 5.--15. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 4. "      PCIE_CAP_CRS_SW_VISIBILITY_EN           ,Configuration Request Retry Status [CRS] Software Visibility Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REGPCIE_CAP_CRS_SW_VISIBILITY ? RW : RO" "0,1"
textline "                                                              "
bitfld.long 0x00 3. " PCIE_CAP_PME_INT_EN                   ,PME Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 2. "         PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN        ,System Error on Fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN  ,System Error on Non-fatal Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN         ,System Error on Correctable Error Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1090++0x3
hide.long 0x00 "PCIE_RC_ROOT_STATUS_REG,Root Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1094++0x3
line.long 0x00 "PCIE_RC_DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--30. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 18.--19. "        PCIE_CAP_OBFF_SUPPORT                   ,[OBFF] Optimized Buffer Flush/fill Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 17. " PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT      ,10-Bit Tag Requester Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
bitfld.long 0x00 16. "         PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT       ,10-Bit Tag Completer Supported For a description of this standard PCIe register field, see the PCI Express Base Specification 40" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " PCIE_CAP_TPH_CMPLT_SUPPORT_1          ,TPH Completer Supported Bit 1 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 12. "         PCIE_CAP_TPH_CMPLT_SUPPORT_0            ,TPH Completer Supported Bit 0 For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 11. " PCIE_CAP_LTR_SUPP                     ,LTR Mechanism Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 10. "         PCIE_CAP_NO_RO_EN_PR2PR_PAR             ,No Relaxed Ordering Enabled PR-PR Passing For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " PCIE_CAP_128_CAS_CPL_SUPP             ,128 Bit CAS Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 8. "         PCIE_CAP_64_ATOMIC_CPL_SUPP             ,64 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " PCIE_CAP_32_ATOMIC_CPL_SUPP           ,32 Bit AtomicOp Completer Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 6. "         PCIE_CAP_ATOMIC_ROUTING_SUPP            ,Atomic Operation Routing Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT          ,ARI Forwarding Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT    ,Completion Timeout Disable Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_RANGE            ,Completion Timeout Ranges Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1098++0x3
line.long 0x00 "PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 5. " PCIE_CAP_ARI_FORWARD_SUPPORT_CS       ,ARI Forwarding Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 4. "         PCIE_CAP_CPL_TIMEOUT_DISABLE            ,Completion Timeout Disable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--3. " PCIE_CAP_CPL_TIMEOUT_VALUE            ,Completion Timeout Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x109C++0x3
line.long 0x00 "PCIE_RC_LINK_CAPABILITIES2_REG,Link Capabilities 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 25.--30. " RSVDP_25                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 9.--22. 1. "        RSVDP_9                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 8. " PCIE_CAP_CROSS_LINK_SUPPORT           ,Cross Link Supported For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR      ,Supported Link Speeds Vector For a description of this standard PCIe register field, see the PCI Express Specification This field has a default of [PCIE_CAP_MAX_LINK_SPEED == 0100] ? 0001111 : [PCIE_CAP_MAX_LINK_SPEED == 0011] ? 0000111 : [PCIE_CAP_MAX_LINK_SPEED == 0010] ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the PCIE_RC_LINK_CAPABILITIES_REG register"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
hgroup.long 0x10A0++0x3
hide.long 0x00 "PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x10B0++0x3
line.long 0x00 "PCIE_RC_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID, Next Pointer, Control Registers. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " PCI_MSIX_ENABLE                       ,MSI-X Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 30. "         PCI_MSIX_FUNCTION_MASK                  ,Function Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--26. 1. "         PCI_MSIX_TABLE_SIZE                     ,MSI-X Table Size For a description of this standard PCIe register field, see the PCI Express Specification SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' [PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG] To write this common value, you must perform a DBI_CS2 write [that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge] while accessing the PCI_MSIX_TABLE_SIZE field in the PF"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " PCI_MSIX_CAP_NEXT_OFFSET              ,MSI-X Next Capability Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        PCI_MSIX_CAP_ID                         ,MSI-X Capability ID For a description of this standard PCIe register field, see the PCI Express Specification"
rgroup.long 0x10B4++0x3
line.long 0x00 "PCIE_RC_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_TABLE_OFFSET                 ,MSI-X Table Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_BIR                            ,MSI-X Table Bar Indicator Register Field For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x10B8++0x3
line.long 0x00 "PCIE_RC_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " PCI_MSIX_PBA_OFFSET                   ,MSI-X PBA Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky"
bitfld.long 0x00 0.--2. "  PCI_MSIX_PBA                            ,MSI-X PBA BIR For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
rgroup.long 0x1100++0x3
line.long 0x00 "PCIE_RC_AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " CAP_ID                                ,AER Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
hgroup.long 0x1104++0x3
hide.long 0x00 "PCIE_RC_UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1108++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_MASK               ,TLP Prefix Blocked Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_MASK        ,AtomicOp Egress Block Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_MASK                     ,Uncorrectable Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_MASK                ,Unsupported Request Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_MASK                         ,ECRC Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_MASK                       ,Malformed TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_MASK                 ,Receiver Overflow Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_MASK                    ,Unexpected Completion Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_MASK                  ,Completer Abort Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_MASK                  ,Completion Timeout Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_MASK                  ,Flow Control Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_MASK                       ,Poisoned TLP Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_MASK                  ,Surprise Down Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_MASK                  ,Data Link Protocol Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110C++0x3
line.long 0x00 "PCIE_RC_UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "        TLP_PRFX_BLOCKED_ERR_SEVERITY           ,TLP Prefix Blocked Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: Not supported Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY    ,AtomicOp Egress Blocked Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INTERNAL_ERR_SEVERITY                 ,Uncorrectable Internal Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         UNSUPPORTED_REQ_ERR_SEVERITY            ,Unsupported Request Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " ECRC_ERR_SEVERITY                     ,ECRC Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 18. "         MALF_TLP_ERR_SEVERITY                   ,Malformed TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " REC_OVERFLOW_ERR_SEVERITY             ,Receiver Overflow Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         UNEXP_CMPLT_ERR_SEVERITY                ,Unexpected Completion Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " CMPLT_ABORT_ERR_SEVERITY              ,Completer Abort Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         CMPLT_TIMEOUT_ERR_SEVERITY              ,Completion Timeout Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " FC_PROTOCOL_ERR_SEVERITY              ,Flow Control Protocol Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 12. "         POIS_TLP_ERR_SEVERITY                   ,Poisoned TLP Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6.--11. " RSVDP_6                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5. "        SURPRISE_DOWN_ERR_SVRITY                ,Surprise Down Error Severity [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REGPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " DL_PROTOCOL_ERR_SEVERITY              ,Data Link Protocol Error Severity For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         RSVDP_0                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1110++0x3
hide.long 0x00 "PCIE_RC_CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
group.long 0x1114++0x3
line.long 0x00 "PCIE_RC_CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 15. "      HEADER_LOG_OVERFLOW_MASK                ,Header Log Overflow Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14. " CORRECTED_INT_ERR_MASK                ,Corrected Internal Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 13. "         ADVISORY_NON_FATAL_ERR_MASK             ,Advisory Non-Fatal Error Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RPL_TIMER_TIMEOUT_MASK                ,Replay Timer Timeout Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 9.--11. "         RSVDP_9                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8. " REPLAY_NO_ROLEOVER_MASK               ,REPLAY_NUM Rollover Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 7. "         BAD_DLLP_MASK                           ,Bad DLLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " BAD_TLP_MASK                          ,Bad TLP Mask For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 1.--5. "         RSVDP_1                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 0. " RX_ERR_MASK                           ,Receiver Error Mask [Optional] For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
group.long 0x1118++0x3
line.long 0x00 "PCIE_RC_ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10. "    MULTIPLE_HEADER_EN                      ,Multiple Header Recording Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " MULTIPLE_HEADER_CAP                   ,Multiple Header Recording Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         ECRC_CHECK_EN                           ,ECRC Check Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " ECRC_CHECK_CAP                        ,ECRC Check Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 6. "         ECRC_GEN_EN                             ,ECRC Generation Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5. " ECRC_GEN_CAP                          ,ECRC Generation Capable For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--4. "         FIRST_ERR_POINTER                       ,First Error Pointer For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x111C++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FIRST_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FIRST_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FIRST_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FIRST_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of First 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1120++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " SECOND_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        SECOND_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " SECOND_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        SECOND_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Second 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1124++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " THIRD_DWORD_FOURTH_BYTE               ,Byte 3 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        THIRD_DWORD_THIRD_BYTE                  ,Byte 2 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " THIRD_DWORD_SECOND_BYTE               ,Byte 1 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        THIRD_DWORD_FIRST_BYTE                  ,Byte 0 of Header log register of Third 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1128++0x3
line.long 0x00 "PCIE_RC_HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " FOURTH_DWORD_FOURTH_BYTE              ,Byte 3 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        FOURTH_DWORD_THIRD_BYTE                 ,Byte 2 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " FOURTH_DWORD_SECOND_BYTE              ,Byte 1 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        FOURTH_DWORD_FIRST_BYTE                 ,Byte 0 of Header log register of Fourth 32 bit Data Word For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
group.long 0x112C++0x3
line.long 0x00 "PCIE_RC_ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 3.--31. 1. " RSVDP_3                               ,Reserved for future use"
bitfld.long 0x00 2. "  FATAL_ERR_REPORTING_EN                  ,Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " NON_FATAL_ERR_REPORTING_EN            ,Non-Fatal Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 0. "         CORR_ERR_REPORTING_EN                   ,Correctable Error Reporting Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hgroup.long 0x1130++0x3
hide.long 0x00 "PCIE_RC_ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x1134++0x3
line.long 0x00 "PCIE_RC_ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " ERR_FATAL_NON_FATAL_SOURCE_ID         ,Source of Fatal/Non-Fatal Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      ERR_COR_SOURCE_ID                       ,Source of Correctable Error For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1138++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_1_FOURTH_BYTE         ,Byte 3 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_1_THIRD_BYTE            ,Byte 2 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_1_SECOND_BYTE         ,Byte 1 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_1_FIRST_BYTE            ,Byte 0 of Error TLP Prefix Log 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x113C++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_2_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_2_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_2_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_2_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 2 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1140++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_3_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_3_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_3_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_3_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 3 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1144++0x3
line.long 0x00 "PCIE_RC_TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " CFG_TLP_PFX_LOG_4_FOURTH_BYTE         ,Byte 3 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 16.--23. 1. "        CFG_TLP_PFX_LOG_4_THIRD_BYTE            ,Byte 2 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " CFG_TLP_PFX_LOG_4_SECOND_BYTE         ,Byte 1 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        CFG_TLP_PFX_LOG_4_FIRST_BYTE            ,Byte 0 Error TLP Prefix Log 4 For a description of this standard PCIe register field, see the PCI Express Specification Note: This register field is sticky"
rgroup.long 0x1148++0x3
line.long 0x00 "PCIE_RC_VC_BASE,VC Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " VC_NEXT_OFFSET                        ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      VC_CAP_VERSION                          ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " VC_PCIE_EXTENDED_CAP_ID               ,VC Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x114C++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_1,Port VC Capability Register 1. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
bitfld.long 0x00 10.--11. "    VC_PORT_ARBI_TBL_ENTRY_SIZE             ,Port Arbitration Table Entry Size For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 8.--9. " VC_REFERENCE_CLOCK                    ,Reference Clock For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
bitfld.long 0x00 7. "         RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " VC_LOW_PRI_EXT_VC_CNT                 ,Low Priority Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "         RSVDP_3                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--2. " VC_EXT_VC_CNT                         ,Extended VC Count For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
rgroup.long 0x1150++0x3
line.long 0x00 "PCIE_RC_VC_CAPABILITIES_REG_2,Port VC Capability Register 2. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_ARBI_TABLE_OFFSET                  ,VC Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.tbyte 0x00 4.--23. 1. "        RSVDP_4                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0.--3. " VC_ARBI_CAP                           ,VC Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W else R Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1154++0x3
line.long 0x00 "PCIE_RC_VC_STATUS_CONTROL_REG,Port VC Control and Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 17.--31. 1. " RSVDP_17                              ,Reserved for future use"
bitfld.long 0x00 16. "      VC_ARBI_TABLE_STATUS                    ,VC Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.word 0x00 4.--15. 1. " RSVDP_4                               ,Reserved for future use"
bitfld.long 0x00 1.--3. "      VC_ARBI_SELECT                          ,VC Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 0. " VC_LOAD_VC_ARBI_TABLE                 ,Requests Hardware to Load VC Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1158++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC0,VC Resource Capability Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC0                ,Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC0                  ,Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC0               ,Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC0                    ,Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x115C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC0,VC Resource Control Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC0                         ,VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC                              ,VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--23. "         RSVDP_18                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 17. " VC_PORT_ARBI_SELECT_VC0               ,Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC0             ,Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC0_BIT1                      ,Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC0                         ,Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1160++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC0,VC Resource Status Register (0). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC0                     ,VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC0         ,Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1164++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC1,VC Resource Capability Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC1                ,VC1 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC1                  ,VC1 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC1               ,VC1 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC1                    ,VC1 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1168++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC1,VC Resource Control Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC1                         ,VC1 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC1                             ,VC1 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC1               ,VC1 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC1             ,VC1 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC1_BIT1                      ,VC1 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC1                         ,VC1 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x116C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC1,VC Resource Status Register (1). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC1                     ,VC1 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC1         ,VC1 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1170++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC2,VC Resource Capability Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC2                ,VC2 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC2                  ,VC2 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC2               ,VC2 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC2                    ,VC2 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1174++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC2,VC Resource Control Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC2                         ,VC2 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC2                             ,VC2 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC2               ,VC2 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC2             ,VC2 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC2_BIT1                      ,VC2 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC2                         ,VC2 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1178++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC2,VC Resource Status Register (2). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC2                     ,VC2 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC2         ,VC2 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x117C++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CAP_REG_VC3,VC Resource Capability Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " VC_PORT_ARBI_TABLE_VC3                ,VC3 Port Arbitration Table Offset For a description of this standard PCIe register field, see the PCI Express Specification"
bitfld.long 0x00 22.--23. "        RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " VC_MAX_TIME_SLOT_VC3                  ,VC3 Maximum Time Slots-1 supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. "        VC_REJECT_SNOOP_TRANS_VC3               ,VC3 Reject Snoop Transactions For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--14. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 0.--7. 1. "        VC_PORT_ARBI_CAP_VC3                    ,VC3 Port Arbitration Capability For a description of this standard PCIe register field, see the PCI Express Specification"
group.long 0x1180++0x3
line.long 0x00 "PCIE_RC_RESOURCE_CON_REG_VC3,VC Resource Control Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " VC_ENABLE_VC3                         ,VC3 VC Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " VC_ID_VC3                             ,VC3 VC ID For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "         RSVDP_20                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 17.--19. " VC_PORT_ARBI_SELECT_VC3               ,VC3 Port Arbitration Select For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "         VC_LOAD_PORT_ARBI_TABLE_VC3             ,VC3 Load Port Arbitration Table For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " RSVDP_8                               ,Reserved for future use"
hexmask.long.byte 0x00 1.--7. 1. "        VC_TC_MAP_VC3_BIT1                      ,VC3 Bits 7:1 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification"
textline "                                                              "
bitfld.long 0x00 0. " VC_TC_MAP_VC3                         ,VC3 Bit 0 of TC to VC Mapping For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
rgroup.long 0x1184++0x3
line.long 0x00 "PCIE_RC_RESOURCE_STATUS_REG_VC3,VC Resource Status Register (3). For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 18.--31. 1. " RSVDP_18                              ,Reserved for future use"
bitfld.long 0x00 17. "      VC_NEGO_PENDING_VC3                     ,VC3 VC Negotiation Pending For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " VC_PORT_ARBI_TABLE_STATUS_VC3         ,VC3 Port Arbitration Table Status For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
hexmask.long.word 0x00 0.--15. 1. "         RSVDP_0                                 ,Reserved for future use"
rgroup.long 0x1198++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,Secondary PCI Express Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x119C++0x3
line.long 0x00 "PCIE_RC_LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  EQ_REQ_INT_EN                           ,Link Equalization Request Interrupt Enable For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PERFORM_EQ                            ,Perform Equalization For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
hgroup.long 0x11A0++0x3
hide.long 0x00 "PCIE_RC_LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register, see the PCI Express Specification."
in
textline "                                                              "
rgroup.long 0x11A4++0x3
line.long 0x00 "PCIE_RC_SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 28.--30. "         USP_RX_PRESET_HINT1                     ,Upstream Port 80 GT/s Receiver Preset Hint 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 24.--27. " USP_TX_PRESET1                        ,Upstream Port 80 GT/s Transmitter Preset 1 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "        RSVDP_23                                ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 20.--22. " DSP_RX_PRESET_HINT1                   ,Downstream Port 80 GT/s Receiver Preset Hint 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "         DSP_TX_PRESET1                          ,Downstream Port 80 GT/s Transmitter Preset 1 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 15. " RSVDP_15                              ,Reserved for future use" "0,1"
bitfld.long 0x00 12.--14. "         USP_RX_PRESET_HINT0                     ,Upstream Port 80 GT/s Receiver Preset Hint 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--11. " USP_TX_PRESET0                        ,Upstream Port 80 GT/s Transmitter Preset 0 The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "        RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 4.--6. " DSP_RX_PRESET_HINT0                   ,Downstream Port 80 GT/s Receiver Preset Hint 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "         DSP_TX_PRESET0                          ,Downstream Port 80 GT/s Transmitter Preset 0 For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x11A8++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " NEXT_OFFSET                           ,Next Capability Offset For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      CAP_VERSION                             ,Capability Version For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID                       ,L1SUB Extended Capability ID For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
group.long 0x11AC++0x3
line.long 0x00 "PCIE_RC_L1SUB_CAPABILITY_REG,L1 Substates Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.byte 0x00 24.--31. 1. " RSVDP_24                              ,Reserved for future use"
bitfld.long 0x00 19.--23. "        PWR_ON_VALUE_SUPPORT                    ,Port T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 18. " RSVDP_18                              ,Reserved for future use" "0,1"
bitfld.long 0x00 16.--17. "         PWR_ON_SCALE_SUPPORT                    ,Port T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1,2,3"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " COMM_MODE_SUPPORT                     ,Port Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
bitfld.long 0x00 5.--7. "        RSVDP_5                                 ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 4. " L1_PMSUB_SUPPORT                      ,L1 PM Substates ECN Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 3. "         L1_1_ASPM_SUPPORT                       ,ASPM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_SUPPORT                     ,ASPM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_SUPPORT                      ,PCI-PM L11 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_SUPPORT                    ,PCI-PM L12 Supported For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
group.long 0x11B0++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. For a description of this standard PCIe register, see the PCI Express Specification."
bitfld.long 0x00 29.--31. " L1_2_TH_SCA                           ,LTR L12 Threshold Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "         RSVDP_26                                ,Reserved for future use" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 16.--25. 1. " L1_2_TH_VAL                           ,LTR L12 Threshold Value For a description of this standard PCIe register field, see the PCI Express Specification"
hexmask.long.byte 0x00 8.--15. 1. "      T_COMMON_MODE                           ,Common Mode Restore Time For a description of this standard PCIe register field, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: R/W"
textline "                                                              "
bitfld.long 0x00 4.--7. " RSVDP_4                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "        L1_1_ASPM_EN                            ,ASPM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " L1_2_ASPM_EN                          ,ASPM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
bitfld.long 0x00 1. "         L1_1_PCIPM_EN                           ,PCI-PM L11 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " L1_2_PCIPM_EN                         ,PCI-PM L12 Enable For a description of this standard PCIe register field, see the PCI Express Specification" "0,1"
group.long 0x11B4++0x3
line.long 0x00 "PCIE_RC_L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 3.--7. "    T_POWER_ON_VALUE                        ,T Power On Value For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 0.--1. "         T_POWER_ON_SCALE                        ,T Power On Scale For a description of this standard PCIe register field, see the PCI Express Specification" "0,1,2,3"
rgroup.long 0x11B8++0x3
line.long 0x00 "PCIE_RC_PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 20.--31. 1. " PTM_NEXT_OFFSET                       ,Precision Time Measurement PCI Express Extended Capability Next Offset For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_CAP_VERSION                         ,Precision Time Measurement PCI Express Extended Capability Version For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_CAP_ID                            ,Precision Time Measurement PCI Express Extended Capability ID For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11BC++0x3
line.long 0x00 "PCIE_RC_PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      PTM_CLK_GRAN                            ,PTM Local Clock Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky]"
textline "                                                              "
bitfld.long 0x00 3.--7. " RSVDP_3                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "        PTM_ROOT_CAPABLE                        ,PTM Root Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 1. " PTM_RES_CAPABLE                       ,PTM Responder Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 0. "         PTM_REQ_CAPABLE                         ,PTM Requester Capable For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
group.long 0x11C0++0x3
line.long 0x00 "PCIE_RC_PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register, see the PCI Express Specification."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      EFF_GRAN                                ,PTM Effective Granularity For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT"
textline "                                                              "
bitfld.long 0x00 2.--7. " RSVDP_2                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        ROOT_SELECT                             ,PTM Root Select When set this Time Source is the PTM Root For a description of this standard PCIe register, see the PCI Express Specification Note: The access attributes of this field are as follows: - Dbi: HWINIT" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_ENABLE                            ,PTM Enable When set, this function is permitted to participate in the PTM mechanism For a description of this standard PCIe register, see the PCI Express Specification" "0,1"
rgroup.long 0x11C4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC)."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_EXT_CAP_NEXT_OFFS             ,Precision Time Measurement Responder VSEC Next Pointer Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_EXT_CAP_VER                     ,Precision Time Measurement Responder VSEC Version Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_EXT_CAP_ID                    ,Precision Time Measurement Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11C8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. ."
hexmask.long.word 0x00 20.--31. 1. " PTM_RES_VSEC_LENGTH                   ,PTM Responder VSEC Length Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
bitfld.long 0x00 16.--19. "      PTM_RES_VSEC_REV                        ,PTM Responder VSEC Revision Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
hexmask.long.word 0x00 0.--15. 1. " PTM_RES_VSEC_ID                       ,PTM Responder VSEC ID Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11CC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_CONTROL_OFF,PTM Responder Control Register. ."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  PTM_RES_CCONTEXT_VALID                  ,PTM Responder Control Context Valid - PTM Local Timing is valid This bit is set over the DBI A speed change or aux_clk_active will set this bit low Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x11D0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_STATUS_OFF,PTM Responder Status Register. ."
hexmask.long 0x00 2.--31. 1. " RSVDP_2                               ,Reserved for future use"
bitfld.long 0x00 1. "  PTM_RES_REQUEST_RECEIVED                ,PTM 1st Request Received - PTM Responder has received the first PTM Request Message Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder, if the context is valid If the context is invalid a Response message will be sent instead Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " PTM_RES_CONTEXT_VALID                 ,PTM Responder Status Context Valid - PTM Local Timing Context is Valid Value set from upstream port Requester in a Switch Shadows the same in the control register in all other products Note: This register field is sticky" "0,1"
rgroup.long 0x11D4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_LSB                     ,PTM Responder Local Clock LSB - Lower 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11D8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_LOCAL_MSB                     ,PTM Responder Local Clock MSB - Upper 32 bits of local timer value Note: The access attributes of this field are as follows: - Dbi: if [DBI_RO_WR_EN == 1] then R/W[sticky] else R[sticky] Note: This register field is sticky"
rgroup.long 0x11DC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_LSB                        ,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2_MSB                        ,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_LSB                       ,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11E8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T2P_MSB                       ,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11EC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_LSB                        ,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F0++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3_MSB                        ,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F4++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_LSB                       ,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
rgroup.long 0x11F8++0x3
line.long 0x00 "PCIE_RC_PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. ."
hexmask.long 0x00 0.--31. 1. " PTM_RES_T3P_MSB                       ,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value Note: This register field is sticky"
group.long 0x11FC++0x3
line.long 0x00 "PCIE_RC_PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_TX_LATENCY                      ,PTM Responder TX Latency - Responder Transmit path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1200++0x3
line.long 0x00 "PCIE_RC_PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. ."
hexmask.long.tbyte 0x00 12.--31. 1. " RSVDP_12                              ,Reserved for future use"
hexmask.long.word 0x00 0.--11. 1. "    PTM_RES_RX_LATENCY                      ,PTM Responder RX Latency - Responder Receive path latency [12 bit wide] Note: This register field is sticky"
group.long 0x1700++0x3
line.long 0x00 "PCIE_RC_ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register."
hexmask.long.word 0x00 16.--31. 1. " REPLAY_TIME_LIMIT                     ,Replay Timer Limit The replay timer expires when it reaches this limit The controller initiates a replay upon reception of a NAK or when the replay timer expires You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 30 specification If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
hexmask.long.word 0x00 0.--15. 1. "      ROUND_TRIP_LATENCY_TIME_LIMIT           ,Ack Latency Timer Limit The Ack latency timer expires when it reaches this limit You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of thePCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 30 specification The limit must reflect the round trip latency from requester to completer If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value It will not change the value in the TIMER_MOD_ACK_NAK field of the PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF register"
group.long 0x1704++0x3
line.long 0x00 "PCIE_RC_VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register."
hexmask.long 0x00 0.--31. 1. " VENDOR_SPEC_DLLP                      ,Vendor Specific DLLP Register Used to send a specific PCI Express DLLP Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of"
hgroup.long 0x1708++0x3
hide.long 0x00 "PCIE_RC_PORT_FORCE_OFF,Port Force Link Register."
in
textline "                                                              "
group.long 0x170C++0x3
line.long 0x00 "PCIE_RC_ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 30. "         ENTER_ASPM                              ,ASPM L1 Entry Control - 1: Core enters ASPM L1 after a period in which it has been idle - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27.--29. " L1_ENTRANCE_LATENCY                   ,L1 Entrance Latency Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "         L0S_ENTRANCE_LATENCY                    ,L0s Entrance Latency Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 16.--23. 1. " COMMON_CLK_N_FTS                      ,Common Clock N_FTS This is the N_FTS when common clock is used The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 This field is only writable [sticky] when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 8.--15. 1. "        ACK_N_FTS                               ,N_FTS The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0 The maximum number of FTS ordered-sets that a component can request is 255 The controller does not support a value of zero a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " ACK_FREQ                              ,Ack Frequency The controller accumulates the number of pending ACKs specified here [up to 255] before sending an ACK DLLP - 0: Indicates that this Ack frequency control feature is turned off The controller schedules a low-priority ACK DLLP for every TLP that it receives - 1- 255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs It might schedule the ACK before receiving this number of TLPs, but never later For a typical system, you do not have to modify the default setting Note: This register field is sticky"
hgroup.long 0x1710++0x3
hide.long 0x00 "PCIE_RC_PORT_LINK_CTRL_OFF,Port Link Control Register."
in
textline "                                                              "
group.long 0x1714++0x3
line.long 0x00 "PCIE_RC_LANE_SKEW_OFF,Lane Skew Register."
bitfld.long 0x00 31. " DISABLE_LANE_TO_LANE_DESKEW           ,Disable Lane-to-Lane Deskew Causes the controller to disable the internal Lane-to-Lane deskew logic Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         IMPLEMENT_NUM_LANES                     ,Implementation-specific Number of Lanes Set the implementation-specific number of lanes Allowed values are: - 4'b 0000: 1 lane - 4'b 0001: 2 lanes - 4'b 0011: 4 lanes - 4'b 0111: 8 lanes - 4'b 1111: 16 lanes The number of lanes to be used when in Loopback Master The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field The controller will transition from LoopbackEntry to LoopbackActive after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 26. " LANE_SKEW_OFF_26                      ,Reserved Read/Write regsiter for future use Note: This register field is sticky" "0,1"
bitfld.long 0x00 25. "         ACK_NAK_DISABLE                         ,Ack/Nak Disable Prevents the controller from sending ACK and NAK DLLPs Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 24. " FLOW_CTRL_DISABLE                     ,Flow Control Disable Prevents the controller from sending FC DLLPs Note: This register field is sticky" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. "         INSERT_LANE_SKEW                        ,Insert Lane Skew for Transmit [not supported for x16] Optional feature that causes the controller to insert skew between Lanes for test purposes There are three bits per Lane The value is in units of one symbol time For example, the value 010b for a Lane forces a skew of two symbol times for that Lane The maximum skew value for any Lane is 5 symbol times Note: This register field is sticky"
group.long 0x1718++0x3
line.long 0x00 "PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register."
bitfld.long 0x00 31. " RSVDP_31                              ,Reserved for future use" "0,1"
bitfld.long 0x00 29.--30. "         FAST_LINK_SCALING_FACTOR                ,Fast Link Timer Scaling Factor Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field inPCIE_RC_PORT_LINK_CTRL_OFF is set to '1' - 0: Scaling Factor is 1024 [1ms is 1us] - 1: Scaling Factor is 256 [1ms is 4us] - 2: Scaling Factor is 64 [1ms is 16us] - 3: Scaling Factor is 16 [1ms is 64us] Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0' Not used for M-PCIe Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--28. " UPDATE_FREQ_TIMER                     ,UPDATE_FREQ_TIMER is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19.--23. "        TIMER_MOD_ACK_NAK                       ,Ack Latency Timer Modifier Increases the timer value for the Ack latency timer in increments of 64 clock cycles A value of '0' represents no modification to the timer value For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                                              "
bitfld.long 0x00 14.--18. " TIMER_MOD_REPLAY_TIMER                ,Replay Timer Limit Modifier Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed A value of '0' represents no modification to the timer limit For more details, see the REPLAY_TIME_LIMIT field of the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--13. "        RSVDP_8                                 ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MAX_FUNC_NUM                          ,Maximum function number that can be used in a request Configuration requests targeted at function numbers above this value are returned with UR [unsupported request] Note: This register field is sticky"
group.long 0x171C++0x3
line.long 0x00 "PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long.word 0x00 16.--31. 1. " MASK_RADM_1                           ,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD 0: For RADM RC filter to not allow CFG transaction being received 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD 0: For RADM RC filter to not allow IO transaction being received 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP 0: Drop MSG TLP [except for Vendor MSG]. Send decoded message on the SII. 1: Do not Drop MSG [except for Vendor MSG]. Send message TLPs to your application on TRGT1 and send decoded message on the SII. The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG = 1, then the default of this bit is '0' [drop message TLPs]. This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 [or AXI bridge master], as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. 0: Discard completions with ECRC errors 1: Allow completions with ECRC errors to be passed up Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD 0: Discard TLPs with ECRC errors 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH 0: Enforce Req Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca 1: Mask Req Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_c? 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR 0: Treat locked Read TLPs as UR for EP; Supported for RC 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR 0: Treat CFG type1 TLPs as UR for EP; Supported for RC 1: Treat CFG type1 TLPs as Supported for EP; UR for RC When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests, if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR 0: Treat out-of-bar TLPs as UR 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS 0: Treat poisoned request TLPs as UR 1: Do not treat poisoned request TLPs as UR The native controller always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH 0: Treat Function MisMatched TLPs as UR 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky."
bitfld.long 0x00 15. "      DISABLE_FC_WD_TIMER                     ,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1"
textline "                                                              "
bitfld.long 0x00 11.--14. " EIDLE_TIMER                           ,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "        SKP_INT_VAL                             ,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register [in a 250 MHz controller], then the controller actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 [because one clock tick = two symbol times in this case]. Note: This value is not used at Gen3 speed. The skip interval is hardcoded to 370 blocks For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows: 2K_PPM_DISABLED = 1: 1280/CX_NB 2K_PPM_DISABLED = 0: 228/CX_NB You need to set this field again, if necessary, when 2K_PPM_DISABLED is changed. Note: This register field is sticky."
group.long 0x1720++0x3
line.long 0x00 "PCIE_RC_FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
hexmask.long 0x00 0.--31. 1. " MASK_RADM_2                           ,Filter Mask 2. This field modifies the RADM filtering and error handling rules. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule."
group.long 0x1724++0x3
line.long 0x00 "PCIE_RC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  OB_RD_SPLIT_BURST_EN                    ,Enable AMBA Multiple Outbound Decomposed NP SubRequests This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device [or switch] is reordering completions that have different tags Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
rgroup.long 0x1728++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG0_OFF,Debug Register 0"
hexmask.long 0x00 0.--31. 1. " DEB_REG_0                             ,The value on cxpl_debug_info[31:0]"
rgroup.long 0x172C++0x3
line.long 0x00 "PCIE_RC_PL_DEBUG1_OFF,Debug Register 1"
hexmask.long 0x00 0.--31. 1. " DEB_REG_1                             ,The value on cxpl_debug_info[63:32]"
rgroup.long 0x1730++0x3
line.long 0x00 "PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_P_HEADER_FC_CREDIT                   ,Transmit Posted Header FC Credits The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_P_DATA_FC_CREDIT                   ,Transmit Posted Data FC Credits The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1734++0x3
line.long 0x00 "PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_NP_HEADER_FC_CREDIT                  ,Transmit Non-Posted Header FC Credits The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_NP_DATA_FC_CREDIT                  ,Transmit Non-Posted Data FC Credits The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
rgroup.long 0x1738++0x3
line.long 0x00 "PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status"
hexmask.long.word 0x00 20.--31. 1. " RSVDP_20                              ,Reserved for future use"
hexmask.long.byte 0x00 12.--19. 1. "      TX_CPL_HEADER_FC_CREDIT                 ,Transmit Completion Header FC Credits The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " TX_CPL_DATA_FC_CREDIT                 ,Transmit Completion Data FC Credits The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts] When the number of advertised completion credits [both header and data] are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]"
hgroup.long 0x173C++0x3
hide.long 0x00 "PCIE_RC_QUEUE_STATUS_OFF,Queue Status"
in
textline "                                                              "
rgroup.long 0x1740++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_3                       ,WRR Weight for VC3 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_2                         ,WRR Weight for VC2 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_1                       ,WRR Weight for VC1 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_0                         ,WRR Weight for VC0 Note: The access attributes of this field are as follows: - Dbi: R"
rgroup.long 0x1744++0x3
line.long 0x00 "PCIE_RC_VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2"
hexmask.long.byte 0x00 24.--31. 1. " WRR_WEIGHT_VC_7                       ,WRR Weight for VC7 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 16.--23. 1. "        WRR_WEIGHT_VC_6                         ,WRR Weight for VC6 Note: The access attributes of this field are as follows: - Dbi: R"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " WRR_WEIGHT_VC_5                       ,WRR Weight for VC5 Note: The access attributes of this field are as follows: - Dbi: R"
hexmask.long.byte 0x00 0.--7. 1. "        WRR_WEIGHT_VC_4                         ,WRR Weight for VC4 Note: The access attributes of this field are as follows: - Dbi: R"
group.long 0x1748++0x3
line.long 0x00 "PCIE_RC_VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control."
bitfld.long 0x00 31. " VC_ORDERING_RX_Q                      ,VC Ordering for Receive Queues Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         TLP_TYPE_ORDERING_VC0                   ,TLP Type Ordering for VC0 Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 26.--27. " VC0_P_DATA_SCALE                      ,VC0 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_P_HDR_SCALE                         ,VC0 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_P_TLP_Q_MODE                      ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_P_HEADER_CREDIT                     ,VC0 Posted Header Credits The number of initial posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_P_DATA_CREDIT                     ,VC0 Posted Data Credits The number of initial posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x174C++0x3
line.long 0x00 "PCIE_RC_VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_NP_DATA_SCALE                     ,VC0 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_NP_HDR_SCALE                        ,VC0 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_NP_HEADER_CREDIT                    ,VC0 Non-Posted Header Credits The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_NP_DATA_CREDIT                    ,VC0 Non-Posted Data Credits The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1750++0x3
line.long 0x00 "PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC0_CPL_DATA_SCALE                    ,VC0 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC0_CPL_HDR_SCALE                       ,VC0 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC0_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC0_CPL_HEADER_CREDIT                   ,VC0 Completion Header Credits The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC0_CPL_DATA_CREDIT                   ,VC0 Completion Data Credits The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1754++0x3
line.long 0x00 "PCIE_RC_VC1_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC1                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC1_P_DATA_SCALE                        ,VC1 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC1_P_HDR_SCALE                       ,VC1 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC1_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC1_P_HEADER_CREDIT                   ,VC1 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC1_P_DATA_CREDIT                       ,VC1 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1758++0x3
line.long 0x00 "PCIE_RC_VC1_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_NP_DATA_SCALE                     ,VC1 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_NP_HDR_SCALE                        ,VC1 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x175C++0x3
line.long 0x00 "PCIE_RC_VC1_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC1_CPL_DATA_SCALE                    ,VC1 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC1_CPL_HDR_SCALE                       ,VC1 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC1_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC1_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC1_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1760++0x3
line.long 0x00 "PCIE_RC_VC2_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC2                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC2_P_DATA_SCALE                        ,VC2 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC2_P_HDR_SCALE                       ,VC2 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC2_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC2_P_HEADER_CREDIT                   ,VC2 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC2_P_DATA_CREDIT                       ,VC2 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1764++0x3
line.long 0x00 "PCIE_RC_VC2_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_NP_DATA_SCALE                     ,VC2 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_NP_HDR_SCALE                        ,VC2 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1768++0x3
line.long 0x00 "PCIE_RC_VC2_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC2_CPL_DATA_SCALE                    ,VC2 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC2_CPL_HDR_SCALE                       ,VC2 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC2_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC2_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC2_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x176C++0x3
line.long 0x00 "PCIE_RC_VC3_P_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Posted Receive Queue Control."
bitfld.long 0x00 30. " TLP_TYPE_ORDERING_VC3                 ,TLP Type Ordering for VC#i Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules [recommended] - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky" "0,1"
bitfld.long 0x00 26.--27. "         VC3_P_DATA_SCALE                        ,VC3 Scale Posted Data Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 24.--25. " VC3_P_HDR_SCALE                       ,VC3 Scale Posted Header Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 21.--23. "         VC3_P_TLP_Q_MODE                        ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 12.--19. 1. " VC3_P_HEADER_CREDIT                   ,VC3 Posted Header Credits The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
hexmask.long.word 0x00 0.--11. 1. "        VC3_P_DATA_CREDIT                       ,VC3 Posted Data Credits The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1770++0x3
line.long 0x00 "PCIE_RC_VC3_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Non-Posted Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_NP_DATA_SCALE                     ,VC3 Scale Non-Posted Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_NP_HDR_SCALE                        ,VC3 Scale Non-Posted Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_NP_TLP_Q_MODE                     ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_NP_HEADER_CREDIT                    ,VC#i Non-Posted Header Credits The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_NP_DATA_CREDIT                    ,VC#i Non-Posted Data Credits The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x1774++0x3
line.long 0x00 "PCIE_RC_VC3_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC#i Completion Receive Queue Control."
bitfld.long 0x00 26.--27. " VC3_CPL_DATA_SCALE                    ,VC3 Scale CPL Data Credites Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 24.--25. "         VC3_CPL_HDR_SCALE                       ,VC3 Scale CPL Header Credites Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 21.--23. " VC3_CPL_TLP_Q_MODE                    ,Reserved Note: This register field is sticky" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 12.--19. 1. "         VC3_CPL_HEADER_CREDIT                   ,VC#i Completion Header Credits The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
textline "                                                              "
hexmask.long.word 0x00 0.--11. 1. " VC3_CPL_DATA_CREDIT                   ,VC#i Completion Data Credits The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration Note: The access attributes of this field are as follows: - Dbi: R [sticky] Note: This register field is sticky"
group.long 0x180C++0x3
line.long 0x00 "PCIE_RC_GEN2_CTRL_OFF,Link Width and Speed Change Control Register."
hexmask.long.word 0x00 22.--31. 1. " RSVDP_22                              ,Reserved for future use"
bitfld.long 0x00 21. "      GEN1_EI_INFERENCE                       ,Electrical Idle Inference Mode at Gen1 Rate Programmable mode to determine inferred electrical idle [EI] in RecoverySpeed or LoopbackActive [as slave] state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking for a '0' on RxValid If the PHY fails to deassert the RxValid signal in RecoverySpeed or LoopbackActive [because of corrupted EIOS for example], then EI cannot be inferred successfully in the controller by just detecting the condition RxValid= 0 - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 20. " SEL_DEEMPHASIS                        ,Used to set the de-emphasis level for upstream ports This bit selects the level of de-emphasis the link operates at - 0: -6 dB - 1: -35 dB This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 19. "         CONFIG_TX_COMP_RX                       ,Config Tx Compliance Receive Bit When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert [equal to '1'] This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 18. " CONFIG_PHY_TX_CHANGE                  ,Config PHY Tx Swing Controls the PHY transmitter voltage swing level The controller drives the mac_phy_txswing output from this register bit field - 0: Full Swing - 1: Low Swing This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 17. "         DIRECT_SPEED_CHANGE                     ,Directed Speed Change Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed When the speed change occurs, the controller will clear the contents of this field and a read to this field by your software will return a '0' To manually initiate the speed change: - Write to PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to '1', then the speed change is initiated automatically after link up, and the controller clears the contents of this field If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register [LINK_CONTROL2_LINK_STATUS2_OFF PCIE_CAP_TARGET_LINK_SPEED] through the DBI before link up This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " AUTO_LANE_FLIP_CTRL_EN                ,Enable Auto flipping of the lanes You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 13.--15. "         PRE_DET_LANE                            ,Predetermined Lane for Auto Flip This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect Allowed values are: - 3'b 000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/ 2-1 or CX_NL/ 4-1 or CX_NL/ 8-1, depending on which lane is detected - 3'b 001: Connect logical Lane0 to physical lane 1 - 3'b 010: Connect logical Lane0 to physical lane 3 - 3'b 011: Connect logical Lane0 to physical lane 7 - 3'b 100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state Note: This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
bitfld.long 0x00 8.--12. " NUM_OF_LANES                          ,Predetermined Number of Lanes Defines the number of lanes which are connected and not bad Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver Indicates the number of lanes to check for exit from Electrical Idle in PollingActive and L2Idle It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured This value is referred to as the 'Predetermined Number of Lanes' in section 42621 of the PCI Express Base 30 Specification, revision 10 Encoding is as follows: - 0x 01: 1 lane - 0x 02: 2 lanes - 0x 03: 3 lanes - When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes You must also change the value in the 'Link Mode Enable' field of PCIE_RC_PORT_LINK_CTRL_OFF The value in this register is normally the same as the encoded value in PCIE_RC_PORT_LINK_CTRL_OFF If you find that one of your used lanes is bad then you must reduce the value in this register This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "        FAST_TRAINING_SEQ                       ,Sets the Number of Fast Training Sequences [N_FTS] that the controller advertises as its N_FTS during Gen2 or Gen3 link training This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state Do not set N_FTS to zero doing so can cause the LTSSM to go into the recovery state when exiting from L0s This field is reserved [fixed to '0'] for M-PCIe Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky"
rgroup.long 0x1810++0x3
line.long 0x00 "PCIE_RC_PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins."
hexmask.long 0x00 0.--31. 1. " PHY_STATUS                            ,PHY Status Data received directly from the phy_cfg_status bus These is a GPIO register reflecting the values on the static phy_cfg_status input signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband status signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x1814++0x3
line.long 0x00 "PCIE_RC_PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins."
hexmask.long 0x00 0.--31. 1. " PHY_CONTROL                           ,PHY Control Data sent directly to the cfg_phy_control bus These is a GPIO register driving the values on the static cfg_phy_control output signals The usage is left completely to the user and does not in any way influence controller functionality You can use it for any static sideband control signalling requirements that you have for your PHY This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
group.long 0x181C++0x3
line.long 0x00 "PCIE_RC_TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register."
bitfld.long 0x00 16.--20. " TARGET_MAP_INDEX                      ,The number of the PF Function on which the Target Values are set This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "        TARGET_MAP_ROM                          ,Target Value for the ROM page of the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1"
textline "                                                              "
bitfld.long 0x00 0.--5. " TARGET_MAP_PF                         ,Target Values for each BAR on the PF Function selected by the index number This register does not respect the Byte Enable setting any write will affect all register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1820++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_ADDR                         ,Integrated MSI Reception Module Address System specified address for MSI memory write transaction termination Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register and also to see if it satisfies the definition of an MSI interrupt request When these conditions are satisfied the Memory Write request is marked as an MSI request Note: This register field is sticky"
group.long 0x1824++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_UPPER_ADDR                   ,Integrated MSI Reception Module Upper Address System specified upper address for MSI memory write transaction termination Allows functions to support a 64-bit MSI address Note: This register field is sticky"
group.long 0x1828++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x182C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_0_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1830++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1834++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1838++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_1_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x183C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1840++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1844++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_2_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1848++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x184C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1850++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_3_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1854++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1858++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x185C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_4_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1860++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1864++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1868++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_5_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x186C++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1870++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1874++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_6_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1878++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x187C++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_EN                     ,MSI Interrupt#i Enable Specifies which interrupts are enabled When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
group.long 0x1880++0x3
line.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register."
hexmask.long 0x00 0.--31. 1. " MSI_CTRL_INT_7_MASK                   ,MSI Interrupt#i Mask Allows enabled interrupts to be masked When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH Each bit corresponds to a single MSI Interrupt Vector Note: This register field is sticky"
hgroup.long 0x1884++0x3
hide.long 0x00 "PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register."
in
textline "                                                              "
group.long 0x1888++0x3
line.long 0x00 "PCIE_RC_MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register."
hexmask.long 0x00 0.--31. 1. " MSI_GPIO_REG                          ,MSI GPIO Register The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky"
group.long 0x188C++0x3
line.long 0x00 "PCIE_RC_CLOCK_GATING_CTRL_OFF,RADM clock gating enable control register. Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g output will always be set to '1'."
hexmask.long 0x00 1.--31. 1. " RSVDP_1                               ,Reserved for future use"
bitfld.long 0x00 0. "  RADM_CLK_GATING_EN                      ,Enable Radm clock gating feature - 0: Disable - 1: Enable[default]" "0,1"
group.long 0x1890++0x3
line.long 0x00 "PCIE_RC_GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The 'Directed Speed Change' field in the 'Link Width and Speed Change Control Register' is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the 'Directed Speed Change' field is set to '1' and (2) the 'Target Link Speed' field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 26.--31. " RSVDP_26                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. "        GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE        ,Eq InvalidRequest and RxEqEval Different Time Assertion Disable Disable the assertion of Eq InvalidRequest and RxEqEval at different time Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19.--20. " RSVDP_19                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 18. "         GEN3_DC_BALANCE_DISABLE                 ,DC Balance Disable Disable DC Balance feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 17. " GEN3_DLLP_XMT_DELAY_DISABLE           ,DLLP Transmission Delay Disable Disable delay transmission of DLLPs before equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         GEN3_EQUALIZATION_DISABLE               ,Equalization Disable Disable equalization feature Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 14.--15. " RSVDP_14                              ,Reserved for future use" "0,1,2,3"
bitfld.long 0x00 13. "         RXEQ_RGRDLESS_RXTS                      ,When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 12. " RXEQ_PH01_EN                          ,Rx Equalization Phase 0/Phase 1 Hold Enable When this bit is set the upstream port holds phase 0 [the downstream port holds phase 1] for 10ms Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY This bit is used during Virtex-7 Gen3 equalization The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/ 3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/ 1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
bitfld.long 0x00 11. "         EQ_REDO                                 ,Equalization Redo Disable Disable autonomous mechanism for requesting to redo the equalization process Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 10. " EQ_EIEOS_CNT                          ,Equalization EIEOS Count Reset Disable Disable requesting reset of EIEOS count during equalization Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         EQ_PHASE_2_3                            ,Equalization Phase 2 and Phase 3 Disable This applies to downstream ports only Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " DISABLE_SCRAMBLER_GEN_3               ,Disable Scrambler for Gen3 and Gen4 Data Rate The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller [for example within the PHY] Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate Note: This register field is sticky" "0,1"
hexmask.long.byte 0x00 1.--7. 1. "         RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " GEN3_ZRXDC_NONCOMPL                   ,Gen3 Receiver Impedance ZRX-DC Not Compliant Receivers that operate at 80 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 25 GT/s [40-60 Ohms] must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled - 0: The receiver complies with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher - 1: The receiver does not comply with the ZRX-DC parameter for 25 GT/s when operating at 8 GT/s or higher Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates Note: This register field is sticky" "0,1"
group.long 0x18A8++0x3
line.long 0x00 "PCIE_RC_GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist."
bitfld.long 0x00 27.--31. " RSVDP_27                              ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP ,Request controller to send back-to-back EIEOS in RecoveryRcvrLock state until presets to coefficients mapping is complete - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 25. " GEN3_EQ_PSET_REQ_AS_COEF              ,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field Do not use Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         GEN3_EQ_FOM_INC_INITIAL_EVAL            ,Include Initial FOM Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.word 0x00 8.--23. 1. " GEN3_EQ_PSET_REQ_VEC                  ,Preset Request Vector Requesting of Presets during the initial part of the EQ Master Phase Encoding scheme is as follows: Bit [15:0] =0x 0: No preset is requested and evaluated in EQ Master Phase Bit [i] = 1: 'Preset=i' is requested and evaluated in EQ Master Phase - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx 1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: You must ensure 24 ms timeout does not occur in presets requests in EQ master phase, ie, you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky"
bitfld.long 0x00 7. "      RSVDP_7                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " GEN3_LOWER_RATE_EQ_REDO_ENABLE        ,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature Note: This register field is sticky" "0,1"
bitfld.long 0x00 5. "         GEN3_EQ_EVAL_2MS_DISABLE                ,Phase2_3 2 ms Timeout Disable Determine behavior in Phase2 for USP [Phase3 if DSP] when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " GEN3_EQ_PHASE23_EXIT_MODE             ,Behavior After 24 ms Timeout [when optimal settings are not found] For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationPhase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the 'Link Status Register 2' For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: RecoverySpeed - 1: RecoveryEqualizationRcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the 'Link Status Register 2' when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the 'Link Status Register 2' Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode EQ requests for Figure Of Merit mode complete before 24 ms timeout Please see GEN3_EQ_PSET_REQ_VEC Register for more Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1"
bitfld.long 0x00 0.--3. "         GEN3_EQ_FB_MODE                         ,Feedback Mode - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - : Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18B4++0x3
line.long 0x00 "PCIE_RC_ORDER_RULE_CTRL_OFF,Order Rule Control Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
hexmask.long.byte 0x00 8.--15. 1. "      CPL_PASS_P                              ,Completion Passing Posted Ordering Rule Control Determines if CPL can pass halted P queue - 0: CPL can not pass P [recommended] - 1: CPL can pass P"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " NP_PASS_P                             ,Non-Posted Passing Posted Ordering Rule Control Determines if NP can pass halted P queue - 0 : NP can not pass P [recommended] - 1 : NP can pass P"
group.long 0x18B8++0x3
line.long 0x00 "PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register."
bitfld.long 0x00 31. " PIPE_LOOPBACK                         ,PIPE Loopback Enable Indicates RMMI Loopback if M-PCIe Note: This register field is sticky" "0,1"
bitfld.long 0x00 27.--30. "         RSVDP_27                                ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 24.--26. " RXSTATUS_VALUE                        ,RXSTATUS_VALUE is an internally reserved field Do not use" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--23. "         RSVDP_22                                ,Reserved for future use" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 16.--21. " RXSTATUS_LANE                         ,RXSTATUS_LANE is an internally reserved field Do not use Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "        LPBK_RXVALID                            ,LPBK_RXVALID is an internally reserved field Do not use Note: This register field is sticky"
group.long 0x18BC++0x3
line.long 0x00 "PCIE_RC_MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register."
hexmask.long 0x00 6.--31. 1. " RSVDP_6                               ,Reserved for future use"
bitfld.long 0x00 5. "  ARI_DEVICE_NUMBER                       ,When ARI is enabled, enables use of the device ID Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 4. " RSVDP_4                               ,Reserved for future use" "0,1"
bitfld.long 0x00 3. "         SIMPLIFIED_REPLAY_TIMER                 ,Enables Simplified Replay Timer [Gen4] Simplified Replay Timer Values are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b Must not be changed while link is in use Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 2. " UR_CA_MASK_4_TRGT1                    ,This field only applies to request TLPs [with UR filtering status] that you have chosen to forward to the application [when you set DEFAULT_TARGET in this register] - When you set this field to '1', the core suppresses error logging, Error Message generation, and CPL generation [for non-posted requests] - You should set this if you have set the Default Target port logic register to '1' Default is CX_MASK_UR_CA_4_TRGT1 configuration parameter Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         DEFAULT_TARGET                          ,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller - 0: The controller drops all incoming I/O or MEM requests [after corresponding error reporting] A completion with UR status will be generated for non-posted requests - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET configuration parameter Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " DBI_RO_WR_EN                          ,Write to RO Registers Using DBI When you set this field to '1', then some RO and HwInit bits are writable from the local application through the DBI Note: This register field is sticky" "0,1"
group.long 0x18C0++0x3
line.long 0x00 "PCIE_RC_MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 7. "    UPCONFIGURE_SUPPORT                     ,Upconfigure Support The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in ConfigurationComplete state This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 6. " DIRECT_LINK_WIDTH_CHANGE              ,Directed Link Width Change The controller always moves to Configuration state through Recovery state when this bit is set to '1' - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in" "0,1"
bitfld.long 0x00 0.--5. "         TARGET_LINK_WIDTH                       ,Target Link Width Values correspond to: - 6'b 000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state - 6'b 000001: x 1 - 6'b 000010: x 2 - 6'b 000100: x 4 - 6'b 001000: x 8 - 6'b 010000: x 16 - 6'b 100000: x32 This field is reserved [fixed to '0'] for M-PCIe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18C4++0x3
line.long 0x00 "PCIE_RC_PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default."
hexmask.long.tbyte 0x00 11.--31. 1. " RSVDP_11                              ,Reserved for future use"
bitfld.long 0x00 10. "    L1_CLK_SEL                              ,L1 Clock control bit - 1: Controller does not request aux_clk switch and core_clk gating in L 1 - 0: Controller requests aux_clk switch and core_clk gating in L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9. " L1_NOWAIT_P1                          ,L1 entry control bit - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L 1 - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1 Note: The access attributes of this field are as follows: - Dbi: R/W [sticky] Note: This register field is sticky" "0,1"
bitfld.long 0x00 8. "         L1SUB_EXIT_MODE                         ,L1 Exit Control Using phy_mac_pclkack_n - 1: Core exits L1 without waiting for the PHY to assert phy_mac_pclkack_n - 0: Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 7. " RSVDP_7                               ,Reserved for future use" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "         RXSTANDBY_CONTROL                       ,Rxstandby Control Bits 05 determine if the controller asserts the RxStandby signal [mac_phy_rxstandby] in the indicated condition Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP 2 - [4]: RxL0sIdle - [5]: EI Infer in L 0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved [fixed to '0'] for M-PCIe Note: This register field is sticky"
hgroup.long 0x18C8++0x3
hide.long 0x00 "PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason. Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire."
in
textline "                                                              "
group.long 0x18CC++0x3
line.long 0x00 "PCIE_RC_LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register."
hexmask.long.byte 0x00 24.--31. 1. " RSVD_I_8                              ,This is an internally reserved field Do not use Note: This register field is sticky"
hexmask.long.tbyte 0x00 1.--23. 1. "        RSVDP_1                                 ,Reserved for future use"
textline "                                                              "
bitfld.long 0x00 0. " AUTO_FLUSH_EN                         ,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge The flushing process is initiated if any of the following events occur: - Hot reset request A downstream port [DSP] can 'hot reset' an upstream port [USP] by sending two consecutive TS1 ordered sets with the hot reset bit asserted - Warm [Soft] reset request Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst= 0 - Link down reset request A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge Note: This register field is sticky" "0,1"
group.long 0x18D0++0x3
line.long 0x00 "PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register."
hexmask.long.word 0x00 16.--31. 1. " RSVDP_16                              ,Reserved for future use"
bitfld.long 0x00 10.--15. "      AMBA_ERROR_RESPONSE_MAP                 ,AXI Slave Response Error Map Allows you to selectively map the errors received from the PCIe completion [for non-posted requests] to the AXI slave responses, slv_rresp or slv_bresp The recommended setting is SLVERR CRS is always mapped to OKAY - [0] -- 0: UR [unsupported request] -> DECERR -- 1: UR [unsupported request] -> SLVERR - [1] -- 0: CRS [configuration retry status] -> DECERR -- 1: CRS [configuration retry status] -> SLVERR - [2] -- 0: CA [completer abort] -> DECERR -- 1: CA [completer abort] -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops [processes internally but not passed to your application] a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface It waits for a timeout and then signals 'Completion Timeout' to the slave interface The controller sets the AXI slave read databus to 0xFFFF for all error responses Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                                              "
bitfld.long 0x00 5.--9. " RSVDP_5                               ,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 3.--4. "        AMBA_ERROR_RESPONSE_CRS                 ,CRS Slave Error Response Mapping Determines the AXI slave response for CRS completions AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " AMBA_ERROR_RESPONSE_VENDORID          ,Vendor ID Non-existent Slave Error Response Mapping Determines the AXI slave response for errors on reads to non-existent Vendor ID register AHB: - 0: OKAY [with FFFF data] The controller ignores the setting in the bit when bit 0 of this register is '0' - 1: ERROR AXI: - 0: OKAY [with FFFF data] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " AMBA_ERROR_RESPONSE_GLOBAL            ,Global Slave Error Response Mapping Determines the AXI slave response for all error scenarios on non-posted requests AHB: - 0: OKAY [with FFFF data for non-posted requests] and ignore the setting in bit [2] of this register - 1: ERROR for normal link [data] accesses and look at bit [2] for other scenarios AXI: - 0: OKAY [with FFFF data for non-posted requests] - 1: SLVERR/DECERR [the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping] The error response mapping is not applicable to Non-existent Vendor ID register reads Note: This register field is sticky" "0,1"
group.long 0x18D4++0x3
line.long 0x00 "PCIE_RC_AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a 'flush' timer. The timeout value of the timer is set by this register. The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests."
hexmask.long.tbyte 0x00 9.--31. 1. " RSVDP_9                               ,Reserved for future use"
bitfld.long 0x00 8. "    LINK_TIMEOUT_ENABLE_DEFAULT             ,Disable Flush You can disable the flush feature by setting this field to '1' Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " LINK_TIMEOUT_PERIOD_DEFAULT           ,Timeout Value [ms] The timer will timeout and then flush the bridge TX request queues after this amount of time The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests The timer is clocked by core_clk For an M-PCIe configuration: - Time unit of this field is 4 ms - Margin of error for RateA clock is < 1% - Margin of error for RateB clock is between 16% and 17% Note: This register field is sticky"
group.long 0x18D8++0x3
line.long 0x00 "PCIE_RC_AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control."
hexmask.long 0x00 5.--31. 1. " RSVDP_5                               ,Reserved for future use"
bitfld.long 0x00 3.--4. "  AX_MSTR_ORDR_P_EVENT_SEL                ,AXI Master Posted Ordering Event Selector This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, 'NP must not pass P' at the AXI Master Interface The AXI protocol does not support ordering between channels Therefore, NP reads can pass P on your AXI bus fabric This can result in an ordering violation when the read overtakes a P that is going to the same address Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination It does this by waiting for the all of the write responses on the B channel This can affect the performance of the master read channel For scenarios where the interconnect serializes the AXI master 'AW', 'W' and 'AR' channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave [default] - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master - 11: Reserved Note 2: This setting will not affect: - MSI interrupt catcher and P data ordering This is always driven by the B'last event - DMA read engine TLP ordering This is always driven by the B'last event - NP write transactions which are always serialized with P write transactions" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2. " RSVDP_2                               ,Reserved for future use" "0,1"
bitfld.long 0x00 1. "         AX_SNP_EN                               ,AXI Serialize Non-Posted Requests Enable This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " RSVDP_0                               ,Reserved for future use" "0,1"
group.long 0x18E0++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1"
hexmask.long 0x00 2.--31. 1. " CFG_MEMTYPE_BOUNDARY_LOW_ADDR         ,Boundary Lower Address For Memory Type Bits [31:0] of dword-aligned address of the boundary for Memory type The two lower address LSBs are '00' Addresses up to but not including this value are in the lower address space region addresses equal or greater than this value are in the upper address space region Note: This register field is sticky"
bitfld.long 0x00 1. "  RSVDP_1                                 ,Reserved for future use" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE                     ,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral upper = Memory - 1: lower = Memory type upper = Peripheral Note: This register field is sticky" "0,1"
group.long 0x18E4++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2"
hexmask.long 0x00 0.--31. 1. " CFG_MEMTYPE_BOUNDARY_HIGH_ADDR        ,Boundary Upper Address For Memory Type Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type Note: This register field is sticky"
group.long 0x18E8++0x3
line.long 0x00 "PCIE_RC_COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3"
bitfld.long 0x00 27.--30. " CFG_MSTR_AWCACHE_VALUE                ,Master Write CACHE Signal Value Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1' Note: not applicable to message requests for message requests the value of mstr_awcache is always '0000' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--22. "        CFG_MSTR_ARCACHE_VALUE                  ,Master Read CACHE Signal Value Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1' Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                                              "
bitfld.long 0x00 11.--14. " CFG_MSTR_AWCACHE_MODE                 ,Master Write CACHE Signal Behavior Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always '0000' regardless of the value of this bit Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--6. "        CFG_MSTR_ARCACHE_MODE                   ,Master Read CACHE Signal Behavior Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18F0++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the and registers."
hexmask.long.tbyte 0x00 12.--31. 1. " CFG_AXIMSTR_MSG_ADDR_LOW              ,Lower 20 bits of the programmable AXI address for Messages Note: This register field is sticky"
group.long 0x18F4++0x3
line.long 0x00 "PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to."
hexmask.long 0x00 0.--31. 1. " CFG_AXIMSTR_MSG_ADDR_HIGH             ,Upper 32 bits of the programmable AXI address for Messages Note: This register field is sticky"
rgroup.long 0x18F8++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_NUMBER                        ,Version Number"
rgroup.long 0x18FC++0x3
line.long 0x00 "PCIE_RC_PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release available on a per-customer basis."
hexmask.long 0x00 0.--31. 1. " VERSION_TYPE                          ,Version Type"
group.long 0x1940++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 2.--31. 1. " MSIX_ADDRESS_MATCH_LOW                ,MSI-X Address Match Low Address Note: This register field is sticky"
bitfld.long 0x00 0. "  MSIX_ADDRESS_MATCH_EN                   ,MSI-X Match Enable Enable the MSI-X Address Match feature when the AXI bridge is present Note: This register field is sticky" "0,1"
group.long 0x1944++0x3
line.long 0x00 "PCIE_RC_MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and ), the controller will load the register with the contents of the MWr and subsequently create and send MSI-X TLPs"
hexmask.long 0x00 0.--31. 1. " MSIX_ADDRESS_MATCH_HIGH               ,MSI-X Address Match High Address Note: This register field is sticky"
group.long 0x1948++0x3
line.long 0x00 "PCIE_RC_MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. - For AXI configurations: when your local application writes (MWr) to the address defined in , the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs."
bitfld.long 0x00 24.--28. " MSIX_DOORBELL_PF                      ,MSIX Doorbell Physical Function This register determines the Physical Function for the MSI-X transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--23. 1. "        MSIX_DOORBELL_VF                        ,MSIX Doorbell Virtual Function This register determines the Virtual Function for the MSI-X transaction"
textline "                                                              "
bitfld.long 0x00 15. " MSIX_DOORBELL_VF_ACTIVE               ,MSIX Doorbell Virtual Function Active This register determines whether a Virtual Function is used to generate the MSI-X transaction" "0,1"
bitfld.long 0x00 12.--14. "         MSIX_DOORBELL_TC                        ,MSIX Doorbell Traffic Class This register determines which traffic class to generate the MSI-X transaction with" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.word 0x00 0.--10. 1. " MSIX_DOORBELL_VECTOR                  ,MSI-X Doorbell Vector This register determines which vector to generate the MSI-X transaction for"
group.long 0x194C++0x3
line.long 0x00 "PCIE_RC_MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests."
bitfld.long 0x00 25. " MSIX_RAM_CTRL_DBG_PBA                 ,MSIX PBA RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the PBA Use can also use the dbg_pba input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
bitfld.long 0x00 24. "         MSIX_RAM_CTRL_DBG_TABLE                 ,MSIX Table RAM Debug Mode Use this bit to activate the debug mode and allow direct read/write access to the Table Use can also use the dbg_table input to activate debug mode Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR [indicated by the BIR] in function 0 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 16. " MSIX_RAM_CTRL_BYPASS                  ,MSIX RAM Control Bypass The bypass field, when set, disables the internal generation of low power signals for both RAMs It is up to the application to ensure the RAMs are in the proper power state before trying to access them Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality Note: This register field is sticky" "0,1"
bitfld.long 0x00 9. "         MSIX_RAM_CTRL_PBA_SD                    ,MSIX PBA RAM Shut Down Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 8. " MSIX_RAM_CTRL_PBA_DS                  ,MSIX PBA RAM Deep Sleep Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
bitfld.long 0x00 1. "         MSIX_RAM_CTRL_TABLE_SD                  ,MSIX Table RAM Shut Down Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 0. " MSIX_RAM_CTRL_TABLE_DS                ,MSIX Table RAM Deep Sleep Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode Note: This register field is sticky" "0,1"
group.long 0x1B40++0x3
line.long 0x00 "PCIE_RC_AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register."
hexmask.long.tbyte 0x00 10.--31. 1. " RSVDP_10                              ,Reserved for future use"
hexmask.long.word 0x00 0.--9. 1. "    AUX_CLK_FREQ                            ,The aux_clk frequency in MHz This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted If the actual frequency [f] of aux_clk does not exactly match the programmed frequency [f_prog], then there is an error in the time counted by the controller that can be expressed in percentage as: err% = [f_prog/f-1]*100 For example if f=25 MHz and f_prog=3 MHz, then err% =[3/ 25-1]* 100 =20%, meaning that the time counted by the controller on aux_clk will be 20 0reater than the time in us programmed in the corresponding time register [for example T_POWER_ON] Note: This register field is sticky"
group.long 0x1B44++0x3
line.long 0x00 "PCIE_RC_L1_SUBSTATES_OFF,L1 Substates Timing Register."
hexmask.long.tbyte 0x00 8.--31. 1. " RSVDP_8                               ,Reserved for future use"
bitfld.long 0x00 6.--7. "    L1SUB_T_PCLKACK                         ,Max delay [in 1us units] between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n If the PHY does not respond within this time the request is aborted Range is 03 Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 2.--5. " L1SUB_T_L1_2                          ,Duration [in 1us units] of L12 Range is 015 Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "        L1SUB_T_POWER_OFF                       ,Duration [in 1us units] of L12Entry Range is 03 Note: This register field is sticky" "0,1,2,3"
group.long 0x6000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x600C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x610C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x620C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x630C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x640C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x650C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x660C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x670C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x680C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_4,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_4,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_4,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x690C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_4,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_5,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_5,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_5,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_5,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_6,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_6,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_6,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_6,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x6E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x6E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x6F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_7,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_7,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x6F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_7,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x6F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x6F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_7,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x6F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x6F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7000++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7004++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7008++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x700C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7010++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7014++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7018++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7100++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_8,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7104++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_8,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7108++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_8,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x710C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7110++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_8,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7114++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7118++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7200++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7204++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7208++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x720C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7210++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7214++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7218++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7300++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_9,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7304++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_9,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7308++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_9,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x730C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7310++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_9,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7314++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7318++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7400++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7404++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7408++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x740C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7410++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7414++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7418++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7500++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_10,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7504++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_10,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7508++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_10,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x750C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7510++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_10,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7514++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7518++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7600++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7604++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7608++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x760C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7610++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7614++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7618++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7700++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_11,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7704++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_11,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7708++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_11,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x770C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7710++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_11,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7714++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7718++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7800++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7804++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7808++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x780C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7810++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7814++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7818++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7900++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_12,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7904++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_12,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7908++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_12,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x790C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7910++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_12,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7914++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7918++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7A04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7A08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7A0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7A10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7A14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7A18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7B00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_13,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7B04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_13,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7B08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_13,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7B0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7B10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_13,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7B14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7B18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7C08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7C0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7C10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7C14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7C18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7D00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_14,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7D04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_14,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7D08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_14,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7D0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7D10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_14,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7D14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7D18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_OUTBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0', then the function number used in generating the function part of the requester ID [RID] field of the TLP is taken from this 5-bit register The value in this register must be 0x0 unless multifunction operation in the controller is enabled [CX_NFUNC > 1] - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct 'Max_Read_Request_Size' and 'Max_Payload_Size' values are used Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7E04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_OUTBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 29. "         INVERT_MODE                             ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 28. " CFG_SHIFT_MODE                        ,CFG Shift Mode The iATU uses bits [27:12] of the untranslated address [on the XALI0/1/2 interface or AXI slave interface address] to form the BDF number of the outgoing CFG TLP This supports the Enhanced Configuration Address Mapping [ECAM] mechanism [Section 722 of the PCI Express Base 31 Specification, revision 10] by allowing all outgoing I/O and MEM TLPs [that have been translated to CFG] to be mapped from memory space into any 256 MB region of the PCIe configuration space Note: This register field is sticky" "0,1"
bitfld.long 0x00 23. "         HEADER_SUBSTITUTE_EN                    ,Header Substitute Enable When enabled and region address is matched, the iATU fully substitutes bytes 8-11 [for 3 DWORD header] or bytes 12-15 [for 4 DWORD header] of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 [for 3 DWORD header] or bytes 12-to-15 [for 4 DWORD header] of the translated TLP header - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 22. " INHIBIT_PAYLOAD                       ,Inhibit TLP Payload Data for TLP's in Matched Region assign iATU region to be TLP without data When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb - 1: Fmt[1] =0 so that only TLP type without data is sent For example, a Msg instead of MsgD will be sent - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent Note: This register field is sticky" "0,1"
bitfld.long 0x00 20. "         SNP                                     ,Serialize Non-Posted Requests In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_BYPASS                           ,Function Number Translation Bypass In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of the 'iATU Control 3 Register' Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         TAG_SUBSTITUTE_EN                       ,TAG Substitute Enable When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD Note [CX_TPH_ENABLE=1]: TAG substitution for MWr will not occur because this field [byte 6] in the TLP header is the ST field ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i Note: This register field is sticky" "0,1"
textline "                                                              "
hexmask.long.byte 0x00 8.--15. 1. " TAG                                   ,TAG The substituted TAG field [byte 6] in the outgoing TLP header when TAG_SUBSTITUTE_EN is set Note: This register field is sticky"
hexmask.long.byte 0x00 0.--7. 1. "        MSG_CODE                                ,MSG TLPs [Message Code] When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD then the message field of the TLP is changed to the value in this register Memory TLPs: [ST Steering Tag] When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space then the ST field of the TLP is changed to the value in this register Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7E08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7E0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
group.long 0x7E10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_OUTBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7E14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15,iATU Lower Target Address Register."
hexmask.long 0x00 0.--31. 1. " LWR_TARGET_RW_OUTBOUND                ,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' [normal operation]: - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region - LWR_TARGET_RW[n-1:0] are not used [The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region [bits n-1:0] are always '0'] - n is log2[CX_ATU_MIN_REGION_SIZE] When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 [for 3 dword header] or bytes 12-15 [for 4 dword header] of the outbound TLP header Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header Note: This register field is sticky"
group.long 0x7E18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region Note: This register field is sticky"
group.long 0x7F00++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_1_OFF_INBOUND_15,iATU Region Control 1 Register."
bitfld.long 0x00 20.--22. " CTRL_1_FUNC_NUM                       ,Function Number - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set - CFG0/CFG 1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds This check is only performed if the 'Function Number Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "         INCREASE_REGION_SIZE                    ,Increase the maximum ATU Region size When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE When clear, the maximum ATU Region size is 4 GB [default] Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 9.--10. " ATTR                                  ,When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3"
bitfld.long 0x00 8. "         TD                                      ,When the TD field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 5.--7. " TC                                    ,When the TC field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set Note: This register field is sticky" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "         TYPE                                    ,When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] Note: This register field is sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7F04++0x3
line.long 0x00 "PCIE_RC_IATU_REGION_CTRL_2_OFF_INBOUND_15,iATU Region Control 2 Register."
bitfld.long 0x00 31. " REGION_EN                             ,Region Enable This bit must be set to '1' for address translation to take place Note: This register field is sticky" "0,1"
bitfld.long 0x00 30. "         MATCH_MODE                              ,Match Mode Determines Inbound matching mode for TLPs The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU operates using addresses as in the outbound direction The Region Base and Limit Registers must be setup - 1:BAR Match Mode BAR matching is used The 'BAR Number' field is relevant Not used for RC For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode The iATU interprets the Routing ID [Bytes 8 to 11 of TLP header] as an address This corresponds to the upper 16 bits of the address in MEM-I/O transactions The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed - 1: Accept Mode The iATU accepts all CFG0 transactions as address matches The routing ID in the CFG0 TLP is ignored This is useful as all received CFG0 TLPs should be processed regardless of the Bus number For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers - 1: Vendor ID Match Mode This mode is relevant for ID-routed Vendor Defined Messages The iATU ignores the Routing ID [Bus, Device, Function] in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 29. " INVERT_MODE                           ,Invert Mode When set the address matching region is inverted Therefore, an address match occurs when the untranslated address is in the region outside the defined range [Base Address to Limit Address] Note: This register field is sticky" "0,1"
bitfld.long 0x00 28. "         CFG_SHIFT_MODE                          ,CFG Shift Mode This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 27. " FUZZY_TYPE_MATCH_CODE                 ,Fuzzy Type Match Mode When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical Similarly with CfgWr0 and CfgWr 1 - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical For example, CFG0 in the TYPE field in the 'iATU Control 1 Register' matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP Note: This register field is sticky" "0,1"
bitfld.long 0x00 24.--25. "         RESPONSE_CODE                           ,Response Code Defines the type of response to give for accesses matching this region This overrides the normal RADM filter response Note that this feature is not available for any region where Single Address Location Translate is enabled - 00 - Normal RADM filter response is used - 01 - Unsupported request [UR] - 10 - Completer abort [CA] - 11 - Not used / undefined / reserved Note: This register field is sticky" "0,1,2,3"
textline "                                                              "
bitfld.long 0x00 23. " SINGLE_ADDR_LOC_TRANS_EN              ,Single Address Location Translate Enable When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region The main usage scenario is translation of Messages [such as Vendor Defined or ATS Messages] to MWr TLPs when the AXI bridge is enabled Note: This register field is sticky" "0,1"
bitfld.long 0x00 21. "         MSG_CODE_MATCH_EN                       ,Message Code Match Enable [Msg TLPS] Ensures that a successful message Code TLP field comparison match [see Message Code field of the 'iATU Control 2 Register'] occurs [in MSG transactions] for address translation to proceed ST Match Enable [Mem TLPs] Ensures that a successful ST TLP field comparison match [see ST field of the 'iATU Control 2 Register'] occurs [in MEM transactions] for address translation to proceed Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 19. " FUNC_NUM_MATCH_EN                     ,Function Number Match Enable Ensures that a successful Function Number TLP field comparison match [see Function Number field of the 'iATU Control 1 Register'] occurs [in MEM-I/O and CFG0/CFG1 transactions] for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 16. "         ATTR_MATCH_EN                           ,ATTR Match Enable Ensures that a successful ATTR TLP field comparison match [see ATTR field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 15. " TD_MATCH_EN                           ,TD Match Enable Ensures that a successful TD TLP field comparison match [see TD field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
bitfld.long 0x00 14. "         TC_MATCH_EN                             ,TC Match Enable Ensures that a successful TC TLP field comparison match [see TC field of the 'iATU Control 1 Register'] occurs for address translation to proceed Note: This register field is sticky" "0,1"
textline "                                                              "
bitfld.long 0x00 13. " MSG_TYPE_MATCH_MODE                   ,Message Type Match Mode When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register [=>TYPE [4:3]=2'b10] will be translated Message type match mode overrides any value of MATCH_MODE field in this register Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface Note: This register field is sticky" "0,1"
bitfld.long 0x00 8.--10. "         BAR_NUM                                 ,BAR Number When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field, address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Match Mode' bit of the 'iATU Control 2 Register' is set - 000b - BAR 0 - 001b - BAR 1 - 010b - BAR 2 - 011b - BAR 3 - 100b - BAR 4 - 101b - BAR 5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR Note: This register field is sticky" "0,1,2,3,4,5,6,7"
textline "                                                              "
hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE                              ,MSG TLPs: [Message Code] When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds [when all other enabled field-matches are successful] This check is only performed if the 'Message Code Match Enable' bit of the 'iATU Control 2 Register' is set Memory TLPs: [ST Steering Tag] When the ST field of an inbound TLP is matched to this value, then address translation proceeds This check is only performed if the 'ST Match Enable' bit of the 'iATU Control2 Register' is set The setting is independent of the setting of the TH field Only Valid when the CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky"
group.long 0x7F08++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_BASE_ADDR_OFF_INBOUND_15,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero."
hexmask.long.word 0x00 16.--31. 1. " LWR_BASE_RW                           ,Forms bits [31:n] of the start address of the address region to be translated n is log2[CX_ATU_MIN_REGION_SIZE] Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_BASE_HW                             ,Forms bits [n- 1:0] of the start address of the address region to be translated The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller n is log2[CX_ATU_MIN_REGION_SIZE]"
group.long 0x7F0C++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15,iATU Upper Base Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_BASE_RW                         ,Forms bits [63:32] of the start [and end] address of the address region to be translated Note: This register field is sticky"
group.long 0x7F10++0x3
line.long 0x00 "PCIE_RC_IATU_LIMIT_ADDR_OFF_INBOUND_15,iATU Limit Address Register."
hexmask.long.word 0x00 16.--31. 1. " LIMIT_ADDR_RW                         ,Forms upper bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LIMIT_ADDR_HW                           ,Forms lower bits of the end address of the address region to be translated The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0 A write to this location is ignored by the PCIe controller"
group.long 0x7F14++0x3
line.long 0x00 "PCIE_RC_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15,iATU Lower Target Address Register."
hexmask.long.word 0x00 16.--31. 1. " LWR_TARGET_RW                         ,Forms MSB's of the Lower Target part of the new address of the translated region These bits are always '0' - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode Note: This register field is sticky"
hexmask.long.word 0x00 0.--15. 1. "      LWR_TARGET_HW                           ,Forms the LSB's of the Lower Target part of the new address of the translated region The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary [in address match mode] and to the Bar size boundary [in BAR match mode] so that these bits are always '0' If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size otherwise it must align to the BAR size A write to this location is ignored by the PCIe controller - Field size depends on log2[CX_ATU_MIN_REGION_SIZE] in address match mode - Field size depends on log2[BAR_MASK+1] in BAR match mode"
group.long 0x7F18++0x3
line.long 0x00 "PCIE_RC_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15,iATU Upper Target Address Register."
hexmask.long 0x00 0.--31. 1. " UPPER_TARGET_RW                       ,Forms bits [63:32] of the start address [Upper Target part] of the new address of the translated region In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect Note: This register field is sticky"
width 0x0B
tree.end
tree.end
tree.end
tree "PCIE_CPTS"
tree "PCIE0_CPTS"
base ad:0x2940000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT         ,Identification value"
bitfld.long 0x00 11.--15. "      RTL_VER        ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " MAJOR_VER        ,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER      ,Minor version value"
group.long 0x8++0x3
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,Added PCIE_CPTS_RFTCLK_SEL Register Bit Field Description RFTCLK Select Register"
bitfld.long 0x00 0.--4. " RFTCLK_SEL       ,Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h: Selects CPSWHSDIV_CLKOUT2 clock 1h: Selects MAINHSDIV_CLKOUT3 clock 2h: Selects MCU_CPTS0_RFT_CLK I/O pin 3h: Selects CPTS0_RFT_CLK I/O pin 4h: Selects MCU_EXT_REFCLK0 I/O pin 5h: Selects EXT_REFCLK1 I/O pin 6h: Selects PCIE0_TXI0_CLK clock 7h: Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the PCIE_CPTS_CONTROL_REG register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0xC++0x3
line.long 0x00 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x00 0. " TS_PUSH          ,Time stamp event push" "0,1"
group.long 0x10++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL      ,Time stamp load low value"
wgroup.long 0x14++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x00 0. " TS_LOAD_EN       ,Time stamp load enable" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_VAL      ,Time stamp comparison low value"
group.long 0x1C++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_LENGTH   ,Time stamp comparison length"
group.long 0x20++0x3
line.long 0x00 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x00 0. " TS_PEND_RAW      ,TS_PEND_RAW int read (before enable)" "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x00 0. " TS_PEND          ,TS_PEND masked interrupt read (after enable)" "0,1"
group.long 0x28++0x3
line.long 0x00 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x00 0. " TS_PEND_EN       ,TS_PEND masked interrupt enable" "0,1"
group.long 0x2C++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE            ,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
wgroup.long 0x30++0x3
line.long 0x00 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x00 0. " EVENT_POP        ,Event pop" "0,1"
rgroup.long 0x34++0x3
line.long 0x00 "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP       ,Time Stamp"
rgroup.long 0x38++0x3
line.long 0x00 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x00 29. " PREMPT_QUEUE     ,Prempt QUEUE" "0,1"
bitfld.long 0x00 24.--28. "         PORT_NUMBER    ,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 20.--23. " EVENT_TYPE       ,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        MESSAGE_TYPE   ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID      ,Sequence ID"
rgroup.long 0x3C++0x3
line.long 0x00 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x00 0.--7. 1. " DOMAIN           ,Domain"
rgroup.long 0x40++0x3
line.long 0x00 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP       ,Time Stamp"
group.long 0x44++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL      ,Time stamp load high value"
group.long 0x48++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_HIGH_VAL ,Time stamp comparison high value"
group.long 0x4C++0x3
line.long 0x00 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x00 0.--2. " ADD_VAL          ,Add Value" "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_PPM_LOW_VAL   ,Time stamp PPM Low value"
group.long 0x54++0x3
line.long 0x00 "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x00 0.--9. 1. " TS_PPM_HIGH_VAL  ,Time stamp PPM High value"
group.long 0x58++0x3
line.long 0x00 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x00 0.--7. 1. " TS_NUDGE_VAL     ,Time stamp Nudge value"
group.long 0x200++0x3
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
hexmask.long 0x00 0.--31. 1. " COMP_LOW         ,Time Stamp Generate Function Comparison Low Value"
group.long 0x204++0x3
line.long 0x00 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
hexmask.long 0x00 0.--31. 1. " COMP_HIGH        ,Time Stamp Generate Function Comparison High Value"
group.long 0x208++0x3
line.long 0x00 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x00 28.--31. " TS_SYNC_SEL      ,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "        HW8_TS_PUSH_EN ,Hardware push 8 enable" "0,1"
textline "                                         "
bitfld.long 0x00 14. " HW7_TS_PUSH_EN   ,Hardware push 7 enable" "0,1"
bitfld.long 0x00 13. "         HW6_TS_PUSH_EN ,Hardware push 6 enable" "0,1"
textline "                                         "
bitfld.long 0x00 12. " HW5_TS_PUSH_EN   ,Hardware push 5 enable" "0,1"
bitfld.long 0x00 11. "         HW4_TS_PUSH_EN ,Hardware push 4 enable" "0,1"
textline "                                         "
bitfld.long 0x00 10. " HW3_TS_PUSH_EN   ,Hardware push 3 enable" "0,1"
bitfld.long 0x00 9. "         HW2_TS_PUSH_EN ,Hardware push 2 enable" "0,1"
textline "                                         "
bitfld.long 0x00 8. " HW1_TS_PUSH_EN   ,Hardware push 1 enable" "0,1"
bitfld.long 0x00 7. "         TS_PPM_DIR     ,Timestamp PPM Direction" "0,1"
textline "                                         "
bitfld.long 0x00 6. " TS_COMP_TOG      ,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode, 1=TS_COMP is in toggle mode" "0,1"
bitfld.long 0x00 5. "         MODE           ,Timestamp mode" "0,1"
textline "                                         "
bitfld.long 0x00 4. " SEQUENCE_EN      ,Sequence Enable" "0,1"
bitfld.long 0x00 3. "         TSTAMP_EN      ,Host Receive Timestamp Enable" "0,1"
textline "                                         "
bitfld.long 0x00 2. " TS_COMP_POLARITY ,TS_COMP polarity" "0,1"
bitfld.long 0x00 1. "         INT_TEST       ,Interrupt test" "0,1"
textline "                                         "
bitfld.long 0x00 0. " CPTS_EN          ,Time sync enable" "0,1"
group.long 0x20C++0x3
line.long 0x00 "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
hexmask.long 0x00 0.--31. 1. " LENGTH           ,Time Stamp Generate Function Length Value"
group.long 0x210++0x3
line.long 0x00 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
hexmask.long 0x00 0.--31. 1. " PPM_LOW          ,Time Stamp Generate Function PPM Low Value"
group.long 0x214++0x3
line.long 0x00 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x00 0.--9. 1. " PPM_HIGH         ,Time Stamp Generate Function PPM High Value"
group.long 0x218++0x3
line.long 0x00 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE            ,Time Stamp Generate Function Nudge Value"
width 0x0B
tree.end
tree "PCIE1_CPTS"
base ad:0x2950000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT         ,Identification value"
bitfld.long 0x00 11.--15. "      RTL_VER        ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 8.--10. " MAJOR_VER        ,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER      ,Minor version value"
group.long 0x8++0x3
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,Added PCIE_CPTS_RFTCLK_SEL Register Bit Field Description RFTCLK Select Register"
bitfld.long 0x00 0.--4. " RFTCLK_SEL       ,Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h: Selects CPSWHSDIV_CLKOUT2 clock 1h: Selects MAINHSDIV_CLKOUT3 clock 2h: Selects MCU_CPTS0_RFT_CLK I/O pin 3h: Selects CPTS0_RFT_CLK I/O pin 4h: Selects MCU_EXT_REFCLK0 I/O pin 5h: Selects EXT_REFCLK1 I/O pin 6h: Selects PCIE0_TXI0_CLK clock 7h: Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the PCIE_CPTS_CONTROL_REG register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0xC++0x3
line.long 0x00 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x00 0. " TS_PUSH          ,Time stamp event push" "0,1"
group.long 0x10++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL      ,Time stamp load low value"
wgroup.long 0x14++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x00 0. " TS_LOAD_EN       ,Time stamp load enable" "0,1"
group.long 0x18++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_VAL      ,Time stamp comparison low value"
group.long 0x1C++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_LENGTH   ,Time stamp comparison length"
group.long 0x20++0x3
line.long 0x00 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x00 0. " TS_PEND_RAW      ,TS_PEND_RAW int read (before enable)" "0,1"
rgroup.long 0x24++0x3
line.long 0x00 "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x00 0. " TS_PEND          ,TS_PEND masked interrupt read (after enable)" "0,1"
group.long 0x28++0x3
line.long 0x00 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x00 0. " TS_PEND_EN       ,TS_PEND masked interrupt enable" "0,1"
group.long 0x2C++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE            ,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
wgroup.long 0x30++0x3
line.long 0x00 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x00 0. " EVENT_POP        ,Event pop" "0,1"
rgroup.long 0x34++0x3
line.long 0x00 "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP       ,Time Stamp"
rgroup.long 0x38++0x3
line.long 0x00 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x00 29. " PREMPT_QUEUE     ,Prempt QUEUE" "0,1"
bitfld.long 0x00 24.--28. "         PORT_NUMBER    ,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 20.--23. " EVENT_TYPE       ,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        MESSAGE_TYPE   ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID      ,Sequence ID"
rgroup.long 0x3C++0x3
line.long 0x00 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x00 0.--7. 1. " DOMAIN           ,Domain"
rgroup.long 0x40++0x3
line.long 0x00 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
hexmask.long 0x00 0.--31. 1. " TIME_STAMP       ,Time Stamp"
group.long 0x44++0x3
line.long 0x00 "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_LOAD_VAL      ,Time stamp load high value"
group.long 0x48++0x3
line.long 0x00 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
hexmask.long 0x00 0.--31. 1. " TS_COMP_HIGH_VAL ,Time stamp comparison high value"
group.long 0x4C++0x3
line.long 0x00 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x00 0.--2. " ADD_VAL          ,Add Value" "0,1,2,3,4,5,6,7"
group.long 0x50++0x3
line.long 0x00 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
hexmask.long 0x00 0.--31. 1. " TS_PPM_LOW_VAL   ,Time stamp PPM Low value"
group.long 0x54++0x3
line.long 0x00 "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x00 0.--9. 1. " TS_PPM_HIGH_VAL  ,Time stamp PPM High value"
group.long 0x58++0x3
line.long 0x00 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x00 0.--7. 1. " TS_NUDGE_VAL     ,Time stamp Nudge value"
group.long 0x200++0x3
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
hexmask.long 0x00 0.--31. 1. " COMP_LOW         ,Time Stamp Generate Function Comparison Low Value"
group.long 0x204++0x3
line.long 0x00 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
hexmask.long 0x00 0.--31. 1. " COMP_HIGH        ,Time Stamp Generate Function Comparison High Value"
group.long 0x208++0x3
line.long 0x00 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x00 28.--31. " TS_SYNC_SEL      ,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "        HW8_TS_PUSH_EN ,Hardware push 8 enable" "0,1"
textline "                                         "
bitfld.long 0x00 14. " HW7_TS_PUSH_EN   ,Hardware push 7 enable" "0,1"
bitfld.long 0x00 13. "         HW6_TS_PUSH_EN ,Hardware push 6 enable" "0,1"
textline "                                         "
bitfld.long 0x00 12. " HW5_TS_PUSH_EN   ,Hardware push 5 enable" "0,1"
bitfld.long 0x00 11. "         HW4_TS_PUSH_EN ,Hardware push 4 enable" "0,1"
textline "                                         "
bitfld.long 0x00 10. " HW3_TS_PUSH_EN   ,Hardware push 3 enable" "0,1"
bitfld.long 0x00 9. "         HW2_TS_PUSH_EN ,Hardware push 2 enable" "0,1"
textline "                                         "
bitfld.long 0x00 8. " HW1_TS_PUSH_EN   ,Hardware push 1 enable" "0,1"
bitfld.long 0x00 7. "         TS_PPM_DIR     ,Timestamp PPM Direction" "0,1"
textline "                                         "
bitfld.long 0x00 6. " TS_COMP_TOG      ,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode, 1=TS_COMP is in toggle mode" "0,1"
bitfld.long 0x00 5. "         MODE           ,Timestamp mode" "0,1"
textline "                                         "
bitfld.long 0x00 4. " SEQUENCE_EN      ,Sequence Enable" "0,1"
bitfld.long 0x00 3. "         TSTAMP_EN      ,Host Receive Timestamp Enable" "0,1"
textline "                                         "
bitfld.long 0x00 2. " TS_COMP_POLARITY ,TS_COMP polarity" "0,1"
bitfld.long 0x00 1. "         INT_TEST       ,Interrupt test" "0,1"
textline "                                         "
bitfld.long 0x00 0. " CPTS_EN          ,Time sync enable" "0,1"
group.long 0x20C++0x3
line.long 0x00 "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
hexmask.long 0x00 0.--31. 1. " LENGTH           ,Time Stamp Generate Function Length Value"
group.long 0x210++0x3
line.long 0x00 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
hexmask.long 0x00 0.--31. 1. " PPM_LOW          ,Time Stamp Generate Function PPM Low Value"
group.long 0x214++0x3
line.long 0x00 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x00 0.--9. 1. " PPM_HIGH         ,Time Stamp Generate Function PPM High Value"
group.long 0x218++0x3
line.long 0x00 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x00 0.--7. 1. " NUDGE            ,Time Stamp Generate Function Nudge Value"
width 0x0B
tree.end
tree.end
tree "PCIE_DAT0"
tree "PCIE0_DAT0"
base ad:0x10000000
width 27.
group.long 0x0++0x3
line.long 0x00 "PCIE_DAT0_PCIE_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
hexmask.long 0x00 0.--31. 1. " PCIE_DATA ,PCIE data region0"
width 0x0B
tree.end
tree "PCIE1_DAT0"
base ad:0x18000000
width 27.
group.long 0x0++0x3
line.long 0x00 "PCIE_DAT0_PCIE_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
hexmask.long 0x00 0.--31. 1. " PCIE_DATA ,PCIE data region0"
width 0x0B
tree.end
tree.end
tree "PCIE_DAT1"
tree "PCIE0_DAT1"
base ad:0x4000000000
width 27.
group.long 0x0++0x3
line.long 0x00 "PCIE_DAT1_PCIE_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
hexmask.long 0x00 0.--31. 1. " PCIE_DATA ,PCIE data region1"
width 0x0B
tree.end
tree "PCIE1_DAT1"
base ad:0x4100000000
width 27.
group.long 0x0++0x3
line.long 0x00 "PCIE_DAT1_PCIE_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
hexmask.long 0x00 0.--31. 1. " PCIE_DATA ,PCIE data region1"
width 0x0B
tree.end
tree.end
tree "PCIE_ECC_AGGR0"
tree "PCIE0_CORE_ECC_AGGR0"
base ad:0x2A28000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                        ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                           ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                     ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                       ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                        ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                       ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                        ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PCIE_ECC0_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                      ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                        ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_PEND            ,Interrupt Pending Status for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_PEND            ,Interrupt Pending Status for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_PEND                ,Interrupt Pending Status for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_PEND        ,Interrupt Pending Status for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_PEND          ,Interrupt Pending Status for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_PEND                     ,Interrupt Pending Status for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_PEND                    ,Interrupt Pending Status for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_PEND            ,Interrupt Pending Status for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_PEND              ,Interrupt Pending Status for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_PEND              ,Interrupt Pending Status for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_PEND             ,Interrupt Pending Status for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_PEND       ,Interrupt Pending Status for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_PEND         ,Interrupt Pending Status for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_PEND                  ,Interrupt Pending Status for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_PEND                     ,Interrupt Pending Status for rbuf_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_ENABLE_SET          ,Interrupt Enable Set Register for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_ENABLE_SET    ,Interrupt Enable Set Register for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_ENABLE_SET               ,Interrupt Enable Set Register for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_ENABLE_SET              ,Interrupt Enable Set Register for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_ENABLE_SET       ,Interrupt Enable Set Register for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_ENABLE_SET ,Interrupt Enable Set Register for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_ENABLE_SET   ,Interrupt Enable Set Register for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_ENABLE_SET            ,Interrupt Enable Set Register for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_ENABLE_SET               ,Interrupt Enable Set Register for rbuf_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                        ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_PEND            ,Interrupt Pending Status for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_PEND            ,Interrupt Pending Status for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_PEND                ,Interrupt Pending Status for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_PEND        ,Interrupt Pending Status for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_PEND          ,Interrupt Pending Status for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_PEND                     ,Interrupt Pending Status for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_PEND                    ,Interrupt Pending Status for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_PEND            ,Interrupt Pending Status for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_PEND              ,Interrupt Pending Status for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_PEND              ,Interrupt Pending Status for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_PEND             ,Interrupt Pending Status for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_PEND       ,Interrupt Pending Status for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_PEND         ,Interrupt Pending Status for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_PEND                  ,Interrupt Pending Status for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_PEND                     ,Interrupt Pending Status for rbuf_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_ENABLE_SET          ,Interrupt Enable Set Register for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_ENABLE_SET    ,Interrupt Enable Set Register for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_ENABLE_SET               ,Interrupt Enable Set Register for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_ENABLE_SET              ,Interrupt Enable Set Register for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_ENABLE_SET       ,Interrupt Enable Set Register for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_ENABLE_SET ,Interrupt Enable Set Register for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_ENABLE_SET   ,Interrupt Enable Set Register for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_ENABLE_SET            ,Interrupt Enable Set Register for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_ENABLE_SET               ,Interrupt Enable Set Register for rbuf_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                       ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                       ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                       ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                       ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "PCIE1_CORE_ECC_AGGR0"
base ad:0x2A2A000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                        ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                           ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                     ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                       ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                        ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                       ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                        ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PCIE_ECC0_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                      ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                        ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_PEND            ,Interrupt Pending Status for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_PEND            ,Interrupt Pending Status for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_PEND                ,Interrupt Pending Status for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_PEND        ,Interrupt Pending Status for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_PEND          ,Interrupt Pending Status for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_PEND                     ,Interrupt Pending Status for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_PEND                    ,Interrupt Pending Status for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_PEND            ,Interrupt Pending Status for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_PEND              ,Interrupt Pending Status for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_PEND              ,Interrupt Pending Status for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_PEND             ,Interrupt Pending Status for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_PEND       ,Interrupt Pending Status for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_PEND         ,Interrupt Pending Status for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_PEND                  ,Interrupt Pending Status for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_PEND                     ,Interrupt Pending Status for rbuf_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_ENABLE_SET          ,Interrupt Enable Set Register for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_ENABLE_SET    ,Interrupt Enable Set Register for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_ENABLE_SET               ,Interrupt Enable Set Register for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_ENABLE_SET              ,Interrupt Enable Set Register for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_ENABLE_SET       ,Interrupt Enable Set Register for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_ENABLE_SET ,Interrupt Enable Set Register for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_ENABLE_SET   ,Interrupt Enable Set Register for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_ENABLE_SET            ,Interrupt Enable Set Register for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_ENABLE_SET               ,Interrupt Enable Set Register for rbuf_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                        ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_PEND            ,Interrupt Pending Status for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_PEND            ,Interrupt Pending Status for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_PEND                ,Interrupt Pending Status for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_PEND        ,Interrupt Pending Status for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_PEND          ,Interrupt Pending Status for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_PEND                     ,Interrupt Pending Status for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_PEND                    ,Interrupt Pending Status for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_PEND            ,Interrupt Pending Status for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_PEND       ,Interrupt Pending Status for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_PEND        ,Interrupt Pending Status for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_PEND              ,Interrupt Pending Status for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_PEND              ,Interrupt Pending Status for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_PEND             ,Interrupt Pending Status for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_PEND       ,Interrupt Pending Status for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_PEND         ,Interrupt Pending Status for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_PEND                  ,Interrupt Pending Status for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_PEND                     ,Interrupt Pending Status for rbuf_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 18. " OB_PDCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_data_pend" "0,1"
bitfld.long 0x00 17. "     OB_PDCMP_HDR_ENABLE_SET      ,Interrupt Enable Set Register for ob_pdcmp_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 16. " OB_NPDCMP_ENABLE_SET          ,Interrupt Enable Set Register for ob_npdcmp_pend" "0,1"
bitfld.long 0x00 15. "     IBH_MCPL_A2C_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ibh_mcpl_a2c_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 14. " IB_MCPL_A2C_CDC_ENABLE_SET    ,Interrupt Enable Set Register for ib_mcpl_a2c_cdc_pend" "0,1"
bitfld.long 0x00 13. "     PBA_ENABLE_SET               ,Interrupt Enable Set Register for pba_pend" "0,1"
textline "                                        "
bitfld.long 0x00 12. " TABLE_ENABLE_SET              ,Interrupt Enable Set Register for table_pend" "0,1"
bitfld.long 0x00 11. "     OB_CCMP_DATA_ENABLE_SET      ,Interrupt Enable Set Register for ob_ccmp_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 10. " IBH_WREQ_PTRK_DATA_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 9. "     IBH_WREQ_PTRK_HDR_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 8. " IB_WREQ_PTRK_DATA_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_data_pend" "0,1"
bitfld.long 0x00 7. "     IB_WREQ_PTRK_HDR_ENABLE_SET  ,Interrupt Enable Set Register for ib_wreq_ptrk_hdr_pend" "0,1"
textline "                                        "
bitfld.long 0x00 6. " IBH_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ibh_mcpl_sb_pend" "0,1"
bitfld.long 0x00 5. "     IB_MCPL_SB_ENABLE_SET        ,Interrupt Enable Set Register for ib_mcpl_sb_pend" "0,1"
textline "                                        "
bitfld.long 0x00 4. " IB_RREQ_ORDR_ENABLE_SET       ,Interrupt Enable Set Register for ib_rreq_ordr_pend" "0,1"
bitfld.long 0x00 3. "     RADM_QBUFFER_DATA_ENABLE_SET ,Interrupt Enable Set Register for radm_qbuffer_data_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RADM_QBUFFER_HDR_ENABLE_SET   ,Interrupt Enable Set Register for radm_qbuffer_hdr_pend" "0,1"
bitfld.long 0x00 1. "     SOTBUF_ENABLE_SET            ,Interrupt Enable Set Register for sotbuf_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " RBUF_ENABLE_SET               ,Interrupt Enable Set Register for rbuf_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                       ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                       ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                       ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                       ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "PCIE_ECC_AGGR1"
tree "PCIE0_CORE_ECC_AGGR1"
base ad:0x2A29000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                     ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                          ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                  ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                      ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                     ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                      ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                     ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PCIE_ECC1_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                   ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                     ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_PEND        ,Interrupt Pending Status for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_PEND            ,Interrupt Pending Status for slv_npw_sab_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_ENABLE_SET      ,Interrupt Enable Set Register for slv_npw_sab_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                     ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_PEND        ,Interrupt Pending Status for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_PEND            ,Interrupt Pending Status for slv_npw_sab_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_ENABLE_SET      ,Interrupt Enable Set Register for slv_npw_sab_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                    ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                      ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                    ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                      ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                    ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                      ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "PCIE1_CORE_ECC_AGGR1"
base ad:0x2A2B000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                     ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                          ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                  ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                      ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                     ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                      ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                     ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PCIE_ECC1_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                   ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                     ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_PEND        ,Interrupt Pending Status for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_PEND            ,Interrupt Pending Status for slv_npw_sab_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_ENABLE_SET      ,Interrupt Enable Set Register for slv_npw_sab_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                     ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_PEND        ,Interrupt Pending Status for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_PEND       ,Interrupt Pending Status for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_PEND            ,Interrupt Pending Status for slv_npw_sab_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. " OB_CPL_C2A_CDC_ENABLE_SET  ,Interrupt Enable Set Register for ob_cpl_c2a_cdc_pend" "0,1"
bitfld.long 0x00 4. "     IBH_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_wreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 3. " IB_WREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_wreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 2. "     IBH_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ibh_rreq_c2a_cdc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " IB_RREQ_C2A_CDC_ENABLE_SET ,Interrupt Enable Set Register for ib_rreq_c2a_cdc_pend" "0,1"
bitfld.long 0x00 0. "     SLV_NPW_SAB_ENABLE_SET      ,Interrupt Enable Set Register for slv_npw_sab_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                    ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                      ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                    ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                      ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                    ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                      ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "PCIE_VMAP_HP"
tree "PCIE0_CORE_VMAP_HP_MMRS"
base ad:0x2908000
width 23.
group.long 0x0++0x3
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. " EN   ,ID enable" "0,1"
group.long 0x4++0x3
line.long 0x00 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. " MASK ,RequesterID mask"
hexmask.long.word 0x00 0.--15. 1. "  RID ,RequesterID"
group.long 0x8++0x3
line.long 0x00 "PCIE_VMAP_HP_VIRTID_j,Virt ID register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 0.--11. 1. " VID  ,Match ID"
width 0x0B
tree.end
tree "PCIE1_CORE_VMAP_HP_MMRS"
base ad:0x2918000
width 23.
group.long 0x0++0x3
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. " EN   ,ID enable" "0,1"
group.long 0x4++0x3
line.long 0x00 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. " MASK ,RequesterID mask"
hexmask.long.word 0x00 0.--15. 1. "  RID ,RequesterID"
group.long 0x8++0x3
line.long 0x00 "PCIE_VMAP_HP_VIRTID_j,Virt ID register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 0.--11. 1. " VID  ,Match ID"
width 0x0B
tree.end
tree.end
tree "PCIE_VMAP_LP"
tree "PCIE0_CORE_VMAP_LP_MMRS"
base ad:0x2900000
width 23.
group.long 0x0++0x3
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. " EN   ,ID enable" "0,1"
group.long 0x4++0x3
line.long 0x00 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. " MASK ,RequesterID mask"
hexmask.long.word 0x00 0.--15. 1. "  RID ,RequesterID"
group.long 0x8++0x3
line.long 0x00 "PCIE_VMAP_LP_VIRTID_j,Virt ID register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 0.--11. 1. " VID  ,Match ID"
width 0x0B
tree.end
tree "PCIE1_CORE_VMAP_LP_MMRS"
base ad:0x2910000
width 23.
group.long 0x0++0x3
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. " EN   ,ID enable" "0,1"
group.long 0x4++0x3
line.long 0x00 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. " MASK ,RequesterID mask"
hexmask.long.word 0x00 0.--15. 1. "  RID ,RequesterID"
group.long 0x8++0x3
line.long 0x00 "PCIE_VMAP_LP_VIRTID_j,Virt ID register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x00 0.--11. 1. " VID  ,Match ID"
width 0x0B
tree.end
tree.end
tree "PDMA0"
base ad:0x2A41000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PDMA0_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                      ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID               ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                  ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                  ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                  ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                  ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PDMA0_ECC_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PDMA0_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PDMA0_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PDMA0_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PDMA0_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PDMA0_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PDMA0_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PDMA0_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PDMA0_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 1. " TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PDMA0_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PDMA0_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                 ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                  ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PDMA0_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PDMA0_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PDMA0_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "PDMA1"
base ad:0x2A42000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "PDMA1_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                      ,bu" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID               ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                  ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " REVMAJ                  ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                  ,Custom version" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " REVMIN                  ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PDMA1_ECC_VECTOR,ECC Vector Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "PDMA1_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PDMA1_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PDMA1_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 4. " L2G_RAMECC_PEND         ,Interrupt Pending Status for l2g_ramecc_pend" "0,1"
bitfld.long 0x00 3. "     RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "     TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PDMA1_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. " L2G_RAMECC_ENABLE_SET   ,Interrupt Enable Set Register for l2g_ramecc_pend" "0,1"
bitfld.long 0x00 3. "     RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "     TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PDMA1_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x13C++0x3
line.long 0x00 "PDMA1_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PDMA1_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 4. " L2G_RAMECC_PEND         ,Interrupt Pending Status for l2g_ramecc_pend" "0,1"
bitfld.long 0x00 3. "     RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "     TPCF1_RAMECC_PEND       ,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " TPCF0_RAMECC_PEND       ,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PDMA1_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. " L2G_RAMECC_ENABLE_SET   ,Interrupt Enable Set Register for l2g_ramecc_pend" "0,1"
bitfld.long 0x00 3. "     RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 2. " RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "     TPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
textline "                                        "
bitfld.long 0x00 0. " TPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PDMA1_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                        "
group.long 0x200++0x3
line.long 0x00 "PDMA1_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                 ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                  ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PDMA1_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                        "
group.long 0x208++0x3
line.long 0x00 "PDMA1_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PDMA1_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "PDMA_DEBUG"
base ad:0x2A40000
width 36.
rgroup.long 0x0++0x3
line.long 0x00 "PDMA_DEBUG_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                      ,bu" "0,1,2,3"
textline "                                             "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID               ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                  ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                             "
bitfld.long 0x00 8.--10. " REVMAJ                  ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                  ,Custom version" "0,1,2,3"
textline "                                             "
bitfld.long 0x00 0.--5. " REVMIN                  ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "PDMA_DEBUG_ECC_VECTOR,ECC Vector Register"
in
textline "                                             "
rgroup.long 0xC++0x3
line.long 0x00 "PDMA_DEBUG_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "PDMA_DEBUG_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "PDMA_DEBUG_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "PDMA_DEBUG_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "PDMA_DEBUG_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                             "
group.long 0x13C++0x3
line.long 0x00 "PDMA_DEBUG_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                  ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "PDMA_DEBUG_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_PEND       ,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_PEND       ,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "PDMA_DEBUG_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. " RPCF1_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "     RPCF0_RAMECC_ENABLE_SET ,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "PDMA_DEBUG_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                             "
group.long 0x200++0x3
line.long 0x00 "PDMA_DEBUG_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                 ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                  ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "PDMA_DEBUG_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                             "
group.long 0x208++0x3
line.long 0x00 "PDMA_DEBUG_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "PDMA_DEBUG_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                 ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                  ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "RAT"
tree "RAT_0"
base ad:0x40F90000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "RAT_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit: 10 = Processors" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "RAT_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "RAT_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to Fh"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits. 0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "RAT_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region. It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "RAT_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "RAT_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to Fh"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "RAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type. 4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code. 1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "RAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "RAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                        "
group.long 0x848++0x3
line.long 0x00 "RAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "RAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                        "
group.long 0x850++0x3
line.long 0x00 "RAT_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree "RAT_1"
base ad:0x40F90000
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "RAT_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit: 10 = Processors" "0,1,2,3"
textline "                                        "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                        "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "RAT_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "RAT_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to Fh"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits. 0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "RAT_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region. It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "RAT_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region. It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "RAT_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to Fh"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "RAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type. 4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code. 1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                        "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                        "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                        "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "RAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "RAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "RAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                        "
group.long 0x848++0x3
line.long 0x00 "RAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "RAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                        "
group.long 0x850++0x3
line.long 0x00 "RAT_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree.end
tree "RTI"
tree "RTI0"
base ad:0x2200000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree "RTI1"
base ad:0x2210000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree "RTI2"
base ad:0x2220000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree "RTI3"
base ad:0x2230000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree "MCU_RTI0"
base ad:0x40600000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree "MCU_RTI1"
base ad:0x40610000
width 18.
group.long 0x0++0x3
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. " COS             ,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode" "0,1"
bitfld.long 0x00 1. "         CNT1EN        ,Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
textline "                           "
bitfld.long 0x00 0. " CNT0EN          ,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0,1"
group.long 0x4++0x3
line.long 0x00 "RTI_TBCTRL,"
bitfld.long 0x00 1. " INC             ,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock" "0,1"
bitfld.long 0x00 0. "         TBEXT         ,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme" "0,1"
group.long 0x8++0x3
line.long 0x00 "RTI_CAPCTRL,"
bitfld.long 0x00 1. " CAPCNTR1        ,Capture Counter 0." "0,1"
bitfld.long 0x00 0. "         CAPCNTR0      ,Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1" "0,1"
group.long 0xC++0x3
line.long 0x00 "RTI_COMPCTRL,"
bitfld.long 0x00 12. " COMPSEL3        ,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 8. "         COMPSEL2      ,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
textline "                           "
bitfld.long 0x00 4. " COMPSEL1        ,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
bitfld.long 0x00 0. "         COMPSEL0      ,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1" "0,1"
group.long 0x10++0x3
line.long 0x00 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously."
hexmask.long 0x00 0.--31. 1. " FRC0            ,Free Running Counter 0. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters, If counters have to be preset, they have to be stopped from counting in the"
group.long 0x14++0x3
line.long 0x00 "RTI_UC0,"
hexmask.long 0x00 0.--31. 1. " UC0             ,Up Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be stopped from counting in the"
group.long 0x18++0x3
line.long 0x00 "RTI_CPUC0,"
hexmask.long 0x00 0.--31. 1. " CPUC0           ,Compare Up Counter 0. ARRAY(0x1f04380) ARRAY(0x1f04410) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed"
rgroup.long 0x20++0x3
line.long 0x00 "RTI_CAFRC0,"
hexmask.long 0x00 0.--31. 1. " CAFRC0          ,Capture Free Running Counter 0. User and privilege mode (read): value of Free Running Counter 0 on a capture event"
rgroup.long 0x24++0x3
line.long 0x00 "RTI_CAUC0,"
hexmask.long 0x00 0.--31. 1. " CAUC0           ,Capture Up Counter 0. User and privilege mode (read): value of Up Counter 0 on a capture event"
group.long 0x30++0x3
line.long 0x00 "RTI_FRC1,"
hexmask.long 0x00 0.--31. 1. " FRC1            ,Free Running Counter 1. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. If counters have to be preset, they have to be stopped from counting in the"
group.long 0x34++0x3
line.long 0x00 "RTI_UC1,"
hexmask.long 0x00 0.--31. 1. " UC1             ,Up Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Presetting counters: If counters have to be preset, they have to be disabled in the"
group.long 0x38++0x3
line.long 0x00 "RTI_CPUC1,"
hexmask.long 0x00 0.--31. 1. " CPUC1           ,Compare Up Counter 1. ARRAY(0x1f1c750) ARRAY(0x1f1c7e0) User and privilege mode (read): current compare value Privilege mode (write): the compare value is updated"
rgroup.long 0x40++0x3
line.long 0x00 "RTI_CAFRC1,"
hexmask.long 0x00 0.--31. 1. " CAFRC1          ,Capture Free Running Counter 1. User and privilege mode (read): value of Free Running Counter 1 on a capture event"
rgroup.long 0x44++0x3
line.long 0x00 "RTI_CAUC1,"
hexmask.long 0x00 0.--31. 1. " CAUC1           ,Capture Up Counter 1. User and privilege mode (read): value of Up Counter 1 on a capture event"
group.long 0x50++0x3
line.long 0x00 "RTI_COMP0,"
hexmask.long 0x00 0.--31. 1. " COMP0           ,Compare 0. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x54++0x3
line.long 0x00 "RTI_UDCP0,"
hexmask.long 0x00 0.--31. 1. " UDCP0           ,Update Compare 0 Register. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value"
group.long 0x58++0x3
line.long 0x00 "RTI_COMP1,"
hexmask.long 0x00 0.--31. 1. " COMP1           ,Compare 1. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x5C++0x3
line.long 0x00 "RTI_UDCP1,"
hexmask.long 0x00 0.--31. 1. " UDCP1           ,Update Compare 1 Register. User and privilege mode (read): value to be added to the compare 1 register on the next compare match Privilege mode (write): new update value"
group.long 0x60++0x3
line.long 0x00 "RTI_COMP2,"
hexmask.long 0x00 0.--31. 1. " COMP2           ,Compare 2. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x64++0x3
line.long 0x00 "RTI_UDCP2,This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention."
hexmask.long 0x00 0.--31. 1. " UDCP2           ,Update Compare 2 Register. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value"
group.long 0x68++0x3
line.long 0x00 "RTI_COMP3,"
hexmask.long 0x00 0.--31. 1. " COMP3           ,Compare 3. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0x6C++0x3
line.long 0x00 "RTI_UDCP3,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x70++0x3
line.long 0x00 "RTI_TBLCOMP,"
hexmask.long 0x00 0.--31. 1. " UDCP3           ,Update Compare 3 Register. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value"
group.long 0x74++0x3
line.long 0x00 "RTI_TBHCOMP,"
hexmask.long 0x00 0.--31. 1. " TBHCOMP         ,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0."
group.long 0x80++0x3
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " SETOVL1INT      ,Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 17. "         SETOVL0INT    ,Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " SETTBINT        ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 11. "         SETDMA3       ,Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " SETDMA2         ,Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 9. "         SETDMA1       ,Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " SETDMA0         ,Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0,1"
bitfld.long 0x00 3. "         SETINT3       ,Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " SETINT2         ,Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
bitfld.long 0x00 1. "         SETINT1       ,Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 0. " SETINT0         ,Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0,1"
group.long 0x84++0x3
line.long 0x00 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
bitfld.long 0x00 18. " CLEAROVL1INT    ,Clear Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 17. "         CLEAROVL0INT  ,Clear Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 16. " CLEARTBINT      ,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 11. "         CLEARDMA3     ,Clear Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 10. " CLEARDMA2       ,Clear Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
bitfld.long 0x00 9. "         CLEARDMA1     ,Clear Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0,1"
textline "                           "
bitfld.long 0x00 8. " CLEARDMA0       ,Clear Compare DMA Request 0." "0,1"
bitfld.long 0x00 3. "         CLEARINT3     ,Clear Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
textline "                           "
bitfld.long 0x00 2. " CLEARINT2       ,Clear Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
bitfld.long 0x00 1. "         CLEARINT1     ,Clear Compare Interrupt 1." "0,1"
textline "                           "
bitfld.long 0x00 0. " CLEARINT0       ,Clear Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0,1"
rgroup.long 0x88++0x3
line.long 0x00 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value, regardless if the interrupt is enabled or not."
bitfld.long 0x00 18. " OVL1INT         ,Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 17. "         OVL0INT       ,Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 3. " INT3            ,Interrupt Flag 3. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 2. "         INT2          ,Interrupt Flag 2. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
textline "                           "
bitfld.long 0x00 1. " INT1            ,Interrupt Flag 1. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
bitfld.long 0x00 0. "         INT0          ,Interrupt Flag 0. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0,1"
group.long 0x90++0x3
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be always enabled or not. If the DWD is always enabled, then the DWD is automatically enabled after system reset is released and cannot be disabled by software. In that case, this register is redundant and any writes to this register have no effect on the DWD functionality. If, however, the DWD is not enabled upon release of system reset, then the software has to write to the DWDCTRL field in order to enable the DWD, as described below. Once enabled, the watchdog can only be disabled by a system reset. The application cannot disable the watchdog. The register also implements a one-time-write constraint. That is, once the application writes to this register to enable the watchdog, all further writes are ignored."
hexmask.long 0x00 0.--31. 1. " DWDCTRL         ,Digital Watchdog Control. User and privilege mode (read): 5312ACEDh = DWD counter is disabled. This is the default value. A98559DAh = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Privilege mode (write): A98559DAh = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) One-Write Functionality of DWDCTRL Register: The"
group.long 0x94++0x3
line.long 0x00 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD         ,Digital Watchdog Preload Value. User and privilege mode (read): A read from this register in any CPU mode returns the current preload value. Privilege mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: ARRAY(0x1F75D70) where:"
rgroup.long 0x98++0x3
line.long 0x00 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These bits are cleared by a power up reset, or by the application."
bitfld.long 0x00 5. " DWWD_ST         ,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and privilege mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Privilege mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the" "0,1"
bitfld.long 0x00 4. "         END_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
textline "                           "
bitfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0." "0,1"
bitfld.long 0x00 2. "         KEYST         ,Watchdog KeyStatus." "0,1"
textline "                           "
bitfld.long 0x00 1. " DWDST           ,Digital Watchdog Status." "0,1"
bitfld.long 0x00 0. "         AWDST         ,Analog Watchdog Status." "0,1"
group.long 0x9C++0x3
line.long 0x00 "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 0.--15. 1. " WDKEY           ,Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1 s. Writing any other value causes a digital watchdog reset. Register write access time precaution: The user has to take into account that the write to the register takes 3 RTI_ICLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Step 1:"
rgroup.long 0xA0++0x3
line.long 0x00 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information, see , RTI Not Supported Features."
hexmask.long.word 0x00 16.--24. 1. " DWDCNTR_24_16   ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
hexmask.long.word 0x00 0.--15. 1. "      DWDCNTR_15_0  ,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002DFFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don t have an effect."
group.long 0xA4++0x3
line.long 0x00 "RTI_WWDRXNCTRL,"
bitfld.long 0x00 0.--3. " WWDRXN          ,Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Configuration of DWWD Reaction: The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x1
line.word 0x00 "RTI_WWDSIZECTRL,"
hexmask.word 0x00 0.--15. 1. "     WWDSIZE         ,Same as below. Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE: 0x00000005 = 100% Window Size (The functionality is the same as the standard time-out digital watchdog.) Value written to WWDSIZE: 0x00000050 = 50% Window Size Value written to WWDSIZE: 0x00000500 = 25% Window Size Value written to WWDSIZE: 0x00005000 = 12.5% Window Size Value written to WWDSIZE: 0x00050000 = 6.25% Window Size Value written to WWDSIZE: 0x00500000 = 3.125% Window Size Value written to WWDSIZE: Any other value = 3.125% Window Size Incorrect value being written to watchdog window size control register: If an incorrect value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Configuration of DWWD Window Size: The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced."
group.long 0xAC++0x3
line.long 0x00 "RTI_INTCLRENABLE,"
bitfld.long 0x00 24.--27. " INTCLRENABLE3   ,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        INTCLRENABLE2 ,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " INTCLRENABLE1   ,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        INTCLRENABLE0 ,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. Hook-up of Compare Interrupt to a device pin: The RTI module generates up to 4 compare interrupts. The connection between one or more of these compare interrupt(s) to a device pin is completely device-dependent. Refer to the device datasheet to identify the actual pin(s) that connects to the compare interrupt(s)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB0++0x3
line.long 0x00 "RTI_COMP0CLR,"
hexmask.long 0x00 0.--31. 1. " COMP0CLR        ,Compare 0 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB4++0x3
line.long 0x00 "RTI_COMP1CLR,"
hexmask.long 0x00 0.--31. 1. " COMP1CLR        ,Compare 1 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xB8++0x3
line.long 0x00 "RTI_COMP2CLR,"
hexmask.long 0x00 0.--31. 1. " COMP2CLR        ,Compare 2 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
group.long 0xBC++0x3
line.long 0x00 "RTI_COMP3CLR,"
hexmask.long 0x00 0.--31. 1. " COMP3CLR        ,Compare 3 Clear. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Reset behavior: A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled."
width 0x0B
tree.end
tree.end
tree "SerDes"
tree "SERDES0"
base ad:0x900000
width 18.
group.long 0x0++0x3
line.long 0x00 "CMU_R000,The cmu_000 register"
hexmask.long.byte 0x00 24.--30. 1. " CMU_PLL_CTRL1_6_0_O                            ,CMU PLL control 1 register [6:0]"
group.long 0x4++0x3
line.long 0x00 "CMU_R004,The cmu_004 register"
bitfld.long 0x00 12. " REFCLK_CTRL1                                   ,Refclk control 1 register" "0,1"
bitfld.long 0x00 11. "       CMU_PLL_CTRL4                                  ,CMU PLL control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 10. " CMU_PLL_CTRL3                                  ,CMU PLL control 3 register" "0,1"
bitfld.long 0x00 8.--9. "       CMU_PLL_CTRL2_9_8                              ,CMU PLL control 2 register [9:8]" "0,1,2,3"
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " CMU_PLL_CTRL2_7_0                              ,CMU PLL control 2 register [7:0]"
group.long 0x8++0x3
line.long 0x00 "CMU_R008,The cmu_008 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_15_8                             ,CMU FSM control 1 register 15-8"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_7_0                              ,CMU FSM control 1 register 7-0"
group.long 0xC++0x3
line.long 0x00 "CMU_R00C,The cmu_00c register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_47_40                            ,CMU FSM control 1 register 47-40"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_39_32                            ,CMU FSM control 1 register 39-32"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_31_24                            ,CMU FSM control 1 register 31-24"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_23_16                            ,CMU FSM control 1 register 23-16"
group.long 0x10++0x3
line.long 0x00 "CMU_R010,The cmu_010 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_79_72                            ,CMU FSM control 1 register 79-72"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_71_64                            ,CMU FSM control 1 register 71-64"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_63_56                            ,CMU FSM control 1 register 63-56"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_55_48                            ,CMU FSM control 1 register 55-48"
group.long 0x14++0x3
line.long 0x00 "CMU_R014,The cmu_014 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_111_104                          ,CMU FSM control 1 register 111-104"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_103_96                           ,CMU FSM control 1 register 103-96"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_95_88                            ,CMU FSM control 1 register 95-88"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_87_80                            ,CMU FSM control 1 register 87-80"
group.long 0x18++0x3
line.long 0x00 "CMU_R018,The cmu_018 register"
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_127_120                          ,CMU FSM control 1 register 127-120"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_119_112                          ,CMU FSM control 1 register 119-112"
group.long 0x5C++0x3
line.long 0x00 "CMU_R05C,The cmu_05c register"
bitfld.long 0x00 31. " AHB_PMA_CM_C1_SEL_O                            ,CMU LF C1 cap select. Enabling increases C1 cap." "0,1"
bitfld.long 0x00 30. "       AHB_PMA_CM_I_HIZ_O                             ,CMU PLL HIZ setting" "0,1"
textline "                           "
bitfld.long 0x00 28.--29. " AHB_PMA_CM_I_CP_SEL_O                          ,Charge pump current gain select." "0,1,2,3"
bitfld.long 0x00 26.--27. "       AHB_PMA_CM_FORCE_ILF_O                         ,CMU loop filter force to common mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " AHB_PMA_CM_I_KVCO_SEL_O                        ,CMU VCO integral path gain" "0,1,2,3"
group.long 0x60++0x3
line.long 0x00 "CMU_R060,The cmu_060 register"
hexmask.long.byte 0x00 24.--31. 1. " AHB_PMA_CM_AFE_CNTL_O                          ,CMU AFE spares"
bitfld.long 0x00 22.--23. "      AHB_PMA_CM_VREGREF_O                           ,CMU reference clock regulator setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 21. " AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O            ,CMU VCO PMOS proportional current decrease" "0,1"
bitfld.long 0x00 20. "       AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O            ,CMU VCO PMOS proportional current increase" "0,1"
textline "                           "
bitfld.long 0x00 19. " AHB_PMA_CM_V2I_FILTER_SW_ON_O                  ,CMU V2I filter enable" "0,1"
bitfld.long 0x00 18. "       SR_NDIV_OVR_ENA_O                              ,Override enable for overriding N-div value" "0,1"
textline "                           "
bitfld.long 0x00 17. " AHB_PMA_CM_PFD_FORCE_UP_O                      ,Force PFD to output up" "0,1"
bitfld.long 0x00 16. "       AHB_PMA_CM_PFD_FORCE_DN_O                      ,Force PFD to output down" "0,1"
textline "                           "
bitfld.long 0x00 14.--15. " AHB_PMA_CM_VREGH_O                             ,CMU VREGH setting" "0,1,2,3"
bitfld.long 0x00 12.--13. "       AHB_PMA_CM_VREG_O                              ,CMU VREG setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--11. " AHB_PMA_CM_VCO_BIAS_O                          ,CMU VCO bias current setting." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "      AHB_PMA_CM_BGSTART_BYP_O                       ,Bandgap startup circuit bypass" "0,1"
textline "                           "
bitfld.long 0x00 4.--6. " AHB_PMA_CM_I_CAP_SEL_O                         ,CMU VCO integral path cap select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "       AHB_PMA_CM_CHPMP_CHOP_ENAN_O                   ,Charge pump chop enable" "0,1"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_PMA_CM_P_CAP_SEL_O                         ,CMU VCO proportional path cap select" "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CMU_R064,The cmu_064 register"
hexmask.long.byte 0x00 8.--14. 1. " AHB_PMA_CM_DIVPSEL_O                           ,CMU P-divider setting"
bitfld.long 0x00 3.--7. "      AHB_PMA_CM_P_KVCO_SEL_O                        ,CMU PLL KVCO setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 2. " AHB_PMA_CM_I_DROPI_O                           ,Enable to reduce charge pump reference current" "0,1"
bitfld.long 0x00 0.--1. "       AHB_PMA_CM_PFD_PW_O                            ,PFD pulse width setting" "0,1,2,3"
group.long 0x6C++0x3
line.long 0x00 "CMU_R06C,The cmu_06c register"
bitfld.long 0x00 15. " PMA_REFCLK_QFWD_R_O                            ,Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o" "0,1"
bitfld.long 0x00 14. "       PMA_REFCLK_QFWD_L_O                            ,Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
textline "                           "
bitfld.long 0x00 11. " PMA_RXCLK_OE_R_O                               ,Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
bitfld.long 0x00 10. "       PMA_RXCLK_OE_L_O                               ,'Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o'" "0,1"
textline "                           "
bitfld.long 0x00 9. " PMA_REFCLK_OE_R_O                              ,'Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o'" "0,1"
bitfld.long 0x00 8. "       PMA_REFCLK_OE_L_O                              ,Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
textline "                           "
bitfld.long 0x00 7. " PMA_REFCLK_SEL_OVR_O                           ,Reference clock select override" "0,1"
bitfld.long 0x00 3.--6. "       PMA_REFCLK_OUTPUT_SEL_O_3_0                    ,Reference clock output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 0.--2. " PMA_CM_SR_BIAS_TC_TRIM_O                       ,sr bias tc trim drving to PMA" "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CMU_R070,The cmu_070 register"
bitfld.long 0x00 29. " EN_FRACN_FRCDIV_MODE_O                         ,Enable fractional division mode and SSC mode" "0,1"
bitfld.long 0x00 28. "       SSC_GEN_FRACSYN_EN_O                           ,Enable for SSC generator with Fractional Synthesis" "0,1"
textline "                           "
bitfld.long 0x00 5. " SSC_EN_O                                       ,Active high Enable for SSC block synth or SSC mode" "0,1"
bitfld.long 0x00 4. "       SSC_GEN_EN_O                                   ,Active high Enable for SSC generator SSC mode" "0,1"
group.long 0x74++0x3
line.long 0x00 "CMU_R074,The cmu_074 register"
group.long 0x78++0x3
line.long 0x00 "CMU_R078,The cmu_078 register"
bitfld.long 0x00 29. " PMA_CM_RX_TERM_OVR_EN_O                        ,Rx Termination override enable" "0,1"
bitfld.long 0x00 24.--28. "       PMA_CM_RX_TERM_OVR_O                           ,Rx Termination override value, every rx lane gets the same value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 21. " PMA_CM_REFCLK_TERM_OVR_EN_O                    ,Refclk Termination override enable" "0,1"
bitfld.long 0x00 16.--20. "       PMA_CM_REFCLK_TERM_OVR_O                       ,Refclk Termination override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C++0x3
line.long 0x00 "CMU_R07C,The cmu_07c register"
bitfld.long 0x00 24. " CMU_MASTER_CDN_O                               ,Master reset for CMU" "0,1"
group.long 0x80++0x3
line.long 0x00 "CMU_R080,The cmu_080 register"
bitfld.long 0x00 24.--27. " TBUS_DATA_SMPL_11_8                            ,Snapshot of digital test bus data [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "      TBUS_DATA_SMPL_7_0                             ,Snapshot of digital test bus data [7:0]"
textline "                           "
bitfld.long 0x00 12.--13. " CMU_OUT_OVR_O_1_0                              ,Override for Reset_smu_fl" "0,1,2,3"
bitfld.long 0x00 8.--11. "       CMU_IN_OVR_O_3_0                               ,Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " AMUX_OVR_O_7_0                                 ,Not used"
group.long 0x84++0x3
line.long 0x00 "CMU_R084,The cmu_084 register"
bitfld.long 0x00 8.--10. " TBUS_ADDR_OVR_O_10_8                           ,CMU Test Bus address 10-8" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "       TBUS_ADDR_OVR_O_7_0                            ,CMU Test Bus address 7-0"
group.long 0x88++0x3
line.long 0x00 "CMU_R088,The cmu_088 register"
bitfld.long 0x00 30.--31. " AHB_PMA_CM_VREGH_GEN3_O                        ,CMU VREGH setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
bitfld.long 0x00 28.--29. "       AHB_PMA_CM_VREG_GEN3_O                         ,CMU VREG setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--27. " AHB_PMA_CM_VCO_BIAS_GEN3_O                     ,CMU VCO bias current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--22. "      AHB_PMA_CM_I_CAP_SEL_GEN3_O                    ,CMU VCO integral path cap select" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19. " AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O              ,Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config" "0,1"
bitfld.long 0x00 16.--18. "       AHB_PMA_CM_P_CAP_SEL_GEN3_O                    ,CMU VCO proportional path cap select" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 15. " AHB_PMA_CM_C1_SEL_GEN3_O                       ,CMU LF C1 cap select. Enabling increases C1 cap." "0,1"
bitfld.long 0x00 14. "       AHB_PMA_CM_I_HIZ_GEN3_O                        ,CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config" "0,1"
textline "                           "
bitfld.long 0x00 12.--13. " AHB_PMA_CM_I_CP_SEL_GEN3_O                     ,Charge pump current gain select." "0,1,2,3"
bitfld.long 0x00 10.--11. "       AHB_PMA_CM_FORCE_ILF_GEN3_O                    ,CMU LF Force value in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " AHB_PMA_CM_I_KVCO_SEL_GEN3_O                   ,CMU VCO proportional current gain" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x00 "CMU_R08C,The cmu_08c register"
hexmask.long.byte 0x00 24.--30. 1. " AHB_PMA_CM_DIVPSEL_GEN3_O                      ,CMU P-divider setting in gen3 rate Used only in PCIe3 1CMU config"
bitfld.long 0x00 19.--23. "      AHB_PMA_CM_P_KVCO_SEL_GEN3_O                   ,CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 18. " AHB_PMA_CM_I_DROPI_GEN3_O                      ,Enable to reduce charge pump reference current" "0,1"
bitfld.long 0x00 16.--17. "       AHB_PMA_CM_PFD_PW_GEN3_O                       ,PFD pulse width setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " AHB_PMA_CM_AFE_CNTL_GEN3_O                     ,CMU AFE spares in gen3 rate Used only in PCIe3 1CMU config"
bitfld.long 0x00 5.--6. "      AHB_PMA_CM_VREGREF_GEN3_O                      ,CMU VDREGREF setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 4. " AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O       ,CMU VCO PMOS proportional current decrease" "0,1"
bitfld.long 0x00 3. "       AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O       ,CMU VCO PMOS proportional current increase" "0,1"
textline "                           "
bitfld.long 0x00 2. " AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O             ,CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config" "0,1"
bitfld.long 0x00 1. "       AHB_PMA_CM_PFD_FORCE_UP_GEN3_O                 ,Force PFD to output up in gen3 rate Used only in PCIe3 1CMU config" "0,1"
textline "                           "
bitfld.long 0x00 0. " AHB_PMA_CM_PFD_FORCE_DN_GEN3_O                 ,Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config" "0,1"
group.long 0x90++0x3
line.long 0x00 "CMU_R090,The cmu_090 register"
bitfld.long 0x00 0.--2. " AHB_PMA_CM_VCOFR_GEN3_O                        ,Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "LANE_R000,The lane_000 register"
bitfld.long 0x00 23. " AHB_RX_CLK_BRCH4_DIV_SEL_O                     ,Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 20.--22. "       AHB_RX_CLK_BRCH4_SRC_SEL_O                     ,Clock source select for RX path branch 4 clock : 3'b 000 - qd_ck_i 3'b 001- pma_lX_rxb_iRecovered byte clock 3'b 010 - lnX_clk_i 3'b 011 - pma_lX_txb_iTransmit byte clock 3'b 100 - ck_soc1_int_root 3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19. " AHB_RX_CLK_BRCH3_DIV_SEL_O                     ,Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 16.--18. "       AHB_RX_CLK_BRCH3_SRC_SEL_O                     ,Clock source select for RX path branch 3 clock : 3'b 000 - qd_ck_i 3'b 001- pma_lX_rxb_iRecovered byte clock 3'b 010 - lnX_clk_i 3'b 011 - pma_lX_txb_iTransmit byte clock 3'b 100 - ck_soc1_int_root 3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 15. " AHB_RX_CLK_BRCH2_DIV_SEL_O                     ,Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 12.--14. "       AHB_RX_CLK_BRCH2_SRC_SEL_O                     ,Clock source select for RX path branch 2 clock : 3'b 000 - pma_lX_rxb_iRecovered byte clock 3'b 001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 11. " AHB_RX_CLK_BRCH1_DIV_SEL_O                     ,Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 8.--10. "       AHB_RX_CLK_BRCH1_SRC_SEL_O                     ,Clock source select for RX path branch 1 clock : 3'b 000 - pma_lX_rxb_iRecovered byte clock 3'b 001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 7. " AHB_TX_CLK_BRCH2_DIV_SEL_O                     ,Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 4.--6. "       AHB_TX_CLK_BRCH2_SRC_SEL_O                     ,Clock source select for TX path branch 2 clock : 3'b 000 - lnX_clk_i 3'b 001- qd_ck_i 3'b 011 - ck_soc1_int_root 3'b010,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_0_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_TX_CLK_BRCH1_SRC_SEL_O                     ,Clock source select for TX path branch 1 clock : 3'b 000 - lnX_clk_i 3'b 001- qd_ck_i 3'b 010 - pma_lX_rxb_iRecovered byte clock 3'b 011 - ck_soc1_int_root 3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_0_i" "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "LANE_R004,The lane_004 register"
bitfld.long 0x00 31. " BIST_GEN_EN_O                                  ,Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data" "0,1"
bitfld.long 0x00 30. "       BIST_GEN_WORD_O                                ,Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20" "0,1"
textline "                           "
bitfld.long 0x00 29. " BIST_GEN_CDN_O                                 ,Bist generator master reset." "0,1"
bitfld.long 0x00 28. "       BIST_TX_CLOCK_ENABLE                           ,Active HIGH clock enable signal for the BIST transmit clock" "0,1"
textline "                           "
bitfld.long 0x00 27. " BIST_GEN_ERR_O                                 ,Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern." "0,1"
bitfld.long 0x00 26. "       BIST_GEN_MODE8B_O                              ,Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits" "0,1"
textline "                           "
bitfld.long 0x00 24.--25. " BIST_RATE_O                                    ,Rate control for BIST" "0,1,2,3"
bitfld.long 0x00 23. "       PMA_LN_TXDRV_BLEED_ENA_RATE1_O                 ,txdrv regulator bleed enable for gen3 rate" "0,1"
textline "                           "
bitfld.long 0x00 22. " PMA_LN_TXDRV_BLEED_ENA_RATE2_O                 ,txdrv regulator bleed enable for gen2 rate" "0,1"
bitfld.long 0x00 21. "       DR_TXDRV_REG_BLEED_EN_O                        ,txdrv regulator bleed enable for gen1 rate" "0,1"
textline "                           "
bitfld.long 0x00 7. " CDR_IQ_CAL_EN_O                                ,IQ Calibration enable" "0,1"
group.long 0x208++0x3
line.long 0x00 "LANE_R008,The lane_008 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_GEN_EN_HIGH_O_7_0                         ,Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information."
hexmask.long.byte 0x00 16.--23. 1. "      BIST_GEN_EN_LOW_O_15_8                         ,Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test."
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_GEN_EN_LOW_O_7_0                          ,Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test."
bitfld.long 0x00 4.--6. "      BIST_GEN_INSERT_COUNT_O_2_0                    ,Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 3. " BIST_GEN_SEND_PREAM_O                          ,Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble." "0,1"
group.long 0x20C++0x3
line.long 0x00 "LANE_R00C,The lane_00c register"
bitfld.long 0x00 31. " BIST_RX_CLOCK_ENABLE                           ,Active HIGH clock enable signal for the BIST receive clock" "0,1"
bitfld.long 0x00 28.--29. "       BIST_CHK_LFSR_LENGTH_O_1_0                     ,BIST PRBS pattern selector." "0,1,2,3"
textline "                           "
bitfld.long 0x00 27. " BIST_CHK_DATA_MODE_O                           ,Bist checker mode select. 0X0 UDP pattern. 0x1 PRBS pattern" "0,1"
bitfld.long 0x00 24.--25. "       BCHK_SRC_O_1_0                                 ,BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks" "0,1,2,3"
textline "                           "
bitfld.long 0x00 22. " BCHK_CLR_O                                     ,BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block" "0,1"
bitfld.long 0x00 21. "       BCHK_EN_O                                      ,BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate" "0,1"
textline "                           "
bitfld.long 0x00 16.--19. " BIST_GEN_INSERT_DELAY_O_11_8                   ,Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "      BIST_GEN_INSERT_DELAY_O_7_0                    ,Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " BIST_GEN_EN_HIGH_O_15_8                        ,Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information."
group.long 0x210++0x3
line.long 0x00 "LANE_R010,The lane_010 register"
bitfld.long 0x00 24.--25. " BIST_CHK_PREAM1_O_9_8                          ,BIST Check Preamble" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "       BIST_CHK_PREAM1_O_7_0                          ,BIST Check Preamble"
textline "                           "
bitfld.long 0x00 13. " BIST_CHK_SYNC_ON_ZEROS                         ,Setting this bit allows BIST to sync to RX value of zero" "0,1"
bitfld.long 0x00 10.--12. "       BIST_CHK_INSERT_LENGTH_O_2_0                   ,BIST Checker Insert word length." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--9. " BIST_CHK_PREAM0_O_9_8                          ,Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block." "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "       BIST_CHK_PREAM0_O_7_0                          ,Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block."
group.long 0x214++0x3
line.long 0x00 "LANE_R014,The lane_014 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_UDP_O_31_24                           ,BIST Check User-defined pattern"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_UDP_O_23_16                           ,BIST Check User-defined pattern"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_UDP_O_15_8                            ,BIST Check User-defined pattern"
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_UDP_O_7_0                             ,BIST checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode."
group.long 0x218++0x3
line.long 0x00 "LANE_R018,The lane_018 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_INSERT_WORD_O_23_16                   ,Bist checker insertion word."
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_INSERT_WORD_O_15_8                    ,Bist checker insertion word."
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_INSERT_WORD_O_7_0                     ,Bist checker insertion word."
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_UDP_O_39_32                           ,BIST Check User-defined pattern"
group.long 0x21C++0x3
line.long 0x00 "LANE_R01C,The lane_01c register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_ERROR_15_8                            ,Bist errors detected"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_ERROR_7_0                             ,Bist errors detected"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_INSERT_WORD_O_39_32                   ,Bist checker insertion word."
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_INSERT_WORD_O_31_24                   ,Bist checker insertion word."
group.long 0x220++0x3
line.long 0x00 "LANE_R020,The lane_020 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_31_24                           ,LANE FSM control 1 register 31-24"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_23_16                           ,LANE FSM control 1 register 23-16"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_15_8                            ,LANE FSM control 1 register 15-8"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_7_0                             ,LANE FSM control 1 register 7-0"
group.long 0x224++0x3
line.long 0x00 "LANE_R024,The lane_024 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_63_56                           ,LANE FSM control 1 register 63-56"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_55_48                           ,LANE FSM control 1 register 55-48"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_47_40                           ,LANE FSM control 1 register 47-40"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_39_32                           ,LANE FSM control 1 register 39-32"
group.long 0x228++0x3
line.long 0x00 "LANE_R028,The lane_028 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_95_88                           ,LANE FSM control 1 register 95-88"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_87_80                           ,LANE FSM control 1 register 87-80"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_79_72                           ,LANE FSM control 1 register 79-72"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_71_64                           ,LANE FSM control 1 register 71-64"
group.long 0x22C++0x3
line.long 0x00 "LANE_R02C,The lane_02c register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_127_120                         ,LANE FSM control 1 register 127-120"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_119_112                         ,LANE FSM control 1 register 119-112"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_111_104                         ,LANE FSM control 1 register 111-104"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_103_96                          ,LANE FSM control 1 register 103-96"
group.long 0x230++0x3
line.long 0x00 "LANE_R030,The lane_030 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_HS_CAL_CNTR2_7_0                          ,LANE High speed calibration counter 2 length [7:0]"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_LS_CAL_CNTR2_7_0                          ,LANE Low speed calibration counter 2 length [7:0]"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_LS_CAL_CNTR1_7_0                          ,LANE Low speed calibration counter 1 length [7:0]"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_HS_CAL_CNTR1_7_0                          ,LANE High speed calibration counter 1 length [7:0]"
group.long 0x240++0x3
line.long 0x00 "LANE_R040,The lane_040 register"
bitfld.long 0x00 31. " LANE_RXIDLE_CTRL1_8                            ,LANE RXIDLE control 1 register [8]" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "       LANE_RXIDLE_CTRL2_6_0                          ,LANE RXIDLE control 2 register [6:0]"
textline "                           "
hexmask.long.byte 0x00 16.--23. 1. " LANE_RXIDLE_CTRL1_7_0                          ,LANE RXIDLE control 1 register [7:0]"
bitfld.long 0x00 10. "      BIST_PREAM_STARTED_I                           ,Preamble transmission started during BIST" "0,1"
textline "                           "
bitfld.long 0x00 9. " BIST_LFPS_DONE_I                               ,Minimum LFPS sending completed during BIST" "0,1"
bitfld.long 0x00 6.--7. "       BIST_TREPEAT_PERIOD_SEL_O                      ,Trepeat period select during BIST 00 = 6 us - 01 = 8 us - 10 = 10 us - 11 = 14 us" "0,1,2,3"
textline "                           "
bitfld.long 0x00 4.--5. " BIST_TBURST_PERIOD_SEL_O                       ,Tburst period select during BIST 00 = 0.6 us - 01 = 0.8 us - 10 = 1.0 us - 11 = 1.4 us" "0,1,2,3"
bitfld.long 0x00 0.--3. "       BIST_NUM_MIN_LFPS_O                            ,Minimum number of LFPS bursts to be send during BIST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x244++0x3
line.long 0x00 "LANE_R044,The lane_044 register"
hexmask.long.byte 0x00 16.--23. 1. " LANE_PLL_CTRL1_7_0                             ,LANE PLL control 1 register [7:0]"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_RXIDLE_CTRL3_7_0                          ,LANE RXIDLE control 3 register [7:0]"
group.long 0x248++0x3
line.long 0x00 "LANE_R048,The lane_048 register"
bitfld.long 0x00 11.--13. " LANE_RXIDLE_CTRL2_9_7                          ,LANE RXIDLE control 2 register [9:7]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "       LANE_RXEQ_CTRL1                                ,LANE RXEQ control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 9. " LANE_PLL_CTRL3                                 ,LANE PLL control 3 register" "0,1"
bitfld.long 0x00 8. "       LANE_PLL_CTRL2                                 ,LANE PLL control 2 register" "0,1"
group.long 0x24C++0x3
line.long 0x00 "LANE_R04C,The lane_04c register"
bitfld.long 0x00 24. " SYM_ALIGN_BYPASS_O                             ,Asserting this register will bypass the symbol aligner" "0,1"
group.long 0x254++0x3
line.long 0x00 "LANE_R054,The lane_054 register"
bitfld.long 0x00 18. " RXCLK_LB_ENA_O                                 ,HS recovered clock to transmit loopback enable." "0,1"
bitfld.long 0x00 17. "       NES_LB_ENA_O                                   ,NES loopback enable." "0,1"
textline "                           "
bitfld.long 0x00 16. " FES_LB_ENA_O                                   ,FES loopback enable." "0,1"
bitfld.long 0x00 12. "       LOOPBACK_EN_O                                  ,Control signal to force decoder into loopback mode" "0,1"
group.long 0x258++0x3
line.long 0x00 "LANE_R058,The lane_058 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_PLL_CTRL5_7_0                             ,LANE PLL control 5 register [7:0]"
bitfld.long 0x00 22.--23. "      AHB_PMA_LN_VREGH_O                             ,Regulator VREGH setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 19.--21. " AHB_PMA_LN_AGC_THSEL_O                         ,AGC threshold select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "       LANE_PLL_CTRL4                                 ,RX FL calibration clock DIV4 enable" "0,1"
textline "                           "
bitfld.long 0x00 11.--13. " AHB_PMA_LN_SD_THSEL_DIV2_O                     ,Signal detect threshold select for div-by-2 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "       AHB_PMA_LN_SD_THSEL_DIV1_O                     ,Signal detect threshold select for Full rate" "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "LANE_R05C,The lane_05c register"
bitfld.long 0x00 28.--30. " AHB_PMA_LN_INT_STEP_O                          ,CDR int step" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "       AHB_PMA_LN_BB_STEP_O                           ,CDR bb_step" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 6. " LANE_PLL_CTRL7                                 ,LANE PLL control 7 register" "0,1"
bitfld.long 0x00 2.--5. "       LANE_PLL_CTRL6_3_0                             ,LANE PLL control 6 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 0.--1. " LANE_PLL_CTRL5_9_8                             ,LANE PLL control 5 register [9:8]" "0,1,2,3"
group.long 0x260++0x3
line.long 0x00 "LANE_R060,The lane_060 register"
bitfld.long 0x00 25. " LANE_RXEQ_CTRL3                                ,LANE RXEQ control 3 register" "0,1"
bitfld.long 0x00 24. "       LANE_RXEQ_CTRL2                                ,LANE RXEQ control 2 register" "0,1"
textline "                           "
bitfld.long 0x00 8.--10. " AHB_PMA_LN_RX_SELC_O                           ,CTLE C degeneration select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "       AHB_PMA_LN_RX_SELR_O                           ,CTLE R degeneration select" "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "LANE_R064,The lane_064 register"
bitfld.long 0x00 28.--31. " PMA_LN_TXEQ_POLARITY_O_3_0                     ,TX coefficient polarity enable. Set to '1' for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "      PMA_LN_SD_BWSEL                                ,RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth" "0,1"
textline "                           "
bitfld.long 0x00 10. " PMA_LN_EYE_SGN_RST_O                           ,Reset signal for eye alignment mechanism." "0,1"
bitfld.long 0x00 9. "       EYE_SCAN_CNTR_READY_I                          ,Counter ready signal from eye scan counter block" "0,1"
textline "                           "
bitfld.long 0x00 8. " PMA_LN_EYE_DLY_O_8_8                           ,On-chip eye diagram X-direction offset control: Bits 0- 1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2- 8: Fine x-direction offset, note bit reversal" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "       PMA_LN_EYE_DLY_O_7_0                           ,On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1- 2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3- 9: Fine x-direction offset, note bit reversal"
group.long 0x268++0x3
line.long 0x00 "LANE_R068,The lane_068 register"
bitfld.long 0x00 11. " PMA_LN_TXDRV_BLEED_ENA_RATE3_O                 ,TX bleed enable" "0,1"
bitfld.long 0x00 8.--10. "       PMA_LN_TX_VREG_LEV_O_2_0                       ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "LANE_R06C,The lane_06c register"
bitfld.long 0x00 7. " LANE_PLL_CTRL8                                 ,LANE PLL control 8 register" "0,1"
bitfld.long 0x00 3.--5. "       AHB_PMA_LN_AGC_THSEL_GEN3_O                    ,AGC threshold select for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_PMA_LN_SD_THSEL_GEN3_O                     ,Signal detect threshold select for Gen3" "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "LANE_R070,The lane_070 register"
bitfld.long 0x00 27.--28. " CSR_GEARBOX_BYPASS_OVERRIDE_O                  ,Bypass override for gearbox." "0,1,2,3"
bitfld.long 0x00 24.--26. "       AHB_PMA_LN_RX_SELC_GEN3_O                      ,CTLE R degeneration select for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19.--21. " AHB_PMA_LN_RX_SELR_GEN3_O                      ,CTLE R degeneration select for Gen3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "       AHB_PMA_LN_INT_STEP_GEN3_O                     ,CDR int step for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--11. " AHB_PMA_LN_BB_STEP_GEN3_O                      ,CDR bb_step for Gen3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x274++0x3
line.long 0x00 "LANE_R074,The lane_074 register"
bitfld.long 0x00 23. " PIPE_IF_MAC_RXEQEVAL_OVR_VAL_O                 ,Override value for MAC input rxeqeval" "0,1"
bitfld.long 0x00 22. "       PIPE_IF_MAC_RXEQEVAL_OVR_EN_O                  ,Override enable for MAC input rxeqeval" "0,1"
textline "                           "
bitfld.long 0x00 21. " PIPE_IF_MAC_RXEQ_IN_PROGRESS_OVR_VAL_O         ,Override value for MAC input rxeq in progress" "0,1"
bitfld.long 0x00 20. "       PIPE_IF_MAC_RXEQ_IN_PROGRESS_OVR_EN_O          ,Override enable for MAC input rxeq in progress" "0,1"
textline "                           "
bitfld.long 0x00 19. " PIPE_IF_MAC_INVALID_REQUEST_OVR_VAL_O          ,Override value for MAC input invalid request" "0,1"
bitfld.long 0x00 18. "       PIPE_IF_MAC_INVALID_REQUEST_OVR_EN_O           ,Override enable for MAC input invalid request" "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " EYE_SCAN_ERR_CNT_7_0_I                         ,Error count from eye scan counter block."
group.long 0x278++0x3
line.long 0x00 "LANE_R078,The lane_078 register"
bitfld.long 0x00 26.--29. " AHB_TXDRV_ATT_IN_O                             ,TX Control override for txdrv_att_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25. "      AHB_TXDRV_PREEM_1LSB_MODE_O                    ,TX Control override for txdrv_preem_1lsb_mode" "0,1"
textline "                           "
bitfld.long 0x00 24. " TX_CTRL_O_0                                    ,TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used" "0,1"
bitfld.long 0x00 20.--23. "       AHB_TX_CXN_OVR                                 ,override calibrated txterm value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " AHB_TX_CXP_OVR                                 ,override calibrated txterm value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27C++0x3
line.long 0x00 "LANE_R07C,The lane_07c register"
hexmask.long.byte 0x00 24.--30. 1. " EYE_SCAN_ERR_CNT_14_8_I                        ,Error count from eye scan counter block."
bitfld.long 0x00 23. "      RXEQ_LN_FORCE_CAL_O_6                          ,This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE" "0,1"
textline "                           "
bitfld.long 0x00 12.--15. " AHB_TXDRV_CM_IN_O                              ,TX Control override for txdrv_cm_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      AHB_TXDRV_C2_IN_O                              ,TX Control override for txdrv_c2_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 3.--7. " AHB_TXDRV_C1_IN_O                              ,TX Control override for txdrv_c1_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x280++0x3
line.long 0x00 "LANE_R080,The lane_080 register"
bitfld.long 0x00 0.--4. " EYE_SCAN_ERR_CNT_19_15_I                       ,Error count from eye scan counter block." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x288++0x3
line.long 0x00 "LANE_R088,The lane_088 register"
hexmask.long.byte 0x00 8.--15. 1. " LANE_RXIDLE_CTRL4_7_0                          ,LANE RXIDLE control 4 register [7:0]"
group.long 0x28C++0x3
line.long 0x00 "LANE_R08C,The lane_08c register"
bitfld.long 0x00 24. " LANE_RXEQ_CTRL6                                ,LANE RXEQ control 6 register" "0,1"
rgroup.long 0x290++0x3
line.long 0x00 "LANE_R090,The lane_090 register"
bitfld.long 0x00 3. " BIST_CHK_RECEIVE_PREAM_I                       ,sync receive preamble status form bist rx." "0,1"
bitfld.long 0x00 2. "       BIST_CHK_SYNCH_I                               ,sync check status form bist rx." "0,1"
group.long 0x2A8++0x3
line.long 0x00 "LANE_R0A8,The lane_0a8 register"
bitfld.long 0x00 16. " BLOCK_DEC_ERR                                  ,decoder sync header error" "0,1"
bitfld.long 0x00 0. "       INIT_RX_PRESET_HINT_EN_O                       ,Enable for primary input lnx_rx_preset_hint during init cal." "0,1"
group.long 0x32C++0x3
line.long 0x00 "LANE_R12C,The lane_12c register"
bitfld.long 0x00 30. " TXTERM_CAL_SEQ_EN_O                            ,Txterm calibration enable" "0,1"
bitfld.long 0x00 29. "       WIDTH_CHNG_EN_O                                ,Enable bit for width_chng module" "0,1"
textline "                           "
bitfld.long 0x00 26.--28. " DMUX_TXB_SEL_O_2_0                             ,Transmit mux B data input select enable." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "       REG0_WORD_O                                    ,Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
textline "                           "
bitfld.long 0x00 24. " REG0_BIT_O                                     ,Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
bitfld.long 0x00 22. "       REG0_POL_O                                     ,Used as Reg0 polarity select" "0,1"
textline "                           "
bitfld.long 0x00 21. " REG1_WORD_O                                    ,Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
bitfld.long 0x00 20. "       REG1_BIT_O                                     ,Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
textline "                           "
bitfld.long 0x00 19. " REG1_POL_O                                     ,Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
bitfld.long 0x00 18. "       TREG1_WORD_O                                   ,TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
textline "                           "
bitfld.long 0x00 17. " TREG1_BIT_O                                    ,TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
bitfld.long 0x00 16. "       TREG1_POL_O                                    ,TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
textline "                           "
bitfld.long 0x00 14. " P2S_RBUF_AUTOFIX_O                             ,P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow" "0,1"
bitfld.long 0x00 12.--13. "       DMUX_TXA_SEL_O_1_0                             ,Transmit mux A data input select." "0,1,2,3"
textline "                           "
bitfld.long 0x00 11. " TREG0_WORD_O                                   ,TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
bitfld.long 0x00 10. "       TREG0_BIT_O                                    ,TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
textline "                           "
bitfld.long 0x00 9. " TREG0_POL_O                                    ,TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
bitfld.long 0x00 8. "       RX_SRC_O                                       ,RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder." "0,1"
group.long 0x330++0x3
line.long 0x00 "LANE_R130,The lane_130 register"
bitfld.long 0x00 31. " USB_LFPS_MODE                                  ,Signal Detect USB mode enable. When disabled it bypasses LFPS detection and makes usb mode 0 to PMA" "0,1"
bitfld.long 0x00 30. "       SAPIS_EN_O                                     ,SAPIS interface block enable." "0,1"
textline "                           "
bitfld.long 0x00 29. " PIPE_EN_O                                      ,PIPE interface block enable." "0,1"
bitfld.long 0x00 16.--19. "       AHB_TX_CDAC_OVR                                ,TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 15. " DEC_EN_O                                       ,8b/10b decoder enable." "0,1"
bitfld.long 0x00 14. "       ENC_EN_O                                       ,8b/10b encoder enable." "0,1"
textline "                           "
bitfld.long 0x00 12.--13. " MODE_8B_O_1_0                                  ,8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits" "0,1,2,3"
bitfld.long 0x00 10.--11. "       AHB_LN_TXBIT_REPEAT_O                          ,Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b 00: no bit stuffing nor stripping 2b 01: 2x bit stuffing and stripping 2b 10: NOT USED 2b 11: 4x bit stuffing and stripping" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " AHB_TXMAC_THRESHOLD_O                          ,An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o." "0,1,2,3"
bitfld.long 0x00 5.--6. "       AHB_MAC_WIDTH_O                                ,Data width selector for PCS/MAC interface. 2b 00: GigE or XAUI 2b 01: GigE or XAUI 2b 10: RXAUI 2b 11: XFI" "0,1,2,3"
textline "                           "
bitfld.long 0x00 3.--4. " AHB_LN_RXBIT_STRIP_O                           ,Bit stripping on rxdata from PMA to PCS 2b 00: no bit stripping 2b 01: 2x bit stripping 2b 10: NOT USED 2b 11: 4x bit stripping" "0,1,2,3"
bitfld.long 0x00 0.--2. "       AHB_PMA_SR_TXDRV_TERM_CAL_PSEL_O               ,tx termination calibration comparator threshold select" "0,1,2,3,4,5,6,7"
group.long 0x334++0x3
line.long 0x00 "LANE_R134,The lane_134 register"
bitfld.long 0x00 31. " DIS_EIEOS_CHK_IN_LB_O                          ,Disables the EIEOS check in loopback" "0,1"
bitfld.long 0x00 30. "       DIS_BLOCK_ALIGN_CTRL_O                         ,Disables the primary input lnX_block_align_control" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " PIPE_LFREQ                                     ,LF value for full swing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 21. "      EN_SKPOS_ERR_O                                 ,Enables skpos error status propagation in Gen3" "0,1"
textline "                           "
bitfld.long 0x00 20. " EBUF_SKP_REM_EN_O                              ,Elastic buffer SKP remove enable" "0,1"
bitfld.long 0x00 19. "       RBUF_RSTN_O                                    ,TX FIFO synchronous reset" "0,1"
textline "                           "
bitfld.long 0x00 18. " EBUF_SKP_ADD_EN_O                              ,Elastic buffer SKP add enable" "0,1"
bitfld.long 0x00 17. "       ALIGN_RSTN_O                                   ,Synchronous clear for block/symbol aligner" "0,1"
textline "                           "
bitfld.long 0x00 16. " EBUF_RSTN_O                                    ,Synchronous clear for elastic buffer" "0,1"
bitfld.long 0x00 1. "       BLOCK_ENC_CLR_ERR_O                            ,128b/130b encoder clear error" "0,1"
group.long 0x338++0x3
line.long 0x00 "LANE_R138,The lane_138 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_BEACON_CTRL1_7_0                          ,LANE beacon control 1 register [7:0]"
bitfld.long 0x00 19. "      LANE_REG_CTRL1                                 ,LANE regulator control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 18. " LANE_PLL_CTRL10                                ,LANE PLL control 10 register" "0,1"
bitfld.long 0x00 17. "       LANE_PLL_CTRL9                                 ,LANE PLL control 9 register" "0,1"
textline "                           "
bitfld.long 0x00 16. " GEN1_OLD_RXDATA_SRC                            ,Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i" "0,1"
bitfld.long 0x00 8.--13. "       PIPE_FS_O_5_0                                  ,Full swing value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 2.--5. " P2S_RBUF_BUF_THRESH_O_3_0                      ,TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "      RXVALID_DIS_AT_RATE_CHG_O_0                    ,Value 1 forces rxvalid to be deasserted during rate change to gen 3" "0,1"
textline "                           "
bitfld.long 0x00 0. " COEF_FE_LIMIT_EN_O                             ,FE TxEq Co-efficient Limiting Enable control" "0,1"
group.long 0x33C++0x3
line.long 0x00 "LANE_R13C,The lane_13c register"
bitfld.long 0x00 28.--29. " LOCKED_OVR_O_1_0                               ,Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value." "0,1,2,3"
bitfld.long 0x00 26.--27. "       RXDET_STATUS_OVR_O_1_0                         ,Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value." "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " TXDETECTRX_OVR_O_1_0                           ,Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value." "0,1,2,3"
bitfld.long 0x00 20.--21. "       RXEQ_SIGDET_1_0                                ,Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value" "0,1,2,3"
textline "                           "
bitfld.long 0x00 16.--17. " SIGDET_OVR_O_1_0                               ,Bit[0]: Overide value. Bit[1] :Override enable for signal detect output" "0,1,2,3"
bitfld.long 0x00 12.--15. "       REGP_OVR_3_0                                   ,Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty Bit[1]: Overide values for bit reverse Bit[2]: Overide values for word reverse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 11. " ENC_EN_OVR_O                                   ,Enables 16b/20b encoder" "0,1"
bitfld.long 0x00 10. "       DEC_EN_OVR_O                                   ,Enables 16b/20b decoder" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " LANE_BEACON_CTRL1_11_8                         ,LANE beacon control 1 register [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x3
line.long 0x00 "LANE_R140,The lane_140 register"
hexmask.long.byte 0x00 24.--31. 1. " LN_IN_OVR_O_31_24                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 16.--23. 1. "      LN_IN_OVR_O_23_16                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LN_IN_OVR_O_15_8                               ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 0.--7. 1. "      LN_IN_OVR_O_7_0                                ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
group.long 0x344++0x3
line.long 0x00 "LANE_R144,The lane_144 register"
bitfld.long 0x00 24.--28. " LANE_PLL_CTRL11                                ,Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150ns delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "      LN_IN_OVR_O_49                                 ," "0,1"
textline "                           "
bitfld.long 0x00 22. " OOB_DET_EN                                     ,OOB detect enable" "0,1"
bitfld.long 0x00 18.--21. "       REGP1_OVR_O_3_0                                ,Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty Bit[1]: Overide values for bit reverse Bit[2]: Overide values for word reverse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 17. " AHB_LN_IN_OVR_CHG_FLAG_O                       ,Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes." "0,1"
bitfld.long 0x00 16. "       LN_IN_OVR_O_48                                 ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used" "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LN_IN_OVR_O_47_40                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 0.--7. 1. "      LN_IN_OVR_O_39_32                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
group.long 0x348++0x3
line.long 0x00 "LANE_R148,The lane_148 register"
bitfld.long 0x00 24.--26. " LN_IN_OVR_O_58_56                              ,Override signals for lane: main interface control [57:55]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "       LN_IN_OVR_O_54_51                              ,Override signals for lane: main interface control [46:43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 19. " LN_IN_OVR_O_50                                 ,Override signals for lane: msm_ln_rate_ow [4:2]" "0,1"
bitfld.long 0x00 15. "       LN_IN_OVR_O_65                                 ,Lane Reset" "0,1"
textline "                           "
bitfld.long 0x00 9.--14. " LN_IN_OVR_O_64_59                              ,Override signals for lane: main interface control [53:48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "      LN_IN_OVR_O_55                                 ,Override signals for lane: main interface control[47]" "0,1"
textline "                           "
bitfld.long 0x00 4.--5. " LANE_REG_CTRL4_1_0                             ,LANE regulator control 4 register [1:0]" "0,1,2,3"
bitfld.long 0x00 2.--3. "       LANE_REG_CTRL3_1_0                             ,LANE regulator control 3 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--1. " LANE_REG_CTRL2_1_0                             ,LANE regulator control 2 register [1:0]" "0,1,2,3"
group.long 0x34C++0x3
line.long 0x00 "LANE_R14C,The lane_14c register"
bitfld.long 0x00 24.--26. " PMA_LN_SR_TXREG_ICTRL_RATE2_O                  ,Tx regulator integral path control setting for PCIe3 Gen3 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19.--21. "       PMA_LN_SR_TXREG_ICTRL_RATE3_O                  ,Tx regulator integral path control setting for PCIe3 Gen3 rate" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 18. " PMA_LN_SR_TXDP_REGULATOR_LDR_EN_O              ,Txdp regulator enable for PCIe Gen1/2 rate" "0,1"
bitfld.long 0x00 17. "       PMA_LN_GEN3_SR_TXDP_REGULATOR_LDR_EN_O         ,Txdp regulator enable for PCIe Gen3 rate" "0,1"
textline "                           "
bitfld.long 0x00 10.--11. " AHB_PMA_LN_SR_LANE_VREGTXA_O                   ,Lane VREGTXA setting" "0,1,2,3"
bitfld.long 0x00 8.--9. "       LN_MSM_SR_TXREG_ICTRL_O                        ,vco regulator override" "0,1,2,3"
textline "                           "
bitfld.long 0x00 6.--7. " LN_MSM_DR_REGH_CTRL_OVR_O                      ,vco regulator override" "0,1,2,3"
bitfld.long 0x00 4.--5. "       AHB_PMA_LN_SR_LANE_VREGA_O                     ,Lane VREGA setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 2.--3. " AHB_PMA_LN_SR_SLICER_VCM_SEL_O                 ,Slicer common mode select" "0,1,2,3"
group.long 0xA00++0x3
line.long 0x00 "COMLANE_R000,The comlane_000 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_ALIGN_PATTERN_GEN3_O_15_8             ,BIST alignment pattern for Gen3"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_ALIGN_PATTERN_GEN3_O_7_0              ,BIST alignment pattern for Gen3"
textline "                           "
bitfld.long 0x00 10. " ASYNC_POWER_CHANGE_ACK_EN_O                    ,When asserted supports PIPE 4-3 spec" "0,1"
bitfld.long 0x00 9. "       BIST_GEN_INV_PRBS_O                            ,Enable/Disable the internal PRBS data pattern inverter. 0x0 Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types." "0,1"
textline "                           "
bitfld.long 0x00 8. " BIST_CHK_INV_PRBS_O                            ,Enable/Disable the internal PRBS data pattern inverter. 0x0 Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types." "0,1"
group.long 0xA14++0x3
line.long 0x00 "COMLANE_R014,The comlane_014 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_BUFFER_CTRL1_7_0                           ,COMLANE buffer control 1 register [7:0]"
bitfld.long 0x00 16. "      SYNC_HDR_QUAL_EN_O                             ,Enables block_aligner skpos_hdr_det qualification" "0,1"
group.long 0xA18++0x3
line.long 0x00 "COMLANE_R018,The comlane_018 register"
bitfld.long 0x00 16.--17. " COM_BUFFER_CTRL2_9_8                           ,COMLANE buffer control 2 register [9:8]" "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "       COM_BUFFER_CTRL2_7_0                           ,COMLANE buffer control 2 register [7:0]"
textline "                           "
bitfld.long 0x00 0.--1. " COM_BUFFER_CTRL1_9_8                           ,COMLANE buffer control 1 register [9:8]" "0,1,2,3"
group.long 0xA1C++0x3
line.long 0x00 "COMLANE_R01C,The comlane_01c register"
bitfld.long 0x00 31. " COM_BER_CTRL1                                  ,COMLANE ber control 1 register" "0,1"
bitfld.long 0x00 30. "       COM_BER_CTRL1                                  ,COMLANE beacon control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " COM_BUFFER_CTRL3_5_0                           ,COMLANE buffer control 3 register [5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA30++0x3
line.long 0x00 "COMLANE_R030,The comlane_030 register"
hexmask.long.byte 0x00 24.--31. 1. " EYE_SCAN_MASK_O_15_8                           ,Mask eye scan results"
hexmask.long.byte 0x00 16.--23. 1. "      EYE_SCAN_MASK_O_7_0                            ,Mask eye scan results"
textline "                           "
bitfld.long 0x00 10.--13. " EYE_SCAN_EYE_DATA_SHIFT_O                      ,Shift edge samples" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "      EYE_SCAN_RUN_O                                 ,Run eye scan counter" "0,1"
textline "                           "
bitfld.long 0x00 8. " EYE_SCAN_COUNTER_EN_O                          ,Enable eye scan counter" "0,1"
group.long 0xA34++0x3
line.long 0x00 "COMLANE_R034,The comlane_034 register"
bitfld.long 0x00 23. " EI_GLUE_MASK_SIGDET_GEN3_O                     ,Mask bits for Gen3 rate for EI Infererence" "0,1"
bitfld.long 0x00 22. "       EI_GLUE_MASK_SIGDET_GEN2_O                     ,Mask bits for Gen2 rate for EI Infererence" "0,1"
textline "                           "
bitfld.long 0x00 21. " EI_GLUE_MASK_SIGDET_GEN1_O                     ,Mask bits for Gen1 rate for EI Infererence" "0,1"
bitfld.long 0x00 20. "       QD_CLK_LANE_CLK_SEL_O                          ,Selects quad clock for Tx Mux 2 and Rx Mux 4" "0,1"
textline "                           "
bitfld.long 0x00 16.--19. " EYE_SCAN_WAIT_LEN_O_11_8                       ,Eye scan wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "      EYE_SCAN_WAIT_LEN_O_7_0                        ,Eye scan wait time"
textline "                           "
bitfld.long 0x00 0.--3. " EYE_SCAN_MASK_O_19_16                          ,Mask eye scan results" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA38++0x3
line.long 0x00 "COMLANE_R038,The comlane_038 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_31_24                            ,COMLANE FSM control 1 register 31-24"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_23_16                            ,COMLANE FSM control 1 register 23-16"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_15_8                             ,COMLANE FSM control 1 register 15-8"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_7_0                              ,COMLANE FSM control 1 register 7-0"
group.long 0xA3C++0x3
line.long 0x00 "COMLANE_R03C,The comlane_03c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_63_56                            ,COMLANE FSM control 1 register 63-56"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_55_48                            ,COMLANE FSM control 1 register 55-48"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_47_40                            ,COMLANE FSM control 1 register 47-40"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_39_32                            ,COMLANE FSM control 1 register 39-32"
group.long 0xA40++0x3
line.long 0x00 "COMLANE_R040,The comlane_040 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_95_88                            ,COMLANE FSM control 1 register 95-88"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_87_80                            ,COMLANE FSM control 1 register 87-80"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_79_72                            ,COMLANE FSM control 1 register 79-72"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_71_64                            ,COMLANE FSM control 1 register 71-64"
group.long 0xA44++0x3
line.long 0x00 "COMLANE_R044,The comlane_044 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_127_120                          ,COMLANE FSM control 1 register 127-120"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_119_112                          ,COMLANE FSM control 1 register 119-112"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_111_104                          ,COMLANE FSM control 1 register 111-104"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_103_96                           ,COMLANE FSM control 1 register 103-96"
group.long 0xA48++0x3
line.long 0x00 "COMLANE_R048,The comlane_048 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_15_8                             ,COMLANE FSM control 2 register [15:8]"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_7_0                              ,COMLANE FSM control 2 register [7:0]"
group.long 0xA4C++0x3
line.long 0x00 "COMLANE_R04C,The comlane_04c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_47_40                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_39_32                            ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_31_24                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_23_16                            ,COMLANE FSM control 2 register"
group.long 0xA50++0x3
line.long 0x00 "COMLANE_R050,The comlane_050 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_79_72                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_71_64                            ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_63_56                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_55_48                            ,COMLANE FSM control 2 register"
group.long 0xA54++0x3
line.long 0x00 "COMLANE_R054,The comlane_054 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_111_104                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_103_96                           ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_95_88                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_87_80                            ,COMLANE FSM control 2 register"
group.long 0xA58++0x3
line.long 0x00 "COMLANE_R058,The comlane_058 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_143_136                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_135_128                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_127_120                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_119_112                          ,COMLANE FSM control 2 register"
group.long 0xA5C++0x3
line.long 0x00 "COMLANE_R05C,The comlane_05c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_175_168                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_167_160                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_159_152                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_151_144                          ,COMLANE FSM control 2 register"
group.long 0xA60++0x3
line.long 0x00 "COMLANE_R060,The comlane_060 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_207_200                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_199_192                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_191_184                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_183_176                          ,COMLANE FSM control 2 register"
group.long 0xA64++0x3
line.long 0x00 "COMLANE_R064,The comlane_064 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_239_232                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_231_224                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_223_216                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_215_208                          ,COMLANE FSM control 2 register"
group.long 0xA68++0x3
line.long 0x00 "COMLANE_R068,The comlane_068 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_271_264                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_263_256                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_255_248                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_247_240                          ,COMLANE FSM control 2 register"
group.long 0xA6C++0x3
line.long 0x00 "COMLANE_R06C,The comlane_06c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_303_296                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_295_288                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_287_280                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_279_272                          ,COMLANE FSM control 2 register"
group.long 0xA70++0x3
line.long 0x00 "COMLANE_R070,The comlane_070 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_335_328                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_327_320                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_319_312                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_311_304                          ,COMLANE FSM control 2 register"
group.long 0xA74++0x3
line.long 0x00 "COMLANE_R074,The comlane_074 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_367_360                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_359_352                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_351_344                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_343_336                          ,COMLANE FSM control 2 register"
group.long 0xA78++0x3
line.long 0x00 "COMLANE_R078,The comlane_078 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_399_392                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_391_384                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_383_376                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_375_368                          ,COMLANE FSM control 2 register"
group.long 0xA7C++0x3
line.long 0x00 "COMLANE_R07C,The comlane_07c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_431_424                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_423_416                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_415_408                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_407_400                          ,COMLANE FSM control 2 register"
group.long 0xA80++0x3
line.long 0x00 "COMLANE_R080,The comlane_080 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_463_456                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_455_448                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_447_440                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_439_432                          ,COMLANE FSM control 2 register"
group.long 0xA84++0x3
line.long 0x00 "COMLANE_R084,The comlane_084 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_495_488                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_487_480                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_479_472                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_471_464                          ,COMLANE FSM control 2 register"
group.long 0xA88++0x3
line.long 0x00 "COMLANE_R088,The comlane_088 register"
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_511_504                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_503_496                          ,COMLANE FSM control 2 register"
group.long 0xAAC++0x3
line.long 0x00 "COMLANE_R0AC,The comlane_0ac register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMINIT_MIN_O_7_0                      ,OOB detector COMINIT maximum idle length."
hexmask.long.byte 0x00 16.--22. 1. "      OOB_DET_BLEN_MAX_O_6_0                         ,OOB detector maximum burst length."
textline "                           "
hexmask.long.byte 0x00 8.--14. 1. " OOB_DET_BLEN_MIN_O_6_0                         ,OOB detector minimum burst length."
group.long 0xAB0++0x3
line.long 0x00 "COMLANE_R0B0,The comlane_0b0 register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMWAKE_MIN_O_7_0                      ,OOB detector COMWAKE minimum idle length."
bitfld.long 0x00 16. "      OOB_DET_COMINIT_MAX_O_8                        ,OOB detector COMINIT maximum idle length." "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " OOB_DET_COMINIT_MAX_O_7_0                      ,OOB detector COMINIT maximum idle length."
bitfld.long 0x00 0. "      OOB_DET_COMINIT_MIN_O_8                        ,OOB detector COMINIT maximum idle length." "0,1"
group.long 0xAB4++0x3
line.long 0x00 "COMLANE_R0B4,The comlane_0b4 register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMSAS_MIN_O_7_0                       ,OOB detector COMSAS maximum idle length."
bitfld.long 0x00 16. "      OOB_DET_COMWAKE_MAX_O_8                        ,OOB detector COMWAKE maximum idle length." "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " OOB_DET_COMWAKE_MAX_O_7_0                      ,OOB detector COMWAKE maximum idle length."
bitfld.long 0x00 0. "      OOB_DET_COMWAKE_MIN_O_8                        ,OOB detector COMWAKE minimum idle length." "0,1"
group.long 0xAB8++0x3
line.long 0x00 "COMLANE_R0B8,The comlane_0b8 register"
bitfld.long 0x00 16. " OOB_DET_COMSAS_MAX_O_8                         ,OOB detector COMSAS maximum idle length." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "       OOB_DET_COMSAS_MAX_O_7_0                       ,OOB detector COMSAS maximum idle length."
textline "                           "
bitfld.long 0x00 0. " OOB_DET_COMSAS_MIN_O_8                         ,OOB detector COMSAS maximum idle length." "0,1"
group.long 0xABC++0x3
line.long 0x00 "COMLANE_R0BC,The comlane_0bc register"
bitfld.long 0x00 28.--31. " TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0            ,TX master coefficient polarity overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_RATE3_TXEQ_POLARITY_3_0                 ,TX rate3 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_RATE2_TXEQ_POLARITY_3_0                 ,TX rate2 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_RATE1_TXEQ_POLARITY_3_0                 ,TX rate1 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_MASTER_TX_SR_DAC_OVR_3_0                ,TX master slew rate DAC overrides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_RATE3_TX_SR_DAC_3_0                     ,TX rate3 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_RATE2_TX_SR_DAC_3_0                     ,TX rate2 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_RATE1_TX_SR_DAC_3_0                     ,TX rate1 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC0++0x3
line.long 0x00 "COMLANE_R0C0,The comlane_0c0 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC4++0x3
line.long 0x00 "COMLANE_R0C4,The comlane_0c4 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC8++0x3
line.long 0x00 "COMLANE_R0C8,The comlane_0c8 register"
bitfld.long 0x00 30. " TXCTRL_MASTER_OVR_EN_O                         ,Tx control master override enable" "0,1"
bitfld.long 0x00 27.--29. "       TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0            ,TX enable fastest slew rate override." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 24.--26. " TXCTRL_RATE3_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 21.--23. "       TXCTRL_RATE2_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 18.--20. " TXCTRL_RATE1_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 17. "       TXCTRL_MASTER_PREEM_1LSB_MODE_OVR              ,TX master 1lsb mode overrides." "0,1"
textline "                           "
bitfld.long 0x00 16. " TXCTRL_PREEM_1LSB_MODE                         ,TX 1lsb mode" "0,1"
bitfld.long 0x00 14.--15. "       TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0              ,TX master slew rate setting overrides." "0,1,2,3"
textline "                           "
bitfld.long 0x00 12.--13. " TXCTRL_RATE3_TX_SLEW_SLD_1_0                   ,TX rate3 slew rate setting" "0,1,2,3"
bitfld.long 0x00 10.--11. "       TXCTRL_RATE2_TX_SLEW_SLD_1_0                   ,TX rate2 slew rate setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " TXCTRL_RATE1_TX_SLEW_SLD_1_0                   ,TX rate1 slew rate setting" "0,1,2,3"
bitfld.long 0x00 0.--3. "       TXCTRL_MASTER_ATT_IN_OVR_3_0                   ,Override value for att in." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xACC++0x3
line.long 0x00 "COMLANE_R0CC,The comlane_0cc register"
bitfld.long 0x00 24.--28. " TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0             ,TX rate2 full swing C1 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--23. "      TXCTRL_RATE1_LOWSWG_C2_IN_3_0                  ,TX rate1 low swing C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " TXCTRL_RATE1_FULLSWG_C2_IN_3_0                 ,TX rate1 full swing C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--12. "      TXCTRL_RATE1_LOWSWG_C1_IN_4_0                  ,TX rate1 low swing C1 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 0.--4. " TXCTRL_RATE1_FULLSWG_6DB_C1_IN_4_0             ,TX rate1 full swing C1 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD0++0x3
line.long 0x00 "COMLANE_R0D0,The comlane_0d0 register"
bitfld.long 0x00 28.--31. " TXCTRL_RATE3_C2_IN_3_0                         ,TX rate3 C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_RATE2_LOWSWG_C2_IN_3_0                  ,TX rate2 low swing C2 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--20. " TXCTRL_RATE2_LOWSWG_C1_IN_4_0                  ,TX rate2 low swing C1 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--15. "      TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0           ,TX rate2 full swing C2 coefficient for 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0             ,TX rate2 full swing C2 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "      TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0           ,TX rate2 full swing C1 coefficient for 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD4++0x3
line.long 0x00 "COMLANE_R0D4,The comlane_0d4 register"
bitfld.long 0x00 31. " TXEQ_C1_FORCE_LOW_EN_O                         ,Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed" "0,1"
bitfld.long 0x00 30. "       TXEQ_CM1_FORCE_LOW_EN_O                        ,Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " REDUCED_SWING_LF_VAL_O_5_0                     ,Reduced swing LowFreq value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20.--23. "      TXCTRL_MASTER_CM_IN_OVR_3_0                    ,TX master CM coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " TXCTRL_RATE2_CM_IN_3_0                         ,TX rate2 CM coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "      TXCTRL_RATE1_CM_IN_3_0                         ,TX rate1 CM coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " TXCTRL_MASTER_C2_IN_OVR_3_0                    ,TX master C2 coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "      TXCTRL_MASTER_C1_IN_OVR_4_0                    ,TX master C1 coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD8++0x3
line.long 0x00 "COMLANE_R0D8,The comlane_0d8 register"
bitfld.long 0x00 8.--10. " ATT_INIT_LOAD_ATT_VAL_O                        ,AGC initial ATT value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "       RX_BIAS_RATE3_O                                ,AFE rx_bias setting. Used when rxvcodiv is 01 or 10" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " RX_BIAS_RATE2_O                                ,AFE rx_bias setting. Used when rxvcodiv is 00" "0,1,2,3,4,5,6,7"
group.long 0xAE0++0x3
line.long 0x00 "COMLANE_R0E0,The comlane_0e0 register"
bitfld.long 0x00 4. " COM_FSM_CTRL7                                  ,COMLANE FSM control 7 register" "0,1"
bitfld.long 0x00 3. "       COM_FSM_CTRL6                                  ,COMLANE FSM control 6 register" "0,1"
textline "                           "
bitfld.long 0x00 2. " COM_FSM_CTRL5                                  ,COMLANE FSM control 5 register" "0,1"
bitfld.long 0x00 1. "       COM_FSM_CTRL4                                  ,COMLANE FSM control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 0. " COM_FSM_CTRL3                                  ,COMLANE FSM control 3 register" "0,1"
group.long 0xAFC++0x3
line.long 0x00 "COMLANE_R0FC,The comlane_0fc register"
group.long 0xB04++0x3
line.long 0x00 "COMLANE_R104,The comlane_104 register"
bitfld.long 0x00 30.--31. " ATT_INIT_LOAD_GAIN_VAL_O                       ,Initial AGC gain value" "0,1,2,3"
group.long 0xB14++0x3
line.long 0x00 "COMLANE_R114,The comlane_114 register"
rgroup.long 0xB18++0x3
line.long 0x00 "COMLANE_R118,The comlane_118 register"
bitfld.long 0x00 28.--31. " TXEQ_ADAPT_DONE_I_3_0                          ,TXEQ Adapt Done status - per lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      RXEQ_CAL_DONE_I_3_0                            ,RXEQ calibration done status - per lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB1C++0x3
line.long 0x00 "COMLANE_R11C,The comlane_11c register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB20++0x3
line.long 0x00 "COMLANE_R120,The comlane_120 register"
bitfld.long 0x00 24.--27. " TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB24++0x3
line.long 0x00 "COMLANE_R124,The comlane_124 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB28++0x3
line.long 0x00 "COMLANE_R128,The comlane_128 register"
hexmask.long.byte 0x00 24.--31. 1. " TXEQ_CM1_CYCLE_LEN_O_7_0                       ,Txeq CM1 coefficient adpatation error measurment wait time during each iteration"
bitfld.long 0x00 16.--18. "      TXCTRL_MASTER_VREG_LEV_OVR_2_0                 ,Does not exist!" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--10. " TXCTRL_RATE3_TX_VREG_LEV_2_0                   ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "       TXCTRL_RATE12_TX_VREG_LEV_2_0                  ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
group.long 0xB2C++0x3
line.long 0x00 "COMLANE_R12C,The comlane_12c register"
hexmask.long.byte 0x00 16.--23. 1. " VERSION_REG                                    ,Version register"
hexmask.long.byte 0x00 0.--7. 1. "      TXEQ_C1_CYCLE_LEN_O_7_0                        ,Txeq C1 coefficient adpatation error measurment wait time during each iteration"
group.long 0xB38++0x3
line.long 0x00 "COMLANE_R138,The comlane_138 register"
hexmask.long.byte 0x00 16.--23. 1. " CONFIG_VERSION_REG                             ,Config files write their version into these registers"
group.long 0xB54++0x3
line.long 0x00 "COMLANE_R154,The comlane_154 register"
hexmask.long.byte 0x00 24.--31. 1. " QAHB_LN_SYM_COM_P_9_2_O                        ,COM symbol for LB_BERT"
bitfld.long 0x00 22.--23. "      QAHB_LN_SYM_COM_P_1_0_O                        ,COM symbol for LB_BERT" "0,1,2,3"
group.long 0xB58++0x3
line.long 0x00 "COMLANE_R158,The comlane_158 register"
bitfld.long 0x00 24.--28. " TXCTRL_RATE1_LOWSWG_0DB_C1_4_0                 ,TX rate1 low swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "      TXCTRL_RATE1_FULLSWG_3P5DB_C1_4_0              ,TX rate1 full swing C1 coefficient 3.5db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB5C++0x3
line.long 0x00 "COMLANE_R15C,The comlane_15c register"
bitfld.long 0x00 16.--20. " TXCTRL_RATE2_LOWSWG_0DB_C1_4_0                 ,TX rate2 low swing C1 coefficient 0 db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "      TXCTRL_RATE2_FULLSWG_0DB_C1_4_0                ,TX rate2 full swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 0.--4. " TXCTRL_RATE1_FULLSWG_0DB_C1_4_0                ,TX rate1 full swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB6C++0x3
line.long 0x00 "COMLANE_R16C,The comlane_16c register"
bitfld.long 0x00 25.--27. " COM_FSM_CTRL10_2_0                             ,COMLANE FSM control 10 register [2:0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "       COM_FSM_CTRL9                                  ,COMLANE FSM control 9 register" "0,1"
textline "                           "
hexmask.long.byte 0x00 16.--23. 1. " COM_FSM_CTRL8_7_0                              ,COMLANE FSM control 8 register [7:0]"
rgroup.long 0xB74++0x3
line.long 0x00 "COMLANE_R174,The comlane_174 register"
bitfld.long 0x00 12.--15. " LN3_RX_LOCKED_I_15_12                          ,Lane 3 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      LN2_RX_LOCKED_I_11_8                           ,Lane 2 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB90++0x3
line.long 0x00 "COMLANE_R190,The comlane_190 register"
bitfld.long 0x00 11. " L3_MASTER_CDN_O                                ,Lane3 master reset" "0,1"
bitfld.long 0x00 10. "       L2_MASTER_CDN_O                                ,Lane2 master reset" "0,1"
textline "                           "
bitfld.long 0x00 9. " L1_MASTER_CDN_O                                ,Lane1 master reset" "0,1"
bitfld.long 0x00 8. "       L0_MASTER_CDN_O                                ,Lane0 master reset" "0,1"
rgroup.long 0xB94++0x3
line.long 0x00 "COMLANE_R194,The comlane_194 register"
bitfld.long 0x00 31. " LN3_OK_I_7                                     ,Lane 3 OK Status" "0,1"
bitfld.long 0x00 30. "       LN2_OK_I_6                                     ,Lane 2 OK Status" "0,1"
textline "                           "
bitfld.long 0x00 29. " LN1_OK_I_5                                     ,Lane 1 OK Status" "0,1"
bitfld.long 0x00 28. "       LN0_OK_I_4                                     ,Lane 0 OK Status" "0,1"
textline "                           "
bitfld.long 0x00 27. " LN3_SIG_LEVEL_VALID_I_3                        ,Lane 3 Signal Detect Valid Status" "0,1"
bitfld.long 0x00 26. "       LN2_SIG_LEVEL_VALID_I_2                        ,Lane 2 Signal Detect Valid Status" "0,1"
textline "                           "
bitfld.long 0x00 25. " LN1_SIG_LEVEL_VALID_I_1                        ,Lane 1 Signal Detect Valid Status" "0,1"
bitfld.long 0x00 24. "       LN0_SIG_LEVEL_VALID_I_0                        ,Lane 0 Signal Detect Valid Status" "0,1"
textline "                           "
bitfld.long 0x00 20. " CMU1_OK_I_1                                    ,CMU1 OK Status" "0,1"
bitfld.long 0x00 19. "       CMU_OK_I_0                                     ,CMU OK Status" "0,1"
textline "                           "
bitfld.long 0x00 16.--18. " MODE_I_2_0                                     ,1000Base-KX Mode status for CPU" "0,1,2,3,4,5,6,7"
group.long 0xB98++0x3
line.long 0x00 "COMLANE_R198,The comlane_198 register"
bitfld.long 0x00 23. " COM_PCIE_OVR6                                  ,COMLANE PCIe override 6 register" "0,1"
bitfld.long 0x00 22. "       COM_PCIE_OVR5                                  ,COMLANE PCIe override 5 register" "0,1"
textline "                           "
bitfld.long 0x00 21. " COM_PCIE_OVR4                                  ,COMLANE PCIe override 4 register" "0,1"
bitfld.long 0x00 20. "       COM_PCIE_OVR3                                  ,COMLANE PCIe override 3 register" "0,1"
textline "                           "
bitfld.long 0x00 19. " COM_PCIE_OVR2                                  ,COMLANE PCIe override 2 register" "0,1"
bitfld.long 0x00 18. "       COM_PCIE_OVR1                                  ,COMLANE PCIe override 1 register" "0,1"
textline "                           "
bitfld.long 0x00 17. " COM_PCIE_CTRL2                                 ,COMLANE PCIe control 2 register" "0,1"
bitfld.long 0x00 16. "       COM_PCIE_CTRL1                                 ,COMLANE PCIe control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 4.--7. " LN1_RX_LOCKED_I_7_4                            ,Lane 1 RX Locked Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      LN0_RX_LOCKED_I_3_0                            ,Lane 0 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB9C++0x3
line.long 0x00 "COMLANE_R19C,The comlane_19c register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P0CP1_O                         ,txpreset_coeff P0 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P0CM1_O                         ,txpreset_coeff P0 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P0C_O                           ,txpreset_coeff P0 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA0++0x3
line.long 0x00 "COMLANE_R1A0,The comlane_1a0 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P2C_O                           ,txpreset_coeff P2 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P1CP1_O                         ,txpreset_coeff P1 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P1CM1_O                         ,txpreset_coeff P1 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P1C_O                           ,txpreset_coeff P1 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA4++0x3
line.long 0x00 "COMLANE_R1A4,The comlane_1a4 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P3CM1_O                         ,txpreset_coeff P3 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P3C_O                           ,txpreset_coeff P3 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P2CP1_O                         ,txpreset_coeff P2 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P2CM1_O                         ,txpreset_coeff P2 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA8++0x3
line.long 0x00 "COMLANE_R1A8,The comlane_1a8 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P4CP1_O                         ,txpreset_coeff P4 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P4CM1_O                         ,txpreset_coeff P4 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P4C_O                           ,txpreset_coeff P4 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P3CP1_O                         ,txpreset_coeff P3 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBAC++0x3
line.long 0x00 "COMLANE_R1AC,The comlane_1ac register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P6C_O                           ,txpreset_coeff P6 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P5CP1_O                         ,txpreset_coeff P5 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P5CM1_O                         ,txpreset_coeff P5 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P5C_O                           ,txpreset_coeff P5 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB0++0x3
line.long 0x00 "COMLANE_R1B0,The comlane_1b0 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P7CM1_O                         ,txpreset_coeff P7 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P7C_O                           ,txpreset_coeff P7 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P6CP1_O                         ,txpreset_coeff P6 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P6CM1_O                         ,txpreset_coeff P6 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB4++0x3
line.long 0x00 "COMLANE_R1B4,The comlane_1b4 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P8CP1_O                         ,txpreset_coeff P8 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P8CM1_O                         ,txpreset_coeff P8 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P8C_O                           ,txpreset_coeff P8 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P7CP1_O                         ,txpreset_coeff P7 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB8++0x3
line.long 0x00 "COMLANE_R1B8,The comlane_1b8 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P10C_O                          ,txpreset_coeff P10 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P9CP1_O                         ,txpreset_coeff P9 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P9CM1_O                         ,txpreset_coeff P9 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P9C_O                           ,txpreset_coeff P9 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBBC++0x3
line.long 0x00 "COMLANE_R1BC,The comlane_1bc register"
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P10CP1_O                        ,txpreset_coeff P10 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P10CM1_O                        ,txpreset_coeff P10 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1400++0x3
line.long 0x00 "COMRXEQ_R000,The comrxeq_000 register"
bitfld.long 0x00 7. " CSR_RXEQ_CONT_CAL_EN_O                         ,This register enables continuous time rxeq adaptation in the background" "0,1"
bitfld.long 0x00 6. "       CSR_FORCE_CAL_O                                ,This register forces one round of rxeq run" "0,1"
textline "                           "
bitfld.long 0x00 5. " CSR_EI_EXIT_CAL_O                              ,This register controls whether to perform any adaptation during electrical idle exit or not." "0,1"
bitfld.long 0x00 4. "       CSR_RATE_CHANGE_CAL_O                          ,This register controls whether to perform any adaptation during rate change or not." "0,1"
textline "                           "
bitfld.long 0x00 3. " CSR_RXEQ_RATE3_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE3." "0,1"
bitfld.long 0x00 2. "       CSR_RXEQ_RATE2_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE2." "0,1"
textline "                           "
bitfld.long 0x00 1. " CSR_RXEQ_RATE1_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE1" "0,1"
bitfld.long 0x00 0. "       CSR_RXEQ_EN_O                                  ,Master enable for rxeq top." "0,1"
group.long 0x1404++0x3
line.long 0x00 "COMRXEQ_R004,The comrxeq_004 register"
hexmask.long.byte 0x00 24.--31. 1. " COMRXEQ_MS_INIT_CTRL_7_0                       ,COMRXEQ mid speed initial calibration control [0] Adapt RXEQ stage 0 during initial mid speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 16.--23. 1. "      COMRXEQ_LS_INIT_CTRL_7_0                       ,COMRXEQ low speed initial calibration control [0] Adapt RXEQ stage 0 during initial low speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
group.long 0x1408++0x3
line.long 0x00 "COMRXEQ_R008,The comrxeq_008 register"
hexmask.long.byte 0x00 24.--31. 1. " CSR_RXEQ_CONT_RUN_RATE3_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE3, 1: calibration 0: load only"
hexmask.long.byte 0x00 16.--23. 1. "      CSR_RXEQ_CONT_RUN_RATE2_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE2, 1: calibration 0: load only"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CSR_RXEQ_CONT_RUN_RATE1_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE1, 1: calibration 0: load only."
hexmask.long.byte 0x00 0.--7. 1. "      COMRXEQ_HS_INIT_CAL_7_0                        ,COMRXEQ high speed initial calibration control [0] Adapt RXEQ stage 0 during initial high speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
group.long 0x140C++0x3
line.long 0x00 "COMRXEQ_R00C,The comrxeq_00c register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_HS_RECAL_CTRL_7_0                      ,COMRXEQ high speed recalibration control [0] Re-adapt RXEQ stage 0 during high speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 8.--15. 1. "      COMRXEQ_MS_RECAL_CTRL_7_0                      ,COMRXEQ mid speed recalibration control [0] Re-adapt RXEQ stage 0 during mid speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " COMRXEQ_LS_RECAL_CTRL_7_0                      ,COMRXEQ low speed recalibration control [0] Re-adapt RXEQ stage 0 during low speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
group.long 0x141C++0x3
line.long 0x00 "COMRXEQ_R01C,The comrxeq_01c register"
bitfld.long 0x00 12.--15. " COMRXEQ_CTRL4_3_0                              ,COMRXEQ control 4 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      COMRXEQ_CTRL3_3_0                              ,COMRXEQ control 3 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_CTRL2                                  ,COMRXEQ control 2 register" "0,1"
bitfld.long 0x00 3. "       COMRXEQ_HS_CONT_CAL_CTRL1                      ,COMRXEQ high speed continuous calibration control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 2. " COMRXEQ_MS_CONT_CAL_CTRL1                      ,COMRXEQ mid speed continuous calibration control 1 register" "0,1"
bitfld.long 0x00 1. "       COMRXEQ_LS_CONT_CAL_CTRL1                      ,COMRXEQ low speed continuous calibration control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 0. " COMRXEQ_CTRL1                                  ,COMRXEQ control 1 register" "0,1"
group.long 0x1428++0x3
line.long 0x00 "COMRXEQ_R028,The comrxeq_028 register"
bitfld.long 0x00 30. " COMRXEQ_CTRL9                                  ,COMRXEQ control 9 register" "0,1"
bitfld.long 0x00 29. "       COMRXEQ_CTRL8                                  ,COMRXEQ control 8 register" "0,1"
textline "                           "
bitfld.long 0x00 28. " COMRXEQ_CTRL7                                  ,COMRXEQ control 7 register" "0,1"
bitfld.long 0x00 26.--27. "       COMRXEQ_CTRL6_1_0                              ,COMRXEQ control 6 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " COMRXEQ_CTRL5_1_0                              ,COMRXEQ control 5 register [1:0]" "0,1,2,3"
group.long 0x1434++0x3
line.long 0x00 "COMRXEQ_R034,The comrxeq_034 register"
bitfld.long 0x00 24. " COMRXEQ_CTRL12                                 ,COMRXEQ control 12 register" "0,1"
bitfld.long 0x00 19.--20. "       COMRXEQ_CTRL11_2_0                             ,COMRXEQ control 11 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 16.--18. " COMRXEQ_CTRL10_2_0                             ,COMRXEQ control 10 register [2:0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11.--12. "       CSR_GEN2_GAIN_START_VAL_O                      ,Start value for GAIN Gen2 rate" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--10. " CSR_GEN2_ATT_START_VAL_O                       ,Start value for ATT adaptation Gen2 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "       CSR_GEN1_GAIN_START_VAL_O                      ,Start value for GAIN Gen1 rate" "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--2. " CSR_GEN1_ATT_START_VAL_O                       ,Start value for ATT adaptation for Gen1 rate" "0,1,2,3,4,5,6,7"
group.long 0x143C++0x3
line.long 0x00 "COMRXEQ_R03C,The comrxeq_03c register"
hexmask.long.byte 0x00 8.--14. 1. " COMRXEQ_PATT_CTRL1_6_0                         ,COMRXEQ pattern control 1 register [6:0]"
group.long 0x1444++0x3
line.long 0x00 "COMRXEQ_R044,The comrxeq_044 register"
bitfld.long 0x00 7. " COMRXEQ_CTRL13                                 ,COMRXEQ control 13 register" "0,1"
bitfld.long 0x00 6. "       COMRXEQ_PATT_CTRL4                             ,COMRXEQ pattern control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_PATT_CTRL3                             ,COMRXEQ pattern control 3 register" "0,1"
bitfld.long 0x00 4. "       COMRXEQ_PATT_CTRL2                             ,COMRXEQ pattern control 2 register" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " COMRXEQ_START_CTRL1_3_0                        ,COMRXEQ start value control 1 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1448++0x3
line.long 0x00 "COMRXEQ_R048,The comrxeq_048 register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_PATT_CTRL5_7_0                         ,COMRXEQ pattern control 5 register [7:0]"
bitfld.long 0x00 0.--3. "      CSR_BSTADAPT_GEN2_BOOST_START_O                ,Edge Based Boost Start value for Gen2 rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x144C++0x3
line.long 0x00 "COMRXEQ_R04C,The comrxeq_04c register"
bitfld.long 0x00 7. " COMRXEQ_CTRL16                                 ,COMRXEQ control 16 register" "0,1"
bitfld.long 0x00 6. "       COMRXEQ_CTRL15                                 ,COMRXEQ control 15 register" "0,1"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_PATT_CTRL5_8                           ,COMRXEQ pattern control 5 register [8]" "0,1"
bitfld.long 0x00 4. "       COMRXEQ_PATT_CTRL6                             ,COMRXEQ pattern control 6 register" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " COMRXEQ_CTRL14_3_0                             ,COMRXEQ control 14 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1458++0x3
line.long 0x00 "COMRXEQ_R058,The comrxeq_058 register"
hexmask.long.byte 0x00 0.--6. 1. " COMRXEQ_PATT_CTRL7_6_0                         ,COMRXEQ pattern control 7 register [6:0]"
group.long 0x1460++0x3
line.long 0x00 "COMRXEQ_R060,The comrxeq_060 register"
hexmask.long.byte 0x00 24.--30. 1. " COMRXEQ_PATT_CTRL8_6_0                         ,COMRXEQ pattern control 8 register [6:0]"
group.long 0x1464++0x3
line.long 0x00 "COMRXEQ_R064,The comrxeq_064 register"
hexmask.long.byte 0x00 24.--30. 1. " COMRXEQ_PATT_CTRL11_6_0                        ,COMRXEQ pattern control 11 register [6:0]"
hexmask.long.byte 0x00 16.--22. 1. "      COMRXEQ_PATT_CTRL10_6_0                        ,COMRXEQ pattern control 10 register [6:0]"
textline "                           "
hexmask.long.byte 0x00 0.--6. 1. " COMRXEQ_PATT_CTRL9_6_0                         ,COMRXEQ pattern control 9 register [6:0]"
group.long 0x1470++0x3
line.long 0x00 "COMRXEQ_R070,The comrxeq_070 register"
hexmask.long.byte 0x00 16.--22. 1. " COMRXEQ_PATT_CTRL12_6_0                        ,COMRXEQ pattern control 12 register [6:0]"
group.long 0x1474++0x3
line.long 0x00 "COMRXEQ_R074,The comrxeq_074 register"
hexmask.long.byte 0x00 8.--14. 1. " COMRXEQ_PATT_CTRL13_6_0                        ,COMRXEQ pattern control 13 register [6:0]"
group.long 0x1484++0x3
line.long 0x00 "COMRXEQ_R084,The comrxeq_084 register"
bitfld.long 0x00 20.--23. " COMRXEQ_CTRL18_3_0                             ,COMRXEQ control 18 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      COMRXEQ_CTRL17_3_0                             ,COMRXEQ control 17 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1490++0x3
line.long 0x00 "COMRXEQ_R090,The comrxeq_090 register"
bitfld.long 0x00 13. " COMRXEQ_CTRL24                                 ,COMRXEQ control 24 register" "0,1"
bitfld.long 0x00 12. "       COMRXEQ_CTRL23                                 ,COMRXEQ control 23 register" "0,1"
textline "                           "
bitfld.long 0x00 11. " COMRXEQ_CTRL22                                 ,COMRXEQ control 22 register" "0,1"
bitfld.long 0x00 10. "       COMRXEQ_CTRL21                                 ,COMRXEQ control 21 register" "0,1"
textline "                           "
bitfld.long 0x00 9. " COMRXEQ_CTRL20                                 ,COMRXEQ control 20 register" "0,1"
bitfld.long 0x00 8. "       COMRXEQ_CTRL19                                 ,COMRXEQ control 19 register" "0,1"
group.long 0x1494++0x3
line.long 0x00 "COMRXEQ_R094,The comrxeq_094 register"
hexmask.long.byte 0x00 24.--31. 1. " COMRXEQ_CTRL25_7_0                             ,COMRXEQ control 25 register [7:0]"
hexmask.long.byte 0x00 16.--23. 1. "      CSR_DFE_GEN2_TAP_START_VAL_O                   ,Start value for DFE tap adaptation for Gen2 rate"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CSR_DFE_GEN1_TAP_START_VAL_O                   ,Start value for DFE tap adaptation for Gen1 rate"
group.long 0x1498++0x3
line.long 0x00 "COMRXEQ_R098,The comrxeq_098 register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_HS_RCHANGE_CTRL_7_0                    ,COMRXEQ high speed rate change calibration control [0] Adapt RXEQ stage 0 during high speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 8.--15. 1. "      CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O           ,COMRXEQ mid speed rate change calibration control [0] Adapt RXEQ stage 0 during mid speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7..."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE1_O           ,COMRXEQ low speed rate change calibration control [0] Adapt RXEQ stage 0 during low speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7..."
rgroup.long 0x1FC0++0x3
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the SERDES module."
hexmask.long.word 0x00 16.--31. 1. " MODULE_ID                                      ,SERDES module ID."
bitfld.long 0x00 11.--15. "    RTL_VERSION                                    ,RTL Version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 8.--10. " MAJOR_REVISION                                 ,Major Revision." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "       CUSTOM_REVISION                                ,Custom Revision." "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--5. " MINOR_REVISION                                 ,Minor Revision." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1FD0++0x3
line.long 0x00 "SERDES_CTRL,Sets the SERDES control state."
bitfld.long 0x00 29. " POR_EN                                         ,The POR_EN allows the system to place the SERDES in a reset state. Accesses to the SERDES registers are ignored." "0,1"
rgroup.long 0x1FD4++0x3
line.long 0x00 "LANE_PLL_STS,The Lane and PLL Status register is used to indicate the current configuration of the REFCLK distribution and Lane Mux selection."
bitfld.long 0x00 31. " PLL0_PWR_ON                                    ,Indicates the state of the PLL0 REFCLK supplies. 0 - REFCLK power is off 1 - REFCLK power is on" "0,1"
bitfld.long 0x00 27. "       PLL0_SEL_EXT                                   ,Indicates the chaining for the right side will be opposite of the PLL0_CHAIN_EN field used for the left chaining. 0 - Chaining for left and right will match PLL0_CHAIN_EN field. 1 - Chain left is PLL0_CHAIN_EN field and chain right is !PLL0_CHAIN_EN field." "0,1"
textline "                           "
bitfld.long 0x00 26. " PLL0_LEFT_SEL                                  ,Indicates the REFCLK source used for PLL0. This bit indicates that the left REFCLK input is used for the PLL0. When both PLL0_LEFT_SEL and PLL0_RIGHT_SEL are zero, the REFCLK pads are used for the PLL0." "0,1"
bitfld.long 0x00 25. "       PLL0_CHAIN_EN                                  ,Indicates the REFCLK chaining is enabled. 0 - REFCLK right and left are driven from the REFCLK pads of this Serdes 1 - REFCLK right or left is driven from left or right respectively." "0,1"
textline "                           "
bitfld.long 0x00 24. " PLL0_RIGHT_SEL                                 ,Indicates the REFCLK source used for PLL0. This bit indicates that the right REFCLK input is used for the PLL0. When both PLL0_LEFT_SEL and PLL0_RIGHT_SEL are zero, the REFCLK pads are used for the PLL0." "0,1"
bitfld.long 0x00 3. "       LANE0_PLL_LOCK                                 ,Indicates that the lane 0 tx clock is valid." "0,1"
textline "                           "
bitfld.long 0x00 2. " LANE0_RST_ISO                                  ,Indicates that the selected IF has the Lane 0 reset isolation signal set." "0,1"
bitfld.long 0x00 0.--1. "       LANE0_IP_SEL                                   ,Indicates which interface is used for lane 0. See , Interface Selection" "0,1,2,3"
rgroup.long 0x1FD8++0x3
line.long 0x00 "SERDES_FEATURE,The SERDES Feature register contains the features of the SERDES."
bitfld.long 0x00 0.--2. " LANES                                          ,Indicates the number of lanes in this serdes" "0,1,2,3,4,5,6,7"
group.long 0x1FE0++0x3
line.long 0x00 "LANEXCTL_STS,The lane x control and status provides the ability to override SERDES configuration settings. It is mainly provided for test, but sometimes used for mission setup as well."
bitfld.long 0x00 31. " TX0_ENABLE_OVL                                 ,The Tx Enable Overlay bit, when set allows the Tx Enable Value to override the CFGTX.Enable input." "0,1"
bitfld.long 0x00 29.--30. "       TX0_ENABLE_VAL                                 ,The Tx Enable Value when used allows the Tx lane to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 28. " TX0_RATE_OVL                                   ,The Tx Rate Overlay bit, when set allows the Tx Rate Value to override the CFGTX.Rate input." "0,1"
bitfld.long 0x00 26.--27. "       TX0_RATE_VAL                                   ,The Tx Rate Value when used allows the Tx lane to be placed into 0 - Full Rate mode. 1 - Half Rate mode. 2 - Quarter Rate mode." "0,1,2,3"
textline "                           "
bitfld.long 0x00 25. " TX0_IDLE_OVL                                   ,The Tx Idle Overlay bit, when set allows the Tx Idle Value to override the CFGTX.Idle input." "0,1"
bitfld.long 0x00 24. "       TX0_IDLE_VAL                                   ,The Tx Idle Value, when used allows the Tx lane to be placed electrical Idle state in non Pipe Interface mode." "0,1"
textline "                           "
bitfld.long 0x00 23. " TX0_WIDTH_OVL                                  ,The Tx Width Overlay bit, when set allows the Tx Width Value to override the CFGTX.Width input." "0,1"
bitfld.long 0x00 21.--22. "       TX0_WIDTH_VAL                                  ,The Tx Width Value, when used allows the Tx lane to be placed into 0 - 10 bit mode 1 - 16 bit mode 2 - 20 bit mode 3 - 40 bit mode This field is ignored in Pipe Interface Mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 15. " RX0_ENABLE_OVL                                 ,The Rx Enable Overlay bi,t when set allows the Rx Enable Value to override the CFGRX.Enable input." "0,1"
bitfld.long 0x00 13.--14. "       RX0_ENABLE_VAL                                 ,The Rx Enable Valu,e when used allows the Rx lane to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 12. " RX0_RATE_OVL                                   ,The Rx Rate Overlay bit, when set allows the Rx Rate Value to override the CFGRX.Rate input." "0,1"
bitfld.long 0x00 10.--11. "       RX0_RATE_VAL                                   ,The Rx Rate Value when used allows the Rx lane to be placed into 0 - Full Rate mode. 1 - Half Rate mode. 2 - Quarter Rate mode." "0,1,2,3"
textline "                           "
bitfld.long 0x00 9. " RX0_POLARITY_OVL                               ,The Rx Polarity Overlay bit, when set allows the Rx Polarity Value to override the CFGRX.Polarity input." "0,1"
bitfld.long 0x00 8. "       RX0_POLARITY_VAL                               ,The Rx Polarity Value, when used allows the lane Rx Polarity to be inverted." "0,1"
textline "                           "
bitfld.long 0x00 7. " RX0_ALIGN_OVL                                  ,The Rx Align Overlay bit, when set allows the Rx Align Value to override the CFGRX.Align input." "0,1"
bitfld.long 0x00 6. "       RX0_ALIGN_VAL                                  ,The Rx Align Value, when used allows the Rx lane to align to K28.1, K28.5 and K28.7 characters otherwise known as Comma Characters." "0,1"
textline "                           "
bitfld.long 0x00 5. " RX0_WIDTH_OVL                                  ,The Rx Width Overlay bit, when set allows the Rx Width Value to override the CFGRX.Width input." "0,1"
bitfld.long 0x00 3.--4. "       RX0_WIDTH_VAL                                  ,The Rx Width Value when used allows the Rx lane to be placed into 0 - 10-bit mode 1 - 16-bit mode 2 - 20-bit mode 3 - 40-bit mode This field is ignored in Pipe Interface Mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 1. " RX0_OK                                         ,The Rx OK indicate that the lane is in a functional state." "0,1"
bitfld.long 0x00 0. "       RX0_LOSS                                       ,The Rx Signal Loss Indicates that the data has not been detected or the CDR is not locked." "0,1"
group.long 0x1FF4++0x3
line.long 0x00 "PLL_CTRL,The PLL Control register provides the ability to override the PLL state and control events for debug purposes."
bitfld.long 0x00 31. " PLL_ENABLE_OVL                                 ,The PLL Enable Overlay bit, when set allows the PLL Enable Value to override the CFGPLL.Enable input." "0,1"
bitfld.long 0x00 29.--30. "       PLL_ENABLE_VAL                                 ,The PLL Enable Value when used allows the PLL to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 28. " PLL_OK                                         ,The PLL Ok indicate that the transmit clocks are valid and the PLL circuits are ready for use." "0,1"
bitfld.long 0x00 17. "       LN_WAFTER_OK                                   ,The LN_WAFTER_OK field will cause the lane OK indication to be Blocked until the LN0_CONT_OK is set. This allows code to run after the lane OK but before the hardware can use the lane." "0,1"
textline "                           "
bitfld.long 0x00 16. " LN_WAFTER_SD                                   ,The LN_WAFTER_SD field will cause the Rx signal indication to be Blocked until the LN0_CONT_SD is set. This allows code to run after signal detect but before the hardware can use the data." "0,1"
bitfld.long 0x00 12. "       LN0_CONT_OK                                    ,The LN0_CONT_OK allows the Blocked lane OK for lane 0 to now pass to the controlling PCS IP. This bit is auto cleared when LN0_OK_STATE is driven inactive." "0,1"
textline "                           "
bitfld.long 0x00 8. " LN0_OK_STATE                                   ,The LN0_OK_STATE indicate the current state of the lane OK signal for lane 0." "0,1"
bitfld.long 0x00 4. "       LN0_CONT_SD                                    ,The LN0_CONT_SD allows the Blocked signal detect for lane 0 to now pass to the controlling PCS IP. This bit is auto cleared when LN0_SD_STATE is driven inactive." "0,1"
textline "                           "
bitfld.long 0x00 0. " LN0_SD_STATE                                   ,The LN0_SD_STATE indicate the current state of the signal detect signal for lane 0." "0,1"
rgroup.long 0x1FF8++0x3
line.long 0x00 "COMMA_LINK_DELAY,The Comma Link Delay register defines the added delay due to comma alignment for the SERDES lanes. This value should be added to the receive time stamp to accurately time stamp the packet arrival. For a 1G link the value is 800pS per bit. This value may change any time the link is established."
hexmask.long.byte 0x00 0.--7. 1. " LANE0_CDELAY                                   ,Defines the number of network bits the comma aligner has added to the fixed delay of the PCS/PMA layer for lane 0."
group.long 0x1FFC++0x3
line.long 0x00 "CMU_WAIT,The CMU Wait is used to create a 150 micro second delay between the completion of the SERDES configuration writes and activating the SERDES CMU logic allowing for supplies to settle."
hexmask.long.byte 0x00 24.--31. 1. " IDDQ_CNT                                       ,Defines the number of clock cycles times 256 between pll_enable and cmu_master_cdn being set and the cmu_iddq going low."
bitfld.long 0x00 20.--23. "      PHAN_VAL                                       ,Defines the number of ~i(WAIT_VAL+1)*~i(PHAN_VAL+1) clock cycles between CMU Reset and when the phantom CMU_OK is generated. This allows the Serdes to start using valid clocks. The Phantom CMU_OK is used in Pipe mode. If this field is 0, the Phantom CMU_OK is equal to the actual CMU_OK." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
hexmask.long.tbyte 0x00 0.--16. 1. " WAIT_VAL                                       ,Defines the number of clock cycles between writing to the CMU Reset register and cmu_reset_i activation. The value should be 150 ?s or more."
width 0x0B
tree.end
tree "SERDES1"
base ad:0x910000
width 18.
group.long 0x0++0x3
line.long 0x00 "CMU_R000,The cmu_000 register"
hexmask.long.byte 0x00 24.--30. 1. " CMU_PLL_CTRL1_6_0_O                            ,CMU PLL control 1 register [6:0]"
group.long 0x4++0x3
line.long 0x00 "CMU_R004,The cmu_004 register"
bitfld.long 0x00 12. " REFCLK_CTRL1                                   ,Refclk control 1 register" "0,1"
bitfld.long 0x00 11. "       CMU_PLL_CTRL4                                  ,CMU PLL control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 10. " CMU_PLL_CTRL3                                  ,CMU PLL control 3 register" "0,1"
bitfld.long 0x00 8.--9. "       CMU_PLL_CTRL2_9_8                              ,CMU PLL control 2 register [9:8]" "0,1,2,3"
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " CMU_PLL_CTRL2_7_0                              ,CMU PLL control 2 register [7:0]"
group.long 0x8++0x3
line.long 0x00 "CMU_R008,The cmu_008 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_15_8                             ,CMU FSM control 1 register 15-8"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_7_0                              ,CMU FSM control 1 register 7-0"
group.long 0xC++0x3
line.long 0x00 "CMU_R00C,The cmu_00c register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_47_40                            ,CMU FSM control 1 register 47-40"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_39_32                            ,CMU FSM control 1 register 39-32"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_31_24                            ,CMU FSM control 1 register 31-24"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_23_16                            ,CMU FSM control 1 register 23-16"
group.long 0x10++0x3
line.long 0x00 "CMU_R010,The cmu_010 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_79_72                            ,CMU FSM control 1 register 79-72"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_71_64                            ,CMU FSM control 1 register 71-64"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_63_56                            ,CMU FSM control 1 register 63-56"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_55_48                            ,CMU FSM control 1 register 55-48"
group.long 0x14++0x3
line.long 0x00 "CMU_R014,The cmu_014 register"
hexmask.long.byte 0x00 24.--31. 1. " CMU_FSM_CTRL1_111_104                          ,CMU FSM control 1 register 111-104"
hexmask.long.byte 0x00 16.--23. 1. "      CMU_FSM_CTRL1_103_96                           ,CMU FSM control 1 register 103-96"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_95_88                            ,CMU FSM control 1 register 95-88"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_87_80                            ,CMU FSM control 1 register 87-80"
group.long 0x18++0x3
line.long 0x00 "CMU_R018,The cmu_018 register"
hexmask.long.byte 0x00 8.--15. 1. " CMU_FSM_CTRL1_127_120                          ,CMU FSM control 1 register 127-120"
hexmask.long.byte 0x00 0.--7. 1. "      CMU_FSM_CTRL1_119_112                          ,CMU FSM control 1 register 119-112"
group.long 0x5C++0x3
line.long 0x00 "CMU_R05C,The cmu_05c register"
bitfld.long 0x00 31. " AHB_PMA_CM_C1_SEL_O                            ,CMU LF C1 cap select. Enabling increases C1 cap." "0,1"
bitfld.long 0x00 30. "       AHB_PMA_CM_I_HIZ_O                             ,CMU PLL HIZ setting" "0,1"
textline "                           "
bitfld.long 0x00 28.--29. " AHB_PMA_CM_I_CP_SEL_O                          ,Charge pump current gain select." "0,1,2,3"
bitfld.long 0x00 26.--27. "       AHB_PMA_CM_FORCE_ILF_O                         ,CMU loop filter force to common mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " AHB_PMA_CM_I_KVCO_SEL_O                        ,CMU VCO integral path gain" "0,1,2,3"
group.long 0x60++0x3
line.long 0x00 "CMU_R060,The cmu_060 register"
hexmask.long.byte 0x00 24.--31. 1. " AHB_PMA_CM_AFE_CNTL_O                          ,CMU AFE spares"
bitfld.long 0x00 22.--23. "      AHB_PMA_CM_VREGREF_O                           ,CMU reference clock regulator setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 21. " AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O            ,CMU VCO PMOS proportional current decrease" "0,1"
bitfld.long 0x00 20. "       AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O            ,CMU VCO PMOS proportional current increase" "0,1"
textline "                           "
bitfld.long 0x00 19. " AHB_PMA_CM_V2I_FILTER_SW_ON_O                  ,CMU V2I filter enable" "0,1"
bitfld.long 0x00 18. "       SR_NDIV_OVR_ENA_O                              ,Override enable for overriding N-div value" "0,1"
textline "                           "
bitfld.long 0x00 17. " AHB_PMA_CM_PFD_FORCE_UP_O                      ,Force PFD to output up" "0,1"
bitfld.long 0x00 16. "       AHB_PMA_CM_PFD_FORCE_DN_O                      ,Force PFD to output down" "0,1"
textline "                           "
bitfld.long 0x00 14.--15. " AHB_PMA_CM_VREGH_O                             ,CMU VREGH setting" "0,1,2,3"
bitfld.long 0x00 12.--13. "       AHB_PMA_CM_VREG_O                              ,CMU VREG setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--11. " AHB_PMA_CM_VCO_BIAS_O                          ,CMU VCO bias current setting." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "      AHB_PMA_CM_BGSTART_BYP_O                       ,Bandgap startup circuit bypass" "0,1"
textline "                           "
bitfld.long 0x00 4.--6. " AHB_PMA_CM_I_CAP_SEL_O                         ,CMU VCO integral path cap select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "       AHB_PMA_CM_CHPMP_CHOP_ENAN_O                   ,Charge pump chop enable" "0,1"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_PMA_CM_P_CAP_SEL_O                         ,CMU VCO proportional path cap select" "0,1,2,3,4,5,6,7"
group.long 0x64++0x3
line.long 0x00 "CMU_R064,The cmu_064 register"
hexmask.long.byte 0x00 8.--14. 1. " AHB_PMA_CM_DIVPSEL_O                           ,CMU P-divider setting"
bitfld.long 0x00 3.--7. "      AHB_PMA_CM_P_KVCO_SEL_O                        ,CMU PLL KVCO setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 2. " AHB_PMA_CM_I_DROPI_O                           ,Enable to reduce charge pump reference current" "0,1"
bitfld.long 0x00 0.--1. "       AHB_PMA_CM_PFD_PW_O                            ,PFD pulse width setting" "0,1,2,3"
group.long 0x6C++0x3
line.long 0x00 "CMU_R06C,The cmu_06c register"
bitfld.long 0x00 15. " PMA_REFCLK_QFWD_R_O                            ,Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o" "0,1"
bitfld.long 0x00 14. "       PMA_REFCLK_QFWD_L_O                            ,Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
textline "                           "
bitfld.long 0x00 11. " PMA_RXCLK_OE_R_O                               ,Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
bitfld.long 0x00 10. "       PMA_RXCLK_OE_L_O                               ,'Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o'" "0,1"
textline "                           "
bitfld.long 0x00 9. " PMA_REFCLK_OE_R_O                              ,'Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o'" "0,1"
bitfld.long 0x00 8. "       PMA_REFCLK_OE_L_O                              ,Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o" "0,1"
textline "                           "
bitfld.long 0x00 7. " PMA_REFCLK_SEL_OVR_O                           ,Reference clock select override" "0,1"
bitfld.long 0x00 3.--6. "       PMA_REFCLK_OUTPUT_SEL_O_3_0                    ,Reference clock output select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 0.--2. " PMA_CM_SR_BIAS_TC_TRIM_O                       ,sr bias tc trim drving to PMA" "0,1,2,3,4,5,6,7"
group.long 0x70++0x3
line.long 0x00 "CMU_R070,The cmu_070 register"
bitfld.long 0x00 29. " EN_FRACN_FRCDIV_MODE_O                         ,Enable fractional division mode and SSC mode" "0,1"
bitfld.long 0x00 28. "       SSC_GEN_FRACSYN_EN_O                           ,Enable for SSC generator with Fractional Synthesis" "0,1"
textline "                           "
bitfld.long 0x00 5. " SSC_EN_O                                       ,Active high Enable for SSC block synth or SSC mode" "0,1"
bitfld.long 0x00 4. "       SSC_GEN_EN_O                                   ,Active high Enable for SSC generator SSC mode" "0,1"
group.long 0x74++0x3
line.long 0x00 "CMU_R074,The cmu_074 register"
group.long 0x78++0x3
line.long 0x00 "CMU_R078,The cmu_078 register"
bitfld.long 0x00 29. " PMA_CM_RX_TERM_OVR_EN_O                        ,Rx Termination override enable" "0,1"
bitfld.long 0x00 24.--28. "       PMA_CM_RX_TERM_OVR_O                           ,Rx Termination override value, every rx lane gets the same value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 21. " PMA_CM_REFCLK_TERM_OVR_EN_O                    ,Refclk Termination override enable" "0,1"
bitfld.long 0x00 16.--20. "       PMA_CM_REFCLK_TERM_OVR_O                       ,Refclk Termination override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C++0x3
line.long 0x00 "CMU_R07C,The cmu_07c register"
bitfld.long 0x00 24. " CMU_MASTER_CDN_O                               ,Master reset for CMU" "0,1"
group.long 0x80++0x3
line.long 0x00 "CMU_R080,The cmu_080 register"
bitfld.long 0x00 24.--27. " TBUS_DATA_SMPL_11_8                            ,Snapshot of digital test bus data [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "      TBUS_DATA_SMPL_7_0                             ,Snapshot of digital test bus data [7:0]"
textline "                           "
bitfld.long 0x00 12.--13. " CMU_OUT_OVR_O_1_0                              ,Override for Reset_smu_fl" "0,1,2,3"
bitfld.long 0x00 8.--11. "       CMU_IN_OVR_O_3_0                               ,Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " AMUX_OVR_O_7_0                                 ,Not used"
group.long 0x84++0x3
line.long 0x00 "CMU_R084,The cmu_084 register"
bitfld.long 0x00 8.--10. " TBUS_ADDR_OVR_O_10_8                           ,CMU Test Bus address 10-8" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "       TBUS_ADDR_OVR_O_7_0                            ,CMU Test Bus address 7-0"
group.long 0x88++0x3
line.long 0x00 "CMU_R088,The cmu_088 register"
bitfld.long 0x00 30.--31. " AHB_PMA_CM_VREGH_GEN3_O                        ,CMU VREGH setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
bitfld.long 0x00 28.--29. "       AHB_PMA_CM_VREG_GEN3_O                         ,CMU VREG setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--27. " AHB_PMA_CM_VCO_BIAS_GEN3_O                     ,CMU VCO bias current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--22. "      AHB_PMA_CM_I_CAP_SEL_GEN3_O                    ,CMU VCO integral path cap select" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19. " AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O              ,Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config" "0,1"
bitfld.long 0x00 16.--18. "       AHB_PMA_CM_P_CAP_SEL_GEN3_O                    ,CMU VCO proportional path cap select" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 15. " AHB_PMA_CM_C1_SEL_GEN3_O                       ,CMU LF C1 cap select. Enabling increases C1 cap." "0,1"
bitfld.long 0x00 14. "       AHB_PMA_CM_I_HIZ_GEN3_O                        ,CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config" "0,1"
textline "                           "
bitfld.long 0x00 12.--13. " AHB_PMA_CM_I_CP_SEL_GEN3_O                     ,Charge pump current gain select." "0,1,2,3"
bitfld.long 0x00 10.--11. "       AHB_PMA_CM_FORCE_ILF_GEN3_O                    ,CMU LF Force value in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " AHB_PMA_CM_I_KVCO_SEL_GEN3_O                   ,CMU VCO proportional current gain" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x00 "CMU_R08C,The cmu_08c register"
hexmask.long.byte 0x00 24.--30. 1. " AHB_PMA_CM_DIVPSEL_GEN3_O                      ,CMU P-divider setting in gen3 rate Used only in PCIe3 1CMU config"
bitfld.long 0x00 19.--23. "      AHB_PMA_CM_P_KVCO_SEL_GEN3_O                   ,CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 18. " AHB_PMA_CM_I_DROPI_GEN3_O                      ,Enable to reduce charge pump reference current" "0,1"
bitfld.long 0x00 16.--17. "       AHB_PMA_CM_PFD_PW_GEN3_O                       ,PFD pulse width setting in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " AHB_PMA_CM_AFE_CNTL_GEN3_O                     ,CMU AFE spares in gen3 rate Used only in PCIe3 1CMU config"
bitfld.long 0x00 5.--6. "      AHB_PMA_CM_VREGREF_GEN3_O                      ,CMU VDREGREF setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 4. " AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O       ,CMU VCO PMOS proportional current decrease" "0,1"
bitfld.long 0x00 3. "       AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O       ,CMU VCO PMOS proportional current increase" "0,1"
textline "                           "
bitfld.long 0x00 2. " AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O             ,CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config" "0,1"
bitfld.long 0x00 1. "       AHB_PMA_CM_PFD_FORCE_UP_GEN3_O                 ,Force PFD to output up in gen3 rate Used only in PCIe3 1CMU config" "0,1"
textline "                           "
bitfld.long 0x00 0. " AHB_PMA_CM_PFD_FORCE_DN_GEN3_O                 ,Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config" "0,1"
group.long 0x90++0x3
line.long 0x00 "CMU_R090,The cmu_090 register"
bitfld.long 0x00 0.--2. " AHB_PMA_CM_VCOFR_GEN3_O                        ,Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1CMU config" "0,1,2,3,4,5,6,7"
group.long 0x200++0x3
line.long 0x00 "LANE_R000,The lane_000 register"
bitfld.long 0x00 23. " AHB_RX_CLK_BRCH4_DIV_SEL_O                     ,Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 20.--22. "       AHB_RX_CLK_BRCH4_SRC_SEL_O                     ,Clock source select for RX path branch 4 clock : 3'b 000 - qd_ck_i 3'b 001- pma_lX_rxb_iRecovered byte clock 3'b 010 - lnX_clk_i 3'b 011 - pma_lX_txb_iTransmit byte clock 3'b 100 - ck_soc1_int_root 3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19. " AHB_RX_CLK_BRCH3_DIV_SEL_O                     ,Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 16.--18. "       AHB_RX_CLK_BRCH3_SRC_SEL_O                     ,Clock source select for RX path branch 3 clock : 3'b 000 - qd_ck_i 3'b 001- pma_lX_rxb_iRecovered byte clock 3'b 010 - lnX_clk_i 3'b 011 - pma_lX_txb_iTransmit byte clock 3'b 100 - ck_soc1_int_root 3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 15. " AHB_RX_CLK_BRCH2_DIV_SEL_O                     ,Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 12.--14. "       AHB_RX_CLK_BRCH2_SRC_SEL_O                     ,Clock source select for RX path branch 2 clock : 3'b 000 - pma_lX_rxb_iRecovered byte clock 3'b 001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 11. " AHB_RX_CLK_BRCH1_DIV_SEL_O                     ,Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 8.--10. "       AHB_RX_CLK_BRCH1_SRC_SEL_O                     ,Clock source select for RX path branch 1 clock : 3'b 000 - pma_lX_rxb_iRecovered byte clock 3'b 001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_1_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 7. " AHB_TX_CLK_BRCH2_DIV_SEL_O                     ,Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2" "0,1"
bitfld.long 0x00 4.--6. "       AHB_TX_CLK_BRCH2_SRC_SEL_O                     ,Clock source select for TX path branch 2 clock : 3'b 000 - lnX_clk_i 3'b 001- qd_ck_i 3'b 011 - ck_soc1_int_root 3'b010,3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_0_i" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_TX_CLK_BRCH1_SRC_SEL_O                     ,Clock source select for TX path branch 1 clock : 3'b 000 - lnX_clk_i 3'b 001- qd_ck_i 3'b 010 - pma_lX_rxb_iRecovered byte clock 3'b 011 - ck_soc1_int_root 3'b100,3'b101,3'b 110 - NOT USED 3'b 111 - test_clk_0_i" "0,1,2,3,4,5,6,7"
group.long 0x204++0x3
line.long 0x00 "LANE_R004,The lane_004 register"
bitfld.long 0x00 31. " BIST_GEN_EN_O                                  ,Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data" "0,1"
bitfld.long 0x00 30. "       BIST_GEN_WORD_O                                ,Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20" "0,1"
textline "                           "
bitfld.long 0x00 29. " BIST_GEN_CDN_O                                 ,Bist generator master reset." "0,1"
bitfld.long 0x00 28. "       BIST_TX_CLOCK_ENABLE                           ,Active HIGH clock enable signal for the BIST transmit clock" "0,1"
textline "                           "
bitfld.long 0x00 27. " BIST_GEN_ERR_O                                 ,Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern." "0,1"
bitfld.long 0x00 26. "       BIST_GEN_MODE8B_O                              ,Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits" "0,1"
textline "                           "
bitfld.long 0x00 24.--25. " BIST_RATE_O                                    ,Rate control for BIST" "0,1,2,3"
bitfld.long 0x00 23. "       PMA_LN_TXDRV_BLEED_ENA_RATE1_O                 ,txdrv regulator bleed enable for gen3 rate" "0,1"
textline "                           "
bitfld.long 0x00 22. " PMA_LN_TXDRV_BLEED_ENA_RATE2_O                 ,txdrv regulator bleed enable for gen2 rate" "0,1"
bitfld.long 0x00 21. "       DR_TXDRV_REG_BLEED_EN_O                        ,txdrv regulator bleed enable for gen1 rate" "0,1"
textline "                           "
bitfld.long 0x00 7. " CDR_IQ_CAL_EN_O                                ,IQ Calibration enable" "0,1"
group.long 0x208++0x3
line.long 0x00 "LANE_R008,The lane_008 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_GEN_EN_HIGH_O_7_0                         ,Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information."
hexmask.long.byte 0x00 16.--23. 1. "      BIST_GEN_EN_LOW_O_15_8                         ,Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test."
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_GEN_EN_LOW_O_7_0                          ,Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test."
bitfld.long 0x00 4.--6. "      BIST_GEN_INSERT_COUNT_O_2_0                    ,Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 3. " BIST_GEN_SEND_PREAM_O                          ,Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble." "0,1"
group.long 0x20C++0x3
line.long 0x00 "LANE_R00C,The lane_00c register"
bitfld.long 0x00 31. " BIST_RX_CLOCK_ENABLE                           ,Active HIGH clock enable signal for the BIST receive clock" "0,1"
bitfld.long 0x00 28.--29. "       BIST_CHK_LFSR_LENGTH_O_1_0                     ,BIST PRBS pattern selector." "0,1,2,3"
textline "                           "
bitfld.long 0x00 27. " BIST_CHK_DATA_MODE_O                           ,Bist checker mode select. 0X0 UDP pattern. 0x1 PRBS pattern" "0,1"
bitfld.long 0x00 24.--25. "       BCHK_SRC_O_1_0                                 ,BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks" "0,1,2,3"
textline "                           "
bitfld.long 0x00 22. " BCHK_CLR_O                                     ,BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block" "0,1"
bitfld.long 0x00 21. "       BCHK_EN_O                                      ,BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate" "0,1"
textline "                           "
bitfld.long 0x00 16.--19. " BIST_GEN_INSERT_DELAY_O_11_8                   ,Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "      BIST_GEN_INSERT_DELAY_O_7_0                    ,Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " BIST_GEN_EN_HIGH_O_15_8                        ,Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information."
group.long 0x210++0x3
line.long 0x00 "LANE_R010,The lane_010 register"
bitfld.long 0x00 24.--25. " BIST_CHK_PREAM1_O_9_8                          ,BIST Check Preamble" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "       BIST_CHK_PREAM1_O_7_0                          ,BIST Check Preamble"
textline "                           "
bitfld.long 0x00 13. " BIST_CHK_SYNC_ON_ZEROS                         ,Setting this bit allows BIST to sync to RX value of zero" "0,1"
bitfld.long 0x00 10.--12. "       BIST_CHK_INSERT_LENGTH_O_2_0                   ,BIST Checker Insert word length." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--9. " BIST_CHK_PREAM0_O_9_8                          ,Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block." "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "       BIST_CHK_PREAM0_O_7_0                          ,Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block."
group.long 0x214++0x3
line.long 0x00 "LANE_R014,The lane_014 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_UDP_O_31_24                           ,BIST Check User-defined pattern"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_UDP_O_23_16                           ,BIST Check User-defined pattern"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_UDP_O_15_8                            ,BIST Check User-defined pattern"
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_UDP_O_7_0                             ,BIST checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode."
group.long 0x218++0x3
line.long 0x00 "LANE_R018,The lane_018 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_INSERT_WORD_O_23_16                   ,Bist checker insertion word."
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_INSERT_WORD_O_15_8                    ,Bist checker insertion word."
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_INSERT_WORD_O_7_0                     ,Bist checker insertion word."
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_UDP_O_39_32                           ,BIST Check User-defined pattern"
group.long 0x21C++0x3
line.long 0x00 "LANE_R01C,The lane_01c register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_ERROR_15_8                            ,Bist errors detected"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_ERROR_7_0                             ,Bist errors detected"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " BIST_CHK_INSERT_WORD_O_39_32                   ,Bist checker insertion word."
hexmask.long.byte 0x00 0.--7. 1. "      BIST_CHK_INSERT_WORD_O_31_24                   ,Bist checker insertion word."
group.long 0x220++0x3
line.long 0x00 "LANE_R020,The lane_020 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_31_24                           ,LANE FSM control 1 register 31-24"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_23_16                           ,LANE FSM control 1 register 23-16"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_15_8                            ,LANE FSM control 1 register 15-8"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_7_0                             ,LANE FSM control 1 register 7-0"
group.long 0x224++0x3
line.long 0x00 "LANE_R024,The lane_024 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_63_56                           ,LANE FSM control 1 register 63-56"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_55_48                           ,LANE FSM control 1 register 55-48"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_47_40                           ,LANE FSM control 1 register 47-40"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_39_32                           ,LANE FSM control 1 register 39-32"
group.long 0x228++0x3
line.long 0x00 "LANE_R028,The lane_028 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_95_88                           ,LANE FSM control 1 register 95-88"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_87_80                           ,LANE FSM control 1 register 87-80"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_79_72                           ,LANE FSM control 1 register 79-72"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_71_64                           ,LANE FSM control 1 register 71-64"
group.long 0x22C++0x3
line.long 0x00 "LANE_R02C,The lane_02c register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_FSM_CTRL1_127_120                         ,LANE FSM control 1 register 127-120"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_FSM_CTRL1_119_112                         ,LANE FSM control 1 register 119-112"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_FSM_CTRL1_111_104                         ,LANE FSM control 1 register 111-104"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_FSM_CTRL1_103_96                          ,LANE FSM control 1 register 103-96"
group.long 0x230++0x3
line.long 0x00 "LANE_R030,The lane_030 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_HS_CAL_CNTR2_7_0                          ,LANE High speed calibration counter 2 length [7:0]"
hexmask.long.byte 0x00 16.--23. 1. "      LANE_LS_CAL_CNTR2_7_0                          ,LANE Low speed calibration counter 2 length [7:0]"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LANE_LS_CAL_CNTR1_7_0                          ,LANE Low speed calibration counter 1 length [7:0]"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_HS_CAL_CNTR1_7_0                          ,LANE High speed calibration counter 1 length [7:0]"
group.long 0x240++0x3
line.long 0x00 "LANE_R040,The lane_040 register"
bitfld.long 0x00 31. " LANE_RXIDLE_CTRL1_8                            ,LANE RXIDLE control 1 register [8]" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "       LANE_RXIDLE_CTRL2_6_0                          ,LANE RXIDLE control 2 register [6:0]"
textline "                           "
hexmask.long.byte 0x00 16.--23. 1. " LANE_RXIDLE_CTRL1_7_0                          ,LANE RXIDLE control 1 register [7:0]"
bitfld.long 0x00 10. "      BIST_PREAM_STARTED_I                           ,Preamble transmission started during BIST" "0,1"
textline "                           "
bitfld.long 0x00 9. " BIST_LFPS_DONE_I                               ,Minimum LFPS sending completed during BIST" "0,1"
bitfld.long 0x00 6.--7. "       BIST_TREPEAT_PERIOD_SEL_O                      ,Trepeat period select during BIST 00 = 6 us - 01 = 8 us - 10 = 10 us - 11 = 14 us" "0,1,2,3"
textline "                           "
bitfld.long 0x00 4.--5. " BIST_TBURST_PERIOD_SEL_O                       ,Tburst period select during BIST 00 = 0.6 us - 01 = 0.8 us - 10 = 1.0 us - 11 = 1.4 us" "0,1,2,3"
bitfld.long 0x00 0.--3. "       BIST_NUM_MIN_LFPS_O                            ,Minimum number of LFPS bursts to be send during BIST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x244++0x3
line.long 0x00 "LANE_R044,The lane_044 register"
hexmask.long.byte 0x00 16.--23. 1. " LANE_PLL_CTRL1_7_0                             ,LANE PLL control 1 register [7:0]"
hexmask.long.byte 0x00 0.--7. 1. "      LANE_RXIDLE_CTRL3_7_0                          ,LANE RXIDLE control 3 register [7:0]"
group.long 0x248++0x3
line.long 0x00 "LANE_R048,The lane_048 register"
bitfld.long 0x00 11.--13. " LANE_RXIDLE_CTRL2_9_7                          ,LANE RXIDLE control 2 register [9:7]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10. "       LANE_RXEQ_CTRL1                                ,LANE RXEQ control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 9. " LANE_PLL_CTRL3                                 ,LANE PLL control 3 register" "0,1"
bitfld.long 0x00 8. "       LANE_PLL_CTRL2                                 ,LANE PLL control 2 register" "0,1"
group.long 0x24C++0x3
line.long 0x00 "LANE_R04C,The lane_04c register"
bitfld.long 0x00 24. " SYM_ALIGN_BYPASS_O                             ,Asserting this register will bypass the symbol aligner" "0,1"
group.long 0x254++0x3
line.long 0x00 "LANE_R054,The lane_054 register"
bitfld.long 0x00 18. " RXCLK_LB_ENA_O                                 ,HS recovered clock to transmit loopback enable." "0,1"
bitfld.long 0x00 17. "       NES_LB_ENA_O                                   ,NES loopback enable." "0,1"
textline "                           "
bitfld.long 0x00 16. " FES_LB_ENA_O                                   ,FES loopback enable." "0,1"
bitfld.long 0x00 12. "       LOOPBACK_EN_O                                  ,Control signal to force decoder into loopback mode" "0,1"
group.long 0x258++0x3
line.long 0x00 "LANE_R058,The lane_058 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_PLL_CTRL5_7_0                             ,LANE PLL control 5 register [7:0]"
bitfld.long 0x00 22.--23. "      AHB_PMA_LN_VREGH_O                             ,Regulator VREGH setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 19.--21. " AHB_PMA_LN_AGC_THSEL_O                         ,AGC threshold select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "       LANE_PLL_CTRL4                                 ,RX FL calibration clock DIV4 enable" "0,1"
textline "                           "
bitfld.long 0x00 11.--13. " AHB_PMA_LN_SD_THSEL_DIV2_O                     ,Signal detect threshold select for div-by-2 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "       AHB_PMA_LN_SD_THSEL_DIV1_O                     ,Signal detect threshold select for Full rate" "0,1,2,3,4,5,6,7"
group.long 0x25C++0x3
line.long 0x00 "LANE_R05C,The lane_05c register"
bitfld.long 0x00 28.--30. " AHB_PMA_LN_INT_STEP_O                          ,CDR int step" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "       AHB_PMA_LN_BB_STEP_O                           ,CDR bb_step" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 6. " LANE_PLL_CTRL7                                 ,LANE PLL control 7 register" "0,1"
bitfld.long 0x00 2.--5. "       LANE_PLL_CTRL6_3_0                             ,LANE PLL control 6 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 0.--1. " LANE_PLL_CTRL5_9_8                             ,LANE PLL control 5 register [9:8]" "0,1,2,3"
group.long 0x260++0x3
line.long 0x00 "LANE_R060,The lane_060 register"
bitfld.long 0x00 25. " LANE_RXEQ_CTRL3                                ,LANE RXEQ control 3 register" "0,1"
bitfld.long 0x00 24. "       LANE_RXEQ_CTRL2                                ,LANE RXEQ control 2 register" "0,1"
textline "                           "
bitfld.long 0x00 8.--10. " AHB_PMA_LN_RX_SELC_O                           ,CTLE C degeneration select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "       AHB_PMA_LN_RX_SELR_O                           ,CTLE R degeneration select" "0,1,2,3,4,5,6,7"
group.long 0x264++0x3
line.long 0x00 "LANE_R064,The lane_064 register"
bitfld.long 0x00 28.--31. " PMA_LN_TXEQ_POLARITY_O_3_0                     ,TX coefficient polarity enable. Set to '1' for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "      PMA_LN_SD_BWSEL                                ,RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth" "0,1"
textline "                           "
bitfld.long 0x00 10. " PMA_LN_EYE_SGN_RST_O                           ,Reset signal for eye alignment mechanism." "0,1"
bitfld.long 0x00 9. "       EYE_SCAN_CNTR_READY_I                          ,Counter ready signal from eye scan counter block" "0,1"
textline "                           "
bitfld.long 0x00 8. " PMA_LN_EYE_DLY_O_8_8                           ,On-chip eye diagram X-direction offset control: Bits 0- 1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2- 8: Fine x-direction offset, note bit reversal" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "       PMA_LN_EYE_DLY_O_7_0                           ,On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1- 2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3- 9: Fine x-direction offset, note bit reversal"
group.long 0x268++0x3
line.long 0x00 "LANE_R068,The lane_068 register"
bitfld.long 0x00 11. " PMA_LN_TXDRV_BLEED_ENA_RATE3_O                 ,TX bleed enable" "0,1"
bitfld.long 0x00 8.--10. "       PMA_LN_TX_VREG_LEV_O_2_0                       ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
group.long 0x26C++0x3
line.long 0x00 "LANE_R06C,The lane_06c register"
bitfld.long 0x00 7. " LANE_PLL_CTRL8                                 ,LANE PLL control 8 register" "0,1"
bitfld.long 0x00 3.--5. "       AHB_PMA_LN_AGC_THSEL_GEN3_O                    ,AGC threshold select for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " AHB_PMA_LN_SD_THSEL_GEN3_O                     ,Signal detect threshold select for Gen3" "0,1,2,3,4,5,6,7"
group.long 0x270++0x3
line.long 0x00 "LANE_R070,The lane_070 register"
bitfld.long 0x00 27.--28. " CSR_GEARBOX_BYPASS_OVERRIDE_O                  ,Bypass override for gearbox." "0,1,2,3"
bitfld.long 0x00 24.--26. "       AHB_PMA_LN_RX_SELC_GEN3_O                      ,CTLE R degeneration select for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 19.--21. " AHB_PMA_LN_RX_SELR_GEN3_O                      ,CTLE R degeneration select for Gen3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "       AHB_PMA_LN_INT_STEP_GEN3_O                     ,CDR int step for Gen3" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--11. " AHB_PMA_LN_BB_STEP_GEN3_O                      ,CDR bb_step for Gen3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x274++0x3
line.long 0x00 "LANE_R074,The lane_074 register"
bitfld.long 0x00 23. " PIPE_IF_MAC_RXEQEVAL_OVR_VAL_O                 ,Override value for MAC input rxeqeval" "0,1"
bitfld.long 0x00 22. "       PIPE_IF_MAC_RXEQEVAL_OVR_EN_O                  ,Override enable for MAC input rxeqeval" "0,1"
textline "                           "
bitfld.long 0x00 21. " PIPE_IF_MAC_RXEQ_IN_PROGRESS_OVR_VAL_O         ,Override value for MAC input rxeq in progress" "0,1"
bitfld.long 0x00 20. "       PIPE_IF_MAC_RXEQ_IN_PROGRESS_OVR_EN_O          ,Override enable for MAC input rxeq in progress" "0,1"
textline "                           "
bitfld.long 0x00 19. " PIPE_IF_MAC_INVALID_REQUEST_OVR_VAL_O          ,Override value for MAC input invalid request" "0,1"
bitfld.long 0x00 18. "       PIPE_IF_MAC_INVALID_REQUEST_OVR_EN_O           ,Override enable for MAC input invalid request" "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " EYE_SCAN_ERR_CNT_7_0_I                         ,Error count from eye scan counter block."
group.long 0x278++0x3
line.long 0x00 "LANE_R078,The lane_078 register"
bitfld.long 0x00 26.--29. " AHB_TXDRV_ATT_IN_O                             ,TX Control override for txdrv_att_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 25. "      AHB_TXDRV_PREEM_1LSB_MODE_O                    ,TX Control override for txdrv_preem_1lsb_mode" "0,1"
textline "                           "
bitfld.long 0x00 24. " TX_CTRL_O_0                                    ,TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used" "0,1"
bitfld.long 0x00 20.--23. "       AHB_TX_CXN_OVR                                 ,override calibrated txterm value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " AHB_TX_CXP_OVR                                 ,override calibrated txterm value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27C++0x3
line.long 0x00 "LANE_R07C,The lane_07c register"
hexmask.long.byte 0x00 24.--30. 1. " EYE_SCAN_ERR_CNT_14_8_I                        ,Error count from eye scan counter block."
bitfld.long 0x00 23. "      RXEQ_LN_FORCE_CAL_O_6                          ,This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE" "0,1"
textline "                           "
bitfld.long 0x00 12.--15. " AHB_TXDRV_CM_IN_O                              ,TX Control override for txdrv_cm_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      AHB_TXDRV_C2_IN_O                              ,TX Control override for txdrv_c2_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 3.--7. " AHB_TXDRV_C1_IN_O                              ,TX Control override for txdrv_c1_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x280++0x3
line.long 0x00 "LANE_R080,The lane_080 register"
bitfld.long 0x00 0.--4. " EYE_SCAN_ERR_CNT_19_15_I                       ,Error count from eye scan counter block." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x288++0x3
line.long 0x00 "LANE_R088,The lane_088 register"
hexmask.long.byte 0x00 8.--15. 1. " LANE_RXIDLE_CTRL4_7_0                          ,LANE RXIDLE control 4 register [7:0]"
group.long 0x28C++0x3
line.long 0x00 "LANE_R08C,The lane_08c register"
bitfld.long 0x00 24. " LANE_RXEQ_CTRL6                                ,LANE RXEQ control 6 register" "0,1"
rgroup.long 0x290++0x3
line.long 0x00 "LANE_R090,The lane_090 register"
bitfld.long 0x00 3. " BIST_CHK_RECEIVE_PREAM_I                       ,sync receive preamble status form bist rx." "0,1"
bitfld.long 0x00 2. "       BIST_CHK_SYNCH_I                               ,sync check status form bist rx." "0,1"
group.long 0x2A8++0x3
line.long 0x00 "LANE_R0A8,The lane_0a8 register"
bitfld.long 0x00 16. " BLOCK_DEC_ERR                                  ,decoder sync header error" "0,1"
bitfld.long 0x00 0. "       INIT_RX_PRESET_HINT_EN_O                       ,Enable for primary input lnx_rx_preset_hint during init cal." "0,1"
group.long 0x32C++0x3
line.long 0x00 "LANE_R12C,The lane_12c register"
bitfld.long 0x00 30. " TXTERM_CAL_SEQ_EN_O                            ,Txterm calibration enable" "0,1"
bitfld.long 0x00 29. "       WIDTH_CHNG_EN_O                                ,Enable bit for width_chng module" "0,1"
textline "                           "
bitfld.long 0x00 26.--28. " DMUX_TXB_SEL_O_2_0                             ,Transmit mux B data input select enable." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25. "       REG0_WORD_O                                    ,Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
textline "                           "
bitfld.long 0x00 24. " REG0_BIT_O                                     ,Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
bitfld.long 0x00 22. "       REG0_POL_O                                     ,Used as Reg0 polarity select" "0,1"
textline "                           "
bitfld.long 0x00 21. " REG1_WORD_O                                    ,Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
bitfld.long 0x00 20. "       REG1_BIT_O                                     ,Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
textline "                           "
bitfld.long 0x00 19. " REG1_POL_O                                     ,Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
bitfld.long 0x00 18. "       TREG1_WORD_O                                   ,TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
textline "                           "
bitfld.long 0x00 17. " TREG1_BIT_O                                    ,TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
bitfld.long 0x00 16. "       TREG1_POL_O                                    ,TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
textline "                           "
bitfld.long 0x00 14. " P2S_RBUF_AUTOFIX_O                             ,P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow" "0,1"
bitfld.long 0x00 12.--13. "       DMUX_TXA_SEL_O_1_0                             ,Transmit mux A data input select." "0,1,2,3"
textline "                           "
bitfld.long 0x00 11. " TREG0_WORD_O                                   ,TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped." "0,1"
bitfld.long 0x00 10. "       TREG0_BIT_O                                    ,TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed." "0,1"
textline "                           "
bitfld.long 0x00 9. " TREG0_POL_O                                    ,TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed." "0,1"
bitfld.long 0x00 8. "       RX_SRC_O                                       ,RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder." "0,1"
group.long 0x330++0x3
line.long 0x00 "LANE_R130,The lane_130 register"
bitfld.long 0x00 31. " USB_LFPS_MODE                                  ,Signal Detect USB mode enable. When disabled it bypasses LFPS detection and makes usb mode 0 to PMA" "0,1"
bitfld.long 0x00 30. "       SAPIS_EN_O                                     ,SAPIS interface block enable." "0,1"
textline "                           "
bitfld.long 0x00 29. " PIPE_EN_O                                      ,PIPE interface block enable." "0,1"
bitfld.long 0x00 16.--19. "       AHB_TX_CDAC_OVR                                ,TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 15. " DEC_EN_O                                       ,8b/10b decoder enable." "0,1"
bitfld.long 0x00 14. "       ENC_EN_O                                       ,8b/10b encoder enable." "0,1"
textline "                           "
bitfld.long 0x00 12.--13. " MODE_8B_O_1_0                                  ,8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits" "0,1,2,3"
bitfld.long 0x00 10.--11. "       AHB_LN_TXBIT_REPEAT_O                          ,Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2b 00: no bit stuffing nor stripping 2b 01: 2x bit stuffing and stripping 2b 10: NOT USED 2b 11: 4x bit stuffing and stripping" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " AHB_TXMAC_THRESHOLD_O                          ,An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o." "0,1,2,3"
bitfld.long 0x00 5.--6. "       AHB_MAC_WIDTH_O                                ,Data width selector for PCS/MAC interface. 2b 00: GigE or XAUI 2b 01: GigE or XAUI 2b 10: RXAUI 2b 11: XFI" "0,1,2,3"
textline "                           "
bitfld.long 0x00 3.--4. " AHB_LN_RXBIT_STRIP_O                           ,Bit stripping on rxdata from PMA to PCS 2b 00: no bit stripping 2b 01: 2x bit stripping 2b 10: NOT USED 2b 11: 4x bit stripping" "0,1,2,3"
bitfld.long 0x00 0.--2. "       AHB_PMA_SR_TXDRV_TERM_CAL_PSEL_O               ,tx termination calibration comparator threshold select" "0,1,2,3,4,5,6,7"
group.long 0x334++0x3
line.long 0x00 "LANE_R134,The lane_134 register"
bitfld.long 0x00 31. " DIS_EIEOS_CHK_IN_LB_O                          ,Disables the EIEOS check in loopback" "0,1"
bitfld.long 0x00 30. "       DIS_BLOCK_ALIGN_CTRL_O                         ,Disables the primary input lnX_block_align_control" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " PIPE_LFREQ                                     ,LF value for full swing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 21. "      EN_SKPOS_ERR_O                                 ,Enables skpos error status propagation in Gen3" "0,1"
textline "                           "
bitfld.long 0x00 20. " EBUF_SKP_REM_EN_O                              ,Elastic buffer SKP remove enable" "0,1"
bitfld.long 0x00 19. "       RBUF_RSTN_O                                    ,TX FIFO synchronous reset" "0,1"
textline "                           "
bitfld.long 0x00 18. " EBUF_SKP_ADD_EN_O                              ,Elastic buffer SKP add enable" "0,1"
bitfld.long 0x00 17. "       ALIGN_RSTN_O                                   ,Synchronous clear for block/symbol aligner" "0,1"
textline "                           "
bitfld.long 0x00 16. " EBUF_RSTN_O                                    ,Synchronous clear for elastic buffer" "0,1"
bitfld.long 0x00 1. "       BLOCK_ENC_CLR_ERR_O                            ,128b/130b encoder clear error" "0,1"
group.long 0x338++0x3
line.long 0x00 "LANE_R138,The lane_138 register"
hexmask.long.byte 0x00 24.--31. 1. " LANE_BEACON_CTRL1_7_0                          ,LANE beacon control 1 register [7:0]"
bitfld.long 0x00 19. "      LANE_REG_CTRL1                                 ,LANE regulator control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 18. " LANE_PLL_CTRL10                                ,LANE PLL control 10 register" "0,1"
bitfld.long 0x00 17. "       LANE_PLL_CTRL9                                 ,LANE PLL control 9 register" "0,1"
textline "                           "
bitfld.long 0x00 16. " GEN1_OLD_RXDATA_SRC                            ,Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i" "0,1"
bitfld.long 0x00 8.--13. "       PIPE_FS_O_5_0                                  ,Full swing value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 2.--5. " P2S_RBUF_BUF_THRESH_O_3_0                      ,TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "      RXVALID_DIS_AT_RATE_CHG_O_0                    ,Value 1 forces rxvalid to be deasserted during rate change to gen 3" "0,1"
textline "                           "
bitfld.long 0x00 0. " COEF_FE_LIMIT_EN_O                             ,FE TxEq Co-efficient Limiting Enable control" "0,1"
group.long 0x33C++0x3
line.long 0x00 "LANE_R13C,The lane_13c register"
bitfld.long 0x00 28.--29. " LOCKED_OVR_O_1_0                               ,Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value." "0,1,2,3"
bitfld.long 0x00 26.--27. "       RXDET_STATUS_OVR_O_1_0                         ,Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value." "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " TXDETECTRX_OVR_O_1_0                           ,Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value." "0,1,2,3"
bitfld.long 0x00 20.--21. "       RXEQ_SIGDET_1_0                                ,Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value" "0,1,2,3"
textline "                           "
bitfld.long 0x00 16.--17. " SIGDET_OVR_O_1_0                               ,Bit[0]: Overide value. Bit[1] :Override enable for signal detect output" "0,1,2,3"
bitfld.long 0x00 12.--15. "       REGP_OVR_3_0                                   ,Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty Bit[1]: Overide values for bit reverse Bit[2]: Overide values for word reverse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 11. " ENC_EN_OVR_O                                   ,Enables 16b/20b encoder" "0,1"
bitfld.long 0x00 10. "       DEC_EN_OVR_O                                   ,Enables 16b/20b decoder" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " LANE_BEACON_CTRL1_11_8                         ,LANE beacon control 1 register [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x3
line.long 0x00 "LANE_R140,The lane_140 register"
hexmask.long.byte 0x00 24.--31. 1. " LN_IN_OVR_O_31_24                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 16.--23. 1. "      LN_IN_OVR_O_23_16                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LN_IN_OVR_O_15_8                               ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 0.--7. 1. "      LN_IN_OVR_O_7_0                                ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
group.long 0x344++0x3
line.long 0x00 "LANE_R144,The lane_144 register"
bitfld.long 0x00 24.--28. " LANE_PLL_CTRL11                                ,Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150ns delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 23. "      LN_IN_OVR_O_49                                 ," "0,1"
textline "                           "
bitfld.long 0x00 22. " OOB_DET_EN                                     ,OOB detect enable" "0,1"
bitfld.long 0x00 18.--21. "       REGP1_OVR_O_3_0                                ,Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty Bit[1]: Overide values for bit reverse Bit[2]: Overide values for word reverse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 17. " AHB_LN_IN_OVR_CHG_FLAG_O                       ,Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes." "0,1"
bitfld.long 0x00 16. "       LN_IN_OVR_O_48                                 ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used" "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " LN_IN_OVR_O_47_40                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
hexmask.long.byte 0x00 0.--7. 1. "      LN_IN_OVR_O_39_32                              ,Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit { [17:15], [3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used"
group.long 0x348++0x3
line.long 0x00 "LANE_R148,The lane_148 register"
bitfld.long 0x00 24.--26. " LN_IN_OVR_O_58_56                              ,Override signals for lane: main interface control [57:55]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--23. "       LN_IN_OVR_O_54_51                              ,Override signals for lane: main interface control [46:43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 19. " LN_IN_OVR_O_50                                 ,Override signals for lane: msm_ln_rate_ow [4:2]" "0,1"
bitfld.long 0x00 15. "       LN_IN_OVR_O_65                                 ,Lane Reset" "0,1"
textline "                           "
bitfld.long 0x00 9.--14. " LN_IN_OVR_O_64_59                              ,Override signals for lane: main interface control [53:48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8. "      LN_IN_OVR_O_55                                 ,Override signals for lane: main interface control[47]" "0,1"
textline "                           "
bitfld.long 0x00 4.--5. " LANE_REG_CTRL4_1_0                             ,LANE regulator control 4 register [1:0]" "0,1,2,3"
bitfld.long 0x00 2.--3. "       LANE_REG_CTRL3_1_0                             ,LANE regulator control 3 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--1. " LANE_REG_CTRL2_1_0                             ,LANE regulator control 2 register [1:0]" "0,1,2,3"
group.long 0x34C++0x3
line.long 0x00 "LANE_R14C,The lane_14c register"
bitfld.long 0x00 24.--26. " PMA_LN_SR_TXREG_ICTRL_RATE2_O                  ,Tx regulator integral path control setting for PCIe3 Gen3 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19.--21. "       PMA_LN_SR_TXREG_ICTRL_RATE3_O                  ,Tx regulator integral path control setting for PCIe3 Gen3 rate" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 18. " PMA_LN_SR_TXDP_REGULATOR_LDR_EN_O              ,Txdp regulator enable for PCIe Gen1/2 rate" "0,1"
bitfld.long 0x00 17. "       PMA_LN_GEN3_SR_TXDP_REGULATOR_LDR_EN_O         ,Txdp regulator enable for PCIe Gen3 rate" "0,1"
textline "                           "
bitfld.long 0x00 10.--11. " AHB_PMA_LN_SR_LANE_VREGTXA_O                   ,Lane VREGTXA setting" "0,1,2,3"
bitfld.long 0x00 8.--9. "       LN_MSM_SR_TXREG_ICTRL_O                        ,vco regulator override" "0,1,2,3"
textline "                           "
bitfld.long 0x00 6.--7. " LN_MSM_DR_REGH_CTRL_OVR_O                      ,vco regulator override" "0,1,2,3"
bitfld.long 0x00 4.--5. "       AHB_PMA_LN_SR_LANE_VREGA_O                     ,Lane VREGA setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 2.--3. " AHB_PMA_LN_SR_SLICER_VCM_SEL_O                 ,Slicer common mode select" "0,1,2,3"
group.long 0xA00++0x3
line.long 0x00 "COMLANE_R000,The comlane_000 register"
hexmask.long.byte 0x00 24.--31. 1. " BIST_CHK_ALIGN_PATTERN_GEN3_O_15_8             ,BIST alignment pattern for Gen3"
hexmask.long.byte 0x00 16.--23. 1. "      BIST_CHK_ALIGN_PATTERN_GEN3_O_7_0              ,BIST alignment pattern for Gen3"
textline "                           "
bitfld.long 0x00 10. " ASYNC_POWER_CHANGE_ACK_EN_O                    ,When asserted supports PIPE 4-3 spec" "0,1"
bitfld.long 0x00 9. "       BIST_GEN_INV_PRBS_O                            ,Enable/Disable the internal PRBS data pattern inverter. 0x0 Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types." "0,1"
textline "                           "
bitfld.long 0x00 8. " BIST_CHK_INV_PRBS_O                            ,Enable/Disable the internal PRBS data pattern inverter. 0x0 Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types." "0,1"
group.long 0xA14++0x3
line.long 0x00 "COMLANE_R014,The comlane_014 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_BUFFER_CTRL1_7_0                           ,COMLANE buffer control 1 register [7:0]"
bitfld.long 0x00 16. "      SYNC_HDR_QUAL_EN_O                             ,Enables block_aligner skpos_hdr_det qualification" "0,1"
group.long 0xA18++0x3
line.long 0x00 "COMLANE_R018,The comlane_018 register"
bitfld.long 0x00 16.--17. " COM_BUFFER_CTRL2_9_8                           ,COMLANE buffer control 2 register [9:8]" "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "       COM_BUFFER_CTRL2_7_0                           ,COMLANE buffer control 2 register [7:0]"
textline "                           "
bitfld.long 0x00 0.--1. " COM_BUFFER_CTRL1_9_8                           ,COMLANE buffer control 1 register [9:8]" "0,1,2,3"
group.long 0xA1C++0x3
line.long 0x00 "COMLANE_R01C,The comlane_01c register"
bitfld.long 0x00 31. " COM_BER_CTRL1                                  ,COMLANE ber control 1 register" "0,1"
bitfld.long 0x00 30. "       COM_BER_CTRL1                                  ,COMLANE beacon control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " COM_BUFFER_CTRL3_5_0                           ,COMLANE buffer control 3 register [5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA30++0x3
line.long 0x00 "COMLANE_R030,The comlane_030 register"
hexmask.long.byte 0x00 24.--31. 1. " EYE_SCAN_MASK_O_15_8                           ,Mask eye scan results"
hexmask.long.byte 0x00 16.--23. 1. "      EYE_SCAN_MASK_O_7_0                            ,Mask eye scan results"
textline "                           "
bitfld.long 0x00 10.--13. " EYE_SCAN_EYE_DATA_SHIFT_O                      ,Shift edge samples" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "      EYE_SCAN_RUN_O                                 ,Run eye scan counter" "0,1"
textline "                           "
bitfld.long 0x00 8. " EYE_SCAN_COUNTER_EN_O                          ,Enable eye scan counter" "0,1"
group.long 0xA34++0x3
line.long 0x00 "COMLANE_R034,The comlane_034 register"
bitfld.long 0x00 23. " EI_GLUE_MASK_SIGDET_GEN3_O                     ,Mask bits for Gen3 rate for EI Infererence" "0,1"
bitfld.long 0x00 22. "       EI_GLUE_MASK_SIGDET_GEN2_O                     ,Mask bits for Gen2 rate for EI Infererence" "0,1"
textline "                           "
bitfld.long 0x00 21. " EI_GLUE_MASK_SIGDET_GEN1_O                     ,Mask bits for Gen1 rate for EI Infererence" "0,1"
bitfld.long 0x00 20. "       QD_CLK_LANE_CLK_SEL_O                          ,Selects quad clock for Tx Mux 2 and Rx Mux 4" "0,1"
textline "                           "
bitfld.long 0x00 16.--19. " EYE_SCAN_WAIT_LEN_O_11_8                       ,Eye scan wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "      EYE_SCAN_WAIT_LEN_O_7_0                        ,Eye scan wait time"
textline "                           "
bitfld.long 0x00 0.--3. " EYE_SCAN_MASK_O_19_16                          ,Mask eye scan results" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA38++0x3
line.long 0x00 "COMLANE_R038,The comlane_038 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_31_24                            ,COMLANE FSM control 1 register 31-24"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_23_16                            ,COMLANE FSM control 1 register 23-16"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_15_8                             ,COMLANE FSM control 1 register 15-8"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_7_0                              ,COMLANE FSM control 1 register 7-0"
group.long 0xA3C++0x3
line.long 0x00 "COMLANE_R03C,The comlane_03c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_63_56                            ,COMLANE FSM control 1 register 63-56"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_55_48                            ,COMLANE FSM control 1 register 55-48"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_47_40                            ,COMLANE FSM control 1 register 47-40"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_39_32                            ,COMLANE FSM control 1 register 39-32"
group.long 0xA40++0x3
line.long 0x00 "COMLANE_R040,The comlane_040 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_95_88                            ,COMLANE FSM control 1 register 95-88"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_87_80                            ,COMLANE FSM control 1 register 87-80"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_79_72                            ,COMLANE FSM control 1 register 79-72"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_71_64                            ,COMLANE FSM control 1 register 71-64"
group.long 0xA44++0x3
line.long 0x00 "COMLANE_R044,The comlane_044 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL1_127_120                          ,COMLANE FSM control 1 register 127-120"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL1_119_112                          ,COMLANE FSM control 1 register 119-112"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL1_111_104                          ,COMLANE FSM control 1 register 111-104"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL1_103_96                           ,COMLANE FSM control 1 register 103-96"
group.long 0xA48++0x3
line.long 0x00 "COMLANE_R048,The comlane_048 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_15_8                             ,COMLANE FSM control 2 register [15:8]"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_7_0                              ,COMLANE FSM control 2 register [7:0]"
group.long 0xA4C++0x3
line.long 0x00 "COMLANE_R04C,The comlane_04c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_47_40                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_39_32                            ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_31_24                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_23_16                            ,COMLANE FSM control 2 register"
group.long 0xA50++0x3
line.long 0x00 "COMLANE_R050,The comlane_050 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_79_72                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_71_64                            ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_63_56                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_55_48                            ,COMLANE FSM control 2 register"
group.long 0xA54++0x3
line.long 0x00 "COMLANE_R054,The comlane_054 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_111_104                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_103_96                           ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_95_88                            ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_87_80                            ,COMLANE FSM control 2 register"
group.long 0xA58++0x3
line.long 0x00 "COMLANE_R058,The comlane_058 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_143_136                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_135_128                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_127_120                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_119_112                          ,COMLANE FSM control 2 register"
group.long 0xA5C++0x3
line.long 0x00 "COMLANE_R05C,The comlane_05c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_175_168                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_167_160                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_159_152                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_151_144                          ,COMLANE FSM control 2 register"
group.long 0xA60++0x3
line.long 0x00 "COMLANE_R060,The comlane_060 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_207_200                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_199_192                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_191_184                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_183_176                          ,COMLANE FSM control 2 register"
group.long 0xA64++0x3
line.long 0x00 "COMLANE_R064,The comlane_064 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_239_232                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_231_224                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_223_216                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_215_208                          ,COMLANE FSM control 2 register"
group.long 0xA68++0x3
line.long 0x00 "COMLANE_R068,The comlane_068 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_271_264                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_263_256                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_255_248                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_247_240                          ,COMLANE FSM control 2 register"
group.long 0xA6C++0x3
line.long 0x00 "COMLANE_R06C,The comlane_06c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_303_296                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_295_288                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_287_280                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_279_272                          ,COMLANE FSM control 2 register"
group.long 0xA70++0x3
line.long 0x00 "COMLANE_R070,The comlane_070 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_335_328                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_327_320                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_319_312                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_311_304                          ,COMLANE FSM control 2 register"
group.long 0xA74++0x3
line.long 0x00 "COMLANE_R074,The comlane_074 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_367_360                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_359_352                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_351_344                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_343_336                          ,COMLANE FSM control 2 register"
group.long 0xA78++0x3
line.long 0x00 "COMLANE_R078,The comlane_078 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_399_392                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_391_384                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_383_376                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_375_368                          ,COMLANE FSM control 2 register"
group.long 0xA7C++0x3
line.long 0x00 "COMLANE_R07C,The comlane_07c register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_431_424                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_423_416                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_415_408                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_407_400                          ,COMLANE FSM control 2 register"
group.long 0xA80++0x3
line.long 0x00 "COMLANE_R080,The comlane_080 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_463_456                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_455_448                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_447_440                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_439_432                          ,COMLANE FSM control 2 register"
group.long 0xA84++0x3
line.long 0x00 "COMLANE_R084,The comlane_084 register"
hexmask.long.byte 0x00 24.--31. 1. " COM_FSM_CTRL2_495_488                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 16.--23. 1. "      COM_FSM_CTRL2_487_480                          ,COMLANE FSM control 2 register"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_479_472                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_471_464                          ,COMLANE FSM control 2 register"
group.long 0xA88++0x3
line.long 0x00 "COMLANE_R088,The comlane_088 register"
hexmask.long.byte 0x00 8.--15. 1. " COM_FSM_CTRL2_511_504                          ,COMLANE FSM control 2 register"
hexmask.long.byte 0x00 0.--7. 1. "      COM_FSM_CTRL2_503_496                          ,COMLANE FSM control 2 register"
group.long 0xAAC++0x3
line.long 0x00 "COMLANE_R0AC,The comlane_0ac register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMINIT_MIN_O_7_0                      ,OOB detector COMINIT maximum idle length."
hexmask.long.byte 0x00 16.--22. 1. "      OOB_DET_BLEN_MAX_O_6_0                         ,OOB detector maximum burst length."
textline "                           "
hexmask.long.byte 0x00 8.--14. 1. " OOB_DET_BLEN_MIN_O_6_0                         ,OOB detector minimum burst length."
group.long 0xAB0++0x3
line.long 0x00 "COMLANE_R0B0,The comlane_0b0 register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMWAKE_MIN_O_7_0                      ,OOB detector COMWAKE minimum idle length."
bitfld.long 0x00 16. "      OOB_DET_COMINIT_MAX_O_8                        ,OOB detector COMINIT maximum idle length." "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " OOB_DET_COMINIT_MAX_O_7_0                      ,OOB detector COMINIT maximum idle length."
bitfld.long 0x00 0. "      OOB_DET_COMINIT_MIN_O_8                        ,OOB detector COMINIT maximum idle length." "0,1"
group.long 0xAB4++0x3
line.long 0x00 "COMLANE_R0B4,The comlane_0b4 register"
hexmask.long.byte 0x00 24.--31. 1. " OOB_DET_COMSAS_MIN_O_7_0                       ,OOB detector COMSAS maximum idle length."
bitfld.long 0x00 16. "      OOB_DET_COMWAKE_MAX_O_8                        ,OOB detector COMWAKE maximum idle length." "0,1"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " OOB_DET_COMWAKE_MAX_O_7_0                      ,OOB detector COMWAKE maximum idle length."
bitfld.long 0x00 0. "      OOB_DET_COMWAKE_MIN_O_8                        ,OOB detector COMWAKE minimum idle length." "0,1"
group.long 0xAB8++0x3
line.long 0x00 "COMLANE_R0B8,The comlane_0b8 register"
bitfld.long 0x00 16. " OOB_DET_COMSAS_MAX_O_8                         ,OOB detector COMSAS maximum idle length." "0,1"
hexmask.long.byte 0x00 8.--15. 1. "       OOB_DET_COMSAS_MAX_O_7_0                       ,OOB detector COMSAS maximum idle length."
textline "                           "
bitfld.long 0x00 0. " OOB_DET_COMSAS_MIN_O_8                         ,OOB detector COMSAS maximum idle length." "0,1"
group.long 0xABC++0x3
line.long 0x00 "COMLANE_R0BC,The comlane_0bc register"
bitfld.long 0x00 28.--31. " TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0            ,TX master coefficient polarity overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_RATE3_TXEQ_POLARITY_3_0                 ,TX rate3 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_RATE2_TXEQ_POLARITY_3_0                 ,TX rate2 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_RATE1_TXEQ_POLARITY_3_0                 ,TX rate1 coefficent polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_MASTER_TX_SR_DAC_OVR_3_0                ,TX master slew rate DAC overrides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_RATE3_TX_SR_DAC_3_0                     ,TX rate3 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_RATE2_TX_SR_DAC_3_0                     ,TX rate2 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_RATE1_TX_SR_DAC_3_0                     ,TX rate1 slew rate DAC setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC0++0x3
line.long 0x00 "COMLANE_R0C0,The comlane_0c0 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0  ,PIPE tx_margin low swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC4++0x3
line.long 0x00 "COMLANE_R0C4,The comlane_0c4 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0 ,PIPE tx_margin full swing setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC8++0x3
line.long 0x00 "COMLANE_R0C8,The comlane_0c8 register"
bitfld.long 0x00 30. " TXCTRL_MASTER_OVR_EN_O                         ,Tx control master override enable" "0,1"
bitfld.long 0x00 27.--29. "       TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0            ,TX enable fastest slew rate override." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 24.--26. " TXCTRL_RATE3_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 21.--23. "       TXCTRL_RATE2_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 18.--20. " TXCTRL_RATE1_TX_SLEW_SLD3F_2_0                 ,TX enable fastest slew rate set to 1." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 17. "       TXCTRL_MASTER_PREEM_1LSB_MODE_OVR              ,TX master 1lsb mode overrides." "0,1"
textline "                           "
bitfld.long 0x00 16. " TXCTRL_PREEM_1LSB_MODE                         ,TX 1lsb mode" "0,1"
bitfld.long 0x00 14.--15. "       TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0              ,TX master slew rate setting overrides." "0,1,2,3"
textline "                           "
bitfld.long 0x00 12.--13. " TXCTRL_RATE3_TX_SLEW_SLD_1_0                   ,TX rate3 slew rate setting" "0,1,2,3"
bitfld.long 0x00 10.--11. "       TXCTRL_RATE2_TX_SLEW_SLD_1_0                   ,TX rate2 slew rate setting" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--9. " TXCTRL_RATE1_TX_SLEW_SLD_1_0                   ,TX rate1 slew rate setting" "0,1,2,3"
bitfld.long 0x00 0.--3. "       TXCTRL_MASTER_ATT_IN_OVR_3_0                   ,Override value for att in." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xACC++0x3
line.long 0x00 "COMLANE_R0CC,The comlane_0cc register"
bitfld.long 0x00 24.--28. " TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0             ,TX rate2 full swing C1 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--23. "      TXCTRL_RATE1_LOWSWG_C2_IN_3_0                  ,TX rate1 low swing C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " TXCTRL_RATE1_FULLSWG_C2_IN_3_0                 ,TX rate1 full swing C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--12. "      TXCTRL_RATE1_LOWSWG_C1_IN_4_0                  ,TX rate1 low swing C1 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 0.--4. " TXCTRL_RATE1_FULLSWG_6DB_C1_IN_4_0             ,TX rate1 full swing C1 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD0++0x3
line.long 0x00 "COMLANE_R0D0,The comlane_0d0 register"
bitfld.long 0x00 28.--31. " TXCTRL_RATE3_C2_IN_3_0                         ,TX rate3 C2 coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_RATE2_LOWSWG_C2_IN_3_0                  ,TX rate2 low swing C2 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--20. " TXCTRL_RATE2_LOWSWG_C1_IN_4_0                  ,TX rate2 low swing C1 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--15. "      TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0           ,TX rate2 full swing C2 coefficient for 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0             ,TX rate2 full swing C2 coefficient for 6 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "      TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0           ,TX rate2 full swing C1 coefficient for 3.5 dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD4++0x3
line.long 0x00 "COMLANE_R0D4,The comlane_0d4 register"
bitfld.long 0x00 31. " TXEQ_C1_FORCE_LOW_EN_O                         ,Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed" "0,1"
bitfld.long 0x00 30. "       TXEQ_CM1_FORCE_LOW_EN_O                        ,Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed" "0,1"
textline "                           "
bitfld.long 0x00 24.--29. " REDUCED_SWING_LF_VAL_O_5_0                     ,Reduced swing LowFreq value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20.--23. "      TXCTRL_MASTER_CM_IN_OVR_3_0                    ,TX master CM coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 16.--19. " TXCTRL_RATE2_CM_IN_3_0                         ,TX rate2 CM coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "      TXCTRL_RATE1_CM_IN_3_0                         ,TX rate1 CM coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 8.--11. " TXCTRL_MASTER_C2_IN_OVR_3_0                    ,TX master C2 coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "      TXCTRL_MASTER_C1_IN_OVR_4_0                    ,TX master C1 coefficient overrides." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAD8++0x3
line.long 0x00 "COMLANE_R0D8,The comlane_0d8 register"
bitfld.long 0x00 8.--10. " ATT_INIT_LOAD_ATT_VAL_O                        ,AGC initial ATT value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "       RX_BIAS_RATE3_O                                ,AFE rx_bias setting. Used when rxvcodiv is 01 or 10" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 0.--2. " RX_BIAS_RATE2_O                                ,AFE rx_bias setting. Used when rxvcodiv is 00" "0,1,2,3,4,5,6,7"
group.long 0xAE0++0x3
line.long 0x00 "COMLANE_R0E0,The comlane_0e0 register"
bitfld.long 0x00 4. " COM_FSM_CTRL7                                  ,COMLANE FSM control 7 register" "0,1"
bitfld.long 0x00 3. "       COM_FSM_CTRL6                                  ,COMLANE FSM control 6 register" "0,1"
textline "                           "
bitfld.long 0x00 2. " COM_FSM_CTRL5                                  ,COMLANE FSM control 5 register" "0,1"
bitfld.long 0x00 1. "       COM_FSM_CTRL4                                  ,COMLANE FSM control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 0. " COM_FSM_CTRL3                                  ,COMLANE FSM control 3 register" "0,1"
group.long 0xAFC++0x3
line.long 0x00 "COMLANE_R0FC,The comlane_0fc register"
group.long 0xB04++0x3
line.long 0x00 "COMLANE_R104,The comlane_104 register"
bitfld.long 0x00 30.--31. " ATT_INIT_LOAD_GAIN_VAL_O                       ,Initial AGC gain value" "0,1,2,3"
group.long 0xB14++0x3
line.long 0x00 "COMLANE_R114,The comlane_114 register"
rgroup.long 0xB18++0x3
line.long 0x00 "COMLANE_R118,The comlane_118 register"
bitfld.long 0x00 28.--31. " TXEQ_ADAPT_DONE_I_3_0                          ,TXEQ Adapt Done status - per lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      RXEQ_CAL_DONE_I_3_0                            ,RXEQ calibration done status - per lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB1C++0x3
line.long 0x00 "COMLANE_R11C,The comlane_11c register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB20++0x3
line.long 0x00 "COMLANE_R120,The comlane_120 register"
bitfld.long 0x00 24.--27. " TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0   ,PIPE tx_margin low swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB24++0x3
line.long 0x00 "COMLANE_R124,The comlane_124 register"
bitfld.long 0x00 28.--31. " TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "      TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 20.--23. " TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 12.--15. " TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 4.--7. " TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0  ,PIPE tx_margin full swing setting rate3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB28++0x3
line.long 0x00 "COMLANE_R128,The comlane_128 register"
hexmask.long.byte 0x00 24.--31. 1. " TXEQ_CM1_CYCLE_LEN_O_7_0                       ,Txeq CM1 coefficient adpatation error measurment wait time during each iteration"
bitfld.long 0x00 16.--18. "      TXCTRL_MASTER_VREG_LEV_OVR_2_0                 ,Does not exist!" "0,1,2,3,4,5,6,7"
textline "                           "
bitfld.long 0x00 8.--10. " TXCTRL_RATE3_TX_VREG_LEV_2_0                   ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "       TXCTRL_RATE12_TX_VREG_LEV_2_0                  ,TX driver regulator voltage setting." "0,1,2,3,4,5,6,7"
group.long 0xB2C++0x3
line.long 0x00 "COMLANE_R12C,The comlane_12c register"
hexmask.long.byte 0x00 16.--23. 1. " VERSION_REG                                    ,Version register"
hexmask.long.byte 0x00 0.--7. 1. "      TXEQ_C1_CYCLE_LEN_O_7_0                        ,Txeq C1 coefficient adpatation error measurment wait time during each iteration"
group.long 0xB38++0x3
line.long 0x00 "COMLANE_R138,The comlane_138 register"
hexmask.long.byte 0x00 16.--23. 1. " CONFIG_VERSION_REG                             ,Config files write their version into these registers"
group.long 0xB54++0x3
line.long 0x00 "COMLANE_R154,The comlane_154 register"
hexmask.long.byte 0x00 24.--31. 1. " QAHB_LN_SYM_COM_P_9_2_O                        ,COM symbol for LB_BERT"
bitfld.long 0x00 22.--23. "      QAHB_LN_SYM_COM_P_1_0_O                        ,COM symbol for LB_BERT" "0,1,2,3"
group.long 0xB58++0x3
line.long 0x00 "COMLANE_R158,The comlane_158 register"
bitfld.long 0x00 24.--28. " TXCTRL_RATE1_LOWSWG_0DB_C1_4_0                 ,TX rate1 low swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "      TXCTRL_RATE1_FULLSWG_3P5DB_C1_4_0              ,TX rate1 full swing C1 coefficient 3.5db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB5C++0x3
line.long 0x00 "COMLANE_R15C,The comlane_15c register"
bitfld.long 0x00 16.--20. " TXCTRL_RATE2_LOWSWG_0DB_C1_4_0                 ,TX rate2 low swing C1 coefficient 0 db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "      TXCTRL_RATE2_FULLSWG_0DB_C1_4_0                ,TX rate2 full swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 0.--4. " TXCTRL_RATE1_FULLSWG_0DB_C1_4_0                ,TX rate1 full swing C1 coefficient 0db" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB6C++0x3
line.long 0x00 "COMLANE_R16C,The comlane_16c register"
bitfld.long 0x00 25.--27. " COM_FSM_CTRL10_2_0                             ,COMLANE FSM control 10 register [2:0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "       COM_FSM_CTRL9                                  ,COMLANE FSM control 9 register" "0,1"
textline "                           "
hexmask.long.byte 0x00 16.--23. 1. " COM_FSM_CTRL8_7_0                              ,COMLANE FSM control 8 register [7:0]"
rgroup.long 0xB74++0x3
line.long 0x00 "COMLANE_R174,The comlane_174 register"
bitfld.long 0x00 12.--15. " LN3_RX_LOCKED_I_15_12                          ,Lane 3 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      LN2_RX_LOCKED_I_11_8                           ,Lane 2 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB90++0x3
line.long 0x00 "COMLANE_R190,The comlane_190 register"
bitfld.long 0x00 11. " L3_MASTER_CDN_O                                ,Lane3 master reset" "0,1"
bitfld.long 0x00 10. "       L2_MASTER_CDN_O                                ,Lane2 master reset" "0,1"
textline "                           "
bitfld.long 0x00 9. " L1_MASTER_CDN_O                                ,Lane1 master reset" "0,1"
bitfld.long 0x00 8. "       L0_MASTER_CDN_O                                ,Lane0 master reset" "0,1"
rgroup.long 0xB94++0x3
line.long 0x00 "COMLANE_R194,The comlane_194 register"
bitfld.long 0x00 31. " LN3_OK_I_7                                     ,Lane 3 OK Status" "0,1"
bitfld.long 0x00 30. "       LN2_OK_I_6                                     ,Lane 2 OK Status" "0,1"
textline "                           "
bitfld.long 0x00 29. " LN1_OK_I_5                                     ,Lane 1 OK Status" "0,1"
bitfld.long 0x00 28. "       LN0_OK_I_4                                     ,Lane 0 OK Status" "0,1"
textline "                           "
bitfld.long 0x00 27. " LN3_SIG_LEVEL_VALID_I_3                        ,Lane 3 Signal Detect Valid Status" "0,1"
bitfld.long 0x00 26. "       LN2_SIG_LEVEL_VALID_I_2                        ,Lane 2 Signal Detect Valid Status" "0,1"
textline "                           "
bitfld.long 0x00 25. " LN1_SIG_LEVEL_VALID_I_1                        ,Lane 1 Signal Detect Valid Status" "0,1"
bitfld.long 0x00 24. "       LN0_SIG_LEVEL_VALID_I_0                        ,Lane 0 Signal Detect Valid Status" "0,1"
textline "                           "
bitfld.long 0x00 20. " CMU1_OK_I_1                                    ,CMU1 OK Status" "0,1"
bitfld.long 0x00 19. "       CMU_OK_I_0                                     ,CMU OK Status" "0,1"
textline "                           "
bitfld.long 0x00 16.--18. " MODE_I_2_0                                     ,1000Base-KX Mode status for CPU" "0,1,2,3,4,5,6,7"
group.long 0xB98++0x3
line.long 0x00 "COMLANE_R198,The comlane_198 register"
bitfld.long 0x00 23. " COM_PCIE_OVR6                                  ,COMLANE PCIe override 6 register" "0,1"
bitfld.long 0x00 22. "       COM_PCIE_OVR5                                  ,COMLANE PCIe override 5 register" "0,1"
textline "                           "
bitfld.long 0x00 21. " COM_PCIE_OVR4                                  ,COMLANE PCIe override 4 register" "0,1"
bitfld.long 0x00 20. "       COM_PCIE_OVR3                                  ,COMLANE PCIe override 3 register" "0,1"
textline "                           "
bitfld.long 0x00 19. " COM_PCIE_OVR2                                  ,COMLANE PCIe override 2 register" "0,1"
bitfld.long 0x00 18. "       COM_PCIE_OVR1                                  ,COMLANE PCIe override 1 register" "0,1"
textline "                           "
bitfld.long 0x00 17. " COM_PCIE_CTRL2                                 ,COMLANE PCIe control 2 register" "0,1"
bitfld.long 0x00 16. "       COM_PCIE_CTRL1                                 ,COMLANE PCIe control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 4.--7. " LN1_RX_LOCKED_I_7_4                            ,Lane 1 RX Locked Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "      LN0_RX_LOCKED_I_3_0                            ,Lane 0 RX Locked status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB9C++0x3
line.long 0x00 "COMLANE_R19C,The comlane_19c register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P0CP1_O                         ,txpreset_coeff P0 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P0CM1_O                         ,txpreset_coeff P0 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P0C_O                           ,txpreset_coeff P0 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA0++0x3
line.long 0x00 "COMLANE_R1A0,The comlane_1a0 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P2C_O                           ,txpreset_coeff P2 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P1CP1_O                         ,txpreset_coeff P1 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P1CM1_O                         ,txpreset_coeff P1 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P1C_O                           ,txpreset_coeff P1 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA4++0x3
line.long 0x00 "COMLANE_R1A4,The comlane_1a4 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P3CM1_O                         ,txpreset_coeff P3 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P3C_O                           ,txpreset_coeff P3 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P2CP1_O                         ,txpreset_coeff P2 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P2CM1_O                         ,txpreset_coeff P2 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBA8++0x3
line.long 0x00 "COMLANE_R1A8,The comlane_1a8 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P4CP1_O                         ,txpreset_coeff P4 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P4CM1_O                         ,txpreset_coeff P4 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P4C_O                           ,txpreset_coeff P4 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P3CP1_O                         ,txpreset_coeff P3 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBAC++0x3
line.long 0x00 "COMLANE_R1AC,The comlane_1ac register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P6C_O                           ,txpreset_coeff P6 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P5CP1_O                         ,txpreset_coeff P5 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P5CM1_O                         ,txpreset_coeff P5 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P5C_O                           ,txpreset_coeff P5 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB0++0x3
line.long 0x00 "COMLANE_R1B0,The comlane_1b0 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P7CM1_O                         ,txpreset_coeff P7 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P7C_O                           ,txpreset_coeff P7 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P6CP1_O                         ,txpreset_coeff P6 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P6CM1_O                         ,txpreset_coeff P6 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB4++0x3
line.long 0x00 "COMLANE_R1B4,The comlane_1b4 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P8CP1_O                         ,txpreset_coeff P8 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P8CM1_O                         ,txpreset_coeff P8 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P8C_O                           ,txpreset_coeff P8 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P7CP1_O                         ,txpreset_coeff P7 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBB8++0x3
line.long 0x00 "COMLANE_R1B8,The comlane_1b8 register"
bitfld.long 0x00 24.--29. " TXPRESET_COEFF_P10C_O                          ,txpreset_coeff P10 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "      TXPRESET_COEFF_P9CP1_O                         ,txpreset_coeff P9 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                           "
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P9CM1_O                         ,txpreset_coeff P9 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P9C_O                           ,txpreset_coeff P9 C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBBC++0x3
line.long 0x00 "COMLANE_R1BC,The comlane_1bc register"
bitfld.long 0x00 8.--13. " TXPRESET_COEFF_P10CP1_O                        ,txpreset_coeff P10 C+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "      TXPRESET_COEFF_P10CM1_O                        ,txpreset_coeff P10 C-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1400++0x3
line.long 0x00 "COMRXEQ_R000,The comrxeq_000 register"
bitfld.long 0x00 7. " CSR_RXEQ_CONT_CAL_EN_O                         ,This register enables continuous time rxeq adaptation in the background" "0,1"
bitfld.long 0x00 6. "       CSR_FORCE_CAL_O                                ,This register forces one round of rxeq run" "0,1"
textline "                           "
bitfld.long 0x00 5. " CSR_EI_EXIT_CAL_O                              ,This register controls whether to perform any adaptation during electrical idle exit or not." "0,1"
bitfld.long 0x00 4. "       CSR_RATE_CHANGE_CAL_O                          ,This register controls whether to perform any adaptation during rate change or not." "0,1"
textline "                           "
bitfld.long 0x00 3. " CSR_RXEQ_RATE3_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE3." "0,1"
bitfld.long 0x00 2. "       CSR_RXEQ_RATE2_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE2." "0,1"
textline "                           "
bitfld.long 0x00 1. " CSR_RXEQ_RATE1_ADAPT_EN_O                      ,This is the master enable for all adaptations in RATE1" "0,1"
bitfld.long 0x00 0. "       CSR_RXEQ_EN_O                                  ,Master enable for rxeq top." "0,1"
group.long 0x1404++0x3
line.long 0x00 "COMRXEQ_R004,The comrxeq_004 register"
hexmask.long.byte 0x00 24.--31. 1. " COMRXEQ_MS_INIT_CTRL_7_0                       ,COMRXEQ mid speed initial calibration control [0] Adapt RXEQ stage 0 during initial mid speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 16.--23. 1. "      COMRXEQ_LS_INIT_CTRL_7_0                       ,COMRXEQ low speed initial calibration control [0] Adapt RXEQ stage 0 during initial low speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
group.long 0x1408++0x3
line.long 0x00 "COMRXEQ_R008,The comrxeq_008 register"
hexmask.long.byte 0x00 24.--31. 1. " CSR_RXEQ_CONT_RUN_RATE3_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE3, 1: calibration 0: load only"
hexmask.long.byte 0x00 16.--23. 1. "      CSR_RXEQ_CONT_RUN_RATE2_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE2, 1: calibration 0: load only"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CSR_RXEQ_CONT_RUN_RATE1_O                      ,This register mentions which blocks to be adapted during continuous calibration in RATE1, 1: calibration 0: load only."
hexmask.long.byte 0x00 0.--7. 1. "      COMRXEQ_HS_INIT_CAL_7_0                        ,COMRXEQ high speed initial calibration control [0] Adapt RXEQ stage 0 during initial high speed cal [1] Adapt RXEQ stage 1 [2] Adapt RXEQ stage 2 [3] Adapt RXEQ stage 3 [4] Adapt RXEQ stage 4 [5] Adapt RXEQ stage 5 [6] Adapt RXEQ stage 6 [7] Adapt RXEQ stage 7 ..."
group.long 0x140C++0x3
line.long 0x00 "COMRXEQ_R00C,The comrxeq_00c register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_HS_RECAL_CTRL_7_0                      ,COMRXEQ high speed recalibration control [0] Re-adapt RXEQ stage 0 during high speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 8.--15. 1. "      COMRXEQ_MS_RECAL_CTRL_7_0                      ,COMRXEQ mid speed recalibration control [0] Re-adapt RXEQ stage 0 during mid speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " COMRXEQ_LS_RECAL_CTRL_7_0                      ,COMRXEQ low speed recalibration control [0] Re-adapt RXEQ stage 0 during low speed recalibration [1] Re-adapt RXEQ stage 1 [2] Re-adapt RXEQ stage 2 [3] Re-adapt RXEQ stage 3 [4] Re-adapt RXEQ stage 4 [5] Re-adapt RXEQ stage 5 [6] Re-adapt RXEQ stage 6 [7] Re-adapt RXEQ stage 7 ..."
group.long 0x141C++0x3
line.long 0x00 "COMRXEQ_R01C,The comrxeq_01c register"
bitfld.long 0x00 12.--15. " COMRXEQ_CTRL4_3_0                              ,COMRXEQ control 4 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "      COMRXEQ_CTRL3_3_0                              ,COMRXEQ control 3 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_CTRL2                                  ,COMRXEQ control 2 register" "0,1"
bitfld.long 0x00 3. "       COMRXEQ_HS_CONT_CAL_CTRL1                      ,COMRXEQ high speed continuous calibration control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 2. " COMRXEQ_MS_CONT_CAL_CTRL1                      ,COMRXEQ mid speed continuous calibration control 1 register" "0,1"
bitfld.long 0x00 1. "       COMRXEQ_LS_CONT_CAL_CTRL1                      ,COMRXEQ low speed continuous calibration control 1 register" "0,1"
textline "                           "
bitfld.long 0x00 0. " COMRXEQ_CTRL1                                  ,COMRXEQ control 1 register" "0,1"
group.long 0x1428++0x3
line.long 0x00 "COMRXEQ_R028,The comrxeq_028 register"
bitfld.long 0x00 30. " COMRXEQ_CTRL9                                  ,COMRXEQ control 9 register" "0,1"
bitfld.long 0x00 29. "       COMRXEQ_CTRL8                                  ,COMRXEQ control 8 register" "0,1"
textline "                           "
bitfld.long 0x00 28. " COMRXEQ_CTRL7                                  ,COMRXEQ control 7 register" "0,1"
bitfld.long 0x00 26.--27. "       COMRXEQ_CTRL6_1_0                              ,COMRXEQ control 6 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 24.--25. " COMRXEQ_CTRL5_1_0                              ,COMRXEQ control 5 register [1:0]" "0,1,2,3"
group.long 0x1434++0x3
line.long 0x00 "COMRXEQ_R034,The comrxeq_034 register"
bitfld.long 0x00 24. " COMRXEQ_CTRL12                                 ,COMRXEQ control 12 register" "0,1"
bitfld.long 0x00 19.--20. "       COMRXEQ_CTRL11_2_0                             ,COMRXEQ control 11 register [1:0]" "0,1,2,3"
textline "                           "
bitfld.long 0x00 16.--18. " COMRXEQ_CTRL10_2_0                             ,COMRXEQ control 10 register [2:0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11.--12. "       CSR_GEN2_GAIN_START_VAL_O                      ,Start value for GAIN Gen2 rate" "0,1,2,3"
textline "                           "
bitfld.long 0x00 8.--10. " CSR_GEN2_ATT_START_VAL_O                       ,Start value for ATT adaptation Gen2 rate" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "       CSR_GEN1_GAIN_START_VAL_O                      ,Start value for GAIN Gen1 rate" "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--2. " CSR_GEN1_ATT_START_VAL_O                       ,Start value for ATT adaptation for Gen1 rate" "0,1,2,3,4,5,6,7"
group.long 0x143C++0x3
line.long 0x00 "COMRXEQ_R03C,The comrxeq_03c register"
hexmask.long.byte 0x00 8.--14. 1. " COMRXEQ_PATT_CTRL1_6_0                         ,COMRXEQ pattern control 1 register [6:0]"
group.long 0x1444++0x3
line.long 0x00 "COMRXEQ_R044,The comrxeq_044 register"
bitfld.long 0x00 7. " COMRXEQ_CTRL13                                 ,COMRXEQ control 13 register" "0,1"
bitfld.long 0x00 6. "       COMRXEQ_PATT_CTRL4                             ,COMRXEQ pattern control 4 register" "0,1"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_PATT_CTRL3                             ,COMRXEQ pattern control 3 register" "0,1"
bitfld.long 0x00 4. "       COMRXEQ_PATT_CTRL2                             ,COMRXEQ pattern control 2 register" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " COMRXEQ_START_CTRL1_3_0                        ,COMRXEQ start value control 1 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1448++0x3
line.long 0x00 "COMRXEQ_R048,The comrxeq_048 register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_PATT_CTRL5_7_0                         ,COMRXEQ pattern control 5 register [7:0]"
bitfld.long 0x00 0.--3. "      CSR_BSTADAPT_GEN2_BOOST_START_O                ,Edge Based Boost Start value for Gen2 rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x144C++0x3
line.long 0x00 "COMRXEQ_R04C,The comrxeq_04c register"
bitfld.long 0x00 7. " COMRXEQ_CTRL16                                 ,COMRXEQ control 16 register" "0,1"
bitfld.long 0x00 6. "       COMRXEQ_CTRL15                                 ,COMRXEQ control 15 register" "0,1"
textline "                           "
bitfld.long 0x00 5. " COMRXEQ_PATT_CTRL5_8                           ,COMRXEQ pattern control 5 register [8]" "0,1"
bitfld.long 0x00 4. "       COMRXEQ_PATT_CTRL6                             ,COMRXEQ pattern control 6 register" "0,1"
textline "                           "
bitfld.long 0x00 0.--3. " COMRXEQ_CTRL14_3_0                             ,COMRXEQ control 14 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1458++0x3
line.long 0x00 "COMRXEQ_R058,The comrxeq_058 register"
hexmask.long.byte 0x00 0.--6. 1. " COMRXEQ_PATT_CTRL7_6_0                         ,COMRXEQ pattern control 7 register [6:0]"
group.long 0x1460++0x3
line.long 0x00 "COMRXEQ_R060,The comrxeq_060 register"
hexmask.long.byte 0x00 24.--30. 1. " COMRXEQ_PATT_CTRL8_6_0                         ,COMRXEQ pattern control 8 register [6:0]"
group.long 0x1464++0x3
line.long 0x00 "COMRXEQ_R064,The comrxeq_064 register"
hexmask.long.byte 0x00 24.--30. 1. " COMRXEQ_PATT_CTRL11_6_0                        ,COMRXEQ pattern control 11 register [6:0]"
hexmask.long.byte 0x00 16.--22. 1. "      COMRXEQ_PATT_CTRL10_6_0                        ,COMRXEQ pattern control 10 register [6:0]"
textline "                           "
hexmask.long.byte 0x00 0.--6. 1. " COMRXEQ_PATT_CTRL9_6_0                         ,COMRXEQ pattern control 9 register [6:0]"
group.long 0x1470++0x3
line.long 0x00 "COMRXEQ_R070,The comrxeq_070 register"
hexmask.long.byte 0x00 16.--22. 1. " COMRXEQ_PATT_CTRL12_6_0                        ,COMRXEQ pattern control 12 register [6:0]"
group.long 0x1474++0x3
line.long 0x00 "COMRXEQ_R074,The comrxeq_074 register"
hexmask.long.byte 0x00 8.--14. 1. " COMRXEQ_PATT_CTRL13_6_0                        ,COMRXEQ pattern control 13 register [6:0]"
group.long 0x1484++0x3
line.long 0x00 "COMRXEQ_R084,The comrxeq_084 register"
bitfld.long 0x00 20.--23. " COMRXEQ_CTRL18_3_0                             ,COMRXEQ control 18 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "      COMRXEQ_CTRL17_3_0                             ,COMRXEQ control 17 register [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1490++0x3
line.long 0x00 "COMRXEQ_R090,The comrxeq_090 register"
bitfld.long 0x00 13. " COMRXEQ_CTRL24                                 ,COMRXEQ control 24 register" "0,1"
bitfld.long 0x00 12. "       COMRXEQ_CTRL23                                 ,COMRXEQ control 23 register" "0,1"
textline "                           "
bitfld.long 0x00 11. " COMRXEQ_CTRL22                                 ,COMRXEQ control 22 register" "0,1"
bitfld.long 0x00 10. "       COMRXEQ_CTRL21                                 ,COMRXEQ control 21 register" "0,1"
textline "                           "
bitfld.long 0x00 9. " COMRXEQ_CTRL20                                 ,COMRXEQ control 20 register" "0,1"
bitfld.long 0x00 8. "       COMRXEQ_CTRL19                                 ,COMRXEQ control 19 register" "0,1"
group.long 0x1494++0x3
line.long 0x00 "COMRXEQ_R094,The comrxeq_094 register"
hexmask.long.byte 0x00 24.--31. 1. " COMRXEQ_CTRL25_7_0                             ,COMRXEQ control 25 register [7:0]"
hexmask.long.byte 0x00 16.--23. 1. "      CSR_DFE_GEN2_TAP_START_VAL_O                   ,Start value for DFE tap adaptation for Gen2 rate"
textline "                           "
hexmask.long.byte 0x00 8.--15. 1. " CSR_DFE_GEN1_TAP_START_VAL_O                   ,Start value for DFE tap adaptation for Gen1 rate"
group.long 0x1498++0x3
line.long 0x00 "COMRXEQ_R098,The comrxeq_098 register"
hexmask.long.byte 0x00 16.--23. 1. " COMRXEQ_HS_RCHANGE_CTRL_7_0                    ,COMRXEQ high speed rate change calibration control [0] Adapt RXEQ stage 0 during high speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7 ..."
hexmask.long.byte 0x00 8.--15. 1. "      CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O           ,COMRXEQ mid speed rate change calibration control [0] Adapt RXEQ stage 0 during mid speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7..."
textline "                           "
hexmask.long.byte 0x00 0.--7. 1. " CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE1_O           ,COMRXEQ low speed rate change calibration control [0] Adapt RXEQ stage 0 during low speed rate change [1] Adapt RXEQ stage 1 ... [2] Adapt RXEQ stage 2 ... [3] Adapt RXEQ stage 3 ... [4] Adapt RXEQ stage 4 ... [5] Adapt RXEQ stage 5 ... [6] Adapt RXEQ stage 6 ... [7] Adapt RXEQ stage 7..."
rgroup.long 0x1FC0++0x3
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the SERDES module."
hexmask.long.word 0x00 16.--31. 1. " MODULE_ID                                      ,SERDES module ID."
bitfld.long 0x00 11.--15. "    RTL_VERSION                                    ,RTL Version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                           "
bitfld.long 0x00 8.--10. " MAJOR_REVISION                                 ,Major Revision." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "       CUSTOM_REVISION                                ,Custom Revision." "0,1,2,3"
textline "                           "
bitfld.long 0x00 0.--5. " MINOR_REVISION                                 ,Minor Revision." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1FD0++0x3
line.long 0x00 "SERDES_CTRL,Sets the SERDES control state."
bitfld.long 0x00 29. " POR_EN                                         ,The POR_EN allows the system to place the SERDES in a reset state. Accesses to the SERDES registers are ignored." "0,1"
rgroup.long 0x1FD4++0x3
line.long 0x00 "LANE_PLL_STS,The Lane and PLL Status register is used to indicate the current configuration of the REFCLK distribution and Lane Mux selection."
bitfld.long 0x00 31. " PLL0_PWR_ON                                    ,Indicates the state of the PLL0 REFCLK supplies. 0 - REFCLK power is off 1 - REFCLK power is on" "0,1"
bitfld.long 0x00 27. "       PLL0_SEL_EXT                                   ,Indicates the chaining for the right side will be opposite of the PLL0_CHAIN_EN field used for the left chaining. 0 - Chaining for left and right will match PLL0_CHAIN_EN field. 1 - Chain left is PLL0_CHAIN_EN field and chain right is !PLL0_CHAIN_EN field." "0,1"
textline "                           "
bitfld.long 0x00 26. " PLL0_LEFT_SEL                                  ,Indicates the REFCLK source used for PLL0. This bit indicates that the left REFCLK input is used for the PLL0. When both PLL0_LEFT_SEL and PLL0_RIGHT_SEL are zero, the REFCLK pads are used for the PLL0." "0,1"
bitfld.long 0x00 25. "       PLL0_CHAIN_EN                                  ,Indicates the REFCLK chaining is enabled. 0 - REFCLK right and left are driven from the REFCLK pads of this Serdes 1 - REFCLK right or left is driven from left or right respectively." "0,1"
textline "                           "
bitfld.long 0x00 24. " PLL0_RIGHT_SEL                                 ,Indicates the REFCLK source used for PLL0. This bit indicates that the right REFCLK input is used for the PLL0. When both PLL0_LEFT_SEL and PLL0_RIGHT_SEL are zero, the REFCLK pads are used for the PLL0." "0,1"
bitfld.long 0x00 3. "       LANE0_PLL_LOCK                                 ,Indicates that the lane 0 tx clock is valid." "0,1"
textline "                           "
bitfld.long 0x00 2. " LANE0_RST_ISO                                  ,Indicates that the selected IF has the Lane 0 reset isolation signal set." "0,1"
bitfld.long 0x00 0.--1. "       LANE0_IP_SEL                                   ,Indicates which interface is used for lane 0. See , Interface Selection" "0,1,2,3"
rgroup.long 0x1FD8++0x3
line.long 0x00 "SERDES_FEATURE,The SERDES Feature register contains the features of the SERDES."
bitfld.long 0x00 0.--2. " LANES                                          ,Indicates the number of lanes in this serdes" "0,1,2,3,4,5,6,7"
group.long 0x1FE0++0x3
line.long 0x00 "LANEXCTL_STS,The lane x control and status provides the ability to override SERDES configuration settings. It is mainly provided for test, but sometimes used for mission setup as well."
bitfld.long 0x00 31. " TX0_ENABLE_OVL                                 ,The Tx Enable Overlay bit, when set allows the Tx Enable Value to override the CFGTX.Enable input." "0,1"
bitfld.long 0x00 29.--30. "       TX0_ENABLE_VAL                                 ,The Tx Enable Value when used allows the Tx lane to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 28. " TX0_RATE_OVL                                   ,The Tx Rate Overlay bit, when set allows the Tx Rate Value to override the CFGTX.Rate input." "0,1"
bitfld.long 0x00 26.--27. "       TX0_RATE_VAL                                   ,The Tx Rate Value when used allows the Tx lane to be placed into 0 - Full Rate mode. 1 - Half Rate mode. 2 - Quarter Rate mode." "0,1,2,3"
textline "                           "
bitfld.long 0x00 25. " TX0_IDLE_OVL                                   ,The Tx Idle Overlay bit, when set allows the Tx Idle Value to override the CFGTX.Idle input." "0,1"
bitfld.long 0x00 24. "       TX0_IDLE_VAL                                   ,The Tx Idle Value, when used allows the Tx lane to be placed electrical Idle state in non Pipe Interface mode." "0,1"
textline "                           "
bitfld.long 0x00 23. " TX0_WIDTH_OVL                                  ,The Tx Width Overlay bit, when set allows the Tx Width Value to override the CFGTX.Width input." "0,1"
bitfld.long 0x00 21.--22. "       TX0_WIDTH_VAL                                  ,The Tx Width Value, when used allows the Tx lane to be placed into 0 - 10 bit mode 1 - 16 bit mode 2 - 20 bit mode 3 - 40 bit mode This field is ignored in Pipe Interface Mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 15. " RX0_ENABLE_OVL                                 ,The Rx Enable Overlay bi,t when set allows the Rx Enable Value to override the CFGRX.Enable input." "0,1"
bitfld.long 0x00 13.--14. "       RX0_ENABLE_VAL                                 ,The Rx Enable Valu,e when used allows the Rx lane to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 12. " RX0_RATE_OVL                                   ,The Rx Rate Overlay bit, when set allows the Rx Rate Value to override the CFGRX.Rate input." "0,1"
bitfld.long 0x00 10.--11. "       RX0_RATE_VAL                                   ,The Rx Rate Value when used allows the Rx lane to be placed into 0 - Full Rate mode. 1 - Half Rate mode. 2 - Quarter Rate mode." "0,1,2,3"
textline "                           "
bitfld.long 0x00 9. " RX0_POLARITY_OVL                               ,The Rx Polarity Overlay bit, when set allows the Rx Polarity Value to override the CFGRX.Polarity input." "0,1"
bitfld.long 0x00 8. "       RX0_POLARITY_VAL                               ,The Rx Polarity Value, when used allows the lane Rx Polarity to be inverted." "0,1"
textline "                           "
bitfld.long 0x00 7. " RX0_ALIGN_OVL                                  ,The Rx Align Overlay bit, when set allows the Rx Align Value to override the CFGRX.Align input." "0,1"
bitfld.long 0x00 6. "       RX0_ALIGN_VAL                                  ,The Rx Align Value, when used allows the Rx lane to align to K28.1, K28.5 and K28.7 characters otherwise known as Comma Characters." "0,1"
textline "                           "
bitfld.long 0x00 5. " RX0_WIDTH_OVL                                  ,The Rx Width Overlay bit, when set allows the Rx Width Value to override the CFGRX.Width input." "0,1"
bitfld.long 0x00 3.--4. "       RX0_WIDTH_VAL                                  ,The Rx Width Value when used allows the Rx lane to be placed into 0 - 10-bit mode 1 - 16-bit mode 2 - 20-bit mode 3 - 40-bit mode This field is ignored in Pipe Interface Mode" "0,1,2,3"
textline "                           "
bitfld.long 0x00 1. " RX0_OK                                         ,The Rx OK indicate that the lane is in a functional state." "0,1"
bitfld.long 0x00 0. "       RX0_LOSS                                       ,The Rx Signal Loss Indicates that the data has not been detected or the CDR is not locked." "0,1"
group.long 0x1FF4++0x3
line.long 0x00 "PLL_CTRL,The PLL Control register provides the ability to override the PLL state and control events for debug purposes."
bitfld.long 0x00 31. " PLL_ENABLE_OVL                                 ,The PLL Enable Overlay bit, when set allows the PLL Enable Value to override the CFGPLL.Enable input." "0,1"
bitfld.long 0x00 29.--30. "       PLL_ENABLE_VAL                                 ,The PLL Enable Value when used allows the PLL to be placed in a 0 - Disable state. 1 - Sleep state. 2 - Snooze state. 3 - Enabled state." "0,1,2,3"
textline "                           "
bitfld.long 0x00 28. " PLL_OK                                         ,The PLL Ok indicate that the transmit clocks are valid and the PLL circuits are ready for use." "0,1"
bitfld.long 0x00 17. "       LN_WAFTER_OK                                   ,The LN_WAFTER_OK field will cause the lane OK indication to be Blocked until the LN0_CONT_OK is set. This allows code to run after the lane OK but before the hardware can use the lane." "0,1"
textline "                           "
bitfld.long 0x00 16. " LN_WAFTER_SD                                   ,The LN_WAFTER_SD field will cause the Rx signal indication to be Blocked until the LN0_CONT_SD is set. This allows code to run after signal detect but before the hardware can use the data." "0,1"
bitfld.long 0x00 12. "       LN0_CONT_OK                                    ,The LN0_CONT_OK allows the Blocked lane OK for lane 0 to now pass to the controlling PCS IP. This bit is auto cleared when LN0_OK_STATE is driven inactive." "0,1"
textline "                           "
bitfld.long 0x00 8. " LN0_OK_STATE                                   ,The LN0_OK_STATE indicate the current state of the lane OK signal for lane 0." "0,1"
bitfld.long 0x00 4. "       LN0_CONT_SD                                    ,The LN0_CONT_SD allows the Blocked signal detect for lane 0 to now pass to the controlling PCS IP. This bit is auto cleared when LN0_SD_STATE is driven inactive." "0,1"
textline "                           "
bitfld.long 0x00 0. " LN0_SD_STATE                                   ,The LN0_SD_STATE indicate the current state of the signal detect signal for lane 0." "0,1"
rgroup.long 0x1FF8++0x3
line.long 0x00 "COMMA_LINK_DELAY,The Comma Link Delay register defines the added delay due to comma alignment for the SERDES lanes. This value should be added to the receive time stamp to accurately time stamp the packet arrival. For a 1G link the value is 800pS per bit. This value may change any time the link is established."
hexmask.long.byte 0x00 0.--7. 1. " LANE0_CDELAY                                   ,Defines the number of network bits the comma aligner has added to the fixed delay of the PCS/PMA layer for lane 0."
group.long 0x1FFC++0x3
line.long 0x00 "CMU_WAIT,The CMU Wait is used to create a 150 micro second delay between the completion of the SERDES configuration writes and activating the SERDES CMU logic allowing for supplies to settle."
hexmask.long.byte 0x00 24.--31. 1. " IDDQ_CNT                                       ,Defines the number of clock cycles times 256 between pll_enable and cmu_master_cdn being set and the cmu_iddq going low."
bitfld.long 0x00 20.--23. "      PHAN_VAL                                       ,Defines the number of ~i(WAIT_VAL+1)*~i(PHAN_VAL+1) clock cycles between CMU Reset and when the phantom CMU_OK is generated. This allows the Serdes to start using valid clocks. The Phantom CMU_OK is used in Pipe mode. If this field is 0, the Phantom CMU_OK is equal to the actual CMU_OK." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                           "
hexmask.long.tbyte 0x00 0.--16. 1. " WAIT_VAL                                       ,Defines the number of clock cycles between writing to the CMU Reset register and cmu_reset_i activation. The value should be 150 ?s or more."
width 0x0B
tree.end
tree.end
tree "Timers"
tree "TIMER0"
base ad:0x2400000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER1"
base ad:0x2410000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER2"
base ad:0x2420000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER3"
base ad:0x2430000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER4"
base ad:0x2440000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER5"
base ad:0x2450000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER6"
base ad:0x2460000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER7"
base ad:0x2470000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER8"
base ad:0x2480000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER9"
base ad:0x2490000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER10"
base ad:0x24A0000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "TIMER11"
base ad:0x24B0000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "MCU_TIMER0"
base ad:0x40400000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "MCU_TIMER1"
base ad:0x40410000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "MCU_TIMER2"
base ad:0x40420000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree "MCU_TIMER3"
base ad:0x40430000
width 21.
rgroup.long 0x0++0x3
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility."
hexmask.long 0x00 0.--31. 1. " REVISION           ,IP Revision"
group.long 0x10++0x3
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the L4 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information, see , Timers Not Supported Features."
bitfld.long 0x00 2.--3. " IDLEMODE           ,Power management, req/ack control 0h (R/W) = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h (R/W) = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h (R/W) = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events. 3h (R/W) = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented." "0,1,2,3"
bitfld.long 0x00 1. "         EMUFREE     ,Emulation mode 0h (R/W) = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h (R/W) = The timer runs free, regardless of PINSUSPENDN value." "0,1"
textline "                              "
bitfld.long 0x00 0. " SOFTRESET          ,Software reset 0h (R/W) = Read 0: reset done, no pending action Write 0: No action 1h (R/W) = Read 1: initiate software reset Write 1: Reset ongoing" "0,1"
group.long 0x20++0x3
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)."
bitfld.long 0x00 0. " LINE_NUMBER        ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1"
group.long 0x24++0x3
line.long 0x00 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x28++0x3
line.long 0x00 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)."
bitfld.long 0x00 2. " TCAR_IT_FLAG       ,IRQ status for capture" "0,1"
bitfld.long 0x00 1. "         OVF_IT_FLAG ,IRQ status for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_IT_FLAG        ,IRQ status for match" "0,1"
group.long 0x2C++0x3
line.long 0x00 "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x30++0x3
line.long 0x00 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register."
bitfld.long 0x00 2. " TCAR_EN_FLAG       ,IRQ enable for compare" "0,1"
bitfld.long 0x00 1. "         OVF_EN_FLAG ,IRQ enable for overflow" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_EN_FLAG        ,IRQ enable for match" "0,1"
group.long 0x34++0x3
line.long 0x00 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up."
bitfld.long 0x00 2. " TCAR_WUP_ENA       ,Wake-up generation for compare 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
bitfld.long 0x00 1. "         OVF_WUP_ENA ,Wake-up generation for overflow 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
textline "                              "
bitfld.long 0x00 0. " MAT_WUP_ENA        ,Wake-up generation for match 0h (R/W) = Wake-up disabled 1h (R/W) = Wake-up enabled" "0,1"
group.long 0x38++0x3
line.long 0x00 "TIMER_TCLR,This register controls optional features specific to the timer functionality."
bitfld.long 0x00 14. " GPO_CFG            ,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h (R/W) = TIMER IO pin functions as PWM output. 1h (R/W) = TIMER IO pin functions as TRIGGER input." "0,1"
bitfld.long 0x00 13. "         CAPT_MODE   ,Capture mode select bit (first/second) 0h (R/W) = Single capture: Capture the first enabled capture event in 1h (R/W) = Capture on second event: Capture the second enabled capture event in" "0,1"
textline "                              "
bitfld.long 0x00 12. " PT                 ,Pulse or toggle mode on POTIMERPWM output pin 0h (R/W) = Pulse modulation 1h (R/W) = Toggle modulation" "0,1"
bitfld.long 0x00 10.--11. "         TRG         ,Trigger output mode on POTIMERPWM output pin 0h (R/W) = No trigger 1h (R/W) = Trigger on overflow. 2h (R/W) = Trigger on overflow and match. 3h (R/W) = Reserved" "0,1,2,3"
textline "                              "
bitfld.long 0x00 8.--9. " TCM                ,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h (R/W) = No capture 1h (R/W) = Capture on rising edges of EVENT_CAPTURE pin 2h (R/W) = Capture on falling edges of EVENT_CAPTURE pin 3h (R/W) = Capture on both edges of EVENT_CAPTURE pin" "0,1,2,3"
bitfld.long 0x00 7. "         SCPWM       ,Pulse width modulation output pin default setting 0h (R/W) = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h (R/W) = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1"
textline "                              "
bitfld.long 0x00 6. " CE                 ,Compare enable 0h (R/W) = Compare mode is disable. 1h (R/W) = Compare mode is enable." "0,1"
bitfld.long 0x00 5. "         PRE         ,Prescaler enable 0h (R/W) = The TIMER clock input pin clocks the counter. 1h (R/W) = The divided input pin clocks the counter." "0,1"
textline "                              "
bitfld.long 0x00 2.--4. " PTV                ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "         AR          ,Autoreload mode 0h (R/W) = One shot timer 1h (R/W) = Autoreload timer" "0,1"
textline "                              "
bitfld.long 0x00 0. " ST                 ,Start/stop timer control 0h (R/W) = Stop timer: Only the counter is frozen. If one-shot mode selected (AR =0), this bit is automatically reset by internal logic when the counter is overflowed. 1h (R/W) = Start timer" "0,1"
group.long 0x3C++0x3
line.long 0x00 "TIMER_TCRR,This register holds the value of the internal counter."
hexmask.long 0x00 0.--31. 1. " TIMER_COUNTER      ,Value of TIMER counter"
group.long 0x40++0x3
line.long 0x00 "TIMER_TLDR,This register holds the timer load value."
hexmask.long 0x00 0.--31. 1. " LOAD_VALUE         ,Timer counter value loaded on overflow in autoreload mode or on"
group.long 0x44++0x3
line.long 0x00 "TIMER_TTGR,The read value of this register is always FFFF FFFFh."
hexmask.long 0x00 0.--31. 1. " TTGR_VALUE         ,Writing to the"
rgroup.long 0x48++0x3
line.long 0x00 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers."
bitfld.long 0x00 9. " W_PEND_TOWR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 8. "         W_PEND_TOCR ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 7. " W_PEND_TCVR        ,Write pending for the 0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 6. "         W_PEND_TNIR ,Write pending for the 0h (R) = No negative increment register write pending 1h (R) = Negative increment register write pending" "0,1"
textline "                              "
bitfld.long 0x00 5. " W_PEND_TPIR        ,Write pending for the 0h (R) = No positive increment register write pending 1h (R) = Positive increment register write pending" "0,1"
bitfld.long 0x00 4. "         W_PEND_TMAR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 3. " W_PEND_TTGR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 2. "         W_PEND_TLDR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
textline "                              "
bitfld.long 0x00 1. " W_PEND_TCRR        ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
bitfld.long 0x00 0. "         W_PEND_TCLR ,Write pending for the0h (R) = No write pending 1h (R) = Write pending" "0,1"
group.long 0x4C++0x3
line.long 0x00 "TIMER_TMAR,The register holds the match value to be compared with the counter's value."
hexmask.long 0x00 0.--31. 1. " COMPARE_VALUE      ,Value to be compared to the timer counter"
rgroup.long 0x50++0x3
line.long 0x00 "TIMER_TCAR1,This register holds the first captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE1     ,First timer counter value captured on an external event trigger"
group.long 0x54++0x3
line.long 0x00 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x00 3. " READ_MODE          ,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted." "0,1"
bitfld.long 0x00 2. "         POSTED      ,Posted mode selection 0h (R/W) = Posted mode inactive: Delay the command accept output signal. 1h (R/W) = Posted mode active" "0,1"
textline "                              "
bitfld.long 0x00 1. " SFT                ,This bit resets all the functional part of the module. All read accesses return 0. 0h (R/W) = Software reset is disabled. 1h (R/W) = Software reset is enabled." "0,1"
rgroup.long 0x58++0x3
line.long 0x00 "TIMER_TCAR2,This register holds the second captured value of the counter register."
hexmask.long 0x00 0.--31. 1. " CAPTURE_VALUE2     ,Second timer counter value captured on an external event trigger"
group.long 0x5C++0x3
line.long 0x00 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment"
group.long 0x60++0x3
line.long 0x00 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment"
group.long 0x64++0x3
line.long 0x00 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value."
hexmask.long 0x00 0.--31. 1. " COUNTER_VALUE      ,Value of CVR counter"
group.long 0x68++0x3
line.long 0x00 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_COUNTER_VALUE  ,Number of overflow events"
group.long 0x6C++0x3
line.long 0x00 "TIMER_TOWR,This register holds the number of masked overflow interrupts."
hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts"
width 0x0B
tree.end
tree.end
tree "Time_Sync_Routers"
tree "TIMESYNC_INTRTR0"
base ad:0xA40000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "TIMESYNC_INTRTR0_PID,Description: Peripheral identification register. Uniquely identifies the module and its specific revision."
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "TIMESYNC_INTRTR0_MUXCNTL_y,Description: Event mux control register. Offset = 4h + (y * 4h); where y = 0h to 27h."
bitfld.long 0x00 0.--5. " ENABLE ,Mux control for event N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 0x0B
tree.end
tree "CMPEVT_INTRTR0"
base ad:0xA30000
width 26.
rgroup.long 0x0++0x3
line.long 0x00 "CMPEVT_INTRTR0_PID,Description: Peripheral identification register. Uniquely identifies the module and its specific revision."
hexmask.long 0x00 0.--31. 1. " REV    ,TI internal data. Identifies revision of peripheral."
group.long 0x4++0x3
line.long 0x00 "CMPEVT_INTRTR0_MUXCNTL_y,Description: Event mux control register. Offset = 4h + (y * 4h); where y = 0h to 1Fh."
hexmask.long.byte 0x00 0.--6. 1. " ENABLE ,Mux control for event N"
width 0x0B
tree.end
tree.end
tree "UART"
tree "UART0"
base ad:0x2800000
width 23.
group.long 0x0++0x3
line.long 0x00 "UART_DLL,This register, with , stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor."
hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB               ,Stores the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the . If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the is not overwritten."
hexmask.long.byte 0x00 0.--7. 1. " RHR                     ,Receive holding register"
wgroup.long 0x0++0x3
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data."
hexmask.long.byte 0x00 0.--7. 1. " THR                     ,Transmit holding register"
group.long 0x4++0x3
line.long 0x00 "UART_DLH,This register, with , stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor."
bitfld.long 0x00 0.--5. " CLOCK_MSB               ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0."
bitfld.long 0x00 6.--7. " NOT_USED                ," "0,1,2,3"
bitfld.long 0x00 5. "                                             TX_STATUS_IT                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             RX_STOP_IT                             ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_TRIG_IT                       ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             LAST_RX_BYTE_IT                        ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, interrupt, interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit."
bitfld.long 0x00 7. " CTS_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             RTS_IT                                 ," "0,1"
textline "                                "
bitfld.long 0x00 5. " XOFF_IT                 ," "0,1"
bitfld.long 0x00 4. "                                             SLEEP_MODE                             ," "0,1"
textline "                                "
bitfld.long 0x00 3. " MODEM_STS_IT            ," "0,1"
bitfld.long 0x00 2. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x8++0x3
line.long 0x00 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but [4] enables write accesses to [5:4], the TX trigger level, which is also used in IrDA modes."
bitfld.long 0x00 7. " AUTO_CTS_EN             ,Auto-CTS enable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      AUTO_RTS_EN                            ,Auto-RTS enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT     ," "Disabled,Enabled"
bitfld.long 0x00 4. "                                      ENHANCED_EN                            ,Enhanced functions write enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL         ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2"
wgroup.long 0x8++0x3
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting restriction when [7] = 1."
bitfld.long 0x00 6.--7. " RX_FIFO_TRIG            ,Sets the trigger level for the RX FIFO: If" "8,16,56,60"
bitfld.long 0x00 4.--5. "                                            TX_FIFO_TRIG                           ,Sets the trigger level for the TX FIFO: If" "8,16,32,56"
textline "                                "
bitfld.long 0x00 3. " DMA_MODE                ,This register is considered if" "Disabled,Enabled"
bitfld.long 0x00 2. "                                      TX_FIFO_CLEAR                          ," "No_effect,Clear"
textline "                                "
bitfld.long 0x00 1. " RX_FIFO_CLEAR           ," "No_effect,Clear"
bitfld.long 0x00 0. "                                     FIFO_EN                                ," "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active."
bitfld.long 0x00 5. " TX_STATUS_IT            ,Read 0h = TX status interrupt inactive" "0,1"
bitfld.long 0x00 3. "                                             RX_OE_IT                               ,Read 0h = RX overrun interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 2. " RX_STOP_IT              ,Read 0h = Receive stop interrupt inactive" "0,1"
bitfld.long 0x00 1. "                                             THR_IT                                 ,Read 0h = THR interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 0. " RHR_IT                  ,Read 0h = RHR interrupt inactive" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OE_IT                ," "0,1"
bitfld.long 0x00 2. "                                             RX_FIFO_LAST_BYTE_IT                   ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner."
bitfld.long 0x00 6.--7. " FCR_MIRROR              ,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "                                             IT_TYPE                                ,Read 0h = Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 0. " IT_PENDING              ,Read 0h = An interrupt is pending." "0,1"
group.long 0xC++0x3
line.long 0x00 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1, the TX line is forced to 0 and remains in this state as long as [6] = 1."
bitfld.long 0x00 7. " DIV_EN                  ," "Disabled,Enabled"
bitfld.long 0x00 6. "                                      BREAK_EN                               ,Break control bit" "Normal,Forced_low"
textline "                                "
bitfld.long 0x00 5. " PARITY_TYPE2            ,Selects the forced parity format (if" "No_parity,Odd_parity"
bitfld.long 0x00 4. "                                    PARITY_TYPE1                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " PARITY_EN               ,0h = No parity" "0,1"
bitfld.long 0x00 2. "                                             NB_STOP                                ,Specifies the number of stop-bits" "1,1.5"
textline "                                "
bitfld.long 0x00 0.--1. " CHAR_LENGTH             ,Specifies the word length to be transmitted or received" "5,6,7,8"
group.long 0x10++0x3
line.long 0x00 "UART_MCR,Modem control register [3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem."
bitfld.long 0x00 6. " TCR_TLR                 ,0h = No action" "Disabled,Enabled"
bitfld.long 0x00 5. "                                      XON_EN                                 ,0h = Disable XON any function." "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 4. " LOOPBACK_EN             ,0h = Normal operating mode" "Disabled,Enabled"
bitfld.long 0x00 3. "                                      CD_STS_CH                              ,0h = In loopback, forces DCD* input high and IRQ outputs to inactive state" "High,Low"
textline "                                "
bitfld.long 0x00 2. " RI_STS_CH               ,0h = In loopback, forces RI* input high" "High,Low"
bitfld.long 0x00 1. "                                          RTS                                    ,In loopback, controls the" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0. " DTR                     ,0h = Force DTR* output to inactive (high)." "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1               ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 5. "                                             RX_STOP                                ,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
textline "                                "
bitfld.long 0x00 0. " RX_FIFO_E               ,Read 0h = At least one data character in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)."
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 6. "                                             STS_FIFO_FULL                          ,Read 0h = Status FIFO not full" "0,1"
textline "                                "
bitfld.long 0x00 5. " RX_LAST_BYTE            ,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1"
bitfld.long 0x00 4. "                                             FRAME_TOO_LONG                         ,Read 0h = No frame-too-long error in frame" "0,1"
textline "                                "
bitfld.long 0x00 3. " ABORT                   ,Read 0h = No abort pattern error in frame" "0,1"
bitfld.long 0x00 2. "                                             CRC                                    ,Read 0h = No CRC error in frame" "0,1"
textline "                                "
bitfld.long 0x00 1. " STS_FIFO_E              ,Read 0h = Status FIFO not empty" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. " RX_FIFO_STS             ,Read 0h = Normal operation" "0,1"
bitfld.long 0x00 6. "                                             TX_SR_E                                ,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_FIFO_E               ,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 4. "                                             RX_BI                                  ,Read 0h = No break condition" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_FE                   ,Read 0h = No framing error in data RX FIFO" "0,1"
bitfld.long 0x00 2. "                                             RX_PE                                  ,Read 0h = No parity error in data from RX FIFO" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_OE                   ,Read 0h = No overrun error" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
group.long 0x14++0x3
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2               ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
rgroup.long 0x18++0x3
line.long 0x00 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state."
bitfld.long 0x00 7. " NCD_STS                 ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 6. "                                             NRI_STS                                ,This bit is the complement of the RI* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 5. " NDSR_STS                ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 4. "                                             NCTS_STS                               ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 3. " DCD_STS                 ,Indicates that DCD* input (or" "0,1"
bitfld.long 0x00 2. "                                             RI_STS                                 ,Indicates that RI* input (or" "0,1"
textline "                                "
bitfld.long 0x00 1. " DSR_STS                 ," "0,1"
bitfld.long 0x00 0. "                                             CTS_STS                                ," "0,1"
group.long 0x18++0x3
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that [3:0] > [7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level ([7:4] or [7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START      ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.long 0x00 0.--3. "                                            RX_FIFO_TRIG_HALT                      ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.long 0x18++0x3
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1              ,Stores the 8-bit XOFF1 character used in UART modes"
group.long 0x1C++0x3
line.long 0x00 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD                ,Scratchpad register"
group.long 0x1C++0x3
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA        ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                                            TX_FIFO_TRIG_DMA                       ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x3
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2              ,Stores the 8-bit XOFF2 character used in UART modes."
group.long 0x20++0x3
line.long 0x00 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (, , and ). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags."
bitfld.long 0x00 7. " FRAME_END_MODE          ,IrDA mode only" "Frame-length,EOT"
bitfld.long 0x00 6. "                                  SIP_MODE                               ,MIR/FIR modes only" "Manual_SIP,Automatic_SIP"
textline "                                "
bitfld.long 0x00 5. " SCT                     ,Store and control the transmission." "THR,ACREG[2]"
bitfld.long 0x00 4. "                                      SET_TXIR                               ,Used to configure the infrared transceiver" "TXIR_low,IRTX_high"
textline "                                "
bitfld.long 0x00 3. " IR_SLEEP                ,0h = IrDA/CIR sleep mode disabled" "Disabled,Enabled"
bitfld.long 0x00 0.--2. "                                      MODE_SELECT                            ,0h = UART 16x mode" "UART_16x,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled"
group.long 0x24++0x3
line.long 0x00 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in [2:0]. Note: The [6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin."
bitfld.long 0x00 7. " SET_TXIR_ALT            ,Provide alternate function for" "Normal,Alternate"
bitfld.long 0x00 6. "                                     IRRXINVERT                             ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1"
textline "                                "
bitfld.long 0x00 4.--5. " CIR_PULSE_MODE          ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3"
bitfld.long 0x00 3. "                                             UART_PULSE                             ,UART mode only. Allows pulse shaping in UART mode." "0,1"
textline "                                "
bitfld.long 0x00 1.--2. " STS_FIFO_TRIG           ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3"
bitfld.long 0x00 0. "                                             IRTX_UNDERRUN                          ,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1"
rgroup.long 0x28++0x3
line.long 0x00 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer ( and must be read first)."
bitfld.long 0x00 4. " OE_ERROR                ,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "No_error,Error"
bitfld.long 0x00 3. "                                      FRAME_TOO_LONG_ERROR                   ,Read 1h = Frame-length too long error in frame at top of RX FIFO" "No_error,Error"
textline "                                "
bitfld.long 0x00 2. " ABORT_DETECT            ,Read 1h = Abort pattern detected in frame at top of RX FIFO" "No_error,Error"
bitfld.long 0x00 1. "                                      CRC_ERROR                              ,Read 1h = CRC error in frame at top of RX FIFO" "No_error,Error"
wgroup.long 0x28++0x3
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
hexmask.long.byte 0x00 0.--7. 1. " TXFLL                   ,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00."
hexmask.long.byte 0x00 0.--7. 1. " RESUME                  ,Dummy read to restart the TX or RX"
wgroup.long 0x2C++0x3
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
bitfld.long 0x00 0.--4. " TXFLH                   ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x30++0x3
line.long 0x00 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
hexmask.long.byte 0x00 0.--7. 1. " RXFLL                   ,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
hexmask.long.byte 0x00 0.--7. 1. " SFREGL                  ,LSB part of the frame length"
wgroup.long 0x34++0x3
line.long 0x00 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
bitfld.long 0x00 0.--3. " RXFLH                   ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x3
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
bitfld.long 0x00 0.--3. " SFREGH                  ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte)."
bitfld.long 0x00 7. " STS_FIFO_RESET          ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset"
bitfld.long 0x00 6. "                                      XBOF_TYPE                              ,SIR xBOF select" "0xFF,0xC0"
rgroup.long 0x38++0x3
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition. Note: When the UART is in autobauding mode, this register, instead of the , , and registers, is used to set up transmission according to the characteristics of the previous reception. To reset the autobauding hardware (to start a new AT detection), set [2:0] to 111 (reset value), then set [2:1] to 010 (UART in autobaud mode). To set the UART to standard mode (no autobaud), set [2:1] to 000."
bitfld.long 0x00 6.--7. " PARITY_TYPE             ,Read 0h = No parity identified" "No_parity,Parity_space,Even,Odd"
bitfld.long 0x00 5. "                                  BIT_BY_CHAR                            ,Read 0h = 7-bit character identified" "7,8"
textline "                                "
bitfld.long 0x00 0.--4. " SPEED                   ,Used to report the speed identified" "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
group.long 0x3C++0x3
line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only."
bitfld.long 0x00 7. " PULSE_TYPE              ,SIR pulse width select" "3/16_of_baud-rate,1.6_us"
bitfld.long 0x00 6. "                             SD_MOD                                 ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "High,Low"
textline "                                "
bitfld.long 0x00 5. " DIS_IR_RX               ,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "No,Yes"
bitfld.long 0x00 4. "                                           DIS_TX_UNDERRUN                        ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "No,Yes"
textline "                                "
bitfld.long 0x00 3. " SEND_SIP                ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "No_action,Sent"
bitfld.long 0x00 2. "                                     SCTX_EN                                ,Store and controlled TX start. When" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " ABORT_EN                ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "Disabled,Enabled"
bitfld.long 0x00 0. "                                      EOT_EN                                 ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the [1] bit must be checked. To clear the wake-up interrupt, bit [4] must be reset to 0."
bitfld.long 0x00 7. " RX_TRIG_GRANU1          ,0h = Disables the granularity of 1 for trigger RX level" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      TX_TRIG_GRANU1                         ,0h = Disables the granularity of 1 for trigger TX level" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " DSR_IT                  ,0h = Disables DSR* interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "                                      RX_CTS_DSR_WAKE_UP_ENABLE              ,0h = Disables the wake-up interrupt and clears SSR[1]" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 3. " TX_EMPTY_CTL_IT         ,0h = Normal mode for THR interrupt" "No_interrupt,Interrupt"
bitfld.long 0x00 1.--2. "                                  DMA_MODE_2                             ,Used to specify the DMA mode valid if the" "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX"
textline "                                "
bitfld.long 0x00 0. " DMA_MODE_CTL            ,0h = The DMA_MODE is set with" "UART_FCR[3],UART_SCR[2:1]"
group.long 0x44++0x3
line.long 0x00 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0."
bitfld.long 0x00 2. " DMA_COUNTER_RST         ,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "No_reset,Reset"
bitfld.long 0x00 1. "                                      RX_CTS_DSR_WAKE_UP_STS                 ,Read 0h = No falling edge event on RX, CTS*, and DSR*" "Not_occurred,Occurred"
textline "                                "
bitfld.long 0x00 0. " TX_FIFO_FULL            ,Read 0h = TX FIFO is not full." "Not_full,Full"
group.long 0x48++0x3
line.long 0x00 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the [5] to 1. Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO."
hexmask.long.byte 0x00 0.--7. 1. " EBLR                    ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification."
rgroup.long 0x50++0x3
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned."
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "                                             FUNC                                   ,Function revision number of module"
textline "                                "
bitfld.long 0x00 11.--15. " RTL                     ,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "                                            MAJOR                                  ,Major revision number of the module" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 6.--7. " CUSTOM                  ,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "                                             MINOR                                  ,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x3
line.long 0x00 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset."
bitfld.long 0x00 3.--4. " IDLEMODE                ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "Force_idle,No-idle,Smart_idle,Reserved"
bitfld.long 0x00 2. "                                    ENAWAKEUP                              ,Wake-up feature control" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " SOFTRESET               ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "No_reset,Reset"
bitfld.long 0x00 0. "                                      AUTOIDLE                               ,Internal OCP clock gating strategy" "Running,Gated"
rgroup.long 0x58++0x3
line.long 0x00 "UART_SYSS,System status register"
bitfld.long 0x00 0. " RESETDONE               ,Internal reset monitoring" "Not_completed,Completed"
group.long 0x5C++0x3
line.long 0x00 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt."
bitfld.long 0x00 7. " EVENT_7_TX_WAKEUP_EN    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 6. "                                             EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT   ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 4. "                                             EVENT_4_RX_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0h = Event is not allowed to wake up the system" "0,1"
bitfld.long 0x00 2. "                                             EVENT_2_RI_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 0. "                                             EVENT_0_CTS_ACTIVITY                   ,0h = Event is not allowed to wake up the system." "0,1"
group.long 0x60++0x3
line.long 0x00 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple."
hexmask.long.byte 0x00 0.--7. 1. " CFPS                    ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:"
rgroup.long 0x64++0x3
line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL              ,Shows the number of received bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL              ,Shows the number of written bytes in the TX FIFO"
group.long 0x6C++0x3
line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x00 1. " EN_TXFIFO_EMPTY         ,Enables TX FIFO empty corresponding interrupt" "Enabled,Disabled"
bitfld.long 0x00 0. "                                      EN_RXFIFO_EMPTY                        ,Enables RX FIFO empty corresponding interrupt" "Enabled,Disabled"
hgroup.long 0x70++0x3
hide.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
in
textline "                                "
group.long 0x74++0x3
line.long 0x00 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL                ,Sets the sample per bit if nondefault frequency is used."
group.long 0x78++0x3
line.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
group.long 0x7C++0x3
line.long 0x00 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x3
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. " DIR_EN                  ,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "                                             DIR_POL                                ,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0" "0,1"
textline "                                "
bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD    ,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "                                             NONDEFAULT_FREQ                        ,Used to enable the NONDEFAULT fclk frequencies." "0,1"
textline "                                "
bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD    ,Used to enable CIR RX demodulation." "0,1"
group.long 0x84++0x3
line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register."
bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD        ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x3
line.long 0x00 "UART_MDR4,Mode definition register 4"
bitfld.long 0x00 6. " MODE9                   ,9-bit character length When '1', overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x00 3.--5. "                                             FREQ_SEL_H                             ,Upper 3 bits of" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--2. " MODE                    ,New modes [when set, overrides" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x00 7. " BROADCAST               ,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x00 6. "                                             TIMEOUT_BEHAVE                         ,Specifies how timeout is measured" "0,1"
textline "                                "
bitfld.long 0x00 5. " C8                      ,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x00 4. "                                             C4                                     ,Value for ISO 7816 C4 pin for software control" "0,1"
textline "                                "
bitfld.long 0x00 3. " C2                      ,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x00 2. "                                             MULTIDROP                              ,Enables parity Multi-drop mode [overrides" "0,1"
textline "                                "
bitfld.long 0x00 1. " RHR_OVERRUN             ," "0,1"
bitfld.long 0x00 0. "                                             ENDIAN                                 ,Endianness" "0,1"
group.long 0x90++0x3
line.long 0x00 "UART_ECR,Enhanced Control register"
bitfld.long 0x00 5. " CLEAR_TX_PE             ,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
bitfld.long 0x00 4. "                                             TX_EN                                  ,Enables/Disables the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_EN                   ,Enables/Disables the receiver" "0,1"
bitfld.long 0x00 2. "                                             TX_RST                                 ,Writing 1h = resets the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_RST                  ,Writing 1h = resets the receiver" "0,1"
bitfld.long 0x00 0. "                                             A_MULTIDROP                            ,In multi-drop mode, when written with the value '1' causes the next byte written into" "0,1"
group.long 0x94++0x3
line.long 0x00 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x00 0.--7. 1. " TIMEGUARD               ,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices"
group.long 0x98++0x3
line.long 0x00 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_L               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]"
group.long 0x9C++0x3
line.long 0x00 "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_H               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]"
group.long 0xA0++0x3
line.long 0x00 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x00 7. " DSNACK                  ,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x00 6. "                                             INACK                                  ,Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
textline "                                "
bitfld.long 0x00 0.--2. " MAX_ITERATION           ,Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x00 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ERHR                    ,Extended Receive Holding Register - allows accessing the full 9bit"
wgroup.long 0xA4++0x3
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ETHR                    ,Extended Transmit Holding Register - allows writing the full 9bit"
group.long 0xA8++0x3
line.long 0x00 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS                 ,Multidrop match address value"
group.long 0xAC++0x3
line.long 0x00 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " MASK                    ,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
group.long 0xB0++0x3
line.long 0x00 "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x00 0.--7. 1. " BROADCAST_ADDRESS       ,Broadcast address for address matching"
width 0x0B
tree.end
tree "UART1"
base ad:0x2810000
width 23.
group.long 0x0++0x3
line.long 0x00 "UART_DLL,This register, with , stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor."
hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB               ,Stores the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the . If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the is not overwritten."
hexmask.long.byte 0x00 0.--7. 1. " RHR                     ,Receive holding register"
wgroup.long 0x0++0x3
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data."
hexmask.long.byte 0x00 0.--7. 1. " THR                     ,Transmit holding register"
group.long 0x4++0x3
line.long 0x00 "UART_DLH,This register, with , stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor."
bitfld.long 0x00 0.--5. " CLOCK_MSB               ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0."
bitfld.long 0x00 6.--7. " NOT_USED                ," "0,1,2,3"
bitfld.long 0x00 5. "                                             TX_STATUS_IT                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             RX_STOP_IT                             ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_TRIG_IT                       ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             LAST_RX_BYTE_IT                        ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, interrupt, interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit."
bitfld.long 0x00 7. " CTS_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             RTS_IT                                 ," "0,1"
textline "                                "
bitfld.long 0x00 5. " XOFF_IT                 ," "0,1"
bitfld.long 0x00 4. "                                             SLEEP_MODE                             ," "0,1"
textline "                                "
bitfld.long 0x00 3. " MODEM_STS_IT            ," "0,1"
bitfld.long 0x00 2. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x8++0x3
line.long 0x00 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but [4] enables write accesses to [5:4], the TX trigger level, which is also used in IrDA modes."
bitfld.long 0x00 7. " AUTO_CTS_EN             ,Auto-CTS enable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      AUTO_RTS_EN                            ,Auto-RTS enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT     ," "Disabled,Enabled"
bitfld.long 0x00 4. "                                      ENHANCED_EN                            ,Enhanced functions write enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL         ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2"
wgroup.long 0x8++0x3
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting restriction when [7] = 1."
bitfld.long 0x00 6.--7. " RX_FIFO_TRIG            ,Sets the trigger level for the RX FIFO: If" "8,16,56,60"
bitfld.long 0x00 4.--5. "                                            TX_FIFO_TRIG                           ,Sets the trigger level for the TX FIFO: If" "8,16,32,56"
textline "                                "
bitfld.long 0x00 3. " DMA_MODE                ,This register is considered if" "Disabled,Enabled"
bitfld.long 0x00 2. "                                      TX_FIFO_CLEAR                          ," "No_effect,Clear"
textline "                                "
bitfld.long 0x00 1. " RX_FIFO_CLEAR           ," "No_effect,Clear"
bitfld.long 0x00 0. "                                     FIFO_EN                                ," "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active."
bitfld.long 0x00 5. " TX_STATUS_IT            ,Read 0h = TX status interrupt inactive" "0,1"
bitfld.long 0x00 3. "                                             RX_OE_IT                               ,Read 0h = RX overrun interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 2. " RX_STOP_IT              ,Read 0h = Receive stop interrupt inactive" "0,1"
bitfld.long 0x00 1. "                                             THR_IT                                 ,Read 0h = THR interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 0. " RHR_IT                  ,Read 0h = RHR interrupt inactive" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OE_IT                ," "0,1"
bitfld.long 0x00 2. "                                             RX_FIFO_LAST_BYTE_IT                   ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner."
bitfld.long 0x00 6.--7. " FCR_MIRROR              ,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "                                             IT_TYPE                                ,Read 0h = Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 0. " IT_PENDING              ,Read 0h = An interrupt is pending." "0,1"
group.long 0xC++0x3
line.long 0x00 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1, the TX line is forced to 0 and remains in this state as long as [6] = 1."
bitfld.long 0x00 7. " DIV_EN                  ," "Disabled,Enabled"
bitfld.long 0x00 6. "                                      BREAK_EN                               ,Break control bit" "Normal,Forced_low"
textline "                                "
bitfld.long 0x00 5. " PARITY_TYPE2            ,Selects the forced parity format (if" "No_parity,Odd_parity"
bitfld.long 0x00 4. "                                    PARITY_TYPE1                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " PARITY_EN               ,0h = No parity" "0,1"
bitfld.long 0x00 2. "                                             NB_STOP                                ,Specifies the number of stop-bits" "1,1.5"
textline "                                "
bitfld.long 0x00 0.--1. " CHAR_LENGTH             ,Specifies the word length to be transmitted or received" "5,6,7,8"
group.long 0x10++0x3
line.long 0x00 "UART_MCR,Modem control register [3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem."
bitfld.long 0x00 6. " TCR_TLR                 ,0h = No action" "Disabled,Enabled"
bitfld.long 0x00 5. "                                      XON_EN                                 ,0h = Disable XON any function." "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 4. " LOOPBACK_EN             ,0h = Normal operating mode" "Disabled,Enabled"
bitfld.long 0x00 3. "                                      CD_STS_CH                              ,0h = In loopback, forces DCD* input high and IRQ outputs to inactive state" "High,Low"
textline "                                "
bitfld.long 0x00 2. " RI_STS_CH               ,0h = In loopback, forces RI* input high" "High,Low"
bitfld.long 0x00 1. "                                          RTS                                    ,In loopback, controls the" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0. " DTR                     ,0h = Force DTR* output to inactive (high)." "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1               ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 5. "                                             RX_STOP                                ,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
textline "                                "
bitfld.long 0x00 0. " RX_FIFO_E               ,Read 0h = At least one data character in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)."
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 6. "                                             STS_FIFO_FULL                          ,Read 0h = Status FIFO not full" "0,1"
textline "                                "
bitfld.long 0x00 5. " RX_LAST_BYTE            ,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1"
bitfld.long 0x00 4. "                                             FRAME_TOO_LONG                         ,Read 0h = No frame-too-long error in frame" "0,1"
textline "                                "
bitfld.long 0x00 3. " ABORT                   ,Read 0h = No abort pattern error in frame" "0,1"
bitfld.long 0x00 2. "                                             CRC                                    ,Read 0h = No CRC error in frame" "0,1"
textline "                                "
bitfld.long 0x00 1. " STS_FIFO_E              ,Read 0h = Status FIFO not empty" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. " RX_FIFO_STS             ,Read 0h = Normal operation" "0,1"
bitfld.long 0x00 6. "                                             TX_SR_E                                ,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_FIFO_E               ,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 4. "                                             RX_BI                                  ,Read 0h = No break condition" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_FE                   ,Read 0h = No framing error in data RX FIFO" "0,1"
bitfld.long 0x00 2. "                                             RX_PE                                  ,Read 0h = No parity error in data from RX FIFO" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_OE                   ,Read 0h = No overrun error" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
group.long 0x14++0x3
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2               ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
rgroup.long 0x18++0x3
line.long 0x00 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state."
bitfld.long 0x00 7. " NCD_STS                 ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 6. "                                             NRI_STS                                ,This bit is the complement of the RI* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 5. " NDSR_STS                ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 4. "                                             NCTS_STS                               ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 3. " DCD_STS                 ,Indicates that DCD* input (or" "0,1"
bitfld.long 0x00 2. "                                             RI_STS                                 ,Indicates that RI* input (or" "0,1"
textline "                                "
bitfld.long 0x00 1. " DSR_STS                 ," "0,1"
bitfld.long 0x00 0. "                                             CTS_STS                                ," "0,1"
group.long 0x18++0x3
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that [3:0] > [7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level ([7:4] or [7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START      ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.long 0x00 0.--3. "                                            RX_FIFO_TRIG_HALT                      ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.long 0x18++0x3
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1              ,Stores the 8-bit XOFF1 character used in UART modes"
group.long 0x1C++0x3
line.long 0x00 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD                ,Scratchpad register"
group.long 0x1C++0x3
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA        ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                                            TX_FIFO_TRIG_DMA                       ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x3
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2              ,Stores the 8-bit XOFF2 character used in UART modes."
group.long 0x20++0x3
line.long 0x00 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (, , and ). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags."
bitfld.long 0x00 7. " FRAME_END_MODE          ,IrDA mode only" "Frame-length,EOT"
bitfld.long 0x00 6. "                                  SIP_MODE                               ,MIR/FIR modes only" "Manual_SIP,Automatic_SIP"
textline "                                "
bitfld.long 0x00 5. " SCT                     ,Store and control the transmission." "THR,ACREG[2]"
bitfld.long 0x00 4. "                                      SET_TXIR                               ,Used to configure the infrared transceiver" "TXIR_low,IRTX_high"
textline "                                "
bitfld.long 0x00 3. " IR_SLEEP                ,0h = IrDA/CIR sleep mode disabled" "Disabled,Enabled"
bitfld.long 0x00 0.--2. "                                      MODE_SELECT                            ,0h = UART 16x mode" "UART_16x,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled"
group.long 0x24++0x3
line.long 0x00 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in [2:0]. Note: The [6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin."
bitfld.long 0x00 7. " SET_TXIR_ALT            ,Provide alternate function for" "Normal,Alternate"
bitfld.long 0x00 6. "                                     IRRXINVERT                             ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1"
textline "                                "
bitfld.long 0x00 4.--5. " CIR_PULSE_MODE          ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3"
bitfld.long 0x00 3. "                                             UART_PULSE                             ,UART mode only. Allows pulse shaping in UART mode." "0,1"
textline "                                "
bitfld.long 0x00 1.--2. " STS_FIFO_TRIG           ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3"
bitfld.long 0x00 0. "                                             IRTX_UNDERRUN                          ,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1"
rgroup.long 0x28++0x3
line.long 0x00 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer ( and must be read first)."
bitfld.long 0x00 4. " OE_ERROR                ,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "No_error,Error"
bitfld.long 0x00 3. "                                      FRAME_TOO_LONG_ERROR                   ,Read 1h = Frame-length too long error in frame at top of RX FIFO" "No_error,Error"
textline "                                "
bitfld.long 0x00 2. " ABORT_DETECT            ,Read 1h = Abort pattern detected in frame at top of RX FIFO" "No_error,Error"
bitfld.long 0x00 1. "                                      CRC_ERROR                              ,Read 1h = CRC error in frame at top of RX FIFO" "No_error,Error"
wgroup.long 0x28++0x3
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
hexmask.long.byte 0x00 0.--7. 1. " TXFLL                   ,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00."
hexmask.long.byte 0x00 0.--7. 1. " RESUME                  ,Dummy read to restart the TX or RX"
wgroup.long 0x2C++0x3
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
bitfld.long 0x00 0.--4. " TXFLH                   ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x30++0x3
line.long 0x00 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
hexmask.long.byte 0x00 0.--7. 1. " RXFLL                   ,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
hexmask.long.byte 0x00 0.--7. 1. " SFREGL                  ,LSB part of the frame length"
wgroup.long 0x34++0x3
line.long 0x00 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
bitfld.long 0x00 0.--3. " RXFLH                   ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x3
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
bitfld.long 0x00 0.--3. " SFREGH                  ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte)."
bitfld.long 0x00 7. " STS_FIFO_RESET          ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset"
bitfld.long 0x00 6. "                                      XBOF_TYPE                              ,SIR xBOF select" "0xFF,0xC0"
rgroup.long 0x38++0x3
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition. Note: When the UART is in autobauding mode, this register, instead of the , , and registers, is used to set up transmission according to the characteristics of the previous reception. To reset the autobauding hardware (to start a new AT detection), set [2:0] to 111 (reset value), then set [2:1] to 010 (UART in autobaud mode). To set the UART to standard mode (no autobaud), set [2:1] to 000."
bitfld.long 0x00 6.--7. " PARITY_TYPE             ,Read 0h = No parity identified" "No_parity,Parity_space,Even,Odd"
bitfld.long 0x00 5. "                                  BIT_BY_CHAR                            ,Read 0h = 7-bit character identified" "7,8"
textline "                                "
bitfld.long 0x00 0.--4. " SPEED                   ,Used to report the speed identified" "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
group.long 0x3C++0x3
line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only."
bitfld.long 0x00 7. " PULSE_TYPE              ,SIR pulse width select" "3/16_of_baud-rate,1.6_us"
bitfld.long 0x00 6. "                             SD_MOD                                 ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "High,Low"
textline "                                "
bitfld.long 0x00 5. " DIS_IR_RX               ,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "No,Yes"
bitfld.long 0x00 4. "                                           DIS_TX_UNDERRUN                        ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "No,Yes"
textline "                                "
bitfld.long 0x00 3. " SEND_SIP                ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "No_action,Sent"
bitfld.long 0x00 2. "                                     SCTX_EN                                ,Store and controlled TX start. When" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " ABORT_EN                ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "Disabled,Enabled"
bitfld.long 0x00 0. "                                      EOT_EN                                 ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the [1] bit must be checked. To clear the wake-up interrupt, bit [4] must be reset to 0."
bitfld.long 0x00 7. " RX_TRIG_GRANU1          ,0h = Disables the granularity of 1 for trigger RX level" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      TX_TRIG_GRANU1                         ,0h = Disables the granularity of 1 for trigger TX level" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " DSR_IT                  ,0h = Disables DSR* interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "                                      RX_CTS_DSR_WAKE_UP_ENABLE              ,0h = Disables the wake-up interrupt and clears SSR[1]" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 3. " TX_EMPTY_CTL_IT         ,0h = Normal mode for THR interrupt" "No_interrupt,Interrupt"
bitfld.long 0x00 1.--2. "                                  DMA_MODE_2                             ,Used to specify the DMA mode valid if the" "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX"
textline "                                "
bitfld.long 0x00 0. " DMA_MODE_CTL            ,0h = The DMA_MODE is set with" "UART_FCR[3],UART_SCR[2:1]"
group.long 0x44++0x3
line.long 0x00 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0."
bitfld.long 0x00 2. " DMA_COUNTER_RST         ,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "No_reset,Reset"
bitfld.long 0x00 1. "                                      RX_CTS_DSR_WAKE_UP_STS                 ,Read 0h = No falling edge event on RX, CTS*, and DSR*" "Not_occurred,Occurred"
textline "                                "
bitfld.long 0x00 0. " TX_FIFO_FULL            ,Read 0h = TX FIFO is not full." "Not_full,Full"
group.long 0x48++0x3
line.long 0x00 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the [5] to 1. Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO."
hexmask.long.byte 0x00 0.--7. 1. " EBLR                    ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification."
rgroup.long 0x50++0x3
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned."
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "                                             FUNC                                   ,Function revision number of module"
textline "                                "
bitfld.long 0x00 11.--15. " RTL                     ,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "                                            MAJOR                                  ,Major revision number of the module" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 6.--7. " CUSTOM                  ,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "                                             MINOR                                  ,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x3
line.long 0x00 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset."
bitfld.long 0x00 3.--4. " IDLEMODE                ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "Force_idle,No-idle,Smart_idle,Reserved"
bitfld.long 0x00 2. "                                    ENAWAKEUP                              ,Wake-up feature control" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " SOFTRESET               ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "No_reset,Reset"
bitfld.long 0x00 0. "                                      AUTOIDLE                               ,Internal OCP clock gating strategy" "Running,Gated"
rgroup.long 0x58++0x3
line.long 0x00 "UART_SYSS,System status register"
bitfld.long 0x00 0. " RESETDONE               ,Internal reset monitoring" "Not_completed,Completed"
group.long 0x5C++0x3
line.long 0x00 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt."
bitfld.long 0x00 7. " EVENT_7_TX_WAKEUP_EN    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 6. "                                             EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT   ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 4. "                                             EVENT_4_RX_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0h = Event is not allowed to wake up the system" "0,1"
bitfld.long 0x00 2. "                                             EVENT_2_RI_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 0. "                                             EVENT_0_CTS_ACTIVITY                   ,0h = Event is not allowed to wake up the system." "0,1"
group.long 0x60++0x3
line.long 0x00 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple."
hexmask.long.byte 0x00 0.--7. 1. " CFPS                    ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:"
rgroup.long 0x64++0x3
line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL              ,Shows the number of received bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL              ,Shows the number of written bytes in the TX FIFO"
group.long 0x6C++0x3
line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x00 1. " EN_TXFIFO_EMPTY         ,Enables TX FIFO empty corresponding interrupt" "Enabled,Disabled"
bitfld.long 0x00 0. "                                      EN_RXFIFO_EMPTY                        ,Enables RX FIFO empty corresponding interrupt" "Enabled,Disabled"
hgroup.long 0x70++0x3
hide.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
in
textline "                                "
group.long 0x74++0x3
line.long 0x00 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL                ,Sets the sample per bit if nondefault frequency is used."
group.long 0x78++0x3
line.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
group.long 0x7C++0x3
line.long 0x00 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x3
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. " DIR_EN                  ,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "                                             DIR_POL                                ,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0" "0,1"
textline "                                "
bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD    ,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "                                             NONDEFAULT_FREQ                        ,Used to enable the NONDEFAULT fclk frequencies." "0,1"
textline "                                "
bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD    ,Used to enable CIR RX demodulation." "0,1"
group.long 0x84++0x3
line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register."
bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD        ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x3
line.long 0x00 "UART_MDR4,Mode definition register 4"
bitfld.long 0x00 6. " MODE9                   ,9-bit character length When '1', overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x00 3.--5. "                                             FREQ_SEL_H                             ,Upper 3 bits of" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--2. " MODE                    ,New modes [when set, overrides" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x00 7. " BROADCAST               ,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x00 6. "                                             TIMEOUT_BEHAVE                         ,Specifies how timeout is measured" "0,1"
textline "                                "
bitfld.long 0x00 5. " C8                      ,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x00 4. "                                             C4                                     ,Value for ISO 7816 C4 pin for software control" "0,1"
textline "                                "
bitfld.long 0x00 3. " C2                      ,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x00 2. "                                             MULTIDROP                              ,Enables parity Multi-drop mode [overrides" "0,1"
textline "                                "
bitfld.long 0x00 1. " RHR_OVERRUN             ," "0,1"
bitfld.long 0x00 0. "                                             ENDIAN                                 ,Endianness" "0,1"
group.long 0x90++0x3
line.long 0x00 "UART_ECR,Enhanced Control register"
bitfld.long 0x00 5. " CLEAR_TX_PE             ,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
bitfld.long 0x00 4. "                                             TX_EN                                  ,Enables/Disables the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_EN                   ,Enables/Disables the receiver" "0,1"
bitfld.long 0x00 2. "                                             TX_RST                                 ,Writing 1h = resets the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_RST                  ,Writing 1h = resets the receiver" "0,1"
bitfld.long 0x00 0. "                                             A_MULTIDROP                            ,In multi-drop mode, when written with the value '1' causes the next byte written into" "0,1"
group.long 0x94++0x3
line.long 0x00 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x00 0.--7. 1. " TIMEGUARD               ,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices"
group.long 0x98++0x3
line.long 0x00 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_L               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]"
group.long 0x9C++0x3
line.long 0x00 "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_H               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]"
group.long 0xA0++0x3
line.long 0x00 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x00 7. " DSNACK                  ,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x00 6. "                                             INACK                                  ,Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
textline "                                "
bitfld.long 0x00 0.--2. " MAX_ITERATION           ,Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x00 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ERHR                    ,Extended Receive Holding Register - allows accessing the full 9bit"
wgroup.long 0xA4++0x3
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ETHR                    ,Extended Transmit Holding Register - allows writing the full 9bit"
group.long 0xA8++0x3
line.long 0x00 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS                 ,Multidrop match address value"
group.long 0xAC++0x3
line.long 0x00 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " MASK                    ,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
group.long 0xB0++0x3
line.long 0x00 "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x00 0.--7. 1. " BROADCAST_ADDRESS       ,Broadcast address for address matching"
width 0x0B
tree.end
tree "UART2"
base ad:0x2820000
width 23.
group.long 0x0++0x3
line.long 0x00 "UART_DLL,This register, with , stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor."
hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB               ,Stores the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the . If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the is not overwritten."
hexmask.long.byte 0x00 0.--7. 1. " RHR                     ,Receive holding register"
wgroup.long 0x0++0x3
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data."
hexmask.long.byte 0x00 0.--7. 1. " THR                     ,Transmit holding register"
group.long 0x4++0x3
line.long 0x00 "UART_DLH,This register, with , stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor."
bitfld.long 0x00 0.--5. " CLOCK_MSB               ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0."
bitfld.long 0x00 6.--7. " NOT_USED                ," "0,1,2,3"
bitfld.long 0x00 5. "                                             TX_STATUS_IT                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             RX_STOP_IT                             ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_TRIG_IT                       ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             LAST_RX_BYTE_IT                        ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, interrupt, interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit."
bitfld.long 0x00 7. " CTS_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             RTS_IT                                 ," "0,1"
textline "                                "
bitfld.long 0x00 5. " XOFF_IT                 ," "0,1"
bitfld.long 0x00 4. "                                             SLEEP_MODE                             ," "0,1"
textline "                                "
bitfld.long 0x00 3. " MODEM_STS_IT            ," "0,1"
bitfld.long 0x00 2. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x8++0x3
line.long 0x00 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but [4] enables write accesses to [5:4], the TX trigger level, which is also used in IrDA modes."
bitfld.long 0x00 7. " AUTO_CTS_EN             ,Auto-CTS enable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      AUTO_RTS_EN                            ,Auto-RTS enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT     ," "Disabled,Enabled"
bitfld.long 0x00 4. "                                      ENHANCED_EN                            ,Enhanced functions write enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL         ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2"
wgroup.long 0x8++0x3
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting restriction when [7] = 1."
bitfld.long 0x00 6.--7. " RX_FIFO_TRIG            ,Sets the trigger level for the RX FIFO: If" "8,16,56,60"
bitfld.long 0x00 4.--5. "                                            TX_FIFO_TRIG                           ,Sets the trigger level for the TX FIFO: If" "8,16,32,56"
textline "                                "
bitfld.long 0x00 3. " DMA_MODE                ,This register is considered if" "Disabled,Enabled"
bitfld.long 0x00 2. "                                      TX_FIFO_CLEAR                          ," "No_effect,Clear"
textline "                                "
bitfld.long 0x00 1. " RX_FIFO_CLEAR           ," "No_effect,Clear"
bitfld.long 0x00 0. "                                     FIFO_EN                                ," "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active."
bitfld.long 0x00 5. " TX_STATUS_IT            ,Read 0h = TX status interrupt inactive" "0,1"
bitfld.long 0x00 3. "                                             RX_OE_IT                               ,Read 0h = RX overrun interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 2. " RX_STOP_IT              ,Read 0h = Receive stop interrupt inactive" "0,1"
bitfld.long 0x00 1. "                                             THR_IT                                 ,Read 0h = THR interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 0. " RHR_IT                  ,Read 0h = RHR interrupt inactive" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OE_IT                ," "0,1"
bitfld.long 0x00 2. "                                             RX_FIFO_LAST_BYTE_IT                   ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner."
bitfld.long 0x00 6.--7. " FCR_MIRROR              ,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "                                             IT_TYPE                                ,Read 0h = Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 0. " IT_PENDING              ,Read 0h = An interrupt is pending." "0,1"
group.long 0xC++0x3
line.long 0x00 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1, the TX line is forced to 0 and remains in this state as long as [6] = 1."
bitfld.long 0x00 7. " DIV_EN                  ," "Disabled,Enabled"
bitfld.long 0x00 6. "                                      BREAK_EN                               ,Break control bit" "Normal,Forced_low"
textline "                                "
bitfld.long 0x00 5. " PARITY_TYPE2            ,Selects the forced parity format (if" "No_parity,Odd_parity"
bitfld.long 0x00 4. "                                    PARITY_TYPE1                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " PARITY_EN               ,0h = No parity" "0,1"
bitfld.long 0x00 2. "                                             NB_STOP                                ,Specifies the number of stop-bits" "1,1.5"
textline "                                "
bitfld.long 0x00 0.--1. " CHAR_LENGTH             ,Specifies the word length to be transmitted or received" "5,6,7,8"
group.long 0x10++0x3
line.long 0x00 "UART_MCR,Modem control register [3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem."
bitfld.long 0x00 6. " TCR_TLR                 ,0h = No action" "Disabled,Enabled"
bitfld.long 0x00 5. "                                      XON_EN                                 ,0h = Disable XON any function." "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 4. " LOOPBACK_EN             ,0h = Normal operating mode" "Disabled,Enabled"
bitfld.long 0x00 3. "                                      CD_STS_CH                              ,0h = In loopback, forces DCD* input high and IRQ outputs to inactive state" "High,Low"
textline "                                "
bitfld.long 0x00 2. " RI_STS_CH               ,0h = In loopback, forces RI* input high" "High,Low"
bitfld.long 0x00 1. "                                          RTS                                    ,In loopback, controls the" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0. " DTR                     ,0h = Force DTR* output to inactive (high)." "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1               ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 5. "                                             RX_STOP                                ,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
textline "                                "
bitfld.long 0x00 0. " RX_FIFO_E               ,Read 0h = At least one data character in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)."
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 6. "                                             STS_FIFO_FULL                          ,Read 0h = Status FIFO not full" "0,1"
textline "                                "
bitfld.long 0x00 5. " RX_LAST_BYTE            ,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1"
bitfld.long 0x00 4. "                                             FRAME_TOO_LONG                         ,Read 0h = No frame-too-long error in frame" "0,1"
textline "                                "
bitfld.long 0x00 3. " ABORT                   ,Read 0h = No abort pattern error in frame" "0,1"
bitfld.long 0x00 2. "                                             CRC                                    ,Read 0h = No CRC error in frame" "0,1"
textline "                                "
bitfld.long 0x00 1. " STS_FIFO_E              ,Read 0h = Status FIFO not empty" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. " RX_FIFO_STS             ,Read 0h = Normal operation" "0,1"
bitfld.long 0x00 6. "                                             TX_SR_E                                ,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_FIFO_E               ,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 4. "                                             RX_BI                                  ,Read 0h = No break condition" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_FE                   ,Read 0h = No framing error in data RX FIFO" "0,1"
bitfld.long 0x00 2. "                                             RX_PE                                  ,Read 0h = No parity error in data from RX FIFO" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_OE                   ,Read 0h = No overrun error" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
group.long 0x14++0x3
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2               ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
rgroup.long 0x18++0x3
line.long 0x00 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state."
bitfld.long 0x00 7. " NCD_STS                 ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 6. "                                             NRI_STS                                ,This bit is the complement of the RI* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 5. " NDSR_STS                ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 4. "                                             NCTS_STS                               ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 3. " DCD_STS                 ,Indicates that DCD* input (or" "0,1"
bitfld.long 0x00 2. "                                             RI_STS                                 ,Indicates that RI* input (or" "0,1"
textline "                                "
bitfld.long 0x00 1. " DSR_STS                 ," "0,1"
bitfld.long 0x00 0. "                                             CTS_STS                                ," "0,1"
group.long 0x18++0x3
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that [3:0] > [7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level ([7:4] or [7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START      ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.long 0x00 0.--3. "                                            RX_FIFO_TRIG_HALT                      ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.long 0x18++0x3
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1              ,Stores the 8-bit XOFF1 character used in UART modes"
group.long 0x1C++0x3
line.long 0x00 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD                ,Scratchpad register"
group.long 0x1C++0x3
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA        ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                                            TX_FIFO_TRIG_DMA                       ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x3
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2              ,Stores the 8-bit XOFF2 character used in UART modes."
group.long 0x20++0x3
line.long 0x00 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (, , and ). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags."
bitfld.long 0x00 7. " FRAME_END_MODE          ,IrDA mode only" "Frame-length,EOT"
bitfld.long 0x00 6. "                                  SIP_MODE                               ,MIR/FIR modes only" "Manual_SIP,Automatic_SIP"
textline "                                "
bitfld.long 0x00 5. " SCT                     ,Store and control the transmission." "THR,ACREG[2]"
bitfld.long 0x00 4. "                                      SET_TXIR                               ,Used to configure the infrared transceiver" "TXIR_low,IRTX_high"
textline "                                "
bitfld.long 0x00 3. " IR_SLEEP                ,0h = IrDA/CIR sleep mode disabled" "Disabled,Enabled"
bitfld.long 0x00 0.--2. "                                      MODE_SELECT                            ,0h = UART 16x mode" "UART_16x,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled"
group.long 0x24++0x3
line.long 0x00 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in [2:0]. Note: The [6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin."
bitfld.long 0x00 7. " SET_TXIR_ALT            ,Provide alternate function for" "Normal,Alternate"
bitfld.long 0x00 6. "                                     IRRXINVERT                             ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1"
textline "                                "
bitfld.long 0x00 4.--5. " CIR_PULSE_MODE          ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3"
bitfld.long 0x00 3. "                                             UART_PULSE                             ,UART mode only. Allows pulse shaping in UART mode." "0,1"
textline "                                "
bitfld.long 0x00 1.--2. " STS_FIFO_TRIG           ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3"
bitfld.long 0x00 0. "                                             IRTX_UNDERRUN                          ,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1"
rgroup.long 0x28++0x3
line.long 0x00 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer ( and must be read first)."
bitfld.long 0x00 4. " OE_ERROR                ,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "No_error,Error"
bitfld.long 0x00 3. "                                      FRAME_TOO_LONG_ERROR                   ,Read 1h = Frame-length too long error in frame at top of RX FIFO" "No_error,Error"
textline "                                "
bitfld.long 0x00 2. " ABORT_DETECT            ,Read 1h = Abort pattern detected in frame at top of RX FIFO" "No_error,Error"
bitfld.long 0x00 1. "                                      CRC_ERROR                              ,Read 1h = CRC error in frame at top of RX FIFO" "No_error,Error"
wgroup.long 0x28++0x3
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
hexmask.long.byte 0x00 0.--7. 1. " TXFLL                   ,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00."
hexmask.long.byte 0x00 0.--7. 1. " RESUME                  ,Dummy read to restart the TX or RX"
wgroup.long 0x2C++0x3
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
bitfld.long 0x00 0.--4. " TXFLH                   ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x30++0x3
line.long 0x00 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
hexmask.long.byte 0x00 0.--7. 1. " RXFLL                   ,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
hexmask.long.byte 0x00 0.--7. 1. " SFREGL                  ,LSB part of the frame length"
wgroup.long 0x34++0x3
line.long 0x00 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
bitfld.long 0x00 0.--3. " RXFLH                   ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x3
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
bitfld.long 0x00 0.--3. " SFREGH                  ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte)."
bitfld.long 0x00 7. " STS_FIFO_RESET          ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset"
bitfld.long 0x00 6. "                                      XBOF_TYPE                              ,SIR xBOF select" "0xFF,0xC0"
rgroup.long 0x38++0x3
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition. Note: When the UART is in autobauding mode, this register, instead of the , , and registers, is used to set up transmission according to the characteristics of the previous reception. To reset the autobauding hardware (to start a new AT detection), set [2:0] to 111 (reset value), then set [2:1] to 010 (UART in autobaud mode). To set the UART to standard mode (no autobaud), set [2:1] to 000."
bitfld.long 0x00 6.--7. " PARITY_TYPE             ,Read 0h = No parity identified" "No_parity,Parity_space,Even,Odd"
bitfld.long 0x00 5. "                                  BIT_BY_CHAR                            ,Read 0h = 7-bit character identified" "7,8"
textline "                                "
bitfld.long 0x00 0.--4. " SPEED                   ,Used to report the speed identified" "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
group.long 0x3C++0x3
line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only."
bitfld.long 0x00 7. " PULSE_TYPE              ,SIR pulse width select" "3/16_of_baud-rate,1.6_us"
bitfld.long 0x00 6. "                             SD_MOD                                 ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "High,Low"
textline "                                "
bitfld.long 0x00 5. " DIS_IR_RX               ,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "No,Yes"
bitfld.long 0x00 4. "                                           DIS_TX_UNDERRUN                        ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "No,Yes"
textline "                                "
bitfld.long 0x00 3. " SEND_SIP                ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "No_action,Sent"
bitfld.long 0x00 2. "                                     SCTX_EN                                ,Store and controlled TX start. When" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " ABORT_EN                ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "Disabled,Enabled"
bitfld.long 0x00 0. "                                      EOT_EN                                 ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the [1] bit must be checked. To clear the wake-up interrupt, bit [4] must be reset to 0."
bitfld.long 0x00 7. " RX_TRIG_GRANU1          ,0h = Disables the granularity of 1 for trigger RX level" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      TX_TRIG_GRANU1                         ,0h = Disables the granularity of 1 for trigger TX level" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " DSR_IT                  ,0h = Disables DSR* interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "                                      RX_CTS_DSR_WAKE_UP_ENABLE              ,0h = Disables the wake-up interrupt and clears SSR[1]" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 3. " TX_EMPTY_CTL_IT         ,0h = Normal mode for THR interrupt" "No_interrupt,Interrupt"
bitfld.long 0x00 1.--2. "                                  DMA_MODE_2                             ,Used to specify the DMA mode valid if the" "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX"
textline "                                "
bitfld.long 0x00 0. " DMA_MODE_CTL            ,0h = The DMA_MODE is set with" "UART_FCR[3],UART_SCR[2:1]"
group.long 0x44++0x3
line.long 0x00 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0."
bitfld.long 0x00 2. " DMA_COUNTER_RST         ,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "No_reset,Reset"
bitfld.long 0x00 1. "                                      RX_CTS_DSR_WAKE_UP_STS                 ,Read 0h = No falling edge event on RX, CTS*, and DSR*" "Not_occurred,Occurred"
textline "                                "
bitfld.long 0x00 0. " TX_FIFO_FULL            ,Read 0h = TX FIFO is not full." "Not_full,Full"
group.long 0x48++0x3
line.long 0x00 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the [5] to 1. Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO."
hexmask.long.byte 0x00 0.--7. 1. " EBLR                    ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification."
rgroup.long 0x50++0x3
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned."
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "                                             FUNC                                   ,Function revision number of module"
textline "                                "
bitfld.long 0x00 11.--15. " RTL                     ,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "                                            MAJOR                                  ,Major revision number of the module" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 6.--7. " CUSTOM                  ,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "                                             MINOR                                  ,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x3
line.long 0x00 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset."
bitfld.long 0x00 3.--4. " IDLEMODE                ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "Force_idle,No-idle,Smart_idle,Reserved"
bitfld.long 0x00 2. "                                    ENAWAKEUP                              ,Wake-up feature control" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " SOFTRESET               ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "No_reset,Reset"
bitfld.long 0x00 0. "                                      AUTOIDLE                               ,Internal OCP clock gating strategy" "Running,Gated"
rgroup.long 0x58++0x3
line.long 0x00 "UART_SYSS,System status register"
bitfld.long 0x00 0. " RESETDONE               ,Internal reset monitoring" "Not_completed,Completed"
group.long 0x5C++0x3
line.long 0x00 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt."
bitfld.long 0x00 7. " EVENT_7_TX_WAKEUP_EN    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 6. "                                             EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT   ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 4. "                                             EVENT_4_RX_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0h = Event is not allowed to wake up the system" "0,1"
bitfld.long 0x00 2. "                                             EVENT_2_RI_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 0. "                                             EVENT_0_CTS_ACTIVITY                   ,0h = Event is not allowed to wake up the system." "0,1"
group.long 0x60++0x3
line.long 0x00 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple."
hexmask.long.byte 0x00 0.--7. 1. " CFPS                    ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:"
rgroup.long 0x64++0x3
line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL              ,Shows the number of received bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL              ,Shows the number of written bytes in the TX FIFO"
group.long 0x6C++0x3
line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x00 1. " EN_TXFIFO_EMPTY         ,Enables TX FIFO empty corresponding interrupt" "Enabled,Disabled"
bitfld.long 0x00 0. "                                      EN_RXFIFO_EMPTY                        ,Enables RX FIFO empty corresponding interrupt" "Enabled,Disabled"
hgroup.long 0x70++0x3
hide.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
in
textline "                                "
group.long 0x74++0x3
line.long 0x00 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL                ,Sets the sample per bit if nondefault frequency is used."
group.long 0x78++0x3
line.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
group.long 0x7C++0x3
line.long 0x00 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x3
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. " DIR_EN                  ,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "                                             DIR_POL                                ,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0" "0,1"
textline "                                "
bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD    ,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "                                             NONDEFAULT_FREQ                        ,Used to enable the NONDEFAULT fclk frequencies." "0,1"
textline "                                "
bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD    ,Used to enable CIR RX demodulation." "0,1"
group.long 0x84++0x3
line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register."
bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD        ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x3
line.long 0x00 "UART_MDR4,Mode definition register 4"
bitfld.long 0x00 6. " MODE9                   ,9-bit character length When '1', overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x00 3.--5. "                                             FREQ_SEL_H                             ,Upper 3 bits of" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--2. " MODE                    ,New modes [when set, overrides" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x00 7. " BROADCAST               ,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x00 6. "                                             TIMEOUT_BEHAVE                         ,Specifies how timeout is measured" "0,1"
textline "                                "
bitfld.long 0x00 5. " C8                      ,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x00 4. "                                             C4                                     ,Value for ISO 7816 C4 pin for software control" "0,1"
textline "                                "
bitfld.long 0x00 3. " C2                      ,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x00 2. "                                             MULTIDROP                              ,Enables parity Multi-drop mode [overrides" "0,1"
textline "                                "
bitfld.long 0x00 1. " RHR_OVERRUN             ," "0,1"
bitfld.long 0x00 0. "                                             ENDIAN                                 ,Endianness" "0,1"
group.long 0x90++0x3
line.long 0x00 "UART_ECR,Enhanced Control register"
bitfld.long 0x00 5. " CLEAR_TX_PE             ,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
bitfld.long 0x00 4. "                                             TX_EN                                  ,Enables/Disables the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_EN                   ,Enables/Disables the receiver" "0,1"
bitfld.long 0x00 2. "                                             TX_RST                                 ,Writing 1h = resets the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_RST                  ,Writing 1h = resets the receiver" "0,1"
bitfld.long 0x00 0. "                                             A_MULTIDROP                            ,In multi-drop mode, when written with the value '1' causes the next byte written into" "0,1"
group.long 0x94++0x3
line.long 0x00 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x00 0.--7. 1. " TIMEGUARD               ,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices"
group.long 0x98++0x3
line.long 0x00 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_L               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]"
group.long 0x9C++0x3
line.long 0x00 "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_H               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]"
group.long 0xA0++0x3
line.long 0x00 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x00 7. " DSNACK                  ,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x00 6. "                                             INACK                                  ,Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
textline "                                "
bitfld.long 0x00 0.--2. " MAX_ITERATION           ,Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x00 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ERHR                    ,Extended Receive Holding Register - allows accessing the full 9bit"
wgroup.long 0xA4++0x3
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ETHR                    ,Extended Transmit Holding Register - allows writing the full 9bit"
group.long 0xA8++0x3
line.long 0x00 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS                 ,Multidrop match address value"
group.long 0xAC++0x3
line.long 0x00 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " MASK                    ,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
group.long 0xB0++0x3
line.long 0x00 "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x00 0.--7. 1. " BROADCAST_ADDRESS       ,Broadcast address for address matching"
width 0x0B
tree.end
tree "MCU_UART0"
base ad:0x40A00000
width 23.
group.long 0x0++0x3
line.long 0x00 "UART_DLL,This register, with , stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor."
hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB               ,Stores the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the . If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the is not overwritten."
hexmask.long.byte 0x00 0.--7. 1. " RHR                     ,Receive holding register"
wgroup.long 0x0++0x3
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data."
hexmask.long.byte 0x00 0.--7. 1. " THR                     ,Transmit holding register"
group.long 0x4++0x3
line.long 0x00 "UART_DLH,This register, with , stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor."
bitfld.long 0x00 0.--5. " CLOCK_MSB               ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0."
bitfld.long 0x00 6.--7. " NOT_USED                ," "0,1,2,3"
bitfld.long 0x00 5. "                                             TX_STATUS_IT                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             RX_STOP_IT                             ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_TRIG_IT                       ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             LAST_RX_BYTE_IT                        ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, interrupt, interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit."
bitfld.long 0x00 7. " CTS_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             RTS_IT                                 ," "0,1"
textline "                                "
bitfld.long 0x00 5. " XOFF_IT                 ," "0,1"
bitfld.long 0x00 4. "                                             SLEEP_MODE                             ," "0,1"
textline "                                "
bitfld.long 0x00 3. " MODEM_STS_IT            ," "0,1"
bitfld.long 0x00 2. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x8++0x3
line.long 0x00 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but [4] enables write accesses to [5:4], the TX trigger level, which is also used in IrDA modes."
bitfld.long 0x00 7. " AUTO_CTS_EN             ,Auto-CTS enable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      AUTO_RTS_EN                            ,Auto-RTS enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT     ," "Disabled,Enabled"
bitfld.long 0x00 4. "                                      ENHANCED_EN                            ,Enhanced functions write enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL         ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2"
wgroup.long 0x8++0x3
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting restriction when [7] = 1."
bitfld.long 0x00 6.--7. " RX_FIFO_TRIG            ,Sets the trigger level for the RX FIFO: If" "8,16,56,60"
bitfld.long 0x00 4.--5. "                                            TX_FIFO_TRIG                           ,Sets the trigger level for the TX FIFO: If" "8,16,32,56"
textline "                                "
bitfld.long 0x00 3. " DMA_MODE                ,This register is considered if" "Disabled,Enabled"
bitfld.long 0x00 2. "                                      TX_FIFO_CLEAR                          ," "No_effect,Clear"
textline "                                "
bitfld.long 0x00 1. " RX_FIFO_CLEAR           ," "No_effect,Clear"
bitfld.long 0x00 0. "                                     FIFO_EN                                ," "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active."
bitfld.long 0x00 5. " TX_STATUS_IT            ,Read 0h = TX status interrupt inactive" "0,1"
bitfld.long 0x00 3. "                                             RX_OE_IT                               ,Read 0h = RX overrun interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 2. " RX_STOP_IT              ,Read 0h = Receive stop interrupt inactive" "0,1"
bitfld.long 0x00 1. "                                             THR_IT                                 ,Read 0h = THR interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 0. " RHR_IT                  ,Read 0h = RHR interrupt inactive" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OE_IT                ," "0,1"
bitfld.long 0x00 2. "                                             RX_FIFO_LAST_BYTE_IT                   ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner."
bitfld.long 0x00 6.--7. " FCR_MIRROR              ,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "                                             IT_TYPE                                ,Read 0h = Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 0. " IT_PENDING              ,Read 0h = An interrupt is pending." "0,1"
group.long 0xC++0x3
line.long 0x00 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1, the TX line is forced to 0 and remains in this state as long as [6] = 1."
bitfld.long 0x00 7. " DIV_EN                  ," "Disabled,Enabled"
bitfld.long 0x00 6. "                                      BREAK_EN                               ,Break control bit" "Normal,Forced_low"
textline "                                "
bitfld.long 0x00 5. " PARITY_TYPE2            ,Selects the forced parity format (if" "No_parity,Odd_parity"
bitfld.long 0x00 4. "                                    PARITY_TYPE1                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " PARITY_EN               ,0h = No parity" "0,1"
bitfld.long 0x00 2. "                                             NB_STOP                                ,Specifies the number of stop-bits" "1,1.5"
textline "                                "
bitfld.long 0x00 0.--1. " CHAR_LENGTH             ,Specifies the word length to be transmitted or received" "5,6,7,8"
group.long 0x10++0x3
line.long 0x00 "UART_MCR,Modem control register [3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem."
bitfld.long 0x00 6. " TCR_TLR                 ,0h = No action" "Disabled,Enabled"
bitfld.long 0x00 5. "                                      XON_EN                                 ,0h = Disable XON any function." "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 4. " LOOPBACK_EN             ,0h = Normal operating mode" "Disabled,Enabled"
bitfld.long 0x00 3. "                                      CD_STS_CH                              ,0h = In loopback, forces DCD* input high and IRQ outputs to inactive state" "High,Low"
textline "                                "
bitfld.long 0x00 2. " RI_STS_CH               ,0h = In loopback, forces RI* input high" "High,Low"
bitfld.long 0x00 1. "                                          RTS                                    ,In loopback, controls the" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0. " DTR                     ,0h = Force DTR* output to inactive (high)." "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1               ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 5. "                                             RX_STOP                                ,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
textline "                                "
bitfld.long 0x00 0. " RX_FIFO_E               ,Read 0h = At least one data character in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)."
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 6. "                                             STS_FIFO_FULL                          ,Read 0h = Status FIFO not full" "0,1"
textline "                                "
bitfld.long 0x00 5. " RX_LAST_BYTE            ,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1"
bitfld.long 0x00 4. "                                             FRAME_TOO_LONG                         ,Read 0h = No frame-too-long error in frame" "0,1"
textline "                                "
bitfld.long 0x00 3. " ABORT                   ,Read 0h = No abort pattern error in frame" "0,1"
bitfld.long 0x00 2. "                                             CRC                                    ,Read 0h = No CRC error in frame" "0,1"
textline "                                "
bitfld.long 0x00 1. " STS_FIFO_E              ,Read 0h = Status FIFO not empty" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. " RX_FIFO_STS             ,Read 0h = Normal operation" "0,1"
bitfld.long 0x00 6. "                                             TX_SR_E                                ,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_FIFO_E               ,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 4. "                                             RX_BI                                  ,Read 0h = No break condition" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_FE                   ,Read 0h = No framing error in data RX FIFO" "0,1"
bitfld.long 0x00 2. "                                             RX_PE                                  ,Read 0h = No parity error in data from RX FIFO" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_OE                   ,Read 0h = No overrun error" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
group.long 0x14++0x3
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2               ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
rgroup.long 0x18++0x3
line.long 0x00 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state."
bitfld.long 0x00 7. " NCD_STS                 ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 6. "                                             NRI_STS                                ,This bit is the complement of the RI* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 5. " NDSR_STS                ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 4. "                                             NCTS_STS                               ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 3. " DCD_STS                 ,Indicates that DCD* input (or" "0,1"
bitfld.long 0x00 2. "                                             RI_STS                                 ,Indicates that RI* input (or" "0,1"
textline "                                "
bitfld.long 0x00 1. " DSR_STS                 ," "0,1"
bitfld.long 0x00 0. "                                             CTS_STS                                ," "0,1"
group.long 0x18++0x3
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that [3:0] > [7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level ([7:4] or [7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START      ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.long 0x00 0.--3. "                                            RX_FIFO_TRIG_HALT                      ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.long 0x18++0x3
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1              ,Stores the 8-bit XOFF1 character used in UART modes"
group.long 0x1C++0x3
line.long 0x00 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD                ,Scratchpad register"
group.long 0x1C++0x3
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA        ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                                            TX_FIFO_TRIG_DMA                       ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x3
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2              ,Stores the 8-bit XOFF2 character used in UART modes."
group.long 0x20++0x3
line.long 0x00 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (, , and ). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags."
bitfld.long 0x00 7. " FRAME_END_MODE          ,IrDA mode only" "Frame-length,EOT"
bitfld.long 0x00 6. "                                  SIP_MODE                               ,MIR/FIR modes only" "Manual_SIP,Automatic_SIP"
textline "                                "
bitfld.long 0x00 5. " SCT                     ,Store and control the transmission." "THR,ACREG[2]"
bitfld.long 0x00 4. "                                      SET_TXIR                               ,Used to configure the infrared transceiver" "TXIR_low,IRTX_high"
textline "                                "
bitfld.long 0x00 3. " IR_SLEEP                ,0h = IrDA/CIR sleep mode disabled" "Disabled,Enabled"
bitfld.long 0x00 0.--2. "                                      MODE_SELECT                            ,0h = UART 16x mode" "UART_16x,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled"
group.long 0x24++0x3
line.long 0x00 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in [2:0]. Note: The [6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin."
bitfld.long 0x00 7. " SET_TXIR_ALT            ,Provide alternate function for" "Normal,Alternate"
bitfld.long 0x00 6. "                                     IRRXINVERT                             ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1"
textline "                                "
bitfld.long 0x00 4.--5. " CIR_PULSE_MODE          ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3"
bitfld.long 0x00 3. "                                             UART_PULSE                             ,UART mode only. Allows pulse shaping in UART mode." "0,1"
textline "                                "
bitfld.long 0x00 1.--2. " STS_FIFO_TRIG           ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3"
bitfld.long 0x00 0. "                                             IRTX_UNDERRUN                          ,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1"
rgroup.long 0x28++0x3
line.long 0x00 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer ( and must be read first)."
bitfld.long 0x00 4. " OE_ERROR                ,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "No_error,Error"
bitfld.long 0x00 3. "                                      FRAME_TOO_LONG_ERROR                   ,Read 1h = Frame-length too long error in frame at top of RX FIFO" "No_error,Error"
textline "                                "
bitfld.long 0x00 2. " ABORT_DETECT            ,Read 1h = Abort pattern detected in frame at top of RX FIFO" "No_error,Error"
bitfld.long 0x00 1. "                                      CRC_ERROR                              ,Read 1h = CRC error in frame at top of RX FIFO" "No_error,Error"
wgroup.long 0x28++0x3
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
hexmask.long.byte 0x00 0.--7. 1. " TXFLL                   ,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00."
hexmask.long.byte 0x00 0.--7. 1. " RESUME                  ,Dummy read to restart the TX or RX"
wgroup.long 0x2C++0x3
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
bitfld.long 0x00 0.--4. " TXFLH                   ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x30++0x3
line.long 0x00 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
hexmask.long.byte 0x00 0.--7. 1. " RXFLL                   ,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
hexmask.long.byte 0x00 0.--7. 1. " SFREGL                  ,LSB part of the frame length"
wgroup.long 0x34++0x3
line.long 0x00 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
bitfld.long 0x00 0.--3. " RXFLH                   ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x3
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
bitfld.long 0x00 0.--3. " SFREGH                  ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte)."
bitfld.long 0x00 7. " STS_FIFO_RESET          ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset"
bitfld.long 0x00 6. "                                      XBOF_TYPE                              ,SIR xBOF select" "0xFF,0xC0"
rgroup.long 0x38++0x3
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition. Note: When the UART is in autobauding mode, this register, instead of the , , and registers, is used to set up transmission according to the characteristics of the previous reception. To reset the autobauding hardware (to start a new AT detection), set [2:0] to 111 (reset value), then set [2:1] to 010 (UART in autobaud mode). To set the UART to standard mode (no autobaud), set [2:1] to 000."
bitfld.long 0x00 6.--7. " PARITY_TYPE             ,Read 0h = No parity identified" "No_parity,Parity_space,Even,Odd"
bitfld.long 0x00 5. "                                  BIT_BY_CHAR                            ,Read 0h = 7-bit character identified" "7,8"
textline "                                "
bitfld.long 0x00 0.--4. " SPEED                   ,Used to report the speed identified" "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
group.long 0x3C++0x3
line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only."
bitfld.long 0x00 7. " PULSE_TYPE              ,SIR pulse width select" "3/16_of_baud-rate,1.6_us"
bitfld.long 0x00 6. "                             SD_MOD                                 ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "High,Low"
textline "                                "
bitfld.long 0x00 5. " DIS_IR_RX               ,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "No,Yes"
bitfld.long 0x00 4. "                                           DIS_TX_UNDERRUN                        ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "No,Yes"
textline "                                "
bitfld.long 0x00 3. " SEND_SIP                ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "No_action,Sent"
bitfld.long 0x00 2. "                                     SCTX_EN                                ,Store and controlled TX start. When" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " ABORT_EN                ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "Disabled,Enabled"
bitfld.long 0x00 0. "                                      EOT_EN                                 ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the [1] bit must be checked. To clear the wake-up interrupt, bit [4] must be reset to 0."
bitfld.long 0x00 7. " RX_TRIG_GRANU1          ,0h = Disables the granularity of 1 for trigger RX level" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      TX_TRIG_GRANU1                         ,0h = Disables the granularity of 1 for trigger TX level" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " DSR_IT                  ,0h = Disables DSR* interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "                                      RX_CTS_DSR_WAKE_UP_ENABLE              ,0h = Disables the wake-up interrupt and clears SSR[1]" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 3. " TX_EMPTY_CTL_IT         ,0h = Normal mode for THR interrupt" "No_interrupt,Interrupt"
bitfld.long 0x00 1.--2. "                                  DMA_MODE_2                             ,Used to specify the DMA mode valid if the" "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX"
textline "                                "
bitfld.long 0x00 0. " DMA_MODE_CTL            ,0h = The DMA_MODE is set with" "UART_FCR[3],UART_SCR[2:1]"
group.long 0x44++0x3
line.long 0x00 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0."
bitfld.long 0x00 2. " DMA_COUNTER_RST         ,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "No_reset,Reset"
bitfld.long 0x00 1. "                                      RX_CTS_DSR_WAKE_UP_STS                 ,Read 0h = No falling edge event on RX, CTS*, and DSR*" "Not_occurred,Occurred"
textline "                                "
bitfld.long 0x00 0. " TX_FIFO_FULL            ,Read 0h = TX FIFO is not full." "Not_full,Full"
group.long 0x48++0x3
line.long 0x00 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the [5] to 1. Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO."
hexmask.long.byte 0x00 0.--7. 1. " EBLR                    ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification."
rgroup.long 0x50++0x3
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned."
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "                                             FUNC                                   ,Function revision number of module"
textline "                                "
bitfld.long 0x00 11.--15. " RTL                     ,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "                                            MAJOR                                  ,Major revision number of the module" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 6.--7. " CUSTOM                  ,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "                                             MINOR                                  ,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x3
line.long 0x00 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset."
bitfld.long 0x00 3.--4. " IDLEMODE                ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "Force_idle,No-idle,Smart_idle,Reserved"
bitfld.long 0x00 2. "                                    ENAWAKEUP                              ,Wake-up feature control" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " SOFTRESET               ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "No_reset,Reset"
bitfld.long 0x00 0. "                                      AUTOIDLE                               ,Internal OCP clock gating strategy" "Running,Gated"
rgroup.long 0x58++0x3
line.long 0x00 "UART_SYSS,System status register"
bitfld.long 0x00 0. " RESETDONE               ,Internal reset monitoring" "Not_completed,Completed"
group.long 0x5C++0x3
line.long 0x00 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt."
bitfld.long 0x00 7. " EVENT_7_TX_WAKEUP_EN    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 6. "                                             EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT   ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 4. "                                             EVENT_4_RX_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0h = Event is not allowed to wake up the system" "0,1"
bitfld.long 0x00 2. "                                             EVENT_2_RI_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 0. "                                             EVENT_0_CTS_ACTIVITY                   ,0h = Event is not allowed to wake up the system." "0,1"
group.long 0x60++0x3
line.long 0x00 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple."
hexmask.long.byte 0x00 0.--7. 1. " CFPS                    ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:"
rgroup.long 0x64++0x3
line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL              ,Shows the number of received bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL              ,Shows the number of written bytes in the TX FIFO"
group.long 0x6C++0x3
line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x00 1. " EN_TXFIFO_EMPTY         ,Enables TX FIFO empty corresponding interrupt" "Enabled,Disabled"
bitfld.long 0x00 0. "                                      EN_RXFIFO_EMPTY                        ,Enables RX FIFO empty corresponding interrupt" "Enabled,Disabled"
hgroup.long 0x70++0x3
hide.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
in
textline "                                "
group.long 0x74++0x3
line.long 0x00 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL                ,Sets the sample per bit if nondefault frequency is used."
group.long 0x78++0x3
line.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
group.long 0x7C++0x3
line.long 0x00 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x3
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. " DIR_EN                  ,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "                                             DIR_POL                                ,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0" "0,1"
textline "                                "
bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD    ,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "                                             NONDEFAULT_FREQ                        ,Used to enable the NONDEFAULT fclk frequencies." "0,1"
textline "                                "
bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD    ,Used to enable CIR RX demodulation." "0,1"
group.long 0x84++0x3
line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register."
bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD        ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x3
line.long 0x00 "UART_MDR4,Mode definition register 4"
bitfld.long 0x00 6. " MODE9                   ,9-bit character length When '1', overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x00 3.--5. "                                             FREQ_SEL_H                             ,Upper 3 bits of" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--2. " MODE                    ,New modes [when set, overrides" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x00 7. " BROADCAST               ,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x00 6. "                                             TIMEOUT_BEHAVE                         ,Specifies how timeout is measured" "0,1"
textline "                                "
bitfld.long 0x00 5. " C8                      ,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x00 4. "                                             C4                                     ,Value for ISO 7816 C4 pin for software control" "0,1"
textline "                                "
bitfld.long 0x00 3. " C2                      ,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x00 2. "                                             MULTIDROP                              ,Enables parity Multi-drop mode [overrides" "0,1"
textline "                                "
bitfld.long 0x00 1. " RHR_OVERRUN             ," "0,1"
bitfld.long 0x00 0. "                                             ENDIAN                                 ,Endianness" "0,1"
group.long 0x90++0x3
line.long 0x00 "UART_ECR,Enhanced Control register"
bitfld.long 0x00 5. " CLEAR_TX_PE             ,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
bitfld.long 0x00 4. "                                             TX_EN                                  ,Enables/Disables the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_EN                   ,Enables/Disables the receiver" "0,1"
bitfld.long 0x00 2. "                                             TX_RST                                 ,Writing 1h = resets the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_RST                  ,Writing 1h = resets the receiver" "0,1"
bitfld.long 0x00 0. "                                             A_MULTIDROP                            ,In multi-drop mode, when written with the value '1' causes the next byte written into" "0,1"
group.long 0x94++0x3
line.long 0x00 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x00 0.--7. 1. " TIMEGUARD               ,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices"
group.long 0x98++0x3
line.long 0x00 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_L               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]"
group.long 0x9C++0x3
line.long 0x00 "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_H               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]"
group.long 0xA0++0x3
line.long 0x00 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x00 7. " DSNACK                  ,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x00 6. "                                             INACK                                  ,Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
textline "                                "
bitfld.long 0x00 0.--2. " MAX_ITERATION           ,Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x00 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ERHR                    ,Extended Receive Holding Register - allows accessing the full 9bit"
wgroup.long 0xA4++0x3
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ETHR                    ,Extended Transmit Holding Register - allows writing the full 9bit"
group.long 0xA8++0x3
line.long 0x00 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS                 ,Multidrop match address value"
group.long 0xAC++0x3
line.long 0x00 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " MASK                    ,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
group.long 0xB0++0x3
line.long 0x00 "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x00 0.--7. 1. " BROADCAST_ADDRESS       ,Broadcast address for address matching"
width 0x0B
tree.end
tree "WKUP_UART0"
base ad:0x42300000
width 23.
group.long 0x0++0x3
line.long 0x00 "UART_DLL,This register, with , stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor."
hexmask.long.byte 0x00 0.--7. 1. " CLOCK_LSB               ,Stores the 8-bit LSB divisor value"
rgroup.long 0x0++0x3
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the . If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the is not overwritten."
hexmask.long.byte 0x00 0.--7. 1. " RHR                     ,Receive holding register"
wgroup.long 0x0++0x3
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data."
hexmask.long.byte 0x00 0.--7. 1. " THR                     ,Transmit holding register"
group.long 0x4++0x3
line.long 0x00 "UART_DLH,This register, with , stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor."
bitfld.long 0x00 0.--5. " CLOCK_MSB               ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0."
bitfld.long 0x00 6.--7. " NOT_USED                ," "0,1,2,3"
bitfld.long 0x00 5. "                                             TX_STATUS_IT                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             RX_STOP_IT                             ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_TRIG_IT                       ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OVERRUN_IT           ," "0,1"
bitfld.long 0x00 2. "                                             LAST_RX_BYTE_IT                        ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x4++0x3
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, interrupt, interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit."
bitfld.long 0x00 7. " CTS_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             RTS_IT                                 ," "0,1"
textline "                                "
bitfld.long 0x00 5. " XOFF_IT                 ," "0,1"
bitfld.long 0x00 4. "                                             SLEEP_MODE                             ," "0,1"
textline "                                "
bitfld.long 0x00 3. " MODEM_STS_IT            ," "0,1"
bitfld.long 0x00 2. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
group.long 0x8++0x3
line.long 0x00 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but [4] enables write accesses to [5:4], the TX trigger level, which is also used in IrDA modes."
bitfld.long 0x00 7. " AUTO_CTS_EN             ,Auto-CTS enable bit" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      AUTO_RTS_EN                            ,Auto-RTS enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " SPECIAL_CHAR_DETECT     ," "Disabled,Enabled"
bitfld.long 0x00 4. "                                      ENHANCED_EN                            ,Enhanced functions write enable bit" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0.--3. " SW_FLOW_CONTROL         ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" "No_transmit/No_receive,No_transmit/Rx_comp._XON2;XOFF2,No_transmit/Rx_comp._XON1;XOFF1,No_transmit/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON2;XOFF2/No_receive,Tx_XON2;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON2;XOFF2/Rx_comp._XON1;XOFF1,Tx_XON2;XOFF2/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XOFF1/No_receive,Tx_XON1;XOFF1/Rx_comp._XON2;XOFF2,Tx_XON1;XOFF1/Rx_comp._XON1;XOFF1,Tx_XON1;XOFF1/Rx_comp._XON1;XON2:XOFF1;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/No_receive,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON2;XOFF2,Tx_XON1;XON2:XOFF1;XOFF2/Rx_comp._XON1;XOFF1,Tx/Rx_comp._XON1;XON2:XOFF1;XOFF2"
wgroup.long 0x8++0x3
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting restriction when [7] = 1."
bitfld.long 0x00 6.--7. " RX_FIFO_TRIG            ,Sets the trigger level for the RX FIFO: If" "8,16,56,60"
bitfld.long 0x00 4.--5. "                                            TX_FIFO_TRIG                           ,Sets the trigger level for the TX FIFO: If" "8,16,32,56"
textline "                                "
bitfld.long 0x00 3. " DMA_MODE                ,This register is considered if" "Disabled,Enabled"
bitfld.long 0x00 2. "                                      TX_FIFO_CLEAR                          ," "No_effect,Clear"
textline "                                "
bitfld.long 0x00 1. " RX_FIFO_CLEAR           ," "No_effect,Clear"
bitfld.long 0x00 0. "                                     FIFO_EN                                ," "Disabled,Enabled"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active."
bitfld.long 0x00 5. " TX_STATUS_IT            ,Read 0h = TX status interrupt inactive" "0,1"
bitfld.long 0x00 3. "                                             RX_OE_IT                               ,Read 0h = RX overrun interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 2. " RX_STOP_IT              ,Read 0h = Receive stop interrupt inactive" "0,1"
bitfld.long 0x00 1. "                                             THR_IT                                 ,Read 0h = THR interrupt inactive" "0,1"
textline "                                "
bitfld.long 0x00 0. " RHR_IT                  ,Read 0h = RHR interrupt inactive" "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active."
bitfld.long 0x00 7. " EOF_IT                  ," "0,1"
bitfld.long 0x00 6. "                                             LINE_STS_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_STATUS_IT            ," "0,1"
bitfld.long 0x00 4. "                                             STS_FIFO_IT                            ," "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_OE_IT                ," "0,1"
bitfld.long 0x00 2. "                                             RX_FIFO_LAST_BYTE_IT                   ," "0,1"
textline "                                "
bitfld.long 0x00 1. " THR_IT                  ," "0,1"
bitfld.long 0x00 0. "                                             RHR_IT                                 ," "0,1"
rgroup.long 0x8++0x3
line.long 0x00 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner."
bitfld.long 0x00 6.--7. " FCR_MIRROR              ,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "                                             IT_TYPE                                ,Read 0h = Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                "
bitfld.long 0x00 0. " IT_PENDING              ,Read 0h = An interrupt is pending." "0,1"
group.long 0xC++0x3
line.long 0x00 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1, the TX line is forced to 0 and remains in this state as long as [6] = 1."
bitfld.long 0x00 7. " DIV_EN                  ," "Disabled,Enabled"
bitfld.long 0x00 6. "                                      BREAK_EN                               ,Break control bit" "Normal,Forced_low"
textline "                                "
bitfld.long 0x00 5. " PARITY_TYPE2            ,Selects the forced parity format (if" "No_parity,Odd_parity"
bitfld.long 0x00 4. "                                    PARITY_TYPE1                           ," "0,1"
textline "                                "
bitfld.long 0x00 3. " PARITY_EN               ,0h = No parity" "0,1"
bitfld.long 0x00 2. "                                             NB_STOP                                ,Specifies the number of stop-bits" "1,1.5"
textline "                                "
bitfld.long 0x00 0.--1. " CHAR_LENGTH             ,Specifies the word length to be transmitted or received" "5,6,7,8"
group.long 0x10++0x3
line.long 0x00 "UART_MCR,Modem control register [3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem."
bitfld.long 0x00 6. " TCR_TLR                 ,0h = No action" "Disabled,Enabled"
bitfld.long 0x00 5. "                                      XON_EN                                 ,0h = Disable XON any function." "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 4. " LOOPBACK_EN             ,0h = Normal operating mode" "Disabled,Enabled"
bitfld.long 0x00 3. "                                      CD_STS_CH                              ,0h = In loopback, forces DCD* input high and IRQ outputs to inactive state" "High,Low"
textline "                                "
bitfld.long 0x00 2. " RI_STS_CH               ,0h = In loopback, forces RI* input high" "High,Low"
bitfld.long 0x00 1. "                                          RTS                                    ,In loopback, controls the" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 0. " DTR                     ,0h = Force DTR* output to inactive (high)." "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD1               ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 5. "                                             RX_STOP                                ,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
textline "                                "
bitfld.long 0x00 0. " RX_FIFO_E               ,Read 0h = At least one data character in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)."
bitfld.long 0x00 7. " THR_EMPTY               ,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 6. "                                             STS_FIFO_FULL                          ,Read 0h = Status FIFO not full" "0,1"
textline "                                "
bitfld.long 0x00 5. " RX_LAST_BYTE            ,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1"
bitfld.long 0x00 4. "                                             FRAME_TOO_LONG                         ,Read 0h = No frame-too-long error in frame" "0,1"
textline "                                "
bitfld.long 0x00 3. " ABORT                   ,Read 0h = No abort pattern error in frame" "0,1"
bitfld.long 0x00 2. "                                             CRC                                    ,Read 0h = No CRC error in frame" "0,1"
textline "                                "
bitfld.long 0x00 1. " STS_FIFO_E              ,Read 0h = Status FIFO not empty" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. " RX_FIFO_STS             ,Read 0h = Normal operation" "0,1"
bitfld.long 0x00 6. "                                             TX_SR_E                                ,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1"
textline "                                "
bitfld.long 0x00 5. " TX_FIFO_E               ,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1"
bitfld.long 0x00 4. "                                             RX_BI                                  ,Read 0h = No break condition" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_FE                   ,Read 0h = No framing error in data RX FIFO" "0,1"
bitfld.long 0x00 2. "                                             RX_PE                                  ,Read 0h = No parity error in data from RX FIFO" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_OE                   ,Read 0h = No overrun error" "0,1"
bitfld.long 0x00 0. "                                             RX_FIFO_E                              ,Read 0h = No data in the RX FIFO" "0,1"
group.long 0x14++0x3
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. " XON_WORD2               ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
rgroup.long 0x18++0x3
line.long 0x00 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state."
bitfld.long 0x00 7. " NCD_STS                 ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 6. "                                             NRI_STS                                ,This bit is the complement of the RI* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 5. " NDSR_STS                ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent to" "0,1"
bitfld.long 0x00 4. "                                             NCTS_STS                               ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent to" "0,1"
textline "                                "
bitfld.long 0x00 3. " DCD_STS                 ,Indicates that DCD* input (or" "0,1"
bitfld.long 0x00 2. "                                             RI_STS                                 ,Indicates that RI* input (or" "0,1"
textline "                                "
bitfld.long 0x00 1. " DSR_STS                 ," "0,1"
bitfld.long 0x00 0. "                                             CTS_STS                                ," "0,1"
group.long 0x18++0x3
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that [3:0] > [7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level ([7:4] or [7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_START      ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.long 0x00 0.--3. "                                            RX_FIFO_TRIG_HALT                      ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.long 0x18++0x3
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD1              ,Stores the 8-bit XOFF1 character used in UART modes"
group.long 0x1C++0x3
line.long 0x00 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data."
hexmask.long.byte 0x00 0.--7. 1. " SPR_WORD                ,Scratchpad register"
group.long 0x1C++0x3
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation."
bitfld.long 0x00 4.--7. " RX_FIFO_TRIG_DMA        ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                                            TX_FIFO_TRIG_DMA                       ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x3
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. " XOFF_WORD2              ,Stores the 8-bit XOFF2 character used in UART modes."
group.long 0x20++0x3
line.long 0x00 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (, , and ). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags."
bitfld.long 0x00 7. " FRAME_END_MODE          ,IrDA mode only" "Frame-length,EOT"
bitfld.long 0x00 6. "                                  SIP_MODE                               ,MIR/FIR modes only" "Manual_SIP,Automatic_SIP"
textline "                                "
bitfld.long 0x00 5. " SCT                     ,Store and control the transmission." "THR,ACREG[2]"
bitfld.long 0x00 4. "                                      SET_TXIR                               ,Used to configure the infrared transceiver" "TXIR_low,IRTX_high"
textline "                                "
bitfld.long 0x00 3. " IR_SLEEP                ,0h = IrDA/CIR sleep mode disabled" "Disabled,Enabled"
bitfld.long 0x00 0.--2. "                                      MODE_SELECT                            ,0h = UART 16x mode" "UART_16x,Reserved,UART_16x_auto-baud,UART_13x,Reserved,Reserved,Reserved,Disabled"
group.long 0x24++0x3
line.long 0x00 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in [2:0]. Note: The [6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin."
bitfld.long 0x00 7. " SET_TXIR_ALT            ,Provide alternate function for" "Normal,Alternate"
bitfld.long 0x00 6. "                                     IRRXINVERT                             ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1"
textline "                                "
bitfld.long 0x00 4.--5. " CIR_PULSE_MODE          ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3"
bitfld.long 0x00 3. "                                             UART_PULSE                             ,UART mode only. Allows pulse shaping in UART mode." "0,1"
textline "                                "
bitfld.long 0x00 1.--2. " STS_FIFO_TRIG           ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3"
bitfld.long 0x00 0. "                                             IRTX_UNDERRUN                          ,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1"
rgroup.long 0x28++0x3
line.long 0x00 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer ( and must be read first)."
bitfld.long 0x00 4. " OE_ERROR                ,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "No_error,Error"
bitfld.long 0x00 3. "                                      FRAME_TOO_LONG_ERROR                   ,Read 1h = Frame-length too long error in frame at top of RX FIFO" "No_error,Error"
textline "                                "
bitfld.long 0x00 2. " ABORT_DETECT            ,Read 1h = Abort pattern detected in frame at top of RX FIFO" "No_error,Error"
bitfld.long 0x00 1. "                                      CRC_ERROR                              ,Read 1h = CRC error in frame at top of RX FIFO" "No_error,Error"
wgroup.long 0x28++0x3
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
hexmask.long.byte 0x00 0.--7. 1. " TXFLL                   ,LSB register used to specify the frame length"
rgroup.long 0x2C++0x3
line.long 0x00 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00."
hexmask.long.byte 0x00 0.--7. 1. " RESUME                  ,Dummy read to restart the TX or RX"
wgroup.long 0x2C++0x3
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is used."
bitfld.long 0x00 0.--4. " TXFLH                   ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x30++0x3
line.long 0x00 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
hexmask.long.byte 0x00 0.--7. 1. " RXFLL                   ,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x3
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
hexmask.long.byte 0x00 0.--7. 1. " SFREGL                  ,LSB part of the frame length"
wgroup.long 0x34++0x3
line.long 0x00 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes, program the and to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag)."
bitfld.long 0x00 0.--3. " RXFLH                   ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x3
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and the MSBs are read from . Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the register."
bitfld.long 0x00 0.--3. " SFREGH                  ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x3
line.long 0x00 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte)."
bitfld.long 0x00 7. " STS_FIFO_RESET          ,Status FIFO reset. This bit is self-clearing." "No_reset,Reset"
bitfld.long 0x00 6. "                                      XBOF_TYPE                              ,SIR xBOF select" "0xFF,0xC0"
rgroup.long 0x38++0x3
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition. Note: When the UART is in autobauding mode, this register, instead of the , , and registers, is used to set up transmission according to the characteristics of the previous reception. To reset the autobauding hardware (to start a new AT detection), set [2:0] to 111 (reset value), then set [2:1] to 010 (UART in autobaud mode). To set the UART to standard mode (no autobaud), set [2:1] to 000."
bitfld.long 0x00 6.--7. " PARITY_TYPE             ,Read 0h = No parity identified" "No_parity,Parity_space,Even,Odd"
bitfld.long 0x00 5. "                                  BIT_BY_CHAR                            ,Read 0h = 7-bit character identified" "7,8"
textline "                                "
bitfld.long 0x00 0.--4. " SPEED                   ,Used to report the speed identified" "No_speed,115_200,57_600,38_400,28_800,19_200,14_400,9_600,4_800,2_400,1_200,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
group.long 0x3C++0x3
line.long 0x00 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only."
bitfld.long 0x00 7. " PULSE_TYPE              ,SIR pulse width select" "3/16_of_baud-rate,1.6_us"
bitfld.long 0x00 6. "                             SD_MOD                                 ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "High,Low"
textline "                                "
bitfld.long 0x00 5. " DIS_IR_RX               ,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "No,Yes"
bitfld.long 0x00 4. "                                           DIS_TX_UNDERRUN                        ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "No,Yes"
textline "                                "
bitfld.long 0x00 3. " SEND_SIP                ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "No_action,Sent"
bitfld.long 0x00 2. "                                     SCTX_EN                                ,Store and controlled TX start. When" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " ABORT_EN                ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "Disabled,Enabled"
bitfld.long 0x00 0. "                                      EOT_EN                                 ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "Disabled,Enabled"
group.long 0x40++0x3
line.long 0x00 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the [1] bit must be checked. To clear the wake-up interrupt, bit [4] must be reset to 0."
bitfld.long 0x00 7. " RX_TRIG_GRANU1          ,0h = Disables the granularity of 1 for trigger RX level" "Disabled,Enabled"
bitfld.long 0x00 6. "                                      TX_TRIG_GRANU1                         ,0h = Disables the granularity of 1 for trigger TX level" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 5. " DSR_IT                  ,0h = Disables DSR* interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "                                      RX_CTS_DSR_WAKE_UP_ENABLE              ,0h = Disables the wake-up interrupt and clears SSR[1]" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 3. " TX_EMPTY_CTL_IT         ,0h = Normal mode for THR interrupt" "No_interrupt,Interrupt"
bitfld.long 0x00 1.--2. "                                  DMA_MODE_2                             ,Used to specify the DMA mode valid if the" "No_DMA,UART_nDMA_REQ[0/1]_in_TX/RX;,UART_nDMA_REQ[0]_in_RX,UART_nDMA_REQ[0]_in_TX"
textline "                                "
bitfld.long 0x00 0. " DMA_MODE_CTL            ,0h = The DMA_MODE is set with" "UART_FCR[3],UART_SCR[2:1]"
group.long 0x44++0x3
line.long 0x00 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0."
bitfld.long 0x00 2. " DMA_COUNTER_RST         ,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "No_reset,Reset"
bitfld.long 0x00 1. "                                      RX_CTS_DSR_WAKE_UP_STS                 ,Read 0h = No falling edge event on RX, CTS*, and DSR*" "Not_occurred,Occurred"
textline "                                "
bitfld.long 0x00 0. " TX_FIFO_FULL            ,Read 0h = TX FIFO is not full." "Not_full,Full"
group.long 0x48++0x3
line.long 0x00 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the [5] to 1. Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO."
hexmask.long.byte 0x00 0.--7. 1. " EBLR                    ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification."
rgroup.long 0x50++0x3
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned."
bitfld.long 0x00 30.--31. " SCHEME                  ,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "                                             FUNC                                   ,Function revision number of module"
textline "                                "
bitfld.long 0x00 11.--15. " RTL                     ,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "                                            MAJOR                                  ,Major revision number of the module" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 6.--7. " CUSTOM                  ,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "                                             MINOR                                  ,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x3
line.long 0x00 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset."
bitfld.long 0x00 3.--4. " IDLEMODE                ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "Force_idle,No-idle,Smart_idle,Reserved"
bitfld.long 0x00 2. "                                    ENAWAKEUP                              ,Wake-up feature control" "Disabled,Enabled"
textline "                                "
bitfld.long 0x00 1. " SOFTRESET               ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "No_reset,Reset"
bitfld.long 0x00 0. "                                      AUTOIDLE                               ,Internal OCP clock gating strategy" "Running,Gated"
rgroup.long 0x58++0x3
line.long 0x00 "UART_SYSS,System status register"
bitfld.long 0x00 0. " RESETDONE               ,Internal reset monitoring" "Not_completed,Completed"
group.long 0x5C++0x3
line.long 0x00 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt."
bitfld.long 0x00 7. " EVENT_7_TX_WAKEUP_EN    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 6. "                                             EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 5. " EVENT_5_RHR_INTERRUPT   ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 4. "                                             EVENT_4_RX_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 3. " EVENT_3_DCD_CD_ACTIVITY ,0h = Event is not allowed to wake up the system" "0,1"
bitfld.long 0x00 2. "                                             EVENT_2_RI_ACTIVITY                    ,0h = Event is not allowed to wake up the system." "0,1"
textline "                                "
bitfld.long 0x00 1. " EVENT_1_DSR_ACTIVITY    ,0h = Event is not allowed to wake up the system." "0,1"
bitfld.long 0x00 0. "                                             EVENT_0_CTS_ACTIVITY                   ,0h = Event is not allowed to wake up the system." "0,1"
group.long 0x60++0x3
line.long 0x00 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple."
hexmask.long.byte 0x00 0.--7. 1. " CFPS                    ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:"
rgroup.long 0x64++0x3
line.long 0x00 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " RXFIFO_LVL              ,Shows the number of received bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x00 0.--7. 1. " TXFIFO_LVL              ,Shows the number of written bytes in the TX FIFO"
group.long 0x6C++0x3
line.long 0x00 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x00 1. " EN_TXFIFO_EMPTY         ,Enables TX FIFO empty corresponding interrupt" "Enabled,Disabled"
bitfld.long 0x00 0. "                                      EN_RXFIFO_EMPTY                        ,Enables RX FIFO empty corresponding interrupt" "Enabled,Disabled"
hgroup.long 0x70++0x3
hide.long 0x00 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
in
textline "                                "
group.long 0x74++0x3
line.long 0x00 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x00 0.--7. 1. " FREQ_SEL                ,Sets the sample per bit if nondefault frequency is used."
group.long 0x78++0x3
line.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
group.long 0x7C++0x3
line.long 0x00 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x3
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. " DIR_EN                  ,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "                                             DIR_POL                                ,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0, RX: RTS=1. 1h = TX: RTS=1, RX: RTS=0" "0,1"
textline "                                "
bitfld.long 0x00 2. " SET_DMA_TX_THRESHOLD    ,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "                                             NONDEFAULT_FREQ                        ,Used to enable the NONDEFAULT fclk frequencies." "0,1"
textline "                                "
bitfld.long 0x00 0. " DISABLE_CIR_RX_DEMOD    ,Used to enable CIR RX demodulation." "0,1"
group.long 0x84++0x3
line.long 0x00 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register."
bitfld.long 0x00 0.--5. " TX_DMA_THRESHOLD        ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x3
line.long 0x00 "UART_MDR4,Mode definition register 4"
bitfld.long 0x00 6. " MODE9                   ,9-bit character length When '1', overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x00 3.--5. "                                             FREQ_SEL_H                             ,Upper 3 bits of" "0,1,2,3,4,5,6,7"
textline "                                "
bitfld.long 0x00 0.--2. " MODE                    ,New modes [when set, overrides" "0,1,2,3,4,5,6,7"
group.long 0x8C++0x3
line.long 0x00 "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x00 7. " BROADCAST               ,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x00 6. "                                             TIMEOUT_BEHAVE                         ,Specifies how timeout is measured" "0,1"
textline "                                "
bitfld.long 0x00 5. " C8                      ,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x00 4. "                                             C4                                     ,Value for ISO 7816 C4 pin for software control" "0,1"
textline "                                "
bitfld.long 0x00 3. " C2                      ,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x00 2. "                                             MULTIDROP                              ,Enables parity Multi-drop mode [overrides" "0,1"
textline "                                "
bitfld.long 0x00 1. " RHR_OVERRUN             ," "0,1"
bitfld.long 0x00 0. "                                             ENDIAN                                 ,Endianness" "0,1"
group.long 0x90++0x3
line.long 0x00 "UART_ECR,Enhanced Control register"
bitfld.long 0x00 5. " CLEAR_TX_PE             ,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
bitfld.long 0x00 4. "                                             TX_EN                                  ,Enables/Disables the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 3. " RX_EN                   ,Enables/Disables the receiver" "0,1"
bitfld.long 0x00 2. "                                             TX_RST                                 ,Writing 1h = resets the transmitter" "0,1"
textline "                                "
bitfld.long 0x00 1. " RX_RST                  ,Writing 1h = resets the receiver" "0,1"
bitfld.long 0x00 0. "                                             A_MULTIDROP                            ,In multi-drop mode, when written with the value '1' causes the next byte written into" "0,1"
group.long 0x94++0x3
line.long 0x00 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x00 0.--7. 1. " TIMEGUARD               ,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices"
group.long 0x98++0x3
line.long 0x00 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_L               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]"
group.long 0x9C++0x3
line.long 0x00 "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT_H               ,Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]"
group.long 0xA0++0x3
line.long 0x00 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x00 7. " DSNACK                  ,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x00 6. "                                             INACK                                  ,Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
textline "                                "
bitfld.long 0x00 0.--2. " MAX_ITERATION           ,Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
rgroup.long 0xA4++0x3
line.long 0x00 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ERHR                    ,Extended Receive Holding Register - allows accessing the full 9bit"
wgroup.long 0xA4++0x3
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. " ETHR                    ,Extended Transmit Holding Register - allows writing the full 9bit"
group.long 0xA8++0x3
line.long 0x00 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x00 0.--7. 1. " ADDRESS                 ,Multidrop match address value"
group.long 0xAC++0x3
line.long 0x00 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " MASK                    ,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
group.long 0xB0++0x3
line.long 0x00 "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x00 0.--7. 1. " BROADCAST_ADDRESS       ,Broadcast address for address matching"
width 0x0B
tree.end
tree.end
tree "USB3SS_PHY"
tree "USB3SS_PHY2"
tree "USB3SS0_PHY2"
base ad:0x4100000
width 29.
group.long 0x0++0x3
line.long 0x00 "USB2PHY_TERMINATION_CONTROL,Contains bits related to control of terminations in USB2PHY"
bitfld.long 0x00 24.--27. " MEM_FS_CODE_SEL      ,FS Code selection control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "  MEM_RTMEM_USE_RTERM_RMX_REG ,Override termination resistor trim code with mem_RTERM_RMX from this register" "0,1"
textline "                                      "
bitfld.long 0x00 15.--20. " MEM_RTERM_RMX        ,The value written to this field is used as Termination resistor trim code if bit 21 is set to 1. BMEM_USE_RTERM_RMX_REG is set to 1. Can be used to improve the HS eye diagram by reducing the termination resistance. Increase the value until eye passes. Also ensure receiver compliance is also met." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "  RTERM_RMX                   ,Returns the current value of RTERM_RMX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "USB2PHY_CHRG_DET,This is the charger detect register. This register is not used in the dead battery case."
bitfld.long 0x00 29. " MEM_USE_CHG_DET_REG  ,Use bits 28-24 and 18-17 from this register" "0,1"
bitfld.long 0x00 28. "   MEM_DIS_CHG_DET             ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 27. " MEM_SRC_ON_DM        ," "0,1"
bitfld.long 0x00 26. "   MEM_SINK_ON_DP              ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 25. " MEM_CHG_DET_EXT_CTL  ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
bitfld.long 0x00 24. "   MEM_RESTART_CHG_DET         ,Restart the charger detection protocol when this goes from 0 to 1" "0,1"
textline "                                      "
bitfld.long 0x00 23. " CHG_DET_DONE         ,Charger detect protocol has completed" "0,1"
bitfld.long 0x00 22. "   CHG_DETECTED                ,Same signal as CE" "0,1"
textline "                                      "
bitfld.long 0x00 21. " DATA_DET             ,Output of the data det comparator" "0,1"
bitfld.long 0x00 18. "   MEM_CHG_ISINK_EN            ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 17. " MEM_CHG_VSRC_EN      ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
bitfld.long 0x00 16. "   COMP_DP                     ,Comparator on the DP line value" "0,1"
textline "                                      "
bitfld.long 0x00 15. " COMP_DM              ,Comparator on the DM line value" "0,1"
bitfld.long 0x00 0. "   MEM_FOR_CE                  ,Force CE = 1 when this bit is set" "0,1"
group.long 0x30++0x3
line.long 0x00 "USB2PHY_GPIO,GPIO mode configurations and reads"
bitfld.long 0x00 31. " MEM_USEGPIOMODEREG   ,When set to 1 use bits 31-24 from this register instead of primary inputs" "0,1"
bitfld.long 0x00 30. "   MEM_GPIOMODE                ,Overrides the GPIO MODE primary input" "0,1"
textline "                                      "
bitfld.long 0x00 29. " MEM_DPGPIOGZ         ,Overrides the DP GPIO GZ primary input" "0,1"
bitfld.long 0x00 28. "   MEM_DMGPIOGZ                ,Overrides the DM GPIO GZ primary input" "0,1"
textline "                                      "
bitfld.long 0x00 27. " MEM_DPGPIOA          ,Overrides the DP GPIO A primary input" "0,1"
bitfld.long 0x00 26. "   MEM_DMGPIOA                 ,Overrides the DM GPIO A primary input" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DPGPIOY              ,DP GPIO Y output is stored here" "0,1"
bitfld.long 0x00 24. "   DMGPIOY                     ,DM GPIO Y output is stored here" "0,1"
textline "                                      "
bitfld.long 0x00 19. " MEM_DMGPIOPIPD       ,GPIO mode DM pull down enabled. Overrides the corresponding primary input" "0,1"
bitfld.long 0x00 18. "   MEM_DPGPIOPIPD              ,GPIO mode DP pull-down enabled. Overrides the corresponding primary input." "0,1"
group.long 0x48++0x3
line.long 0x00 "USB2PHY_AD_INTERFACE_REG3,All bits unless defined are bypass bits for internal analog to digital interface pins with the same name. All the bits of this register, except the over-ride bits return a 0 on read, if VDDLDO is off."
hexmask.long.byte 0x00 10.--17. 1. " MEM_SPARE_IN_LDO     ,Depreciated. Use"
group.long 0x4C++0x3
line.long 0x00 "USB2PHY_ANA_CONFIG1,Used to configure and debug the analog blocks."
bitfld.long 0x00 31. " DISCON_DETECT_BYPASS ,Disconnect detection window mode. 0x0: extends detection window for disconnect to the length of the SOF packet (not compliant with the USB2.0 spec). 0x1: limits the detection window for disconnect to last 8b of the SOF EOP (in compliance with the USB2.0 spec) to avoid incorrectly detecting a disconnect on boards with excessive reflections noise/ringing." "0,1"
group.long 0x50++0x3
line.long 0x00 "USB2PHY_ANA_CONFIG2,Used to configure and debug the analog blocks."
bitfld.long 0x00 15.--19. " MEM_FSRX_TEST        ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "USB3SS1_PHY2"
base ad:0x4110000
width 29.
group.long 0x0++0x3
line.long 0x00 "USB2PHY_TERMINATION_CONTROL,Contains bits related to control of terminations in USB2PHY"
bitfld.long 0x00 24.--27. " MEM_FS_CODE_SEL      ,FS Code selection control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "  MEM_RTMEM_USE_RTERM_RMX_REG ,Override termination resistor trim code with mem_RTERM_RMX from this register" "0,1"
textline "                                      "
bitfld.long 0x00 15.--20. " MEM_RTERM_RMX        ,The value written to this field is used as Termination resistor trim code if bit 21 is set to 1. BMEM_USE_RTERM_RMX_REG is set to 1. Can be used to improve the HS eye diagram by reducing the termination resistance. Increase the value until eye passes. Also ensure receiver compliance is also met." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "  RTERM_RMX                   ,Returns the current value of RTERM_RMX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "USB2PHY_CHRG_DET,This is the charger detect register. This register is not used in the dead battery case."
bitfld.long 0x00 29. " MEM_USE_CHG_DET_REG  ,Use bits 28-24 and 18-17 from this register" "0,1"
bitfld.long 0x00 28. "   MEM_DIS_CHG_DET             ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 27. " MEM_SRC_ON_DM        ," "0,1"
bitfld.long 0x00 26. "   MEM_SINK_ON_DP              ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 25. " MEM_CHG_DET_EXT_CTL  ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
bitfld.long 0x00 24. "   MEM_RESTART_CHG_DET         ,Restart the charger detection protocol when this goes from 0 to 1" "0,1"
textline "                                      "
bitfld.long 0x00 23. " CHG_DET_DONE         ,Charger detect protocol has completed" "0,1"
bitfld.long 0x00 22. "   CHG_DETECTED                ,Same signal as CE" "0,1"
textline "                                      "
bitfld.long 0x00 21. " DATA_DET             ,Output of the data det comparator" "0,1"
bitfld.long 0x00 18. "   MEM_CHG_ISINK_EN            ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
textline "                                      "
bitfld.long 0x00 17. " MEM_CHG_VSRC_EN      ,When read, returns current value of charger detect input. When mem_USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1"
bitfld.long 0x00 16. "   COMP_DP                     ,Comparator on the DP line value" "0,1"
textline "                                      "
bitfld.long 0x00 15. " COMP_DM              ,Comparator on the DM line value" "0,1"
bitfld.long 0x00 0. "   MEM_FOR_CE                  ,Force CE = 1 when this bit is set" "0,1"
group.long 0x30++0x3
line.long 0x00 "USB2PHY_GPIO,GPIO mode configurations and reads"
bitfld.long 0x00 31. " MEM_USEGPIOMODEREG   ,When set to 1 use bits 31-24 from this register instead of primary inputs" "0,1"
bitfld.long 0x00 30. "   MEM_GPIOMODE                ,Overrides the GPIO MODE primary input" "0,1"
textline "                                      "
bitfld.long 0x00 29. " MEM_DPGPIOGZ         ,Overrides the DP GPIO GZ primary input" "0,1"
bitfld.long 0x00 28. "   MEM_DMGPIOGZ                ,Overrides the DM GPIO GZ primary input" "0,1"
textline "                                      "
bitfld.long 0x00 27. " MEM_DPGPIOA          ,Overrides the DP GPIO A primary input" "0,1"
bitfld.long 0x00 26. "   MEM_DMGPIOA                 ,Overrides the DM GPIO A primary input" "0,1"
textline "                                      "
bitfld.long 0x00 25. " DPGPIOY              ,DP GPIO Y output is stored here" "0,1"
bitfld.long 0x00 24. "   DMGPIOY                     ,DM GPIO Y output is stored here" "0,1"
textline "                                      "
bitfld.long 0x00 19. " MEM_DMGPIOPIPD       ,GPIO mode DM pull down enabled. Overrides the corresponding primary input" "0,1"
bitfld.long 0x00 18. "   MEM_DPGPIOPIPD              ,GPIO mode DP pull-down enabled. Overrides the corresponding primary input." "0,1"
group.long 0x48++0x3
line.long 0x00 "USB2PHY_AD_INTERFACE_REG3,All bits unless defined are bypass bits for internal analog to digital interface pins with the same name. All the bits of this register, except the over-ride bits return a 0 on read, if VDDLDO is off."
hexmask.long.byte 0x00 10.--17. 1. " MEM_SPARE_IN_LDO     ,Depreciated. Use"
group.long 0x4C++0x3
line.long 0x00 "USB2PHY_ANA_CONFIG1,Used to configure and debug the analog blocks."
bitfld.long 0x00 31. " DISCON_DETECT_BYPASS ,Disconnect detection window mode. 0x0: extends detection window for disconnect to the length of the SOF packet (not compliant with the USB2.0 spec). 0x1: limits the detection window for disconnect to last 8b of the SOF EOP (in compliance with the USB2.0 spec) to avoid incorrectly detecting a disconnect on boards with excessive reflections noise/ringing." "0,1"
group.long 0x50++0x3
line.long 0x00 "USB2PHY_ANA_CONFIG2,Used to configure and debug the analog blocks."
bitfld.long 0x00 15.--19. " MEM_FSRX_TEST        ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "USB3SS_ECC_AGGR"
tree "USB3SS0_ECC_AGGR"
base ad:0x2A30000
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "USB_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                ,bu" "0,1,2,3"
textline "                                      "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID             ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL            ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " REVMAJ                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom version" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 0.--5. " REVMIN                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "USB_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. " RD_SVBUS_DONE         ,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         RD_SVBUS_ADDRESS  ,Read address"
textline "                                      "
bitfld.long 0x00 15. " RD_SVBUS              ,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "         ECC_VECTOR        ,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x00 "USB_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS              ,Indicates the number of RAMS serviced by the ECC aggregator"
rgroup.long 0x10++0x3
line.long 0x00 "USB_ECC_WRAP_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                ,bu" "0,1,2,3"
textline "                                      "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID             ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL            ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " REVMAJ                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom version" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 0.--5. " REVMIN                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "USB_ECC_CTRL,ECC Control Register"
bitfld.long 0x00 8. " CHECK_SVBUS_TIMEOUT   ,check for svbus timeout errors" "0,1"
bitfld.long 0x00 7. "         CHECK_PARITY      ,check for parity errors" "0,1"
textline "                                      "
bitfld.long 0x00 6. " ERROR_ONCE            ,Force Error only once" "0,1"
bitfld.long 0x00 5. "         FORCE_N_ROW       ,Force Error on any RAM read" "0,1"
textline "                                      "
bitfld.long 0x00 4. " FORCE_DED             ,Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "         FORCE_SEC         ,Force Single Bit Error" "0,1"
textline "                                      "
bitfld.long 0x00 2. " ENABLE_RMW            ,Enable rmw" "0,1"
bitfld.long 0x00 1. "         ECC_CHECK         ,Enable ECC check" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ECC_ENABLE            ,Enable ECC" "0,1"
group.long 0x18++0x3
line.long 0x00 "USB_ECC_ERR_CTRL1,ECC Error Control1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW               ,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
group.long 0x1C++0x3
line.long 0x00 "USB_ECC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT2              ,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x00 0.--15. 1. "      ECC_BIT1          ,Data bit that needs to be flipped when force_sec is set"
hgroup.long 0x20++0x3
hide.long 0x00 "USB_ECC_ERR_STAT1,ECC Error Status1 Register"
in
textline "                                      "
rgroup.long 0x24++0x3
line.long 0x00 "USB_ECC_ERR_STAT2,ECC Error Status2 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW               ,Row address where the single or double-bit error has occurred"
hgroup.long 0x28++0x3
hide.long 0x00 "USB_ECC_ERR_STAT3,ECC Error Status3 Register"
in
textline "                                      "
group.long 0x3C++0x3
line.long 0x00 "USB_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "USB_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 2. " RAM2_PEND             ,Interrupt Pending Status for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_PEND         ,Interrupt Pending Status for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_PEND             ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "USB_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. " RAM2_ENABLE_SET       ,Interrupt Enable Set Register for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_ENABLE_SET   ,Interrupt Enable Set Register for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_ENABLE_SET       ,Interrupt Enable Set Register for ram0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "USB_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                      "
group.long 0x13C++0x3
line.long 0x00 "USB_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "USB_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 2. " RAM2_PEND             ,Interrupt Pending Status for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_PEND         ,Interrupt Pending Status for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_PEND             ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "USB_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. " RAM2_ENABLE_SET       ,Interrupt Enable Set Register for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_ENABLE_SET   ,Interrupt Enable Set Register for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_ENABLE_SET       ,Interrupt Enable Set Register for ram0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "USB_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                      "
group.long 0x200++0x3
line.long 0x00 "USB_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT               ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "         PARITY            ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "USB_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                      "
group.long 0x208++0x3
line.long 0x00 "USB_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PARITY            ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "USB_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PARITY            ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "USB3SS1_ECC_AGGR"
base ad:0x2A31000
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "USB_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                ,bu" "0,1,2,3"
textline "                                      "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID             ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL            ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " REVMAJ                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom version" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 0.--5. " REVMIN                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8++0x3
line.long 0x00 "USB_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. " RD_SVBUS_DONE         ,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "         RD_SVBUS_ADDRESS  ,Read address"
textline "                                      "
bitfld.long 0x00 15. " RD_SVBUS              ,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "         ECC_VECTOR        ,Value written to select the corresponding ECC RAM for control or status"
rgroup.long 0xC++0x3
line.long 0x00 "USB_ECC_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS              ,Indicates the number of RAMS serviced by the ECC aggregator"
rgroup.long 0x10++0x3
line.long 0x00 "USB_ECC_WRAP_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU                ,bu" "0,1,2,3"
textline "                                      "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID             ,Module ID"
bitfld.long 0x00 11.--15. "      REVRTL            ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " REVMAJ                ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM            ,Custom version" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 0.--5. " REVMIN                ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x3
line.long 0x00 "USB_ECC_CTRL,ECC Control Register"
bitfld.long 0x00 8. " CHECK_SVBUS_TIMEOUT   ,check for svbus timeout errors" "0,1"
bitfld.long 0x00 7. "         CHECK_PARITY      ,check for parity errors" "0,1"
textline "                                      "
bitfld.long 0x00 6. " ERROR_ONCE            ,Force Error only once" "0,1"
bitfld.long 0x00 5. "         FORCE_N_ROW       ,Force Error on any RAM read" "0,1"
textline "                                      "
bitfld.long 0x00 4. " FORCE_DED             ,Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "         FORCE_SEC         ,Force Single Bit Error" "0,1"
textline "                                      "
bitfld.long 0x00 2. " ENABLE_RMW            ,Enable rmw" "0,1"
bitfld.long 0x00 1. "         ECC_CHECK         ,Enable ECC check" "0,1"
textline "                                      "
bitfld.long 0x00 0. " ECC_ENABLE            ,Enable ECC" "0,1"
group.long 0x18++0x3
line.long 0x00 "USB_ECC_ERR_CTRL1,ECC Error Control1 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW               ,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
group.long 0x1C++0x3
line.long 0x00 "USB_ECC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT2              ,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x00 0.--15. 1. "      ECC_BIT1          ,Data bit that needs to be flipped when force_sec is set"
hgroup.long 0x20++0x3
hide.long 0x00 "USB_ECC_ERR_STAT1,ECC Error Status1 Register"
in
textline "                                      "
rgroup.long 0x24++0x3
line.long 0x00 "USB_ECC_ERR_STAT2,ECC Error Status2 Register"
hexmask.long 0x00 0.--31. 1. " ECC_ROW               ,Row address where the single or double-bit error has occurred"
hgroup.long 0x28++0x3
hide.long 0x00 "USB_ECC_ERR_STAT3,ECC Error Status3 Register"
in
textline "                                      "
group.long 0x3C++0x3
line.long 0x00 "USB_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "USB_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 2. " RAM2_PEND             ,Interrupt Pending Status for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_PEND         ,Interrupt Pending Status for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_PEND             ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "USB_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. " RAM2_ENABLE_SET       ,Interrupt Enable Set Register for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_ENABLE_SET   ,Interrupt Enable Set Register for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_ENABLE_SET       ,Interrupt Enable Set Register for ram0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "USB_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                      "
group.long 0x13C++0x3
line.long 0x00 "USB_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "USB_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 2. " RAM2_PEND             ,Interrupt Pending Status for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_PEND         ,Interrupt Pending Status for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_PEND             ,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "USB_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. " RAM2_ENABLE_SET       ,Interrupt Enable Set Register for ram2_pend" "0,1"
bitfld.long 0x00 1. "         RAM1_ENABLE_SET   ,Interrupt Enable Set Register for ram1_pend" "0,1"
textline "                                      "
bitfld.long 0x00 0. " RAM0_ENABLE_SET       ,Interrupt Enable Set Register for ram0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "USB_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                      "
group.long 0x200++0x3
line.long 0x00 "USB_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT               ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "         PARITY            ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "USB_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                      "
group.long 0x208++0x3
line.long 0x00 "USB_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PARITY            ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "USB_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT               ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PARITY            ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "USB3SS"
tree "USB3SS0"
base ad:0x4000000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "USB_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 30.--31. " SCHEME               ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                              ,bu" "0,1,2,3"
textline "                                     "
hexmask.long.word 0x00 16.--27. 1. " FUNC                 ,Module ID"
bitfld.long 0x00 11.--15. "  R_RTL                           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                     "
bitfld.long 0x00 8.--10. " X_MAJOR              ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                          ,Custom version" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--5. " Y_MINOR              ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "USB_SYSCONFIG,Controls various parameters of the master and slave interfaces."
bitfld.long 0x00 16. " PME_EN               ,Enable signal for the pme_generation. When the Run/Stop bit of the USB Command Register is cleared during USB suspend mode, the core cannot generate event and cannot assert regular interrupt. In this case, the core asserts pme_generation signal to report any wakeup condition if PME_EN is high." "0,1"
bitfld.long 0x00 15. "     HSIC_SEL                        ,Select USB2PHY when 0, HSIC when 1" "0,1"
textline "                                     "
bitfld.long 0x00 14. " CEGPIOA              ,GPO mode data for CE." "0,1"
bitfld.long 0x00 13. "     CEGPIOGZ                        ,CE GPO output buffer control." "0,1"
group.long 0x20++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_MAIN_i,The IRQ_STATUS_RAW_MAIN_i register allows the usbss interrupt sources to be manually set when writing a 1 to a specific bit. Parameter i ranges from 0 to 15. Offset = 20h + (i * 10h), where: i = 0h to Fh"
bitfld.long 0x00 0. " IRQ_STATUS_RAW_MAIN  ,Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" "0,1"
hgroup.long 0x24++0x3
hide.long 0x00 "USB_IRQ_STATUS_MAIN_i,The IRQ_STATUS_MAIN_i register allows the usbss interrupt sources to be manually cleared when writing a 1 to a specific bit. Parameter i ranges from 0 to 15. Offset = 24h + (i * 10h), where: i = 0h to Fh"
in
textline "                                     "
group.long 0x42C++0x3
line.long 0x00 "USB_IRQ_EOI_MISC,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to."
bitfld.long 0x00 0. " EOI_MISC             ,Write 1 to flag End Of Interrupt 'MISC'" "0,1"
group.long 0x430++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_MISC,The register allows the usbss interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 22. " VBUSVALID_CHANGE     ,Set when VBUSVALID changes state" "0,1"
bitfld.long 0x00 21. "     AVALID_CHANGE                   ,Set when AVALID changes state" "0,1"
textline "                                     "
bitfld.long 0x00 20. " BVALID_CHANGE        ,Set when BVALID changes state" "0,1"
bitfld.long 0x00 19. "     SESSEND_CHANGE                  ,Set when SESSEND changes state" "0,1"
textline "                                     "
bitfld.long 0x00 18. " AXI_ERROR            ,Set by host_system_err when HW detects an error response to AXI master. .HSEE must be set in the controller. Error reflected in the controller .HSE field." "0,1"
hgroup.long 0x434++0x3
hide.long 0x00 "USB_IRQ_STATUS_MISC,The register allows the usbss interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x438++0x3
line.long 0x00 "USB_IRQ_ENABLE_SET_MISC,The register allows the usbss interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 22. " VBUSVALID_CHANGE     ,Event enable set" "0,1"
bitfld.long 0x00 21. "     AVALID_CHANGE                   ,Event enable set" "0,1"
textline "                                     "
bitfld.long 0x00 20. " BVALID_CHANGE        ,Event enable set" "0,1"
bitfld.long 0x00 19. "     SESSEND_CHANGE                  ,Event enable set" "0,1"
textline "                                     "
bitfld.long 0x00 18. " AXI_ERROR            ,Event enable set" "0,1"
hgroup.long 0x43C++0x3
hide.long 0x00 "USB_IRQ_ENABLE_CLR_MISC,The register allows the usbss interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
in
textline "                                     "
group.long 0x450++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_OTG,The Register allows the OTG interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " OTG_EVNT             ,Interrupt raw status for OTG event" "0,1"
hgroup.long 0x454++0x3
hide.long 0x00 "USB_IRQ_STATUS_OTG,The Register allows the OTG source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x460++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_ADP,The Register allows the ADP interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " ADP_EVNT             ,Interrupt raw status for ADP event" "0,1"
hgroup.long 0x464++0x3
hide.long 0x00 "USB_IRQ_STATUS_ADP,The Register allows the ADP source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x470++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_BC,The Register allows the BC interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " BC_EVNT              ,Interrupt raw status for BC event" "0,1"
hgroup.long 0x474++0x3
hide.long 0x00 "USB_IRQ_STATUS_BC,The Register allows the BC source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x480++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_PME_GEN,The Register allows the PME_GEN interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " PME_GEN_EVNT         ,Interrupt raw status for PME_GEN event" "0,1"
hgroup.long 0x484++0x3
hide.long 0x00 "USB_IRQ_STATUS_PME_GEN,The Register allows the PME_GEN source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x614++0x3
line.long 0x00 "USB_VBUS_ID_FILTER,The vbus and id comparator signals may be filtered by controlling these register values."
bitfld.long 0x00 19. " VBUSVALID_ANA_THRESH ,Set threshold for VBUSVALID. Drives VALID_THRESHOLD_SEL on the USB_VBUS_IDD" "0,1"
bitfld.long 0x00 18. "     RID_EN                          ,Enable RID detection when =1" "0,1"
textline "                                     "
bitfld.long 0x00 17. " RID_BYPASS           ,0= use filter, 1= bypass filter" "0,1"
bitfld.long 0x00 15.--16. "     RID_THRESH                      ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for RID_FLOAT, RID_GND, RID_A, RID_B and RID_C" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 14. " IDDIG_BYPASS         ,0= use filter, 1= bypass filter for IDDIG" "0,1"
bitfld.long 0x00 12.--13. "     IDDIG_THRESH                    ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for IDDIG" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 11. " SESSEND_BYPASS       ,0= use filter, 1= bypass filter for SESSEND" "0,1"
bitfld.long 0x00 9.--10. "     SESSEND_THRESH                  ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for SESSEND" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 8. " BVALID_BYPASS        ,0= use filter, 1= bypass filter" "0,1"
bitfld.long 0x00 6.--7. "     BVALID_THRESH                   ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for BVALID" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 5. " AVALID_BYPASS        ,0= use filter, 1= bypass filter for AVALID" "0,1"
bitfld.long 0x00 3.--4. "     AVALID_THRESH                   ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for AVALID" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 2. " VBUSVALID_BYPASS     ,0= use filter, 1= bypass filter for VBUSVALID" "0,1"
bitfld.long 0x00 0.--1. "     VBUSVALID_THRESH                ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for VBUSVALID" "0,1,2,3"
rgroup.long 0x618++0x3
line.long 0x00 "USB_VBUS_ID_STAT,Status bits of VBUS and ID detected signals after filter."
bitfld.long 0x00 9. " RID_FLOAT            ,Filtered RID_FLOAT" "0,1"
bitfld.long 0x00 8. "     RID_GND                         ,Filtered RID_GND" "0,1"
textline "                                     "
bitfld.long 0x00 7. " RID_C                ,Filtered RID_C" "0,1"
bitfld.long 0x00 6. "     RID_B                           ,Filtered RID_B" "0,1"
textline "                                     "
bitfld.long 0x00 5. " RID_A                ,Filtered RID_A" "0,1"
bitfld.long 0x00 4. "     IDDIG                           ,Filtered IDDIG" "0,1"
textline "                                     "
bitfld.long 0x00 3. " SESSEND              ,Filtered SESSEND" "0,1"
bitfld.long 0x00 2. "     BVALID                          ,Filtered BVALID" "0,1"
textline "                                     "
bitfld.long 0x00 1. " AVALID               ,Filtered AVALID" "0,1"
bitfld.long 0x00 0. "     VBUSVALID                       ,Filtered VBUSVALID" "0,1"
group.long 0x61C++0x3
line.long 0x00 "USB_USB2PHY_CTRL_STAT,The USB2PHY ports with corresponding names arecontrolled by these registers. Status bits correspond to the USB2PHY outputs of the same name."
bitfld.long 0x00 21. " CHGDETECTED          ,Corresponds to USB2PHY port CHGDETECTED" "0,1"
bitfld.long 0x00 20. "     CHGDETDONE                      ,Corresponds to USB2PHY port CHGDETDONE" "0,1"
textline "                                     "
bitfld.long 0x00 19. " DATADET              ,Corresponds to USB2PHY port DATADET" "0,1"
bitfld.long 0x00 18. "     CHG_DET_DP_COMP                 ,Corresponds to USB2PHY port CHG_DET_DP_COMP" "0,1"
textline "                                     "
bitfld.long 0x00 17. " CHG_DET_DM_COMP      ,Corresponds to USB2PHY port CHG_DET_DM_COMP" "0,1"
bitfld.long 0x00 14.--16. "     CHG_DET_STATUS                  ,Corresponds to USB2PHY port CHG_DET_STATUS" "0,1,2,3,4,5,6,7"
textline "                                     "
bitfld.long 0x00 13. " CDP_NSDP             ,Allows for charging downstream port control =1." "0,1"
bitfld.long 0x00 12. "     DATAPOLARITYN                   ,Corresponds to USB2PHY port DATAPOLARITYN" "0,1"
textline "                                     "
bitfld.long 0x00 11. " MCPCMODEEN           ,Corresponds to USB2PHY port MCPCMODEEN" "0,1"
bitfld.long 0x00 10. "     MCPCPUEN                        ,Corresponds to USB2PHY port MCPCPUEN" "0,1"
textline "                                     "
bitfld.long 0x00 9. " RESTARTCHGDET        ,Corresponds to USB2PHY port RESTARTCHGDET" "0,1"
bitfld.long 0x00 8. "     SRCONDM                         ,Corresponds to USB2PHY port SRCONDM" "0,1"
textline "                                     "
bitfld.long 0x00 7. " SINKONDP             ,Corresponds to USB2PHY port SINKONDP" "0,1"
bitfld.long 0x00 6. "     CHG_ISINK_EN                    ,Corresponds to USB2PHY port CHG_ISINK_EN" "0,1"
textline "                                     "
bitfld.long 0x00 5. " CHG_VSRC_EN          ,Corresponds to USB2PHY port CHG_VSRC_EN" "0,1"
bitfld.long 0x00 4. "     RDP_PU_CHGDET_EN                ,Corresponds to USB2PHY port RDP_PU_CHGDET_EN" "0,1"
textline "                                     "
bitfld.long 0x00 3. " RDM_PD_CHGDET_EN     ,Corresponds to USB2PHY port RDM_PD_CHGDET_EN" "0,1"
bitfld.long 0x00 2. "     CHG_DET_EXT_CTL                 ,Corresponds to USB2PHY port CHG_DET_EXT_CTL" "0,1"
textline "                                     "
bitfld.long 0x00 1. " DISCHGDET            ,Corresponds to USB2PHY port DISCHGDET" "0,1"
bitfld.long 0x00 0. "     AUTORESUME_EN                   ,Corresponds to USB2PHY port AUTORESUME_EN" "0,1"
group.long 0x700++0x3
line.long 0x00 "USB_MMRAM_OFFSET,Offset of Memory-mapped RAM accesses. Page is remapped from 0x8000 to 0xFFFF (32 kbyte)"
bitfld.long 0x00 15.--19. " OFFSET_MSB           ,Byte offset MSBits = page offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--14. 1. "    OFFSET_LSB                      ,Byte offset LSBits, always 0"
group.long 0x704++0x3
line.long 0x00 "USB_CORE_CTL,XHCI rev, port disable pseudo-static parameters"
bitfld.long 0x00 28. " HOST_U3_PORT_DISABLE ,USB3 port disable, overriding xHCI driver." "0,1"
bitfld.long 0x00 27. "     HOST_U2_PORT_DISABLE            ,USB2 port disable, overriding xHCI driver." "0,1"
group.long 0x708++0x3
line.long 0x00 "USB_DEBUG_CFG,Configuration of debug data for observation and for control. 0x0 = debug outputs are tied low 0x1 = debug outputs are UTMI interface signals 0x2 = debug outputs are PIPE3 interface signals 0x3 = debug outputs are xHC internal signals 0x4 = debug outputs are controller logic_analyzer_trace[31:0] 0x5 = debug outputs are controller logic_analyzer_trace[63:32]"
bitfld.long 0x00 0.--2. " SEL_DBG              ,Selects observed local signals" "0,1,2,3,4,5,6,7"
rgroup.long 0x70C++0x3
line.long 0x00 "USB_DEBUG_DATA,Data that is observable Observable data is selected via .sel_dbg , shown only for sel_dbg = (1,2,3)"
bitfld.long 0x00 31. " DEBUG31              ,sel= 1: utmi_sessend sel= 2: pipe_rxstatus[2] sel= 3: core_sm2bl_cur_mode" "0,1"
bitfld.long 0x00 30. "     DEBUG30                         ,sel= 1: utmi_vbusvalid sel= 2: pipe_rxstatus[1] sel= 3: core_suspend_n" "0,1"
textline "                                     "
bitfld.long 0x00 29. " DEBUG29              ,sel= 1: utmi_bvalid sel= 2: pipe_rxstatus[0] sel= 3: core_suspend_com_n" "0,1"
bitfld.long 0x00 28. "     DEBUG28                         ,sel= 1: utmi_avalid sel= 2: pipe_elecidle sel= 3: core_u2_dssr_state[3]" "0,1"
textline "                                     "
bitfld.long 0x00 27. " DEBUG27              ,sel= 1: utmi_iddig sel= 2: pipe_phystatus sel= 3: core_u2_dssr_state[2]" "0,1"
bitfld.long 0x00 26. "     DEBUG26                         ,sel= 1: utmi_hostdisconnect sel= 2: pipe_rxvalid sel= 3: core_u2_dssr_state[1]" "0,1"
textline "                                     "
bitfld.long 0x00 25. " DEBUG25              ,sel= 1: utmi_txbitstuffenableh sel= 2: pipe_rxdatak[3] sel= 3: core_u2_dssr_state[0]" "0,1"
bitfld.long 0x00 24. "     DEBUG24                         ,sel= 1: utmi_txbitstuffenable sel= 2: pipe_rxdatak[2] sel= 3: core_u2mac_txrx_state_1[4]" "0,1"
textline "                                     "
bitfld.long 0x00 23. " DEBUG23              ,sel= 1: utmi_dischrgvbus sel= 2: pipe_rxdatak[1] sel= 3: core_u2mac_txrx_state_1[3]" "0,1"
bitfld.long 0x00 22. "     DEBUG22                         ,sel= 1: utmi_chrgvbus sel= 2: pipe_rxdatak[0] sel= 3: core_u2mac_txrx_state_1[2]" "0,1"
textline "                                     "
bitfld.long 0x00 21. " DEBUG21              ,sel= 1: utmi_drvvbus sel= 2: pipe_rxpclk sel= 3: core_u2mac_txrx_state_1[1]" "0,1"
bitfld.long 0x00 20. "     DEBUG20                         ,sel= 1: utmi_dmpulldown sel= 2: pipe_rxtermination sel= 3: core_u2mac_txrx_state_1[0]" "0,1"
textline "                                     "
bitfld.long 0x00 19. " DEBUG19              ,sel= 1: utmi_dppulldown sel= 2: pipe_txswing sel= 3: core_u2mac_txrx_state_0[4]" "0,1"
bitfld.long 0x00 18. "     DEBUG18                         ,sel= 1: utmi_idpullup sel= 2: pipe_txmargin[2] sel= 3: core_u2mac_txrx_state_0[3]" "0,1"
textline "                                     "
bitfld.long 0x00 17. " DEBUG17              ,sel= 1: utmi_linestate[1] sel= 2: pipe_txmargin[1] sel= 3: core_u2mac_txrx_state_0[2]" "0,1"
bitfld.long 0x00 16. "     DEBUG16                         ,sel= 1: utmi_linestate[0] sel= 2: pipe_txmargin[0] sel= 3: core_u2mac_txrx_state_0[1]" "0,1"
textline "                                     "
bitfld.long 0x00 15. " DEBUG15              ,sel= 1: utmi_opmode[1] sel= 2: pipe_txdeemph[1] sel= 3: core_u2mac_txrx_state_0[0]" "0,1"
bitfld.long 0x00 14. "     DEBUG14                         ,sel= 1: utmi_opmode[0] sel= 2: pipe_txdeemph[0] sel= 3: core_u2_prt_state[4]" "0,1"
textline "                                     "
bitfld.long 0x00 13. " DEBUG13              ,sel= 1: utmi_termselect sel= 2: pipe_powerdown[1] sel= 3: core_u2_prt_state[3]" "0,1"
bitfld.long 0x00 12. "     DEBUG12                         ,sel= 1: utmi_xcvrselect[1] sel= 2: pipe_powerdown[0] sel= 3: core_u2_prt_state[2]" "0,1"
textline "                                     "
bitfld.long 0x00 11. " DEBUG11              ,sel= 1: utmi_xcvrselect[0] sel= 2: pipe_reset_n sel= 3: core_u2_prt_state[1]" "0,1"
bitfld.long 0x00 10. "     DEBUG10                         ,sel= 1: utmi_suspendm sel= 2: pipe_rxeqtraining sel= 3: core_u2_prt_state[0]" "0,1"
textline "                                     "
bitfld.long 0x00 9. " DEBUG9               ,sel= 1: utmi_reset sel= 2: pipe_rxpolarity sel= 3: core_gsts_buserraddvld" "0,1"
bitfld.long 0x00 8. "     DEBUG8                          ,sel= 1: utmi_rxerror sel= 2: pipe_txoneszeros sel= 3: debug_mclk_usof_number[0]" "0,1"
textline "                                     "
bitfld.long 0x00 7. " DEBUG7               ,sel= 1: utmi_rxvalidh sel= 2: pipe_txelecidle sel= 3: core_ltdb_link_state[3]" "0,1"
bitfld.long 0x00 6. "     DEBUG6                          ,sel= 1: utmi_rxvalid sel= 2: pipe_txdetectrxloopback sel= 3: core_ltdb_link_state[2]" "0,1"
textline "                                     "
bitfld.long 0x00 5. " DEBUG5               ,sel= 1: utmi_rxactive sel= 2: pipe_elasticitybuffermode sel= 3: core_ltdb_link_state[1]" "0,1"
bitfld.long 0x00 4. "     DEBUG4                          ,sel= 1: utmi_txready sel= 2: pipe_txdatak[3] sel= 3: core_ltdb_link_state[0]" "0,1"
textline "                                     "
bitfld.long 0x00 3. " DEBUG3               ,sel= 1: utmi_txdatah sel= 2: pipe_txdatak[2] sel= 3: core_ltdb_substate[3]" "0,1"
bitfld.long 0x00 2. "     DEBUG2                          ,sel= 1: utmi_txdata sel= 2: pipe_txdatak[1] sel= 3: core_ltdb_substate[2]" "0,1"
textline "                                     "
bitfld.long 0x00 1. " DEBUG1               ,sel= 1: utmi_databus16_8 or wordinterface sel= 2: pipe_txdatak[0] sel= 3: core_ltdb_substate[1]" "0,1"
bitfld.long 0x00 0. "     DEBUG0                          ,sel= 1: utmi_clk sel= 2: pipe_txpclk sel= 3: core_ltdb_substate[0]" "0,1"
group.long 0x710++0x3
line.long 0x00 "USB_DEV_EBC_EN,Enable External Buffer Control (EBC) for selected endpoints. Device mode only. INEP[x] Enable EBC HW throttling for IN EP (USB transmit). To enable logical EP IN #i, set [x]. In DEPCFG command for this EP, DEPCMDPAR1[x] = LimitOutstandingTxDMA should then also be set to 1 OUTEP[x] Enable EBC HW throttling for OUT EP, per bit (USB receive). To enable logical OUT EP #i, set [x+16] In DEPCFG command for this EP, DEPCMDPAR1[x] = LimitOutstandingTxDMA should then also be set to 1 x equals 15"
bitfld.long 0x00 31. " OUTEP15              ,ENABLE EBC HW throttling (USB receive) for OUT EP 15" "0,1"
bitfld.long 0x00 30. "     OUTEP14                         ,ENABLE EBC HW throttling (USB receive) for OUT EP 14" "0,1"
textline "                                     "
bitfld.long 0x00 15. " INEP15               ,ENABLE EBC HW throttling (USB transmit) for IN EP 15" "0,1"
bitfld.long 0x00 14. "     INEP14                          ,ENABLE EBC HW throttling (USB transmit) for IN EP 14" "0,1"
group.long 0x714++0x3
line.long 0x00 "USB_HOST_HUB_CTRL,The Register is a collection of various input signals that control the xHC controllers Host or Hub interfaces. These signals are used regardless if a Host or Hub is implemented or not."
bitfld.long 0x00 8.--11. " BUS_FILTER_BYPASS    ,Bus Filter Bypass bit [0]: bypass the filter for vbusvalid bit [1]: bypass the filter for pipe3_PowerPresent bit [2]: bypass the filter for avalid, bvalid, and sessend bit [3]: bypass the filter for iddig 0 = filter enabled 1 = filter disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6.--7. "    HUB_PORT_PERM_ATTACH            ,Indicates if the device attached to a downstream port is permanently attached or not. Bit 6 is the USB2 port and bit 7 is the SS port. 0 - Not permanently attached 1 - Permanently attached" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 5. " XHC_BME              ,This signal is used to disable the bus mastering capability of the xHC. In a PCI system, it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b 0: Bus mastering capability is disabled. The host controller cannot use the bus master interface. 1'b 1: Bus mastering capability is enabled." "0,1"
bitfld.long 0x00 2. "     HOST_PORT_POWER_CONTROL_PRESENT ,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control. 0 - Indicates that the port does not have port power switches. 1 - Indicates that the port has port power switches." "0,1"
textline "                                     "
bitfld.long 0x00 0.--1. " HUB_PORT_OVERCURRENT ,This is the per port Overcurrent indication of the root-hub ports. Bit 0 is the USB2 port and bit 1 is the SS port. 0 - No Overcurrent 1 - Overcurrent" "0,1,2,3"
width 0x0B
tree.end
tree "USB3SS1"
base ad:0x4020000
width 28.
rgroup.long 0x0++0x3
line.long 0x00 "USB_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility"
bitfld.long 0x00 30.--31. " SCHEME               ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                              ,bu" "0,1,2,3"
textline "                                     "
hexmask.long.word 0x00 16.--27. 1. " FUNC                 ,Module ID"
bitfld.long 0x00 11.--15. "  R_RTL                           ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                     "
bitfld.long 0x00 8.--10. " X_MAJOR              ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                          ,Custom version" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 0.--5. " Y_MINOR              ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "USB_SYSCONFIG,Controls various parameters of the master and slave interfaces."
bitfld.long 0x00 16. " PME_EN               ,Enable signal for the pme_generation. When the Run/Stop bit of the USB Command Register is cleared during USB suspend mode, the core cannot generate event and cannot assert regular interrupt. In this case, the core asserts pme_generation signal to report any wakeup condition if PME_EN is high." "0,1"
bitfld.long 0x00 15. "     HSIC_SEL                        ,Select USB2PHY when 0, HSIC when 1" "0,1"
textline "                                     "
bitfld.long 0x00 14. " CEGPIOA              ,GPO mode data for CE." "0,1"
bitfld.long 0x00 13. "     CEGPIOGZ                        ,CE GPO output buffer control." "0,1"
group.long 0x20++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_MAIN_i,The IRQ_STATUS_RAW_MAIN_i register allows the usbss interrupt sources to be manually set when writing a 1 to a specific bit. Parameter i ranges from 0 to 15. Offset = 20h + (i * 10h), where: i = 0h to Fh"
bitfld.long 0x00 0. " IRQ_STATUS_RAW_MAIN  ,Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" "0,1"
hgroup.long 0x24++0x3
hide.long 0x00 "USB_IRQ_STATUS_MAIN_i,The IRQ_STATUS_MAIN_i register allows the usbss interrupt sources to be manually cleared when writing a 1 to a specific bit. Parameter i ranges from 0 to 15. Offset = 24h + (i * 10h), where: i = 0h to Fh"
in
textline "                                     "
group.long 0x42C++0x3
line.long 0x00 "USB_IRQ_EOI_MISC,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to."
bitfld.long 0x00 0. " EOI_MISC             ,Write 1 to flag End Of Interrupt 'MISC'" "0,1"
group.long 0x430++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_MISC,The register allows the usbss interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 22. " VBUSVALID_CHANGE     ,Set when VBUSVALID changes state" "0,1"
bitfld.long 0x00 21. "     AVALID_CHANGE                   ,Set when AVALID changes state" "0,1"
textline "                                     "
bitfld.long 0x00 20. " BVALID_CHANGE        ,Set when BVALID changes state" "0,1"
bitfld.long 0x00 19. "     SESSEND_CHANGE                  ,Set when SESSEND changes state" "0,1"
textline "                                     "
bitfld.long 0x00 18. " AXI_ERROR            ,Set by host_system_err when HW detects an error response to AXI master. .HSEE must be set in the controller. Error reflected in the controller .HSE field." "0,1"
hgroup.long 0x434++0x3
hide.long 0x00 "USB_IRQ_STATUS_MISC,The register allows the usbss interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x438++0x3
line.long 0x00 "USB_IRQ_ENABLE_SET_MISC,The register allows the usbss interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled"
bitfld.long 0x00 22. " VBUSVALID_CHANGE     ,Event enable set" "0,1"
bitfld.long 0x00 21. "     AVALID_CHANGE                   ,Event enable set" "0,1"
textline "                                     "
bitfld.long 0x00 20. " BVALID_CHANGE        ,Event enable set" "0,1"
bitfld.long 0x00 19. "     SESSEND_CHANGE                  ,Event enable set" "0,1"
textline "                                     "
bitfld.long 0x00 18. " AXI_ERROR            ,Event enable set" "0,1"
hgroup.long 0x43C++0x3
hide.long 0x00 "USB_IRQ_ENABLE_CLR_MISC,The register allows the usbss interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled"
in
textline "                                     "
group.long 0x450++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_OTG,The Register allows the OTG interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " OTG_EVNT             ,Interrupt raw status for OTG event" "0,1"
hgroup.long 0x454++0x3
hide.long 0x00 "USB_IRQ_STATUS_OTG,The Register allows the OTG source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x460++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_ADP,The Register allows the ADP interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " ADP_EVNT             ,Interrupt raw status for ADP event" "0,1"
hgroup.long 0x464++0x3
hide.long 0x00 "USB_IRQ_STATUS_ADP,The Register allows the ADP source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x470++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_BC,The Register allows the BC interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " BC_EVNT              ,Interrupt raw status for BC event" "0,1"
hgroup.long 0x474++0x3
hide.long 0x00 "USB_IRQ_STATUS_BC,The Register allows the BC source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x480++0x3
line.long 0x00 "USB_IRQ_STATUS_RAW_PME_GEN,The Register allows the PME_GEN interrupt source to be manually triggered when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending"
bitfld.long 0x00 0. " PME_GEN_EVNT         ,Interrupt raw status for PME_GEN event" "0,1"
hgroup.long 0x484++0x3
hide.long 0x00 "USB_IRQ_STATUS_PME_GEN,The Register allows the PME_GEN source to be manually cleared when writing a 1 to a specific bit. A read of this register returns the interrupt event pending value. General actions per bit: Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending"
in
textline "                                     "
group.long 0x614++0x3
line.long 0x00 "USB_VBUS_ID_FILTER,The vbus and id comparator signals may be filtered by controlling these register values."
bitfld.long 0x00 19. " VBUSVALID_ANA_THRESH ,Set threshold for VBUSVALID. Drives VALID_THRESHOLD_SEL on the USB_VBUS_IDD" "0,1"
bitfld.long 0x00 18. "     RID_EN                          ,Enable RID detection when =1" "0,1"
textline "                                     "
bitfld.long 0x00 17. " RID_BYPASS           ,0= use filter, 1= bypass filter" "0,1"
bitfld.long 0x00 15.--16. "     RID_THRESH                      ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for RID_FLOAT, RID_GND, RID_A, RID_B and RID_C" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 14. " IDDIG_BYPASS         ,0= use filter, 1= bypass filter for IDDIG" "0,1"
bitfld.long 0x00 12.--13. "     IDDIG_THRESH                    ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for IDDIG" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 11. " SESSEND_BYPASS       ,0= use filter, 1= bypass filter for SESSEND" "0,1"
bitfld.long 0x00 9.--10. "     SESSEND_THRESH                  ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for SESSEND" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 8. " BVALID_BYPASS        ,0= use filter, 1= bypass filter" "0,1"
bitfld.long 0x00 6.--7. "     BVALID_THRESH                   ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for BVALID" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 5. " AVALID_BYPASS        ,0= use filter, 1= bypass filter for AVALID" "0,1"
bitfld.long 0x00 3.--4. "     AVALID_THRESH                   ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for AVALID" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 2. " VBUSVALID_BYPASS     ,0= use filter, 1= bypass filter for VBUSVALID" "0,1"
bitfld.long 0x00 0.--1. "     VBUSVALID_THRESH                ,00= 1us, 01= 100us, 10= 5ms, 11= 50ms. UTMI_CLK latency for VBUSVALID" "0,1,2,3"
rgroup.long 0x618++0x3
line.long 0x00 "USB_VBUS_ID_STAT,Status bits of VBUS and ID detected signals after filter."
bitfld.long 0x00 9. " RID_FLOAT            ,Filtered RID_FLOAT" "0,1"
bitfld.long 0x00 8. "     RID_GND                         ,Filtered RID_GND" "0,1"
textline "                                     "
bitfld.long 0x00 7. " RID_C                ,Filtered RID_C" "0,1"
bitfld.long 0x00 6. "     RID_B                           ,Filtered RID_B" "0,1"
textline "                                     "
bitfld.long 0x00 5. " RID_A                ,Filtered RID_A" "0,1"
bitfld.long 0x00 4. "     IDDIG                           ,Filtered IDDIG" "0,1"
textline "                                     "
bitfld.long 0x00 3. " SESSEND              ,Filtered SESSEND" "0,1"
bitfld.long 0x00 2. "     BVALID                          ,Filtered BVALID" "0,1"
textline "                                     "
bitfld.long 0x00 1. " AVALID               ,Filtered AVALID" "0,1"
bitfld.long 0x00 0. "     VBUSVALID                       ,Filtered VBUSVALID" "0,1"
group.long 0x61C++0x3
line.long 0x00 "USB_USB2PHY_CTRL_STAT,The USB2PHY ports with corresponding names arecontrolled by these registers. Status bits correspond to the USB2PHY outputs of the same name."
bitfld.long 0x00 21. " CHGDETECTED          ,Corresponds to USB2PHY port CHGDETECTED" "0,1"
bitfld.long 0x00 20. "     CHGDETDONE                      ,Corresponds to USB2PHY port CHGDETDONE" "0,1"
textline "                                     "
bitfld.long 0x00 19. " DATADET              ,Corresponds to USB2PHY port DATADET" "0,1"
bitfld.long 0x00 18. "     CHG_DET_DP_COMP                 ,Corresponds to USB2PHY port CHG_DET_DP_COMP" "0,1"
textline "                                     "
bitfld.long 0x00 17. " CHG_DET_DM_COMP      ,Corresponds to USB2PHY port CHG_DET_DM_COMP" "0,1"
bitfld.long 0x00 14.--16. "     CHG_DET_STATUS                  ,Corresponds to USB2PHY port CHG_DET_STATUS" "0,1,2,3,4,5,6,7"
textline "                                     "
bitfld.long 0x00 13. " CDP_NSDP             ,Allows for charging downstream port control =1." "0,1"
bitfld.long 0x00 12. "     DATAPOLARITYN                   ,Corresponds to USB2PHY port DATAPOLARITYN" "0,1"
textline "                                     "
bitfld.long 0x00 11. " MCPCMODEEN           ,Corresponds to USB2PHY port MCPCMODEEN" "0,1"
bitfld.long 0x00 10. "     MCPCPUEN                        ,Corresponds to USB2PHY port MCPCPUEN" "0,1"
textline "                                     "
bitfld.long 0x00 9. " RESTARTCHGDET        ,Corresponds to USB2PHY port RESTARTCHGDET" "0,1"
bitfld.long 0x00 8. "     SRCONDM                         ,Corresponds to USB2PHY port SRCONDM" "0,1"
textline "                                     "
bitfld.long 0x00 7. " SINKONDP             ,Corresponds to USB2PHY port SINKONDP" "0,1"
bitfld.long 0x00 6. "     CHG_ISINK_EN                    ,Corresponds to USB2PHY port CHG_ISINK_EN" "0,1"
textline "                                     "
bitfld.long 0x00 5. " CHG_VSRC_EN          ,Corresponds to USB2PHY port CHG_VSRC_EN" "0,1"
bitfld.long 0x00 4. "     RDP_PU_CHGDET_EN                ,Corresponds to USB2PHY port RDP_PU_CHGDET_EN" "0,1"
textline "                                     "
bitfld.long 0x00 3. " RDM_PD_CHGDET_EN     ,Corresponds to USB2PHY port RDM_PD_CHGDET_EN" "0,1"
bitfld.long 0x00 2. "     CHG_DET_EXT_CTL                 ,Corresponds to USB2PHY port CHG_DET_EXT_CTL" "0,1"
textline "                                     "
bitfld.long 0x00 1. " DISCHGDET            ,Corresponds to USB2PHY port DISCHGDET" "0,1"
bitfld.long 0x00 0. "     AUTORESUME_EN                   ,Corresponds to USB2PHY port AUTORESUME_EN" "0,1"
group.long 0x700++0x3
line.long 0x00 "USB_MMRAM_OFFSET,Offset of Memory-mapped RAM accesses. Page is remapped from 0x8000 to 0xFFFF (32 kbyte)"
bitfld.long 0x00 15.--19. " OFFSET_MSB           ,Byte offset MSBits = page offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--14. 1. "    OFFSET_LSB                      ,Byte offset LSBits, always 0"
group.long 0x704++0x3
line.long 0x00 "USB_CORE_CTL,XHCI rev, port disable pseudo-static parameters"
bitfld.long 0x00 28. " HOST_U3_PORT_DISABLE ,USB3 port disable, overriding xHCI driver." "0,1"
bitfld.long 0x00 27. "     HOST_U2_PORT_DISABLE            ,USB2 port disable, overriding xHCI driver." "0,1"
group.long 0x708++0x3
line.long 0x00 "USB_DEBUG_CFG,Configuration of debug data for observation and for control. 0x0 = debug outputs are tied low 0x1 = debug outputs are UTMI interface signals 0x2 = debug outputs are PIPE3 interface signals 0x3 = debug outputs are xHC internal signals 0x4 = debug outputs are controller logic_analyzer_trace[31:0] 0x5 = debug outputs are controller logic_analyzer_trace[63:32]"
bitfld.long 0x00 0.--2. " SEL_DBG              ,Selects observed local signals" "0,1,2,3,4,5,6,7"
rgroup.long 0x70C++0x3
line.long 0x00 "USB_DEBUG_DATA,Data that is observable Observable data is selected via .sel_dbg , shown only for sel_dbg = (1,2,3)"
bitfld.long 0x00 31. " DEBUG31              ,sel= 1: utmi_sessend sel= 2: pipe_rxstatus[2] sel= 3: core_sm2bl_cur_mode" "0,1"
bitfld.long 0x00 30. "     DEBUG30                         ,sel= 1: utmi_vbusvalid sel= 2: pipe_rxstatus[1] sel= 3: core_suspend_n" "0,1"
textline "                                     "
bitfld.long 0x00 29. " DEBUG29              ,sel= 1: utmi_bvalid sel= 2: pipe_rxstatus[0] sel= 3: core_suspend_com_n" "0,1"
bitfld.long 0x00 28. "     DEBUG28                         ,sel= 1: utmi_avalid sel= 2: pipe_elecidle sel= 3: core_u2_dssr_state[3]" "0,1"
textline "                                     "
bitfld.long 0x00 27. " DEBUG27              ,sel= 1: utmi_iddig sel= 2: pipe_phystatus sel= 3: core_u2_dssr_state[2]" "0,1"
bitfld.long 0x00 26. "     DEBUG26                         ,sel= 1: utmi_hostdisconnect sel= 2: pipe_rxvalid sel= 3: core_u2_dssr_state[1]" "0,1"
textline "                                     "
bitfld.long 0x00 25. " DEBUG25              ,sel= 1: utmi_txbitstuffenableh sel= 2: pipe_rxdatak[3] sel= 3: core_u2_dssr_state[0]" "0,1"
bitfld.long 0x00 24. "     DEBUG24                         ,sel= 1: utmi_txbitstuffenable sel= 2: pipe_rxdatak[2] sel= 3: core_u2mac_txrx_state_1[4]" "0,1"
textline "                                     "
bitfld.long 0x00 23. " DEBUG23              ,sel= 1: utmi_dischrgvbus sel= 2: pipe_rxdatak[1] sel= 3: core_u2mac_txrx_state_1[3]" "0,1"
bitfld.long 0x00 22. "     DEBUG22                         ,sel= 1: utmi_chrgvbus sel= 2: pipe_rxdatak[0] sel= 3: core_u2mac_txrx_state_1[2]" "0,1"
textline "                                     "
bitfld.long 0x00 21. " DEBUG21              ,sel= 1: utmi_drvvbus sel= 2: pipe_rxpclk sel= 3: core_u2mac_txrx_state_1[1]" "0,1"
bitfld.long 0x00 20. "     DEBUG20                         ,sel= 1: utmi_dmpulldown sel= 2: pipe_rxtermination sel= 3: core_u2mac_txrx_state_1[0]" "0,1"
textline "                                     "
bitfld.long 0x00 19. " DEBUG19              ,sel= 1: utmi_dppulldown sel= 2: pipe_txswing sel= 3: core_u2mac_txrx_state_0[4]" "0,1"
bitfld.long 0x00 18. "     DEBUG18                         ,sel= 1: utmi_idpullup sel= 2: pipe_txmargin[2] sel= 3: core_u2mac_txrx_state_0[3]" "0,1"
textline "                                     "
bitfld.long 0x00 17. " DEBUG17              ,sel= 1: utmi_linestate[1] sel= 2: pipe_txmargin[1] sel= 3: core_u2mac_txrx_state_0[2]" "0,1"
bitfld.long 0x00 16. "     DEBUG16                         ,sel= 1: utmi_linestate[0] sel= 2: pipe_txmargin[0] sel= 3: core_u2mac_txrx_state_0[1]" "0,1"
textline "                                     "
bitfld.long 0x00 15. " DEBUG15              ,sel= 1: utmi_opmode[1] sel= 2: pipe_txdeemph[1] sel= 3: core_u2mac_txrx_state_0[0]" "0,1"
bitfld.long 0x00 14. "     DEBUG14                         ,sel= 1: utmi_opmode[0] sel= 2: pipe_txdeemph[0] sel= 3: core_u2_prt_state[4]" "0,1"
textline "                                     "
bitfld.long 0x00 13. " DEBUG13              ,sel= 1: utmi_termselect sel= 2: pipe_powerdown[1] sel= 3: core_u2_prt_state[3]" "0,1"
bitfld.long 0x00 12. "     DEBUG12                         ,sel= 1: utmi_xcvrselect[1] sel= 2: pipe_powerdown[0] sel= 3: core_u2_prt_state[2]" "0,1"
textline "                                     "
bitfld.long 0x00 11. " DEBUG11              ,sel= 1: utmi_xcvrselect[0] sel= 2: pipe_reset_n sel= 3: core_u2_prt_state[1]" "0,1"
bitfld.long 0x00 10. "     DEBUG10                         ,sel= 1: utmi_suspendm sel= 2: pipe_rxeqtraining sel= 3: core_u2_prt_state[0]" "0,1"
textline "                                     "
bitfld.long 0x00 9. " DEBUG9               ,sel= 1: utmi_reset sel= 2: pipe_rxpolarity sel= 3: core_gsts_buserraddvld" "0,1"
bitfld.long 0x00 8. "     DEBUG8                          ,sel= 1: utmi_rxerror sel= 2: pipe_txoneszeros sel= 3: debug_mclk_usof_number[0]" "0,1"
textline "                                     "
bitfld.long 0x00 7. " DEBUG7               ,sel= 1: utmi_rxvalidh sel= 2: pipe_txelecidle sel= 3: core_ltdb_link_state[3]" "0,1"
bitfld.long 0x00 6. "     DEBUG6                          ,sel= 1: utmi_rxvalid sel= 2: pipe_txdetectrxloopback sel= 3: core_ltdb_link_state[2]" "0,1"
textline "                                     "
bitfld.long 0x00 5. " DEBUG5               ,sel= 1: utmi_rxactive sel= 2: pipe_elasticitybuffermode sel= 3: core_ltdb_link_state[1]" "0,1"
bitfld.long 0x00 4. "     DEBUG4                          ,sel= 1: utmi_txready sel= 2: pipe_txdatak[3] sel= 3: core_ltdb_link_state[0]" "0,1"
textline "                                     "
bitfld.long 0x00 3. " DEBUG3               ,sel= 1: utmi_txdatah sel= 2: pipe_txdatak[2] sel= 3: core_ltdb_substate[3]" "0,1"
bitfld.long 0x00 2. "     DEBUG2                          ,sel= 1: utmi_txdata sel= 2: pipe_txdatak[1] sel= 3: core_ltdb_substate[2]" "0,1"
textline "                                     "
bitfld.long 0x00 1. " DEBUG1               ,sel= 1: utmi_databus16_8 or wordinterface sel= 2: pipe_txdatak[0] sel= 3: core_ltdb_substate[1]" "0,1"
bitfld.long 0x00 0. "     DEBUG0                          ,sel= 1: utmi_clk sel= 2: pipe_txpclk sel= 3: core_ltdb_substate[0]" "0,1"
group.long 0x710++0x3
line.long 0x00 "USB_DEV_EBC_EN,Enable External Buffer Control (EBC) for selected endpoints. Device mode only. INEP[x] Enable EBC HW throttling for IN EP (USB transmit). To enable logical EP IN #i, set [x]. In DEPCFG command for this EP, DEPCMDPAR1[x] = LimitOutstandingTxDMA should then also be set to 1 OUTEP[x] Enable EBC HW throttling for OUT EP, per bit (USB receive). To enable logical OUT EP #i, set [x+16] In DEPCFG command for this EP, DEPCMDPAR1[x] = LimitOutstandingTxDMA should then also be set to 1 x equals 15"
bitfld.long 0x00 31. " OUTEP15              ,ENABLE EBC HW throttling (USB receive) for OUT EP 15" "0,1"
bitfld.long 0x00 30. "     OUTEP14                         ,ENABLE EBC HW throttling (USB receive) for OUT EP 14" "0,1"
textline "                                     "
bitfld.long 0x00 15. " INEP15               ,ENABLE EBC HW throttling (USB transmit) for IN EP 15" "0,1"
bitfld.long 0x00 14. "     INEP14                          ,ENABLE EBC HW throttling (USB transmit) for IN EP 14" "0,1"
group.long 0x714++0x3
line.long 0x00 "USB_HOST_HUB_CTRL,The Register is a collection of various input signals that control the xHC controllers Host or Hub interfaces. These signals are used regardless if a Host or Hub is implemented or not."
bitfld.long 0x00 8.--11. " BUS_FILTER_BYPASS    ,Bus Filter Bypass bit [0]: bypass the filter for vbusvalid bit [1]: bypass the filter for pipe3_PowerPresent bit [2]: bypass the filter for avalid, bvalid, and sessend bit [3]: bypass the filter for iddig 0 = filter enabled 1 = filter disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6.--7. "    HUB_PORT_PERM_ATTACH            ,Indicates if the device attached to a downstream port is permanently attached or not. Bit 6 is the USB2 port and bit 7 is the SS port. 0 - Not permanently attached 1 - Permanently attached" "0,1,2,3"
textline "                                     "
bitfld.long 0x00 5. " XHC_BME              ,This signal is used to disable the bus mastering capability of the xHC. In a PCI system, it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b 0: Bus mastering capability is disabled. The host controller cannot use the bus master interface. 1'b 1: Bus mastering capability is enabled." "0,1"
bitfld.long 0x00 2. "     HOST_PORT_POWER_CONTROL_PRESENT ,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control. 0 - Indicates that the port does not have port power switches. 1 - Indicates that the port has port power switches." "0,1"
textline "                                     "
bitfld.long 0x00 0.--1. " HUB_PORT_OVERCURRENT ,This is the per port Overcurrent indication of the root-hub ports. Bit 0 is the USB2 port and bit 1 is the SS port. 0 - No Overcurrent 1 - Overcurrent" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree.end
tree "VIM"
tree "VIM_CFG0"
base ad:0x40F80000
width 19.
rgroup.long 0x0++0x3
line.long 0x00 "VIM_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME     ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU     ,Business Unit: 10 = Processors" "0,1,2,3"
textline "                            "
hexmask.long.word 0x00 16.--27. 1. " FUNC       ,Module ID"
bitfld.long 0x00 11.--15. "      RTL    ,RTL revision. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 8.--10. " MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM ,Custom" "0,1,2,3"
textline "                            "
bitfld.long 0x00 0.--5. " MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "VIM_INFO,The Info Register gives the configuration Inforrmation of this VIM."
hexmask.long.word 0x00 0.--10. 1. " INTERRUPTS ,Total number of Interrupts"
rgroup.long 0x8++0x3
line.long 0x00 "VIM_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the highest priority pending IRQ. valid only if the valid flag is set."
rgroup.long 0xC++0x3
line.long 0x00 "VIM_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending FIQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the highest priority pending FIQ. valid only if the valid flag is set."
rgroup.long 0x10++0x3
line.long 0x00 "VIM_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts."
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates that the num field is valid."
rgroup.long 0x14++0x3
line.long 0x00 "VIM_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts."
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates that the num field is valid."
rgroup.long 0x18++0x3
line.long 0x00 "VIM_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true."
rgroup.long 0x1C++0x3
line.long 0x00 "VIM_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true."
rgroup.long 0x20++0x3
line.long 0x00 "VIM_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set."
rgroup.long 0x24++0x3
line.long 0x00 "VIM_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set."
group.long 0x30++0x3
line.long 0x00 "VIM_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address."
group.long 0x400++0x3
line.long 0x00 "VIM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " STS        ,This is the raw status/set for interrupts Group A"
hgroup.long 0x404++0x3
hide.long 0x00 "VIM_STS_j,Masked Status and Clear Register Offset = 404h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
group.long 0x408++0x3
line.long 0x00 "VIM_INTR_EN_SET_j,Enable Set Register Offset = 408h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is the mask enable set for interrupts in Group A"
hgroup.long 0x40C++0x3
hide.long 0x00 "VIM_INTR_EN_CLR_j,Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to Fh"
in
textline "                            "
hgroup.long 0x410++0x3
hide.long 0x00 "VIM_IRQSTS_j,Masked IRQ Status and Clear Register Offset = 410h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
hgroup.long 0x414++0x3
hide.long 0x00 "VIM_FIQSTS_j,Masked FIQ Status and Clear Register Offset = 414h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
group.long 0x418++0x3
line.long 0x00 "VIM_INTMAP_j,Maps interrupts to IRQ or FIQ Offset = 418h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is interrupt map for interrupts in Group A. 0 - IRQ 1 - FIQ"
group.long 0x41C++0x3
line.long 0x00 "VIM_INTTYPE_j,Indicates whether an interrupt is a pulse or level source Offset = 41Ch + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is interrupt type for interrupts in Group A. 0 - Level 1 - Pulse"
group.long 0x1000++0x3
line.long 0x00 "VIM_PRI_INT_j,This register contains the priority for Interrupt A Offset = 1000h + (j * 4h); where j = 0h to 1FFh"
bitfld.long 0x00 0.--3. " VAL        ,This is the priority for interrupt A. 0 - Highest ... 15 - Lowest (Default)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3
line.long 0x00 "VIM_VEC_INT_j,This register contains the vector for Interrupt A Offset = 2000h + (j * 4h); where j = 0h to 1FFh"
hexmask.long 0x00 2.--31. 1. " VAL        ,This is the upper 30 bits of the 32-bits vector for interrupt A."
width 0x0B
tree.end
tree "VIM_CFG1"
base ad:0x40F80000
width 19.
rgroup.long 0x0++0x3
line.long 0x00 "VIM_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME     ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU     ,Business Unit: 10 = Processors" "0,1,2,3"
textline "                            "
hexmask.long.word 0x00 16.--27. 1. " FUNC       ,Module ID"
bitfld.long 0x00 11.--15. "      RTL    ,RTL revision. Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                            "
bitfld.long 0x00 8.--10. " MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM ,Custom" "0,1,2,3"
textline "                            "
bitfld.long 0x00 0.--5. " MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "VIM_INFO,The Info Register gives the configuration Inforrmation of this VIM."
hexmask.long.word 0x00 0.--10. 1. " INTERRUPTS ,Total number of Interrupts"
rgroup.long 0x8++0x3
line.long 0x00 "VIM_PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the highest priority pending IRQ. valid only if the valid flag is set."
rgroup.long 0xC++0x3
line.long 0x00 "VIM_PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending FIQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the highest priority pending FIQ. valid only if the valid flag is set."
rgroup.long 0x10++0x3
line.long 0x00 "VIM_IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts."
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates that the num field is valid."
rgroup.long 0x14++0x3
line.long 0x00 "VIM_FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts."
hexmask.long 0x00 0.--31. 1. " STS        ,Indicates that the num field is valid."
rgroup.long 0x18++0x3
line.long 0x00 "VIM_IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true."
rgroup.long 0x1C++0x3
line.long 0x00 "VIM_FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true."
rgroup.long 0x20++0x3
line.long 0x00 "VIM_ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set."
rgroup.long 0x24++0x3
line.long 0x00 "VIM_ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ."
bitfld.long 0x00 31. " VALID      ,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written. 0h = num field is invalid. 1h = num field is valid." "0,1"
bitfld.long 0x00 16.--19. "         PRI    ,Priority of the highest priority pending IRQ. valid only if the valid flag is set." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                            "
hexmask.long.word 0x00 0.--9. 1. " NUM        ,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set."
group.long 0x30++0x3
line.long 0x00 "VIM_DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ."
hexmask.long 0x00 2.--31. 1. " ADDR       ,Upper 30 bits of the 32-bit vector address."
group.long 0x400++0x3
line.long 0x00 "VIM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " STS        ,This is the raw status/set for interrupts Group A"
hgroup.long 0x404++0x3
hide.long 0x00 "VIM_STS_j,Masked Status and Clear Register Offset = 404h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
group.long 0x408++0x3
line.long 0x00 "VIM_INTR_EN_SET_j,Enable Set Register Offset = 408h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is the mask enable set for interrupts in Group A"
hgroup.long 0x40C++0x3
hide.long 0x00 "VIM_INTR_EN_CLR_j,Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to Fh"
in
textline "                            "
hgroup.long 0x410++0x3
hide.long 0x00 "VIM_IRQSTS_j,Masked IRQ Status and Clear Register Offset = 410h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
hgroup.long 0x414++0x3
hide.long 0x00 "VIM_FIQSTS_j,Masked FIQ Status and Clear Register Offset = 414h + (j * 20h); where j = 0h to Fh"
in
textline "                            "
group.long 0x418++0x3
line.long 0x00 "VIM_INTMAP_j,Maps interrupts to IRQ or FIQ Offset = 418h + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is interrupt map for interrupts in Group A. 0 - IRQ 1 - FIQ"
group.long 0x41C++0x3
line.long 0x00 "VIM_INTTYPE_j,Indicates whether an interrupt is a pulse or level source Offset = 41Ch + (j * 20h); where j = 0h to Fh"
hexmask.long 0x00 0.--31. 1. " MSK        ,This is interrupt type for interrupts in Group A. 0 - Level 1 - Pulse"
group.long 0x1000++0x3
line.long 0x00 "VIM_PRI_INT_j,This register contains the priority for Interrupt A Offset = 1000h + (j * 4h); where j = 0h to 1FFh"
bitfld.long 0x00 0.--3. " VAL        ,This is the priority for interrupt A. 0 - Highest ... 15 - Lowest (Default)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3
line.long 0x00 "VIM_VEC_INT_j,This register contains the vector for Interrupt A Offset = 2000h + (j * 4h); where j = 0h to 1FFh"
hexmask.long 0x00 2.--31. 1. " VAL        ,This is the upper 30 bits of the 32-bits vector for interrupt A."
width 0x0B
tree.end
tree.end
else
tree "ICSS_0"
tree "PRU_ICSSG_CFG"
tree "PRU_ICSSG0_PR1_CFG_SLV"
base eaxi:0xB026000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID_REG,Register"
hexmask.long 0x00 0.--31. 1. " ICSS_IDVER                 ,Module ID field"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_HWDIS_REG,HW Disable Register"
hexmask.long.byte 0x00 0.--7. 1. " HWDIS                      ,Read the state of the efuse bits which drive pr1_hw_disable[7:0]"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_GPCFG0_REG,GP Configuration 0 Register"
in
textline "                                         "
hgroup.long 0xC++0x3
hide.long 0x00 "ICSSG_GPCFG1_REG,GP Configuration 1 Register"
in
textline "                                         "
group.long 0x10++0x3
line.long 0x00 "ICSSG_CGR_REG,Clock Gating Register"
bitfld.long 0x00 31. " ICSS_STOP_ACK              ,ICSS" "0,1"
bitfld.long 0x00 30. "         ICSS_STOP_REQ              ,ICSS" "0,1"
textline "                                         "
bitfld.long 0x00 29. " ICSS_PWR_IDLE              ,ICSS" "0,1"
bitfld.long 0x00 17. "         IEP_CLK_EN                 ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 16. " IEP_CLK_STOP_ACK           ,IEP" "0,1"
bitfld.long 0x00 15. "         IEP_CLK_STOP_REQ           ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 14. " ECAP_CLK_EN                ,ECAP" "0,1"
bitfld.long 0x00 13. "         ECAP_CLK_STOP_ACK          ,ECAP" "0,1"
textline "                                         "
bitfld.long 0x00 12. " ECAP_CLK_STOP_REQ          ,ECAP" "0,1"
bitfld.long 0x00 11. "         UART_CLK_EN                ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 10. " UART_CLK_STOP_ACK          ,UART" "0,1"
bitfld.long 0x00 9. "         UART_CLK_STOP_REQ          ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 8. " INTC_CLK_EN                ,INTC" "0,1"
bitfld.long 0x00 7. "         INTC_CLK_STOP_ACK          ,INTC" "0,1"
textline "                                         "
bitfld.long 0x00 6. " INTC_CLK_STOP_REQ          ,INTC" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_GPECFG0_REG,GP Enc Configuration 0 Register"
bitfld.long 0x00 17. " PRU0_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU0_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU0_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU0_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU0_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU0_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU0_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU0_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x18++0x3
line.long 0x00 "ICSSG_GPECFG1_REG,GP Enc Configuration 1 Register"
bitfld.long 0x00 17. " PRU1_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU1_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU1_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU1_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU1_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU1_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU1_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU1_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_MII_RT_REG,MII_RT Event Enable Register"
bitfld.long 0x00 0. " MII_RT_EVENT_EN            ,Note: This bit field is non-functional on this device." "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_IEPCLK_REG,IEP Configuration Register"
bitfld.long 0x00 1. " IEP1_SLV_EN                ,IEP1 Master Counter Slave enable" "0,1"
bitfld.long 0x00 0. "         IEP_OCP_CLK_EN             ,Defines the source of the IEP CLK" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_SPP_REG,Scratchpad Priority and Shift Register"
bitfld.long 0x00 3. " RTU_XFR_SHIFT_EN           ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 2. "         XFR_BYTE_SHIFT_EN          ,Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations." "0,1"
textline "                                         "
bitfld.long 0x00 1. " XFR_SHIFT_EN               ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 0. "         PRU1_PAD_HP_EN             ,Reserved" "0,1"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CORE_SYNC_REG,CoreSync Configuration Register"
bitfld.long 0x00 0. " CORE_VBUSP_SYNC_EN         ," "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SA_MX_REG,SA Mux Selection Register"
bitfld.long 0x00 10.--11. " PWM3_REMAP_EN              ,pwm3_remap_en controls icss_wrap glue" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_REMAP_EN              ,pwm0_remap_en controls icss_wrap glue" "0,1,2,3"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " SA_MUX_SEL                 ,Reserved"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU0_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU0_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG0,PRU0 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG0,PRU0 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU0_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x50++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG1,PRU0 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0x54++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG1,PRU0 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU0_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0x58++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG2,PRU0 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0x5C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG2,PRU0 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU0_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0x60++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG3,PRU0 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG3,PRU0 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU0_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0x68++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG4,PRU0 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG4,PRU0 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU0_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0x70++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG5,PRU0 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0x74++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG5,PRU0 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU0_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0x78++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG6,PRU0 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG6,PRU0 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU0_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0x80++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG7,PRU0 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0x84++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG7,PRU0 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU0_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0x88++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG8,PRU0 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG8,PRU0 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU0_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0x90++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU1_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU1_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x94++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG0,PRU1 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x98++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG0,PRU1 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU1_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG1,PRU1 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG1,PRU1 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU1_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG2,PRU1 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG2,PRU1 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU1_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG3,PRU1 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG3,PRU1 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU1_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG4,PRU1 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG4,PRU1 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU1_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG5,PRU1 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG5,PRU1 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU1_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG6,PRU1 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG6,PRU1 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU1_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG7,PRU1 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG7,PRU1 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU1_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG8,PRU1 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG8,PRU1 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU1_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_PRU0_ED_RX_CFG_REG,PRU0 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU0_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU0_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_PRU0_ED_TX_CFG_REG,PRU0 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU0_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU0_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU0_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU0_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU0_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU0_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG0_REG,PRU0 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG1_REG,PRU0 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF0++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG0_REG,PRU0 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG1_REG,PRU0 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG0_REG,PRU0 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG1_REG,PRU0 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x100++0x3
line.long 0x00 "ICSSG_PRU1_ED_RX_CFG_REG,PRU1 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU1_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU1_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "ICSSG_PRU1_ED_TX_CFG_REG,PRU1 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU1_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU1_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU1_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU1_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU1_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU1_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0x108++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG0_REG,PRU1 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x10C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG1_REG,PRU1 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x110++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG0_REG,PRU1 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x114++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG1_REG,PRU1 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x118++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG0_REG,PRU1 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG1_REG,PRU1 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x124++0x3
line.long 0x00 "ICSSG_RTU0_POKE_EN0_REG,RTU0 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU0_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU0_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU0_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU0_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU0_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU0_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU0_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU0_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x12C++0x3
line.long 0x00 "ICSSG_RTU1_POKE_EN0_REG,RTU1 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU1_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU1_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU1_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU1_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU1_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU1_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU1_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU1_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x3
line.long 0x00 "ICSSG_PWM0,PWM0 Trip Configuration Register"
bitfld.long 0x00 30. " PWM0_TRIP_S                ,Trip Status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM0_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM0_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM0_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM0_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM0_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM0_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM0_DEBOUNCE_VALUE        ,Debounce counter , defines the number of core_clk required for the pulse not to get rejected"
group.long 0x134++0x3
line.long 0x00 "ICSSG_PWM1,PWM1 Trip Configuration Register"
bitfld.long 0x00 30. " PWM1_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM1_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM1_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM1_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM1_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM1_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM1_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM1_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x138++0x3
line.long 0x00 "ICSSG_PWM2,PWM2 Trip Configuration Register"
bitfld.long 0x00 30. " PWM2_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM2_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM2_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM2_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM2_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM2_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM2_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM2_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_PWM3,PWM3 Trip Configuration Register"
bitfld.long 0x00 30. " PWM3_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM3_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM3_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM3_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM3_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM3_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM3_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM3_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x140++0x3
line.long 0x00 "ICSSG_PWM0_0,PWM0 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM0_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x144++0x3
line.long 0x00 "ICSSG_PWM0_1,PWM0 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM0_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x148++0x3
line.long 0x00 "ICSSG_PWM0_2,PWM0 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM0_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x14C++0x3
line.long 0x00 "ICSSG_PWM1_0,PWM1 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM1_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x150++0x3
line.long 0x00 "ICSSG_PWM1_1,PWM1 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM1_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x154++0x3
line.long 0x00 "ICSSG_PWM1_2,PWM1 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM1_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x158++0x3
line.long 0x00 "ICSSG_PWM2_0,PWM2 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM2_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_PWM2_1,PWM2 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM2_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_PWM2_2,PWM2 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM2_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x164++0x3
line.long 0x00 "ICSSG_PWM3_0,PWM3 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM3_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x168++0x3
line.long 0x00 "ICSSG_PWM3_1,PWM3 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM3_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x16C++0x3
line.long 0x00 "ICSSG_PWM3_2,PWM3 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM3_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x170++0x3
line.long 0x00 "ICSSG_SPIN_LOCK0,Spin Lock 0 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_0       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_0          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_0       ,Spin Lock Status" "0,1"
group.long 0x174++0x3
line.long 0x00 "ICSSG_SPIN_LOCK1,Spin Lock 1 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_1       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_1          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_1       ,Spin Lock Status" "0,1"
group.long 0x178++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG0,PA STATS PDSP0 Vector 0 Register"
bitfld.long 0x00 31. " PA_PDSP0_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP0_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP0_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x17C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT0,PA STATS PDSP0 Status 0 Register"
bitfld.long 0x00 1.--3. " PA_PDSP0_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP0_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG1,PA STATS PDSP0 Vector 1 Register"
bitfld.long 0x00 31. " PA_PDSP1_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP1_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP1_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT1,PA STATS PDSP0 Status 1 Register"
bitfld.long 0x00 1.--3. " PA_PDSP1_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP1_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x188++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG2,PA STATS PDSP0 Vector 2 Register"
bitfld.long 0x00 31. " PA_PDSP2_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP2_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP2_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT2,PA STATS PDSP0 Status 2 Register"
bitfld.long 0x00 1.--3. " PA_PDSP2_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP2_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG3,PA STATS PDSP0 Vector 3 Register"
bitfld.long 0x00 31. " PA_PDSP3_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP3_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP3_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x194++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT3,PA STATS PDSP0 Status 3 Register"
bitfld.long 0x00 1.--3. " PA_PDSP3_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP3_READY             ,pa_pdsp{i}_ready" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_DRAM0"
tree "PRU_ICSSG0_DRAM0_SLV_RAM"
base eaxi:0xB000000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree "PRU_ICSSG0_DRAM1_SLV_RAM"
base eaxi:0xB002000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECAP0"
tree "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV"
base eaxi:0xB030000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_TSCNT,Time Stamp Counter Register"
hexmask.long 0x00 0.--31. 1. " TSCNT      ,Active 32-bit counter register which is used as the capture time-base ."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CNTPHS,Counter Phase Control Register"
hexmask.long 0x00 0.--31. 1. " CNTPHS     ,Counter phase value register that can be programmed for phase lag/lead. This register shadows"
group.long 0x8++0x3
line.long 0x00 "ICSSG_CAP1,Capture-1 Register"
hexmask.long 0x00 0.--31. 1. " CAP1       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.(b) Software may be useful for test purposes/initialisation.(c) APRD shadow register (that is,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_CAP2,Capture-2 Register"
hexmask.long 0x00 0.--31. 1. " CAP2       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.b) Software may be useful for test purposes.c) ACMP shadow register (that is,"
group.long 0x10++0x3
line.long 0x00 "ICSSG_CAP3,Capture-3 Register"
hexmask.long 0x00 0.--31. 1. " CAP3       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APER) register. User updates the PWM period value via this register. In this mode"
group.long 0x14++0x3
line.long 0x00 "ICSSG_CAP4,Capture-4 Register"
hexmask.long 0x00 0.--31. 1. " CAP4       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. User updates the PWM compare value via this register. In this mode"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ECCTL2_ECCTL1,ECAP Control Register 1"
bitfld.long 0x00 27.--31. " FILTER     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        APWMPOL     ,APWM output polarity select:0 = output is active high (that is, compare value defines high time)1 = output is active low (that is, compare value defines low time)Note: This is applicable only in APWM operating mode." "0,1"
textline "                              "
bitfld.long 0x00 25. " CAP_APWM   ,CAP/APWM operating mode select:0 = ECAP module operates in capture mode. This mode forces the following configuration:a) Inhibitsb) Inhibits shadow loads onc) Permits user to enable ICSSG_CAP1 to ICSSG_CAP4 register load.d) ECAP input/APWM output pin operates as a capture input.1 = ECAP module operates in APWM mode. This mode forces the following configuration:a) Resets TSCNT on CTR = PRD event (period boundary).b) Permits shadow loading on ICSSG_CAP1 and ICSSG_CAP2 registers.c) Disables loading of time-stamps into ICSSG_CAP1 to ICSSG_CAP4 registers.d) ECAP input/APWM ouput pin operates as a APWM output." "0,1"
bitfld.long 0x00 24. "         SWSYNC      ,Software forced counter (0 = writing a zero has no effect will always return a zero1 = writing a one will force aNote: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode, the synchronizing can also be done via the CTR = PRD event." "0,1"
textline "                              "
bitfld.long 0x00 22.--23. " SYNCO_SEL  ,Sync-out select:0b00 = select sync-in event to be the sync-out signal (pass through)0b01 = select CTR = PRD event to be the sync-out signal0b10 = disable sync out signal0b11 = disable sync out signalNote: Selection CTR = PRD is meaningful only in APWM mode, however can still be chosen in CAP mode, if user believes it to be useful." "0,1,2,3"
bitfld.long 0x00 21. "         SYNCI_EN    ,Counter (0 = disable sync-in option1 = enable counter (" "0,1"
textline "                              "
bitfld.long 0x00 20. " TSCNTSTP   ,Counter stop (freeze) control:0 = counter stopped1 = counter free running" "0,1"
bitfld.long 0x00 19. "         REARM_RESET ,One-shot re-arming, that is, wait for stop trigger:0 = writing a zero has no effect (reading always returns a 0)1 = writing a one arms the one-shot sequence as follows:1) resets the mod4 counter to zero2) un-freezes the mod4 counter3) enables capture register loadsNote: The re-arm function is valid in onesht or continous mode." "0,1"
textline "                              "
bitfld.long 0x00 17.--18. " STOPVALUE  ,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.0b00 = stop after capture event 10b01 = stop after capture event 20b10 = stop after capture event 30b11 = stop after capture event 4Note: STOPVALUE is compared to mod4 counter, and when equal, the following two actions occur: (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited.Note: In one shot mode, further interrupt events are blocked until re-armed, once the number of events captured has been reached ." "0,1,2,3"
bitfld.long 0x00 16. "         CONT_ONESHT ,Continuous or one-shot mode control (applicable only in capture mode):0 = operate in continuous mode1 = operate in one-shot mode" "0,1"
textline "                              "
bitfld.long 0x00 15. " FREE       ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
bitfld.long 0x00 14. "         SOFT        ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
textline "                              "
bitfld.long 0x00 9.--13. " EVTFLTPS   ,Event filter prescale select:0b00000 divide by 1 (that is, no prescale, by-pass the prescaler)0b00001 divide by 20b00010 divide by 40b00011 divide by 60b00100 divide by 80b00101 divide by 100b11110 divide by 600b11111 divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "        CAPLDEN     ,Enable loading of CAP(1-4) registers on a capture event:0 = disable CAP 1-4 register loads at capture event time1 = enable CAP(1-4) register loads at capture event time" "0,1"
textline "                              "
bitfld.long 0x00 7. " CTRRST4    ,Counter reset on capture event 4:0 = do not reset counter on capture event 4 (absolute time stamp)1 = reset counter after event 4 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 6. "         CAP4POL     ,Capture event 4 polarity select:0 = capture event 4 triggered on a rising edge (RE)1 = capture event 4 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 5. " CTRRST3    ,Counter reset on capture event 3:0 = do not reset counter on capture event 3 (absolute time stamp)1 = reset counter after event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 4. "         CAP3POL     ,Capture event 3 polarity select:0 = capture event 3 triggered on a rising edge (RE)1 = capture event 3 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 3. " CTRRST2    ,Counter reset on capture event 2:0 = do not reset counter on capture event 2 (absolute time stamp)1 = reset counter after event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 2. "         CAP2POL     ,Capture event 2 polarity select:0 = capture event 2 triggered on a rising edge (RE)1 = capture event 2 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 1. " CTRRST1    ,Counter reset on capture event 1:0 = do not reset counter on capture event 1 (absolute time stamp)1 = reset counter after event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 0. "         CAP1POL     ,Capture event 1 polarity select:0 = capture event 1 triggered on a rising edge (RE)1 = capture event 1 triggered on a falling edge (FE)" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ECFLG_ECEINT,ECAP Interrupt Enable Register"
hexmask.long.byte 0x00 24.--31. 1. " FLAG_RESV0 ,"
bitfld.long 0x00 23. "        FLAG_CMPEQ  ,Compare equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 22. " FLAG_PRDEQ ,Period equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
bitfld.long 0x00 21. "         FLAG_CNTOVF ,Counter overflow status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is active in CAP and APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 20. " FLAG_CEVT4 ,Capture event 4 status flag:0 = indicates no event occurred1 = indicates the fourth event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 19. "         FLAG_CEVT3  ,Capture event 3 status flag:0 = indicates no event occurred1 = indicates the third event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 18. " FLAG_CEVT2 ,Capture event 2 status flag:0 = indicates no event occurred1 = indicates the second event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 17. "         FLAG_CEVT1  ,Capture event 1 status flag:0 = indicates no event occurred1 = indicates the first event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 16. " FLAG_INT   ,Global interrupt status flag:0 = indicates no interrupt generated1 = indicates that an interrupt was generated from one of the following events" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         EN_RESV1    ,"
textline "                              "
bitfld.long 0x00 7. " EN_CMPEQ   ,Compare equal interrupt enable:0 = disable compare equal as an interrupt source1 = enable compare equal as an interrupt source" "0,1"
bitfld.long 0x00 6. "         EN_PRDEQ    ,Period equal interrupt enable:0 = disable period equal as an interrupt source1 = enable period equal as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 5. " EN_CNTOVF  ,Counter overflow interrupt enable:0 = disable counter overflow as an interrupt source1 = enable counter overflow as an interrupt source" "0,1"
bitfld.long 0x00 4. "         EN_CEVT4    ,Capture event 4 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 3. " EN_CEVT3   ,Capture event 3 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 2. "         EN_CEVT2    ,Capture event 2 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 1. " EN_CEVT1   ,Capture event 1 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 0. "         EN_RESV0    ," "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_ECCLR,ECAP Interrupt Clear Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV0      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Compare equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Period equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Counter overflow status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Capture event 4 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Capture event 3 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Capture event 2 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Capture event 1 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 0. " INT        ,Global interrupt clear flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the clear flag and enable further interrupts to be generated if any of the clear flags are set to 1" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_ECFRC,ECAP Interrupt Forcing Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV1      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Force compare equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CMPEQ flag bit" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Force period equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the PRDEQ flag bit" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Force counter overflow:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CNTOVF flag bit" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Force capture event 4:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT4 flag bit" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Force capture event 3:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT3 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Force capture event 2:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT2 flag bit" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Force capture event 1:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT1 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 0. " RESV0      ," "0,1"
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_PID,ECAP Peripheral Id Register"
hexmask.long 0x00 0.--31. 1. " REVID      ,TI internal data."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECC_AGGR"
tree "PRU_ICSSG0_ECC_AGGR"
base eahb:0xBF00000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                       ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                           ,bu" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                    ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                       ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " REVMAJ                       ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                       ,Custom version" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " REVMIN                       ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_VECTOR,ECC Vector Register"
in
textline "                                    "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                     ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "ICSSG_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "ICSSG_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x13C++0x3
line.long 0x00 "ICSSG_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "ICSSG_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "ICSSG_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x200++0x3
line.long 0x00 "ICSSG_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                      ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                       ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "ICSSG_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                    "
group.long 0x208++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_IEP0"
tree "PRU_ICSSG0_IEP0"
base eaxi:0xB02E000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree "PRU_ICSSG0_IEP1"
base eaxi:0xB02F000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_INTC"
tree "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"
base eaxi:0xB020000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REVISION_REG,Revision Register"
bitfld.long 0x00 30.--31. " REV_SCHEME            ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     REV_MODULE     ,Module ID"
textline "                                          "
bitfld.long 0x00 11.--15. " REV_RTL               ,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    REV_MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 6.--7. " REV_CUSTOM            ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "     REV_MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x00 4. " PRIORITY_HOLD_MODE    ,Priority Holding Mode" "0,1"
bitfld.long 0x00 2.--3. "     NEST_MODE      ,Nesting Mode" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 1. " WAKEUP_MODE           ,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_GLOBAL_ENABLE_HINT_REG,Global Host Int Enable Register"
bitfld.long 0x00 0. " ENABLE_HINT_ANY       ,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_GLB_NEST_LEVEL_REG,Global Nesting Level Register"
bitfld.long 0x00 31. " GLB_NEST_AUTO_OVR     ,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     GLB_NEST_LEVEL ,Global Nesting Level"
wgroup.long 0x20++0x3
line.long 0x00 "ICSSG_STATUS_SET_INDEX_REG,Status Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_SET_INDEX      ,Status Set Index Register (write index to set status of)"
wgroup.long 0x24++0x3
line.long 0x00 "ICSSG_STATUS_CLR_INDEX_REG,Status Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_CLR_INDEX      ,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ENABLE_SET_INDEX_REG,Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_SET_INDEX      ,Enable Set Index Register (write index to set enable of)"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_INDEX_REG,Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_CLR_INDEX      ,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_SET_INDEX_REG,Host Int Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Enable set for Host Interrupts"
group.long 0x38++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_CLR_INDEX_REG,Host Int Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x00 "ICSSG_GLB_PRI_INTR_REG,Global Prioritized Interrupt Register"
bitfld.long 0x00 31. " GLB_NONE              ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     GLB_PRI_INTR   ,Prioritized Interrupt"
group.long 0x200++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG0,Raw Status Register 0"
bitfld.long 0x00 31. " RAW_STATUS_31         ,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_30  ,Raw Status (write 1 to set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_29         ,Raw Status (write 1 to set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_28  ,Raw Status (write 1 to set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_27         ,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_26  ,Raw Status (write 1 to set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_25         ,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_24  ,Raw Status (write 1 to set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_23         ,Raw Status (write 1 to set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_22  ,Raw Status (write 1 to set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_21         ,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_20  ,Raw Status (write 1 to set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_19         ,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_18  ,Raw Status (write 1 to set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_17         ,Raw Status (write 1 to set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_16  ,Raw Status (write 1 to set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_15         ,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_14  ,Raw Status (write 1 to set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_13         ,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_12  ,Raw Status (write 1 to set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_11         ,Raw Status (write 1 to set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_10  ,Raw Status (write 1 to set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_9          ,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_8   ,Raw Status (write 1 to set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_7          ,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_6   ,Raw Status (write 1 to set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_5          ,Raw Status (write 1 to set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_4   ,Raw Status (write 1 to set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_3          ,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_2   ,Raw Status (write 1 to set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_1          ,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_0   ,Raw Status (write 1 to set) for intr_in[0]" "0,1"
group.long 0x204++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG1,Raw Status Register 1"
bitfld.long 0x00 31. " RAW_STATUS_63         ,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_62  ,Raw Status (write 1 to set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_61         ,Raw Status (write 1 to set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_60  ,Raw Status (write 1 to set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_59         ,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_58  ,Raw Status (write 1 to set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_57         ,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_56  ,Raw Status (write 1 to set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_55         ,Raw Status (write 1 to set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_54  ,Raw Status (write 1 to set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_53         ,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_52  ,Raw Status (write 1 to set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_51         ,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_50  ,Raw Status (write 1 to set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_49         ,Raw Status (write 1 to set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_48  ,Raw Status (write 1 to set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_47         ,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_46  ,Raw Status (write 1 to set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_45         ,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_44  ,Raw Status (write 1 to set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_43         ,Raw Status (write 1 to set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_42  ,Raw Status (write 1 to set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_41         ,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_40  ,Raw Status (write 1 to set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_39         ,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_38  ,Raw Status (write 1 to set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_37         ,Raw Status (write 1 to set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_36  ,Raw Status (write 1 to set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_35         ,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_34  ,Raw Status (write 1 to set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_33         ,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_32  ,Raw Status (write 1 to set) for intr_in[32]" "0,1"
group.long 0x208++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG2,Raw Status Register 2"
bitfld.long 0x00 31. " RAW_STATUS_95         ,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_94  ,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_93         ,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_92  ,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_91         ,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_90  ,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_89         ,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_88  ,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_87         ,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_86  ,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_85         ,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_84  ,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_83         ,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_82  ,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_81         ,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_80  ,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_79         ,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_78  ,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_77         ,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_76  ,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_75         ,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_74  ,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_73         ,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_72  ,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_71         ,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_70  ,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_69         ,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_68  ,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_67         ,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_66  ,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_65         ,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_64  ,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG3,Raw Status Register 3"
bitfld.long 0x00 31. " RAW_STATUS_127        ,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_126 ,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_125        ,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_124 ,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_123        ,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_122 ,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_121        ,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_120 ,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_119        ,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_118 ,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_117        ,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_116 ,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_115        ,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_114 ,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_113        ,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_112 ,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_111        ,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_110 ,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_109        ,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_108 ,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_107        ,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_106 ,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_105        ,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_104 ,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_103        ,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_102 ,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_101        ,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_100 ,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_99         ,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_98  ,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_97         ,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_96  ,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG4,Raw Status Register 4"
bitfld.long 0x00 31. " RAW_STATUS_159        ,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_158 ,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_157        ,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_156 ,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_155        ,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_154 ,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_153        ,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_152 ,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_151        ,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_150 ,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_149        ,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_148 ,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_147        ,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_146 ,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_145        ,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_144 ,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_143        ,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_142 ,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_141        ,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_140 ,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_139        ,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_138 ,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_137        ,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_136 ,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_135        ,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_134 ,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_133        ,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_132 ,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_131        ,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_130 ,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_129        ,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_128 ,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG0,Enabled Status Register 0"
bitfld.long 0x00 31. " ENA_STATUS_31         ,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_30  ,Enabled Status for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_29         ,Enabled Status for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_28  ,Enabled Status for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_27         ,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_26  ,Enabled Status for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_25         ,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_24  ,Enabled Status for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_23         ,Enabled Status for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_22  ,Enabled Status for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_21         ,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_20  ,Enabled Status for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_19         ,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_18  ,Enabled Status for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_17         ,Enabled Status for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_16  ,Enabled Status for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_15         ,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_14  ,Enabled Status for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_13         ,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_12  ,Enabled Status for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_11         ,Enabled Status for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_10  ,Enabled Status for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_9          ,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_8   ,Enabled Status for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_7          ,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_6   ,Enabled Status for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_5          ,Enabled Status for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_4   ,Enabled Status for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_3          ,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_2   ,Enabled Status for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_1          ,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_0   ,Enabled Status for intr_in[0]" "0,1"
group.long 0x284++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG1,Enabled Status Register 1"
bitfld.long 0x00 31. " ENA_STATUS_63         ,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_62  ,Enabled Status for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_61         ,Enabled Status for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_60  ,Enabled Status for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_59         ,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_58  ,Enabled Status for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_57         ,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_56  ,Enabled Status for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_55         ,Enabled Status for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_54  ,Enabled Status for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_53         ,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_52  ,Enabled Status for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_51         ,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_50  ,Enabled Status for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_49         ,Enabled Status for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_48  ,Enabled Status for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_47         ,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_46  ,Enabled Status for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_45         ,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_44  ,Enabled Status for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_43         ,Enabled Status for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_42  ,Enabled Status for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_41         ,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_40  ,Enabled Status for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_39         ,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_38  ,Enabled Status for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_37         ,Enabled Status for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_36  ,Enabled Status for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_35         ,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_34  ,Enabled Status for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_33         ,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_32  ,Enabled Status for intr_in[32]" "0,1"
group.long 0x288++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG2,Enabled Status Register 2"
bitfld.long 0x00 31. " ENA_STATUS_95         ,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_94  ,Enabled Status for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_93         ,Enabled Status for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_92  ,Enabled Status for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_91         ,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_90  ,Enabled Status for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_89         ,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_88  ,Enabled Status for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_87         ,Enabled Status for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_86  ,Enabled Status for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_85         ,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_84  ,Enabled Status for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_83         ,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_82  ,Enabled Status for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_81         ,Enabled Status for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_80  ,Enabled Status for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_79         ,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_78  ,Enabled Status for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_77         ,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_76  ,Enabled Status for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_75         ,Enabled Status for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_74  ,Enabled Status for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_73         ,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_72  ,Enabled Status for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_71         ,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_70  ,Enabled Status for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_69         ,Enabled Status for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_68  ,Enabled Status for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_67         ,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_66  ,Enabled Status for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_65         ,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_64  ,Enabled Status for slv_events_in[0]" "0,1"
group.long 0x28C++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG3,Enabled Status Register 3"
bitfld.long 0x00 31. " ENA_STATUS_127        ,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_126 ,Enabled Status for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_125        ,Enabled Status for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_124 ,Enabled Status for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_123        ,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_122 ,Enabled Status for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_121        ,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_120 ,Enabled Status for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_119        ,Enabled Status for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_118 ,Enabled Status for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_117        ,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_116 ,Enabled Status for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_115        ,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_114 ,Enabled Status for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_113        ,Enabled Status for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_112 ,Enabled Status for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_111        ,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_110 ,Enabled Status for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_109        ,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_108 ,Enabled Status for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_107        ,Enabled Status for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_106 ,Enabled Status for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_105        ,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_104 ,Enabled Status for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_103        ,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_102 ,Enabled Status for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_101        ,Enabled Status for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_100 ,Enabled Status for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_99         ,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_98  ,Enabled Status for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_97         ,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_96  ,Enabled Status for slv_events_in[32]" "0,1"
group.long 0x290++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG4,Enabled Status Register 4"
bitfld.long 0x00 31. " ENA_STATUS_159        ,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_158 ,Enabled Status for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_157        ,Enabled Status for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_156 ,Enabled Status for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_155        ,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_154 ,Enabled Status for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_153        ,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_152 ,Enabled Status for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_151        ,Enabled Status for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_150 ,Enabled Status for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_149        ,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_148 ,Enabled Status for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_147        ,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_146 ,Enabled Status for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_145        ,Enabled Status for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_144 ,Enabled Status for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_143        ,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_142 ,Enabled Status for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_141        ,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_140 ,Enabled Status for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_139        ,Enabled Status for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_138 ,Enabled Status for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_137        ,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_136 ,Enabled Status for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_135        ,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_134 ,Enabled Status for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_133        ,Enabled Status for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_132 ,Enabled Status for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_131        ,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_130 ,Enabled Status for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_129        ,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_128 ,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_ENABLE_REG0,Enable Register 0"
bitfld.long 0x00 31. " ENABLE_31             ,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30      ,Enable (set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29             ,Enable (set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28      ,Enable (set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27             ,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26      ,Enable (set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25             ,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24      ,Enable (set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23             ,Enable (set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22      ,Enable (set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21             ,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20      ,Enable (set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19             ,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18      ,Enable (set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17             ,Enable (set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16      ,Enable (set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15             ,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14      ,Enable (set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13             ,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12      ,Enable (set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11             ,Enable (set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10      ,Enable (set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9              ,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8       ,Enable (set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7              ,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6       ,Enable (set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5              ,Enable (set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4       ,Enable (set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3              ,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2       ,Enable (set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1              ,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0       ,Enable (set) for intr_in[0]" "0,1"
group.long 0x304++0x3
line.long 0x00 "ICSSG_ENABLE_REG1,Enable Register 1"
bitfld.long 0x00 31. " ENABLE_63             ,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62      ,Enable (set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61             ,Enable (set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60      ,Enable (set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59             ,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58      ,Enable (set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57             ,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56      ,Enable (set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55             ,Enable (set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54      ,Enable (set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53             ,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52      ,Enable (set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51             ,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50      ,Enable (set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49             ,Enable (set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48      ,Enable (set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47             ,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46      ,Enable (set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45             ,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44      ,Enable (set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43             ,Enable (set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42      ,Enable (set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41             ,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40      ,Enable (set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39             ,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38      ,Enable (set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37             ,Enable (set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36      ,Enable (set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35             ,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34      ,Enable (set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33             ,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32      ,Enable (set) for intr_in[32]" "0,1"
group.long 0x308++0x3
line.long 0x00 "ICSSG_ENABLE_REG2,Enable Register 2"
bitfld.long 0x00 31. " ENABLE_95             ,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94      ,Enable (set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93             ,Enable (set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92      ,Enable (set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91             ,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90      ,Enable (set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89             ,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88      ,Enable (set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87             ,Enable (set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86      ,Enable (set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85             ,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84      ,Enable (set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83             ,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82      ,Enable (set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81             ,Enable (set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80      ,Enable (set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79             ,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78      ,Enable (set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77             ,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76      ,Enable (set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75             ,Enable (set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74      ,Enable (set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73             ,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72      ,Enable (set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71             ,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70      ,Enable (set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69             ,Enable (set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68      ,Enable (set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67             ,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66      ,Enable (set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65             ,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64      ,Enable (set) for slv_events_in[0]" "0,1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_ENABLE_REG3,Enable Register 3"
bitfld.long 0x00 31. " ENABLE_127            ,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126     ,Enable (set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125            ,Enable (set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124     ,Enable (set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123            ,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122     ,Enable (set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121            ,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120     ,Enable (set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119            ,Enable (set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118     ,Enable (set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117            ,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116     ,Enable (set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115            ,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114     ,Enable (set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113            ,Enable (set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112     ,Enable (set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111            ,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110     ,Enable (set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109            ,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108     ,Enable (set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107            ,Enable (set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106     ,Enable (set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105            ,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104     ,Enable (set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103            ,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102     ,Enable (set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101            ,Enable (set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100     ,Enable (set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99             ,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98      ,Enable (set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97             ,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96      ,Enable (set) for slv_events_in[32]" "0,1"
group.long 0x310++0x3
line.long 0x00 "ICSSG_ENABLE_REG4,Enable Register 4"
bitfld.long 0x00 31. " ENABLE_159            ,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158     ,Enable (set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157            ,Enable (set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156     ,Enable (set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155            ,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154     ,Enable (set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153            ,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152     ,Enable (set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151            ,Enable (set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150     ,Enable (set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149            ,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148     ,Enable (set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147            ,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146     ,Enable (set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145            ,Enable (set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144     ,Enable (set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143            ,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142     ,Enable (set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141            ,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140     ,Enable (set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139            ,Enable (set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138     ,Enable (set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137            ,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136     ,Enable (set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135            ,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134     ,Enable (set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133            ,Enable (set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132     ,Enable (set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131            ,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130     ,Enable (set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129            ,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128     ,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG0,Enable Clear Register 0"
bitfld.long 0x00 31. " ENABLE_31_CLR         ,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30_CLR  ,Enable clear for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29_CLR         ,Enable clear for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28_CLR  ,Enable clear for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27_CLR         ,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26_CLR  ,Enable clear for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25_CLR         ,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24_CLR  ,Enable clear for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23_CLR         ,Enable clear for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22_CLR  ,Enable clear for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21_CLR         ,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20_CLR  ,Enable clear for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19_CLR         ,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18_CLR  ,Enable clear for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17_CLR         ,Enable clear for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16_CLR  ,Enable clear for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15_CLR         ,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14_CLR  ,Enable clear for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13_CLR         ,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12_CLR  ,Enable clear for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11_CLR         ,Enable clear for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10_CLR  ,Enable clear for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9_CLR          ,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8_CLR   ,Enable clear for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7_CLR          ,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6_CLR   ,Enable clear for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5_CLR          ,Enable clear for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4_CLR   ,Enable clear for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3_CLR          ,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2_CLR   ,Enable clear for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1_CLR          ,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0_CLR   ,Enable clear for intr_in[0]" "0,1"
group.long 0x384++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG1,Enable Clear Register 1"
bitfld.long 0x00 31. " ENABLE_63_CLR         ,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62_CLR  ,Enable clear for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61_CLR         ,Enable clear for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60_CLR  ,Enable clear for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59_CLR         ,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58_CLR  ,Enable clear for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57_CLR         ,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56_CLR  ,Enable clear for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55_CLR         ,Enable clear for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54_CLR  ,Enable clear for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53_CLR         ,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52_CLR  ,Enable clear for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51_CLR         ,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50_CLR  ,Enable clear for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49_CLR         ,Enable clear for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48_CLR  ,Enable clear for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47_CLR         ,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46_CLR  ,Enable clear for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45_CLR         ,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44_CLR  ,Enable clear for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43_CLR         ,Enable clear for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42_CLR  ,Enable clear for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41_CLR         ,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40_CLR  ,Enable clear for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39_CLR         ,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38_CLR  ,Enable clear for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37_CLR         ,Enable clear for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36_CLR  ,Enable clear for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35_CLR         ,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34_CLR  ,Enable clear for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33_CLR         ,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32_CLR  ,Enable clear for intr_in[32]" "0,1"
group.long 0x388++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG2,Enable Clear Register 2"
bitfld.long 0x00 31. " ENABLE_95_CLR         ,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94_CLR  ,Enable clear for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93_CLR         ,Enable clear for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92_CLR  ,Enable clear for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91_CLR         ,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90_CLR  ,Enable clear for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89_CLR         ,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88_CLR  ,Enable clear for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87_CLR         ,Enable clear for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86_CLR  ,Enable clear for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85_CLR         ,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84_CLR  ,Enable clear for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83_CLR         ,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82_CLR  ,Enable clear for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81_CLR         ,Enable clear for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80_CLR  ,Enable clear for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79_CLR         ,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78_CLR  ,Enable clear for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77_CLR         ,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76_CLR  ,Enable clear for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75_CLR         ,Enable clear for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74_CLR  ,Enable clear for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73_CLR         ,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72_CLR  ,Enable clear for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71_CLR         ,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70_CLR  ,Enable clear for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69_CLR         ,Enable clear for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68_CLR  ,Enable clear for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67_CLR         ,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66_CLR  ,Enable clear for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65_CLR         ,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64_CLR  ,Enable clear for slv_events_in[0]" "0,1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG3,Enable Clear Register 3"
bitfld.long 0x00 31. " ENABLE_127_CLR        ,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126_CLR ,Enable clear for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125_CLR        ,Enable clear for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124_CLR ,Enable clear for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123_CLR        ,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122_CLR ,Enable clear for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121_CLR        ,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120_CLR ,Enable clear for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119_CLR        ,Enable clear for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118_CLR ,Enable clear for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117_CLR        ,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116_CLR ,Enable clear for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115_CLR        ,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114_CLR ,Enable clear for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113_CLR        ,Enable clear for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112_CLR ,Enable clear for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111_CLR        ,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110_CLR ,Enable clear for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109_CLR        ,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108_CLR ,Enable clear for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107_CLR        ,Enable clear for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106_CLR ,Enable clear for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105_CLR        ,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104_CLR ,Enable clear for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103_CLR        ,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102_CLR ,Enable clear for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101_CLR        ,Enable clear for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100_CLR ,Enable clear for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99_CLR         ,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98_CLR  ,Enable clear for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97_CLR         ,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96_CLR  ,Enable clear for slv_events_in[32]" "0,1"
group.long 0x390++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG4,Enable Clear Register 4"
bitfld.long 0x00 31. " ENABLE_159_CLR        ,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158_CLR ,Enable clear for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157_CLR        ,Enable clear for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156_CLR ,Enable clear for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155_CLR        ,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154_CLR ,Enable clear for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153_CLR        ,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152_CLR ,Enable clear for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151_CLR        ,Enable clear for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150_CLR ,Enable clear for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149_CLR        ,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148_CLR ,Enable clear for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147_CLR        ,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146_CLR ,Enable clear for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145_CLR        ,Enable clear for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144_CLR ,Enable clear for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143_CLR        ,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142_CLR ,Enable clear for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141_CLR        ,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140_CLR ,Enable clear for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139_CLR        ,Enable clear for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138_CLR ,Enable clear for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137_CLR        ,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136_CLR ,Enable clear for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135_CLR        ,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134_CLR ,Enable clear for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133_CLR        ,Enable clear for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132_CLR ,Enable clear for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131_CLR        ,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130_CLR ,Enable clear for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129_CLR        ,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128_CLR ,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x3
line.long 0x00 "ICSSG_CH_MAP_REG0,Interrupt Channel Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " CH_MAP_3              ,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_2       ,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_1              ,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_0       ,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x404++0x3
line.long 0x00 "ICSSG_CH_MAP_REG1,Interrupt Channel Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " CH_MAP_7              ,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_6       ,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_5              ,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_4       ,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x408++0x3
line.long 0x00 "ICSSG_CH_MAP_REG2,Interrupt Channel Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " CH_MAP_11             ,Interrupt Channel Map for intr_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_10      ,Interrupt Channel Map for intr_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_9              ,Interrupt Channel Map for intr_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_8       ,Interrupt Channel Map for intr_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG3,Interrupt Channel Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " CH_MAP_15             ,Interrupt Channel Map for intr_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_14      ,Interrupt Channel Map for intr_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_13             ,Interrupt Channel Map for intr_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_12      ,Interrupt Channel Map for intr_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x410++0x3
line.long 0x00 "ICSSG_CH_MAP_REG4,Interrupt Channel Map Register for 16 to 16+3"
bitfld.long 0x00 24.--28. " CH_MAP_19             ,Interrupt Channel Map for intr_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_18      ,Interrupt Channel Map for intr_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_17             ,Interrupt Channel Map for intr_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_16      ,Interrupt Channel Map for intr_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x414++0x3
line.long 0x00 "ICSSG_CH_MAP_REG5,Interrupt Channel Map Register for 20 to 20+3"
bitfld.long 0x00 24.--28. " CH_MAP_23             ,Interrupt Channel Map for intr_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_22      ,Interrupt Channel Map for intr_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_21             ,Interrupt Channel Map for intr_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_20      ,Interrupt Channel Map for intr_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x418++0x3
line.long 0x00 "ICSSG_CH_MAP_REG6,Interrupt Channel Map Register for 24 to 24+3"
bitfld.long 0x00 24.--28. " CH_MAP_27             ,Interrupt Channel Map for intr_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_26      ,Interrupt Channel Map for intr_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_25             ,Interrupt Channel Map for intr_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_24      ,Interrupt Channel Map for intr_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG7,Interrupt Channel Map Register for 28 to 28+3"
bitfld.long 0x00 24.--28. " CH_MAP_31             ,Interrupt Channel Map for intr_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_30      ,Interrupt Channel Map for intr_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_29             ,Interrupt Channel Map for intr_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_28      ,Interrupt Channel Map for intr_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x420++0x3
line.long 0x00 "ICSSG_CH_MAP_REG8,Interrupt Channel Map Register for 32 to 32+3"
bitfld.long 0x00 24.--28. " CH_MAP_35             ,Interrupt Channel Map for intr_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_34      ,Interrupt Channel Map for intr_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_33             ,Interrupt Channel Map for intr_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_32      ,Interrupt Channel Map for intr_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x424++0x3
line.long 0x00 "ICSSG_CH_MAP_REG9,Interrupt Channel Map Register for 36 to 36+3"
bitfld.long 0x00 24.--28. " CH_MAP_39             ,Interrupt Channel Map for intr_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_38      ,Interrupt Channel Map for intr_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_37             ,Interrupt Channel Map for intr_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_36      ,Interrupt Channel Map for intr_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x428++0x3
line.long 0x00 "ICSSG_CH_MAP_REG10,Interrupt Channel Map Register for 40 to 40+3"
bitfld.long 0x00 24.--28. " CH_MAP_43             ,Interrupt Channel Map for intr_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_42      ,Interrupt Channel Map for intr_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_41             ,Interrupt Channel Map for intr_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_40      ,Interrupt Channel Map for intr_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG11,Interrupt Channel Map Register for 44 to 44+3"
bitfld.long 0x00 24.--28. " CH_MAP_47             ,Interrupt Channel Map for intr_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_46      ,Interrupt Channel Map for intr_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_45             ,Interrupt Channel Map for intr_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_44      ,Interrupt Channel Map for intr_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x430++0x3
line.long 0x00 "ICSSG_CH_MAP_REG12,Interrupt Channel Map Register for 48 to 48+3"
bitfld.long 0x00 24.--28. " CH_MAP_51             ,Interrupt Channel Map for intr_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_50      ,Interrupt Channel Map for intr_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_49             ,Interrupt Channel Map for intr_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_48      ,Interrupt Channel Map for intr_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x434++0x3
line.long 0x00 "ICSSG_CH_MAP_REG13,Interrupt Channel Map Register for 52 to 52+3"
bitfld.long 0x00 24.--28. " CH_MAP_55             ,Interrupt Channel Map for intr_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_54      ,Interrupt Channel Map for intr_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_53             ,Interrupt Channel Map for intr_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_52      ,Interrupt Channel Map for intr_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x438++0x3
line.long 0x00 "ICSSG_CH_MAP_REG14,Interrupt Channel Map Register for 56 to 56+3"
bitfld.long 0x00 24.--28. " CH_MAP_59             ,Interrupt Channel Map for intr_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_58      ,Interrupt Channel Map for intr_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_57             ,Interrupt Channel Map for intr_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_56      ,Interrupt Channel Map for intr_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG15,Interrupt Channel Map Register for 60 to 60+3"
bitfld.long 0x00 24.--28. " CH_MAP_63             ,Interrupt Channel Map for intr_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_62      ,Interrupt Channel Map for intr_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_61             ,Interrupt Channel Map for intr_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_60      ,Interrupt Channel Map for intr_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x440++0x3
line.long 0x00 "ICSSG_CH_MAP_REG16,Interrupt Channel Map Register for 64 to 64+3"
bitfld.long 0x00 24.--28. " CH_MAP_67             ,Interrupt Channel Map for slv_events_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_66      ,Interrupt Channel Map for slv_events_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_65             ,Interrupt Channel Map for slv_events_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_64      ,Interrupt Channel Map for slv_events_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x444++0x3
line.long 0x00 "ICSSG_CH_MAP_REG17,Interrupt Channel Map Register for 68 to 68+3"
bitfld.long 0x00 24.--28. " CH_MAP_71             ,Interrupt Channel Map for slv_events_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_70      ,Interrupt Channel Map for slv_events_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_69             ,Interrupt Channel Map for slv_events_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_68      ,Interrupt Channel Map for slv_events_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x448++0x3
line.long 0x00 "ICSSG_CH_MAP_REG18,Interrupt Channel Map Register for 72 to 72+3"
bitfld.long 0x00 24.--28. " CH_MAP_75             ,Interrupt Channel Map for slv_events_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_74      ,Interrupt Channel Map for slv_events_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_73             ,Interrupt Channel Map for slv_events_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_72      ,Interrupt Channel Map for slv_events_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG19,Interrupt Channel Map Register for 76 to 76+3"
bitfld.long 0x00 24.--28. " CH_MAP_79             ,Interrupt Channel Map for slv_events_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_78      ,Interrupt Channel Map for slv_events_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_77             ,Interrupt Channel Map for slv_events_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_76      ,Interrupt Channel Map for slv_events_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x450++0x3
line.long 0x00 "ICSSG_CH_MAP_REG20,Interrupt Channel Map Register for 80 to 80+3"
bitfld.long 0x00 24.--28. " CH_MAP_83             ,Interrupt Channel Map for slv_events_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_82      ,Interrupt Channel Map for slv_events_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_81             ,Interrupt Channel Map for slv_events_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_80      ,Interrupt Channel Map for slv_events_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x454++0x3
line.long 0x00 "ICSSG_CH_MAP_REG21,Interrupt Channel Map Register for 84 to 84+3"
bitfld.long 0x00 24.--28. " CH_MAP_87             ,Interrupt Channel Map for slv_events_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_86      ,Interrupt Channel Map for slv_events_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_85             ,Interrupt Channel Map for slv_events_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_84      ,Interrupt Channel Map for slv_events_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x458++0x3
line.long 0x00 "ICSSG_CH_MAP_REG22,Interrupt Channel Map Register for 88 to 88+3"
bitfld.long 0x00 24.--28. " CH_MAP_91             ,Interrupt Channel Map for slv_events_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_90      ,Interrupt Channel Map for slv_events_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_89             ,Interrupt Channel Map for slv_events_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_88      ,Interrupt Channel Map for slv_events_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG23,Interrupt Channel Map Register for 92 to 92+3"
bitfld.long 0x00 24.--28. " CH_MAP_95             ,Interrupt Channel Map for slv_events_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_94      ,Interrupt Channel Map for slv_events_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_93             ,Interrupt Channel Map for slv_events_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_92      ,Interrupt Channel Map for slv_events_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x460++0x3
line.long 0x00 "ICSSG_CH_MAP_REG24,Interrupt Channel Map Register for 96 to 96+3"
bitfld.long 0x00 24.--28. " CH_MAP_99             ,Interrupt Channel Map for slv_events_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_98      ,Interrupt Channel Map for slv_events_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_97             ,Interrupt Channel Map for slv_events_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_96      ,Interrupt Channel Map for slv_events_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x464++0x3
line.long 0x00 "ICSSG_CH_MAP_REG25,Interrupt Channel Map Register for 100 to 100+3"
bitfld.long 0x00 24.--28. " CH_MAP_103            ,Interrupt Channel Map for slv_events_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_102     ,Interrupt Channel Map for slv_events_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_101            ,Interrupt Channel Map for slv_events_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_100     ,Interrupt Channel Map for slv_events_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x468++0x3
line.long 0x00 "ICSSG_CH_MAP_REG26,Interrupt Channel Map Register for 104 to 104+3"
bitfld.long 0x00 24.--28. " CH_MAP_107            ,Interrupt Channel Map for slv_events_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_106     ,Interrupt Channel Map for slv_events_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_105            ,Interrupt Channel Map for slv_events_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_104     ,Interrupt Channel Map for slv_events_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG27,Interrupt Channel Map Register for 108 to 108+3"
bitfld.long 0x00 24.--28. " CH_MAP_111            ,Interrupt Channel Map for slv_events_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_110     ,Interrupt Channel Map for slv_events_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_109            ,Interrupt Channel Map for slv_events_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_108     ,Interrupt Channel Map for slv_events_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x470++0x3
line.long 0x00 "ICSSG_CH_MAP_REG28,Interrupt Channel Map Register for 112 to 112+3"
bitfld.long 0x00 24.--28. " CH_MAP_115            ,Interrupt Channel Map for slv_events_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_114     ,Interrupt Channel Map for slv_events_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_113            ,Interrupt Channel Map for slv_events_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_112     ,Interrupt Channel Map for slv_events_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x474++0x3
line.long 0x00 "ICSSG_CH_MAP_REG29,Interrupt Channel Map Register for 116 to 116+3"
bitfld.long 0x00 24.--28. " CH_MAP_119            ,Interrupt Channel Map for slv_events_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_118     ,Interrupt Channel Map for slv_events_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_117            ,Interrupt Channel Map for slv_events_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_116     ,Interrupt Channel Map for slv_events_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x478++0x3
line.long 0x00 "ICSSG_CH_MAP_REG30,Interrupt Channel Map Register for 120 to 120+3"
bitfld.long 0x00 24.--28. " CH_MAP_123            ,Interrupt Channel Map for slv_events_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_122     ,Interrupt Channel Map for slv_events_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_121            ,Interrupt Channel Map for slv_events_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_120     ,Interrupt Channel Map for slv_events_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG31,Interrupt Channel Map Register for 124 to 124+3"
bitfld.long 0x00 24.--28. " CH_MAP_127            ,Interrupt Channel Map for slv_events_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_126     ,Interrupt Channel Map for slv_events_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_125            ,Interrupt Channel Map for slv_events_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_124     ,Interrupt Channel Map for slv_events_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x480++0x3
line.long 0x00 "ICSSG_CH_MAP_REG32,Interrupt Channel Map Register for 128 to 128+3"
bitfld.long 0x00 24.--28. " CH_MAP_131            ,Interrupt Channel Map for slv_events_in[67]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_130     ,Interrupt Channel Map for slv_events_in[66]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_129            ,Interrupt Channel Map for slv_events_in[65]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_128     ,Interrupt Channel Map for slv_events_in[64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x484++0x3
line.long 0x00 "ICSSG_CH_MAP_REG33,Interrupt Channel Map Register for 132 to 132+3"
bitfld.long 0x00 24.--28. " CH_MAP_135            ,Interrupt Channel Map for slv_events_in[71]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_134     ,Interrupt Channel Map for slv_events_in[70]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_133            ,Interrupt Channel Map for slv_events_in[69]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_132     ,Interrupt Channel Map for slv_events_in[68]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x488++0x3
line.long 0x00 "ICSSG_CH_MAP_REG34,Interrupt Channel Map Register for 136 to 136+3"
bitfld.long 0x00 24.--28. " CH_MAP_139            ,Interrupt Channel Map for slv_events_in[75]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_138     ,Interrupt Channel Map for slv_events_in[74]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_137            ,Interrupt Channel Map for slv_events_in[73]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_136     ,Interrupt Channel Map for slv_events_in[72]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG35,Interrupt Channel Map Register for 140 to 140+3"
bitfld.long 0x00 24.--28. " CH_MAP_143            ,Interrupt Channel Map for slv_events_in[79]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_142     ,Interrupt Channel Map for slv_events_in[78]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_141            ,Interrupt Channel Map for slv_events_in[77]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_140     ,Interrupt Channel Map for slv_events_in[76]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x490++0x3
line.long 0x00 "ICSSG_CH_MAP_REG36,Interrupt Channel Map Register for 144 to 144+3"
bitfld.long 0x00 24.--28. " CH_MAP_147            ,Interrupt Channel Map for slv_events_in[83]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_146     ,Interrupt Channel Map for slv_events_in[82]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_145            ,Interrupt Channel Map for slv_events_in[81]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_144     ,Interrupt Channel Map for slv_events_in[80]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x494++0x3
line.long 0x00 "ICSSG_CH_MAP_REG37,Interrupt Channel Map Register for 148 to 148+3"
bitfld.long 0x00 24.--28. " CH_MAP_151            ,Interrupt Channel Map for slv_events_in[87]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_150     ,Interrupt Channel Map for slv_events_in[86]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_149            ,Interrupt Channel Map for slv_events_in[85]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_148     ,Interrupt Channel Map for slv_events_in[84]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x498++0x3
line.long 0x00 "ICSSG_CH_MAP_REG38,Interrupt Channel Map Register for 152 to 152+3"
bitfld.long 0x00 24.--28. " CH_MAP_155            ,Interrupt Channel Map for slv_events_in[91]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_154     ,Interrupt Channel Map for slv_events_in[90]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_153            ,Interrupt Channel Map for slv_events_in[89]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_152     ,Interrupt Channel Map for slv_events_in[88]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG39,Interrupt Channel Map Register for 156 to 156+3"
bitfld.long 0x00 24.--28. " CH_MAP_159            ,Interrupt Channel Map for slv_events_in[95]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_158     ,Interrupt Channel Map for slv_events_in[94]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_157            ,Interrupt Channel Map for slv_events_in[93]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_156     ,Interrupt Channel Map for slv_events_in[92]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x800++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG0,Host Interrupt Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " HINT_MAP_3            ,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_2     ,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_1            ,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_0     ,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x804++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG1,Host Interrupt Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " HINT_MAP_7            ,Host Interrupt Map for Channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_6     ,Host Interrupt Map for Channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_5            ,Host Interrupt Map for Channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_4     ,Host Interrupt Map for Channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x808++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG2,Host Interrupt Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " HINT_MAP_11           ,Host Interrupt Map for Channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_10    ,Host Interrupt Map for Channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_9            ,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_8     ,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG3,Host Interrupt Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " HINT_MAP_15           ,Host Interrupt Map for Channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_14    ,Host Interrupt Map for Channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_13           ,Host Interrupt Map for Channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_12    ,Host Interrupt Map for Channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x810++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG4,Host Interrupt Map Register for 16 to 16+4"
bitfld.long 0x00 24.--28. " HINT_MAP_19           ,Host Interrupt Map for Channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_18    ,Host Interrupt Map for Channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_17           ,Host Interrupt Map for Channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_16    ,Host Interrupt Map for Channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x900++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG0,Host Int 0 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_0           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_0     ,Host Int 0 Prioritized Interrupt"
rgroup.long 0x904++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG1,Host Int 1 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_1           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_1     ,Host Int 1 Prioritized Interrupt"
rgroup.long 0x908++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG2,Host Int 2 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_2           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_2     ,Host Int 2 Prioritized Interrupt"
rgroup.long 0x90C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG3,Host Int 3 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_3           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_3     ,Host Int 3 Prioritized Interrupt"
rgroup.long 0x910++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG4,Host Int 4 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_4           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_4     ,Host Int 4 Prioritized Interrupt"
rgroup.long 0x914++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG5,Host Int 5 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_5           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_5     ,Host Int 5 Prioritized Interrupt"
rgroup.long 0x918++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG6,Host Int 6 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_6           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_6     ,Host Int 6 Prioritized Interrupt"
rgroup.long 0x91C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG7,Host Int 7 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_7           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_7     ,Host Int 7 Prioritized Interrupt"
rgroup.long 0x920++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG8,Host Int 8 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_8           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_8     ,Host Int 8 Prioritized Interrupt"
rgroup.long 0x924++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG9,Host Int 9 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_9           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_9     ,Host Int 9 Prioritized Interrupt"
rgroup.long 0x928++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG10,Host Int 10 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_10          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_10    ,Host Int 10 Prioritized Interrupt"
rgroup.long 0x92C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG11,Host Int 11 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_11          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_11    ,Host Int 11 Prioritized Interrupt"
rgroup.long 0x930++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG12,Host Int 12 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_12          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_12    ,Host Int 12 Prioritized Interrupt"
rgroup.long 0x934++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG13,Host Int 13 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_13          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_13    ,Host Int 13 Prioritized Interrupt"
rgroup.long 0x938++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG14,Host Int 14 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_14          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_14    ,Host Int 14 Prioritized Interrupt"
rgroup.long 0x93C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG15,Host Int 15 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_15          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_15    ,Host Int 15 Prioritized Interrupt"
rgroup.long 0x940++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG16,Host Int 16 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_16          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_16    ,Host Int 16 Prioritized Interrupt"
rgroup.long 0x944++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG17,Host Int 17 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_17          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_17    ,Host Int 17 Prioritized Interrupt"
rgroup.long 0x948++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG18,Host Int 18 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_18          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_18    ,Host Int 18 Prioritized Interrupt"
rgroup.long 0x94C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG19,Host Int 19 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_19          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_19    ,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x3
line.long 0x00 "ICSSG_POLARITY_REG0,Polarity Register 0"
bitfld.long 0x00 31. " POLARITY_31           ,Polarity for intr_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_30    ,Polarity for intr_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_29           ,Polarity for intr_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_28    ,Polarity for intr_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_27           ,Polarity for intr_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_26    ,Polarity for intr_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_25           ,Polarity for intr_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_24    ,Polarity for intr_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_23           ,Polarity for intr_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_22    ,Polarity for intr_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_21           ,Polarity for intr_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_20    ,Polarity for intr_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_19           ,Polarity for intr_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_18    ,Polarity for intr_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_17           ,Polarity for intr_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_16    ,Polarity for intr_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_15           ,Polarity for intr_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_14    ,Polarity for intr_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_13           ,Polarity for intr_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_12    ,Polarity for intr_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_11           ,Polarity for intr_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_10    ,Polarity for intr_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_9            ,Polarity for intr_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_8     ,Polarity for intr_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_7            ,Polarity for intr_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_6     ,Polarity for intr_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_5            ,Polarity for intr_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_4     ,Polarity for intr_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_3            ,Polarity for intr_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_2     ,Polarity for intr_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_1            ,Polarity for intr_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_0     ,Polarity for intr_in[0]0=low" "0,1"
group.long 0xD04++0x3
line.long 0x00 "ICSSG_POLARITY_REG1,Polarity Register 1"
bitfld.long 0x00 31. " POLARITY_63           ,Polarity for intr_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_62    ,Polarity for intr_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_61           ,Polarity for intr_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_60    ,Polarity for intr_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_59           ,Polarity for intr_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_58    ,Polarity for intr_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_57           ,Polarity for intr_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_56    ,Polarity for intr_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_55           ,Polarity for intr_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_54    ,Polarity for intr_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_53           ,Polarity for intr_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_52    ,Polarity for intr_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_51           ,Polarity for intr_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_50    ,Polarity for intr_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_49           ,Polarity for intr_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_48    ,Polarity for intr_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_47           ,Polarity for intr_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_46    ,Polarity for intr_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_45           ,Polarity for intr_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_44    ,Polarity for intr_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_43           ,Polarity for intr_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_42    ,Polarity for intr_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_41           ,Polarity for intr_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_40    ,Polarity for intr_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_39           ,Polarity for intr_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_38    ,Polarity for intr_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_37           ,Polarity for intr_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_36    ,Polarity for intr_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_35           ,Polarity for intr_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_34    ,Polarity for intr_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_33           ,Polarity for intr_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_32    ,Polarity for intr_in[32]0=low" "0,1"
group.long 0xD08++0x3
line.long 0x00 "ICSSG_POLARITY_REG2,Polarity Register 2"
bitfld.long 0x00 31. " POLARITY_95           ,Polarity for slv_events_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_94    ,Polarity for slv_events_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_93           ,Polarity for slv_events_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_92    ,Polarity for slv_events_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_91           ,Polarity for slv_events_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_90    ,Polarity for slv_events_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_89           ,Polarity for slv_events_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_88    ,Polarity for slv_events_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_87           ,Polarity for slv_events_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_86    ,Polarity for slv_events_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_85           ,Polarity for slv_events_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_84    ,Polarity for slv_events_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_83           ,Polarity for slv_events_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_82    ,Polarity for slv_events_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_81           ,Polarity for slv_events_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_80    ,Polarity for slv_events_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_79           ,Polarity for slv_events_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_78    ,Polarity for slv_events_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_77           ,Polarity for slv_events_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_76    ,Polarity for slv_events_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_75           ,Polarity for slv_events_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_74    ,Polarity for slv_events_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_73           ,Polarity for slv_events_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_72    ,Polarity for slv_events_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_71           ,Polarity for slv_events_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_70    ,Polarity for slv_events_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_69           ,Polarity for slv_events_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_68    ,Polarity for slv_events_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_67           ,Polarity for slv_events_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_66    ,Polarity for slv_events_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_65           ,Polarity for slv_events_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_64    ,Polarity for slv_events_in[0]0=low" "0,1"
group.long 0xD0C++0x3
line.long 0x00 "ICSSG_POLARITY_REG3,Polarity Register 3"
bitfld.long 0x00 31. " POLARITY_127          ,Polarity for slv_events_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_126   ,Polarity for slv_events_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_125          ,Polarity for slv_events_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_124   ,Polarity for slv_events_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_123          ,Polarity for slv_events_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_122   ,Polarity for slv_events_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_121          ,Polarity for slv_events_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_120   ,Polarity for slv_events_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_119          ,Polarity for slv_events_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_118   ,Polarity for slv_events_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_117          ,Polarity for slv_events_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_116   ,Polarity for slv_events_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_115          ,Polarity for slv_events_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_114   ,Polarity for slv_events_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_113          ,Polarity for slv_events_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_112   ,Polarity for slv_events_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_111          ,Polarity for slv_events_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_110   ,Polarity for slv_events_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_109          ,Polarity for slv_events_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_108   ,Polarity for slv_events_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_107          ,Polarity for slv_events_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_106   ,Polarity for slv_events_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_105          ,Polarity for slv_events_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_104   ,Polarity for slv_events_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_103          ,Polarity for slv_events_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_102   ,Polarity for slv_events_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_101          ,Polarity for slv_events_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_100   ,Polarity for slv_events_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_99           ,Polarity for slv_events_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_98    ,Polarity for slv_events_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_97           ,Polarity for slv_events_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_96    ,Polarity for slv_events_in[32]0=low" "0,1"
group.long 0xD10++0x3
line.long 0x00 "ICSSG_POLARITY_REG4,Polarity Register 4"
bitfld.long 0x00 31. " POLARITY_159          ,Polarity for slv_events_in[95]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_158   ,Polarity for slv_events_in[94]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_157          ,Polarity for slv_events_in[93]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_156   ,Polarity for slv_events_in[92]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_155          ,Polarity for slv_events_in[91]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_154   ,Polarity for slv_events_in[90]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_153          ,Polarity for slv_events_in[89]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_152   ,Polarity for slv_events_in[88]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_151          ,Polarity for slv_events_in[87]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_150   ,Polarity for slv_events_in[86]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_149          ,Polarity for slv_events_in[85]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_148   ,Polarity for slv_events_in[84]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_147          ,Polarity for slv_events_in[83]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_146   ,Polarity for slv_events_in[82]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_145          ,Polarity for slv_events_in[81]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_144   ,Polarity for slv_events_in[80]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_143          ,Polarity for slv_events_in[79]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_142   ,Polarity for slv_events_in[78]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_141          ,Polarity for slv_events_in[77]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_140   ,Polarity for slv_events_in[76]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_139          ,Polarity for slv_events_in[75]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_138   ,Polarity for slv_events_in[74]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_137          ,Polarity for slv_events_in[73]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_136   ,Polarity for slv_events_in[72]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_135          ,Polarity for slv_events_in[71]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_134   ,Polarity for slv_events_in[70]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_133          ,Polarity for slv_events_in[69]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_132   ,Polarity for slv_events_in[68]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_131          ,Polarity for slv_events_in[67]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_130   ,Polarity for slv_events_in[66]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_129          ,Polarity for slv_events_in[65]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_128   ,Polarity for slv_events_in[64]0=low" "0,1"
group.long 0xD80++0x3
line.long 0x00 "ICSSG_TYPE_REG0,Type Register 0"
bitfld.long 0x00 31. " TYPE_31               ,Type for intr_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_30        ,Type for intr_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_29               ,Type for intr_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_28        ,Type for intr_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_27               ,Type for intr_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_26        ,Type for intr_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_25               ,Type for intr_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_24        ,Type for intr_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_23               ,Type for intr_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_22        ,Type for intr_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_21               ,Type for intr_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_20        ,Type for intr_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_19               ,Type for intr_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_18        ,Type for intr_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_17               ,Type for intr_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_16        ,Type for intr_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_15               ,Type for intr_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_14        ,Type for intr_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_13               ,Type for intr_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_12        ,Type for intr_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_11               ,Type for intr_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_10        ,Type for intr_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_9                ,Type for intr_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_8         ,Type for intr_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_7                ,Type for intr_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_6         ,Type for intr_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_5                ,Type for intr_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_4         ,Type for intr_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_3                ,Type for intr_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_2         ,Type for intr_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_1                ,Type for intr_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_0         ,Type for intr_in[0]0=level" "0,1"
group.long 0xD84++0x3
line.long 0x00 "ICSSG_TYPE_REG1,Type Register 1"
bitfld.long 0x00 31. " TYPE_63               ,Type for intr_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_62        ,Type for intr_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_61               ,Type for intr_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_60        ,Type for intr_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_59               ,Type for intr_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_58        ,Type for intr_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_57               ,Type for intr_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_56        ,Type for intr_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_55               ,Type for intr_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_54        ,Type for intr_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_53               ,Type for intr_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_52        ,Type for intr_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_51               ,Type for intr_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_50        ,Type for intr_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_49               ,Type for intr_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_48        ,Type for intr_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_47               ,Type for intr_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_46        ,Type for intr_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_45               ,Type for intr_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_44        ,Type for intr_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_43               ,Type for intr_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_42        ,Type for intr_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_41               ,Type for intr_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_40        ,Type for intr_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_39               ,Type for intr_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_38        ,Type for intr_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_37               ,Type for intr_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_36        ,Type for intr_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_35               ,Type for intr_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_34        ,Type for intr_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_33               ,Type for intr_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_32        ,Type for intr_in[32]0=level" "0,1"
group.long 0xD88++0x3
line.long 0x00 "ICSSG_TYPE_REG2,Type Register 2"
bitfld.long 0x00 31. " TYPE_95               ,Type for slv_events_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_94        ,Type for slv_events_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_93               ,Type for slv_events_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_92        ,Type for slv_events_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_91               ,Type for slv_events_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_90        ,Type for slv_events_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_89               ,Type for slv_events_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_88        ,Type for slv_events_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_87               ,Type for slv_events_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_86        ,Type for slv_events_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_85               ,Type for slv_events_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_84        ,Type for slv_events_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_83               ,Type for slv_events_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_82        ,Type for slv_events_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_81               ,Type for slv_events_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_80        ,Type for slv_events_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_79               ,Type for slv_events_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_78        ,Type for slv_events_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_77               ,Type for slv_events_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_76        ,Type for slv_events_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_75               ,Type for slv_events_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_74        ,Type for slv_events_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_73               ,Type for slv_events_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_72        ,Type for slv_events_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_71               ,Type for slv_events_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_70        ,Type for slv_events_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_69               ,Type for slv_events_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_68        ,Type for slv_events_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_67               ,Type for slv_events_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_66        ,Type for slv_events_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_65               ,Type for slv_events_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_64        ,Type for slv_events_in[0]0=level" "0,1"
group.long 0xD8C++0x3
line.long 0x00 "ICSSG_TYPE_REG3,Type Register 3"
bitfld.long 0x00 31. " TYPE_127              ,Type for slv_events_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_126       ,Type for slv_events_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_125              ,Type for slv_events_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_124       ,Type for slv_events_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_123              ,Type for slv_events_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_122       ,Type for slv_events_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_121              ,Type for slv_events_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_120       ,Type for slv_events_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_119              ,Type for slv_events_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_118       ,Type for slv_events_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_117              ,Type for slv_events_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_116       ,Type for slv_events_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_115              ,Type for slv_events_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_114       ,Type for slv_events_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_113              ,Type for slv_events_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_112       ,Type for slv_events_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_111              ,Type for slv_events_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_110       ,Type for slv_events_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_109              ,Type for slv_events_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_108       ,Type for slv_events_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_107              ,Type for slv_events_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_106       ,Type for slv_events_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_105              ,Type for slv_events_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_104       ,Type for slv_events_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_103              ,Type for slv_events_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_102       ,Type for slv_events_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_101              ,Type for slv_events_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_100       ,Type for slv_events_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_99               ,Type for slv_events_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_98        ,Type for slv_events_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_97               ,Type for slv_events_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_96        ,Type for slv_events_in[32]0=level" "0,1"
group.long 0xD90++0x3
line.long 0x00 "ICSSG_TYPE_REG4,Type Register 4"
bitfld.long 0x00 31. " TYPE_159              ,Type for slv_events_in[95]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_158       ,Type for slv_events_in[94]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_157              ,Type for slv_events_in[93]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_156       ,Type for slv_events_in[92]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_155              ,Type for slv_events_in[91]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_154       ,Type for slv_events_in[90]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_153              ,Type for slv_events_in[89]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_152       ,Type for slv_events_in[88]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_151              ,Type for slv_events_in[87]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_150       ,Type for slv_events_in[86]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_149              ,Type for slv_events_in[85]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_148       ,Type for slv_events_in[84]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_147              ,Type for slv_events_in[83]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_146       ,Type for slv_events_in[82]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_145              ,Type for slv_events_in[81]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_144       ,Type for slv_events_in[80]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_143              ,Type for slv_events_in[79]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_142       ,Type for slv_events_in[78]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_141              ,Type for slv_events_in[77]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_140       ,Type for slv_events_in[76]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_139              ,Type for slv_events_in[75]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_138       ,Type for slv_events_in[74]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_137              ,Type for slv_events_in[73]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_136       ,Type for slv_events_in[72]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_135              ,Type for slv_events_in[71]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_134       ,Type for slv_events_in[70]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_133              ,Type for slv_events_in[69]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_132       ,Type for slv_events_in[68]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_131              ,Type for slv_events_in[67]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_130       ,Type for slv_events_in[66]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_129              ,Type for slv_events_in[65]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_128       ,Type for slv_events_in[64]0=level" "0,1"
group.long 0x1100++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG0,Host Int 0 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_0    ,Host Int 0 Nesting Level"
group.long 0x1104++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG1,Host Int 1 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_1    ,Host Int 1 Nesting Level"
group.long 0x1108++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG2,Host Int 2 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_2    ,Host Int 2 Nesting Level"
group.long 0x110C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG3,Host Int 3 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_3    ,Host Int 3 Nesting Level"
group.long 0x1110++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG4,Host Int 4 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_4    ,Host Int 4 Nesting Level"
group.long 0x1114++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG5,Host Int 5 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_5    ,Host Int 5 Nesting Level"
group.long 0x1118++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG6,Host Int 6 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_6    ,Host Int 6 Nesting Level"
group.long 0x111C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG7,Host Int 7 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_7    ,Host Int 7 Nesting Level"
group.long 0x1120++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG8,Host Int 8 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_8    ,Host Int 8 Nesting Level"
group.long 0x1124++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG9,Host Int 9 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_9    ,Host Int 9 Nesting Level"
group.long 0x1128++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG10,Host Int 10 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_10   ,Host Int 10 Nesting Level"
group.long 0x112C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG11,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_11   ,Host Int 11 Nesting Level"
group.long 0x1130++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG12,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_12   ,Host Int 12 Nesting Level"
group.long 0x1134++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG13,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_13   ,Host Int 13 Nesting Level"
group.long 0x1138++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG14,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_14   ,Host Int 14 Nesting Level"
group.long 0x113C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG15,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_15   ,Host Int 15 Nesting Level"
group.long 0x1140++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG16,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_16   ,Host Int 16 Nesting Level"
group.long 0x1144++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG17,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_17   ,Host Int 17 Nesting Level"
group.long 0x1148++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG18,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_18   ,Host Int 18 Nesting Level"
group.long 0x114C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG19,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_19   ,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x00 "ICSSG_ENABLE_HINT_REG0,Host Int Enable Register 0"
bitfld.long 0x00 19. " ENABLE_HINT_19        ,Enable for Host Int 19" "0,1"
bitfld.long 0x00 18. "     ENABLE_HINT_18 ,Enable for Host Int 18" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_HINT_17        ,Enable for Host Int 17" "0,1"
bitfld.long 0x00 16. "     ENABLE_HINT_16 ,Enable for Host Int 16" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_HINT_15        ,Enable for Host Int 15" "0,1"
bitfld.long 0x00 14. "     ENABLE_HINT_14 ,Enable for Host Int 14" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_HINT_13        ,Enable for Host Int 13" "0,1"
bitfld.long 0x00 12. "     ENABLE_HINT_12 ,Enable for Host Int 12" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_HINT_11        ,Enable for Host Int 11" "0,1"
bitfld.long 0x00 10. "     ENABLE_HINT_10 ,Enable for Host Int 10" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_HINT_9         ,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "     ENABLE_HINT_8  ,Enable for Host Int 8" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_HINT_7         ,Enable for Host Int 7" "0,1"
bitfld.long 0x00 6. "     ENABLE_HINT_6  ,Enable for Host Int 6" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_HINT_5         ,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "     ENABLE_HINT_4  ,Enable for Host Int 4" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_HINT_3         ,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "     ENABLE_HINT_2  ,Enable for Host Int 2" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_HINT_1         ,Enable for Host Int 1" "0,1"
bitfld.long 0x00 0. "     ENABLE_HINT_0  ,Enable for Host Int 0" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MDIO"
tree "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"
base eaxi:0xB032400
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_MDIO_VERSION_REG,MDIO Version Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                ,Module Identification value"
hexmask.long.byte 0x00 8.--15. 1. "      REVMAJ              ,Major revision value"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " REVMINOR             ,Minor revision value"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_CONTROL_REG,MDIO Control Register"
in
textline "                                        "
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_ALIVE_REG,MDIO Alive Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_LINK_REG,MDIO Link Register"
hexmask.long 0x00 0.--31. 1. " LINK                 ,MDIO Link state."
hgroup.long 0x10++0x3
hide.long 0x00 "ICSSG_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x14++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
in
textline "                                        "
group.long 0x18++0x3
line.long 0x00 "ICSSG_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x00 0. " LINKINTMASKSET       ,MDIO link interrupt mask set." "0,1"
hgroup.long 0x1C++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
in
textline "                                        "
hgroup.long 0x20++0x3
hide.long 0x00 "ICSSG_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x24++0x3
hide.long 0x00 "ICSSG_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
in
textline "                                        "
group.long 0x28++0x3
line.long 0x00 "ICSSG_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x00 0.--1. " USERINTMASKSET       ,MDIO user interrupt mask set for userintmasked[1:0], respectively." "0,1,2,3"
hgroup.long 0x2C++0x3
hide.long 0x00 "ICSSG_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
in
textline "                                        "
group.long 0x30++0x3
line.long 0x00 "ICSSG_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x00 2. " MDIO_MDCLK_O         ,MDIO Clock Output." "0,1"
bitfld.long 0x00 1. "         MDIO_OE             ,MDIO Output Enable." "0,1"
textline "                                        "
bitfld.long 0x00 0. " MDIO_PIN             ,MDIO_Pin Value." "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_POLL_REG,MDIO Poll Inter Register"
bitfld.long 0x00 31. " MANUALMODE           ,Manual Mode." "0,1"
bitfld.long 0x00 30. "         STATECHANGEMODE     ,State Change Mode." "0,1"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " IPG                  ,Polling Inter Packet Gap Value."
group.long 0x38++0x3
line.long 0x00 "ICSSG_POLL_EN_REG,MDIO Poll Enable Register"
hexmask.long 0x00 0.--31. 1. " POLL_EN              ,Poll Enable."
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CLAUS45_REG,Clause 45 Register"
hexmask.long 0x00 0.--31. 1. " CLAUSE45             ,MDIO clause 45 mode."
group.long 0x40++0x3
line.long 0x00 "ICSSG_USER_ADDR0_REG,MDIO User Address 0 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR0           ,User Address 0."
group.long 0x44++0x3
line.long 0x00 "ICSSG_USER_ADDR1_REG,MDIO User Address 1 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR1           ,User Address 1."
group.long 0x80++0x3
line.long 0x00 "ICSSG_USER_ACCESS_REG_j,MDIO User Access j Register Offset = 80h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 31. " GO                   ,Go." "0,1"
bitfld.long 0x00 30. "         WRITE               ,Write enable." "0,1"
textline "                                        "
bitfld.long 0x00 29. " ACK                  ,Acknowledge." "0,1"
bitfld.long 0x00 21.--25. "         REGADR              ,Register address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 16.--20. " PHYADR               ,PHY address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "        DATA                ,User data."
group.long 0x84++0x3
line.long 0x00 "ICSSG_USER_PHY_SEL_REG_j,MDIO User PHY Select j Register Offset = 84h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 7. " LINKSEL              ,Link status determination select." "0,1"
bitfld.long 0x00 6. "         LINKINT_ENABLE      ,Link change interrupt enable." "0,1"
textline "                                        "
bitfld.long 0x00 0.--4. " PHYADR_MON           ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_G_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base eaxi:0xB033000
width 35.
group.long 0x0++0x3
line.long 0x00 "ICSSG_ICSS_G_CFG,ICSSG Config"
bitfld.long 0x00 16. " SGMII_MODE                ,SGMII mode0: Fiber mode 1: SGMII mode" "0,1"
bitfld.long 0x00 10. "         RX_SFD_TX_SOF_EN         ,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RTU_PRU_PSI_SHARE_EN      ,Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO" "0,1"
bitfld.long 0x00 8. "         IEP1_TX_EN               ,Enable IEP1 for TX Enable0: Use IEP0 CMP3_4 1: Use IEP1 CMP3_4" "0,1"
textline "                                            "
bitfld.long 0x00 5.--6. " MII1_MODE                 ,MII1 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
bitfld.long 0x00 3.--4. "         MII0_MODE                ,MII0 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2. " RX_L2_G_EN                ,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 1. "         TX_L2_EN                 ,Enable the TX L2 Fifo0: Disabled 1: Enabled" "0,1"
textline "                                            "
bitfld.long 0x00 0. " TX_L1_EN                  ,Enable the TX L1 Fifo0: Disabled 1: Enabled" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RGMII_CFG,RGMII"
bitfld.long 0x00 22. " RGMII1_FULLDUPLEX_IN      ,RGMII Fullduplex overide0: half 1: full" "0,1"
bitfld.long 0x00 21. "         RGMII1_GIG_IN            ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
textline "                                            "
bitfld.long 0x00 20. " RGMII1_INBAND             ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
bitfld.long 0x00 18. "         RGMII0_FULLDUPLEX_IN     ,RGMII Fullduplex overide0: half 1: full" "0,1"
textline "                                            "
bitfld.long 0x00 17. " RGMII0_GIG_IN             ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
bitfld.long 0x00 16. "         RGMII0_INBAND            ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RGMII_EEE_PHY_ONLY        ,RGMII Phy Only Low Power0: disable 1: enable" "0,1"
bitfld.long 0x00 8. "         RGMII_EEE_EN             ,RGMII Energy Efficient Enable0: disable 1: enable" "0,1"
textline "                                            "
bitfld.long 0x00 7. " RGMII1_FULLDUPLEX         ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
bitfld.long 0x00 5.--6. "         RGMII1_SPEED             ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 4. " RGMII1_LINK               ,RGMII Link Status0: link is down 1: link is up" "0,1"
bitfld.long 0x00 3. "         RGMII0_FULLDUPLEX        ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
textline "                                            "
bitfld.long 0x00 1.--2. " RGMII0_SPEED              ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
bitfld.long 0x00 0. "         RGMII0_LINK              ,RGMII Link Status0: link is down 1: link is up" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_MAC_PRU0_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU0_0                ,MAC pru0 DA3:DA0 Used for SAV and DA match"
group.long 0xC++0x3
line.long 0x00 "ICSSG_MAC_PRU0_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU0_1                ,MAC pru0 DA5:DA4 Used for SAV and DA match"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MAC_PRU1_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU1_0                ,MAC pru1 DA3:DA0 Used for SAV and DA match"
group.long 0x14++0x3
line.long 0x00 "ICSSG_MAC_PRU1_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU1_1                ,MAC pru1 DA5:DA4 Used for SAV and DA match"
group.long 0x18++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_0,MAC_Interface_0"
hexmask.long 0x00 0.--31. 1. " MAC_INF_0                 ,MAC Host interface DA3:DA0 Used for SAV and DA match"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_1,MAC_Interface_1"
hexmask.long.word 0x00 0.--15. 1. " MAC_INF_1                 ,MAC Host interface DA5:DA4 Used for SAV and DA match"
group.long 0x20++0x3
line.long 0x00 "ICSSG_PREEMPT_CFG,Preemption_Cfg"
hexmask.long.byte 0x00 24.--31. 1. " SMD_R                     ,Response frame TAG"
hexmask.long.byte 0x00 16.--23. 1. "        SMD_V                    ,Verification frame TAG"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " EXP_SMD                   ,None preemptable frame start, or express frame"
group.long 0x24++0x3
line.long 0x00 "ICSSG_SMDT1S_CFG,SMDType1SPreemptableFrameStartCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1S_3                  ,SMDT1S3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1S_2                 ,SMDT1S2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1S_1                  ,SMDT1S1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1S_0                 ,SMDT1S0 pattern"
group.long 0x28++0x3
line.long 0x00 "ICSSG_SMDT1C_CFG,SMDType1CNoneInitialFragCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1C_3                  ,SMDT1C3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1C_2                 ,SMDT1C2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1C_1                  ,SMDT1C1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1C_0                 ,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x00 "ICSSG_FRAG_CNT_CFG,FragCntCfg"
hexmask.long.byte 0x00 24.--31. 1. " FRAG_CNT_3                ,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        FRAG_CNT_2               ,FRAG Cnt2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " FRAG_CNT_1                ,FRAG Cnt1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        FRAG_CNT_0               ,FRAG Cnt0 pattern"
group.long 0x40++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH0,PaStatPush0"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_0           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_0          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_0           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_0          ,pa"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH1,PaStatPush1"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_1           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_1          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_1           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_1          ,pa"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH2,PaStatPush2"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_2           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_2          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_2           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_2          ,pa"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH3,PaStatPush3"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_3           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_3          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_3           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_3          ,pa"
group.long 0x60++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG1,FDBCfg1"
hexmask.long.tbyte 0x00 8.--25. 1. " SMEM_VLAN_OFFSET          ,SMEM VLAN FID table base address"
bitfld.long 0x00 3.--6. "    FDB_HASH_SIZE            ,FDB hash size0:64 1:128 2:256 3:512 4:1024 5:2048" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.long 0x00 0.--1. " FDB_BUCKET_SIZE           ,FDB buket size0:1 1:2 2:4 3:8" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG2,FDBCfg2"
bitfld.long 0x00 9.--12. " FDB_GEN_MODE_BYTE_EN      ,FDB General Mode Byte compare size0 = 1 Byte, 15 = 16 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "        FDB_GEN_MODE_EN_BK1      ,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
textline "                                            "
bitfld.long 0x00 7. " FDB_GEN_MODE_EN_BK0       ,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x00 6. "         FDB_VLAN_EN              ,FDB Global VLAN Enable" "0,1"
textline "                                            "
bitfld.long 0x00 5. " FDB_HSR_EN                ,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x00 2. "         FDB_HOST_EN              ,FDB HOST Enable" "0,1"
textline "                                            "
bitfld.long 0x00 1. " FDB_PRU1_EN               ,FDB PRU1 Enable" "0,1"
bitfld.long 0x00 0. "         FDB_PRU0_EN              ,FDB PRU0 Enable" "0,1"
group.long 0x68++0x3
line.long 0x00 "ICSSG_FDB_GEN_STATUS,FDBStatus"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_FDB_DF_VLAN,FDBDefaultPRUVLAN"
hexmask.long.word 0x00 16.--27. 1. " FDB_PRU1_DF_VLAN          ,FDB Default VLAN for PRU1"
hexmask.long.word 0x00 0.--11. 1. "      FDB_PRU0_DF_VLAN         ,FDB Default VLAN for PRU0"
group.long 0x70++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA0,FDB_HOST_DA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_DA0              ,FDB HOST DA3:0"
group.long 0x74++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA1,FDB_HOST_DA5:4_Cfg"
hexmask.long.word 0x00 0.--15. 1. " FDB_HOST_DA1              ,FDB HOST DA5:4"
group.long 0x78++0x3
line.long 0x00 "ICSSG_FDB_HOST_SA0,FDB_HOST_SA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_SA0              ,FDB HOST SA3:0"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_FDB_HOST_VLAN_SA1,FDB_HOST_VLAN_SA5:4_Cfg"
hexmask.long.word 0x00 16.--31. 1. " FDB_HOST_VLAN_HSR         ,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x00 0.--15. 1. "      FDB_HOST_SA1             ,FDB HOST SA5:4"
group.long 0x80++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU0,Filter1StartandLengthPru0"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x84++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU0,Filter1ConfigPru0"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU0,Filter1_0_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU0,Filter1_0_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x90++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU0,Filter1_0_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x94++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU0,Filter1_0_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x98++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU0,Filter1_1_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU0,Filter1_1_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU0,Filter1_1_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU0,Filter1_1_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU0,Filter1_2_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU0,Filter1_2_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU0,Filter1_2_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU0,Filter1_2_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU0,Filter1_3_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU0,Filter1_3_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU0,Filter1_3_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU0,Filter1_3_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU0,Filter1_4_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU0,Filter1_4_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU0,Filter1_4_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU0,Filter1_4_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU0,Filter1_5_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU0,Filter1_5_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU0,Filter1_5_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU0,Filter1_5_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU0,Filter1_6_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU0,Filter1_6_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU0,Filter1_6_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU0,Filter1_6_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU0,Filter1_7_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU0,Filter1_7_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x100++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU0,Filter1_7_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x104++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU0,Filter1_7_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x108++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU0,Filter3_0_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU0,Filter3_0_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x110++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU0,Filter3_0_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x114++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU0,Filter3_0_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x118++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU0,Filter3_0_LenPru0"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU0,Filter3_0_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x120++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU0,Filter3_0_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x124++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU0,Filter3_0_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x128++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU0,Filter3_1_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU0,Filter3_1_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x130++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU0,Filter3_1_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x134++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU0,Filter3_1_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x138++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU0,Filter3_1_LenPru0"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU0,Filter3_1_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x140++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU0,Filter3_1_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x144++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU0,Filter3_1_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x148++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU0,Filter3_2_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU0,Filter3_2_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x150++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU0,Filter3_2_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x154++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU0,Filter3_2_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x158++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU0,Filter3_2_LenPru0"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU0,Filter3_2_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU0,Filter3_2_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x164++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU0,Filter3_2_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x168++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU0,Filter3_3_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU0,Filter3_3_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x170++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU0,Filter3_3_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x174++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU0,Filter3_3_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x178++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU0,Filter3_3_LenPru0"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x17C++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU0,Filter3_3_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x180++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU0,Filter3_3_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x184++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU0,Filter3_3_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x188++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU0,Filter3_4_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU0,Filter3_4_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x190++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU0,Filter3_4_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x194++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU0,Filter3_4_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x198++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU0,Filter3_4_LenPru0"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x19C++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU0,Filter3_4_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1A0++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU0,Filter3_4_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1A4++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU0,Filter3_4_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1A8++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU0,Filter3_5_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU0,Filter3_5_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1B0++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU0,Filter3_5_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1B4++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU0,Filter3_5_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1B8++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU0,Filter3_5_LenPru0"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1BC++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU0,Filter3_5_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1C0++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU0,Filter3_5_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1C4++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU0,Filter3_5_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1C8++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU0,Filter3_6_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU0,Filter3_6_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1D0++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU0,Filter3_6_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1D4++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU0,Filter3_6_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1D8++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU0,Filter3_6_LenPru0"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1DC++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU0,Filter3_6_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1E0++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU0,Filter3_6_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1E4++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU0,Filter3_6_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1E8++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU0,Filter3_7_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU0,Filter3_7_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1F0++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU0,Filter3_7_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1F4++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU0,Filter3_7_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1F8++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU0,Filter3_7_LenPru0"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1FC++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU0,Filter3_7_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x200++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU0,Filter3_7_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x204++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU0,Filter3_7_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x208++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU0,Filter3_8_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU0,Filter3_8_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x210++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU0,Filter3_8_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x214++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU0,Filter3_8_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x218++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU0,Filter3_8_LenPru0"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x21C++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU0,Filter3_8_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x220++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU0,Filter3_8_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x224++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU0,Filter3_8_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x228++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU0,Filter3_9_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU0,Filter3_9_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x230++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU0,Filter3_9_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x234++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU0,Filter3_9_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x238++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU0,Filter3_9_LenPru0"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x23C++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU0,Filter3_9_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x240++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU0,Filter3_9_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x244++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU0,Filter3_9_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x248++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU0,Filter3_10_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU0,Filter3_10_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x250++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU0,Filter3_10_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x254++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU0,Filter3_10_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x258++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU0,Filter3_10_LenPru0"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x25C++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU0,Filter3_10_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x260++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU0,Filter3_10_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x264++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU0,Filter3_10_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x268++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU0,Filter3_11_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU0,Filter3_11_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x270++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU0,Filter3_11_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x274++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU0,Filter3_11_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x278++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU0,Filter3_11_LenPru0"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x27C++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU0,Filter3_11_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x280++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU0,Filter3_11_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x284++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU0,Filter3_11_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x288++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU0,Filter3_12_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU0,Filter3_12_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x290++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU0,Filter3_12_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x294++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU0,Filter3_12_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x298++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU0,Filter3_12_LenPru0"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x29C++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU0,Filter3_12_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2A0++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU0,Filter3_12_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2A4++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU0,Filter3_12_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2A8++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU0,Filter3_13_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU0,Filter3_13_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2B0++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU0,Filter3_13_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2B4++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU0,Filter3_13_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2B8++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU0,Filter3_13_LenPru0"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2BC++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU0,Filter3_13_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2C0++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU0,Filter3_13_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2C4++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU0,Filter3_13_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2C8++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU0,Filter3_14_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU0,Filter3_14_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2D0++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU0,Filter3_14_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2D4++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU0,Filter3_14_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2D8++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU0,Filter3_14_LenPru0"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2DC++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU0,Filter3_14_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2E0++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU0,Filter3_14_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2E4++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU0,Filter3_14_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2E8++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU0,Filter3_15_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU0,Filter3_15_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2F0++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU0,Filter3_15_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2F4++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU0,Filter3_15_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2F8++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU0,Filter3_15_LenPru0"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2FC++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU0,Filter3_15_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x300++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU0,Filter3_15_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x304++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU0,Filter3_15_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x308++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU0,Filter3_0P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU0,Filter3_0P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x310++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x314++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x318++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU0,Filter3_1P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x31C++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU0,Filter3_1P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x320++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x324++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x328++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU0,Filter3_2P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x32C++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU0,Filter3_2P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x330++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x334++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x338++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU0,Filter3_3P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x33C++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU0,Filter3_3P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x340++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x344++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x348++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU0,Filter3_4P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x34C++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU0,Filter3_4P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x350++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x354++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x358++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU0,Filter3_5P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x35C++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU0,Filter3_5P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x360++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x364++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x368++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU0,Filter3_6P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x36C++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU0,Filter3_6P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x370++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x374++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x378++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU0,Filter3_7P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x37C++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU0,Filter3_7P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x380++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x384++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x388++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU0,Filter3_8P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU0,Filter3_8P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x390++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x394++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x398++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU0,Filter3_9P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x39C++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU0,Filter3_9P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x3A0++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3A4++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3A8++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU0,Filter3_10P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x3AC++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU0,Filter3_10P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x3B0++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3B4++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3B8++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU0,Filter3_11P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x3BC++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU0,Filter3_11P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x3C0++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3C4++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3C8++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU0,Filter3_12P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x3CC++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU0,Filter3_12P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x3D0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3D4++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3D8++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU0,Filter3_13P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x3DC++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU0,Filter3_13P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x3E0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3E4++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3E8++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU0,Filter3_14P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x3EC++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU0,Filter3_14P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x3F0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3F4++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3F8++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU0,Filter3_15P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x3FC++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU0,Filter3_15P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x400++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x404++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x408++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU0,FilterByteCountPru0"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU0            ,RX current filter Byte Count"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU0,rx_class0_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x410++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU0,rx_class0_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x414++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU0,rx_class1_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x418++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU0,rx_class1_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU0,rx_class2_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x420++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU0,rx_class2_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x424++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU0,rx_class3_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x428++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU0,rx_class3_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU0,rx_class4_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x430++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU0,rx_class4_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0x434++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU0,rx_class5_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0x438++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU0,rx_class5_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU0,rx_class6_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0x440++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU0,rx_class6_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0x444++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU0,rx_class7_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0x448++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU0,rx_class7_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU0,rx_class8_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0x450++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU0,rx_class8_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0x454++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU0,rx_class9_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0x458++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU0,rx_class9_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU0,rx_class10_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0x460++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU0,rx_class10_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0x464++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU0,rx_class11_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0x468++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU0,rx_class11_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU0,rx_class12_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0x470++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU0,rx_class12_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0x474++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU0,rx_class13_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0x478++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU0,rx_class13_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU0,rx_class14_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0x480++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU0,rx_class14_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0x484++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU0,rx_class15_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0x488++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU0,rx_class15_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU0,rx_class_cfg1Pru0"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0x490++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU0,rx_class_cfg2Pru0"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0x494++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x498++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4AC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4BC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4CC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D4++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU0,RX_greenPru0"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4D8++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU0,SAHashPru0"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0x4DC++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU0,ConnectionHashPru0"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0x4E0++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU0,ConnectionHashStartPru0"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0x4E4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU0,RX_RateConfiguration0Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4E8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU0,RX_RateConfiguration1Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4EC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU0,RX_RateConfiguration2Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU0,RX_RateConfiguration3Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU0,RX_RateConfiguration4Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU0,RX_RateConfiguration5Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4FC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU0,RX_RateConfiguration6Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x500++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU0,RX_RateConfiguration7Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x504++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU0,RX_RateSourceSelect0Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x508++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU0,RX_RateSourceSelect1Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU0,TX_RateConfiguration1_0Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x510++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU0,TX_RateConfiguration2_0Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0x514++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU0,TX_RateConfiguration1_1Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x518++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU0,TX_RateConfiguration2_1Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0x51C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU0,TX_RateConfiguration1_2Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x520++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU0,TX_RateConfiguration2_2Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0x524++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU0,TX_RateConfiguration1_3Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x528++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU0,TX_RateConfiguration2_3Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0x52C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU0,TX_RateConfiguration1_4Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x530++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU0,TX_RateConfiguration2_4Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0x534++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU0,TX_RateConfiguration1_5Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x538++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU0,TX_RateConfiguration2_5Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0x53C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU0,TX_RateConfiguration1_6Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x540++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU0,TX_RateConfiguration2_6Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0x544++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU0,TX_RateConfiguration1_7Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x548++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU0,TX_RateConfiguration2_7Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0x54C++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU0,RXGoodFrameCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0x550++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU0,RXBCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0x554++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU0,RXMCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0x558++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU0,RXCRCErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0x55C++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU0,RXMIIErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0x560++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU0,RXOddNibbleFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0x564++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU0,RXMaxSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0x568++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU0,RXMaxSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0x56C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU0,RXMinSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0x570++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU0,RXMinSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0x574++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU0,RXoverrunFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0x578++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU0       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0x57C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU0       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0x580++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU0       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0x584++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU0       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0x588++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU0       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0x58C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU0       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0x590++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU0       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0x594++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU0       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0x598++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU0       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0x59C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU0       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0x5A0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU0      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0x5A4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU0      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0x5A8++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU0      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0x5AC++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU0      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0x5B0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU0      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0x5B4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU0      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0x5B8++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU0,RXSMDFragErrCountPru0"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU0      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU0    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU0     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU0    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0x5BC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU0,RXBucket1SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0x5C0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU0,RXBucket2SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0x5C4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU0,RXBucket3SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0x5C8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU0,RXBucket4SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0x5CC++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU0,RX64BSizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0x5D0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU0,RXBucket1SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0x5D4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU0,RXBucket2SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x5D8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU0,RXBucket3SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x5DC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU0,RXBucket4SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x5E0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU0,RXBucket5SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0x5E4++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU0,RXTotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0x5E8++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU0,RX_TX_TotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0x5EC++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT0,TXGoodFrameCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0x5F0++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT0,TXBCFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0x5F4++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT0,TXMFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0x5F8++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT0,TXOddNibbleFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0x5FC++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT0,TXUnderFlowErrCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0x600++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT0,TXMaxSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0x604++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT0,TXMaxSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0x608++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT0,TXMinSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0x60C++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT0,TXMinSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0x610++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT0,TXBucket1SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0x614++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT0,TXBucket2SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0x618++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT0,TXBucket3SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0x61C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT0,TXBucket4SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0x620++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT0,TX64BSizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0x624++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT0,TXBucket1SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0x628++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT0,TXBucket2SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x62C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT0,TXBucket3SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x630++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT0,TXBucket4SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x634++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT0,TXBucket5SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0x638++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT0,TXTotalByteCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0x63C++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT0,TXHSRTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0x640++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT0,TXHSRSeqPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0x644++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT0,TXVLANTYPETAGPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0x648++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT0,TXVLANINSTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
group.long 0x64C++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU1,Filter1StartandLengthPru1"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x650++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU1,Filter1ConfigPru1"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x654++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU1,Filter1_0_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x658++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU1,Filter1_0_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x65C++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU1,Filter1_0_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x660++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU1,Filter1_0_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x664++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU1,Filter1_1_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x668++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU1,Filter1_1_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0x66C++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU1,Filter1_1_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x670++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU1,Filter1_1_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x674++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU1,Filter1_2_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0x678++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU1,Filter1_2_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0x67C++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU1,Filter1_2_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x680++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU1,Filter1_2_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x684++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU1,Filter1_3_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0x688++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU1,Filter1_3_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0x68C++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU1,Filter1_3_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x690++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU1,Filter1_3_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x694++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU1,Filter1_4_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0x698++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU1,Filter1_4_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0x69C++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU1,Filter1_4_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6A0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU1,Filter1_4_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6A4++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU1,Filter1_5_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0x6A8++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU1,Filter1_5_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0x6AC++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU1,Filter1_5_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6B0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU1,Filter1_5_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6B4++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU1,Filter1_6_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0x6B8++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU1,Filter1_6_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0x6BC++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU1,Filter1_6_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6C0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU1,Filter1_6_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6C4++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU1,Filter1_7_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0x6C8++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU1,Filter1_7_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x6CC++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU1,Filter1_7_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6D0++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU1,Filter1_7_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6D4++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU1,Filter3_0_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU1,Filter3_0_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6DC++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU1,Filter3_0_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x6E0++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU1,Filter3_0_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x6E4++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU1,Filter3_0_LenPru1"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x6E8++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU1,Filter3_0_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x6EC++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU1,Filter3_0_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x6F0++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU1,Filter3_0_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x6F4++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU1,Filter3_1_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU1,Filter3_1_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6FC++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU1,Filter3_1_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x700++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU1,Filter3_1_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x704++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU1,Filter3_1_LenPru1"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x708++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU1,Filter3_1_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x70C++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU1,Filter3_1_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x710++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU1,Filter3_1_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x714++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU1,Filter3_2_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU1,Filter3_2_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x71C++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU1,Filter3_2_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x720++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU1,Filter3_2_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x724++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU1,Filter3_2_LenPru1"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x728++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU1,Filter3_2_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x72C++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU1,Filter3_2_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x730++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU1,Filter3_2_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x734++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU1,Filter3_3_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU1,Filter3_3_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x73C++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU1,Filter3_3_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x740++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU1,Filter3_3_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x744++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU1,Filter3_3_LenPru1"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x748++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU1,Filter3_3_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x74C++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU1,Filter3_3_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x750++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU1,Filter3_3_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x754++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU1,Filter3_4_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU1,Filter3_4_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x75C++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU1,Filter3_4_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x760++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU1,Filter3_4_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x764++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU1,Filter3_4_LenPru1"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x768++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU1,Filter3_4_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x76C++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU1,Filter3_4_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x770++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU1,Filter3_4_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x774++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU1,Filter3_5_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU1,Filter3_5_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x77C++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU1,Filter3_5_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x780++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU1,Filter3_5_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x784++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU1,Filter3_5_LenPru1"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x788++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU1,Filter3_5_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x78C++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU1,Filter3_5_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x790++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU1,Filter3_5_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x794++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU1,Filter3_6_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU1,Filter3_6_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x79C++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU1,Filter3_6_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7A0++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU1,Filter3_6_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7A4++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU1,Filter3_6_LenPru1"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7A8++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU1,Filter3_6_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7AC++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU1,Filter3_6_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7B0++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU1,Filter3_6_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7B4++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU1,Filter3_7_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU1,Filter3_7_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7BC++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU1,Filter3_7_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7C0++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU1,Filter3_7_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7C4++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU1,Filter3_7_LenPru1"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7C8++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU1,Filter3_7_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7CC++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU1,Filter3_7_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7D0++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU1,Filter3_7_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7D4++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU1,Filter3_8_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU1,Filter3_8_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7DC++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU1,Filter3_8_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7E0++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU1,Filter3_8_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7E4++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU1,Filter3_8_LenPru1"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7E8++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU1,Filter3_8_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7EC++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU1,Filter3_8_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7F0++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU1,Filter3_8_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7F4++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU1,Filter3_9_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU1,Filter3_9_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7FC++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU1,Filter3_9_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x800++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU1,Filter3_9_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x804++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU1,Filter3_9_LenPru1"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x808++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU1,Filter3_9_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU1,Filter3_9_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x810++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU1,Filter3_9_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x814++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU1,Filter3_10_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU1,Filter3_10_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x81C++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU1,Filter3_10_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x820++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU1,Filter3_10_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x824++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU1,Filter3_10_LenPru1"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x828++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU1,Filter3_10_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x82C++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU1,Filter3_10_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x830++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU1,Filter3_10_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x834++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU1,Filter3_11_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU1,Filter3_11_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x83C++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU1,Filter3_11_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x840++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU1,Filter3_11_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x844++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU1,Filter3_11_LenPru1"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x848++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU1,Filter3_11_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x84C++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU1,Filter3_11_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x850++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU1,Filter3_11_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x854++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU1,Filter3_12_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU1,Filter3_12_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x85C++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU1,Filter3_12_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x860++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU1,Filter3_12_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x864++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU1,Filter3_12_LenPru1"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x868++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU1,Filter3_12_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x86C++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU1,Filter3_12_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x870++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU1,Filter3_12_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x874++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU1,Filter3_13_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU1,Filter3_13_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x87C++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU1,Filter3_13_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x880++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU1,Filter3_13_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x884++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU1,Filter3_13_LenPru1"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x888++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU1,Filter3_13_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88C++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU1,Filter3_13_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x890++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU1,Filter3_13_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x894++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU1,Filter3_14_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU1,Filter3_14_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x89C++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU1,Filter3_14_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8A0++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU1,Filter3_14_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8A4++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU1,Filter3_14_LenPru1"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8A8++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU1,Filter3_14_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8AC++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU1,Filter3_14_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8B0++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU1,Filter3_14_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8B4++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU1,Filter3_15_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU1,Filter3_15_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x8BC++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU1,Filter3_15_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8C0++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU1,Filter3_15_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8C4++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU1,Filter3_15_LenPru1"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8C8++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU1,Filter3_15_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8CC++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU1,Filter3_15_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8D0++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU1,Filter3_15_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8D4++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU1,Filter3_0P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x8D8++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU1,Filter3_0P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x8DC++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8E0++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8E4++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU1,Filter3_1P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x8E8++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU1,Filter3_1P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x8EC++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8F0++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8F4++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU1,Filter3_2P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x8F8++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU1,Filter3_2P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x8FC++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x900++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x904++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU1,Filter3_3P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x908++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU1,Filter3_3P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x90C++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x910++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x914++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU1,Filter3_4P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x918++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU1,Filter3_4P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x91C++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x920++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x924++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU1,Filter3_5P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x928++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU1,Filter3_5P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x92C++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x930++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x934++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU1,Filter3_6P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x938++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU1,Filter3_6P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x93C++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x940++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x944++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU1,Filter3_7P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x948++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU1,Filter3_7P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x94C++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x950++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x954++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU1,Filter3_8P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x958++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU1,Filter3_8P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x95C++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x960++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x964++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU1,Filter3_9P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x968++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU1,Filter3_9P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x96C++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x970++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x974++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU1,Filter3_10P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x978++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU1,Filter3_10P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x97C++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x980++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x984++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU1,Filter3_11P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x988++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU1,Filter3_11P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x98C++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x990++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x994++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU1,Filter3_12P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x998++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU1,Filter3_12P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x99C++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9A0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9A4++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU1,Filter3_13P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x9A8++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU1,Filter3_13P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x9AC++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9B0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9B4++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU1,Filter3_14P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x9B8++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU1,Filter3_14P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x9BC++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9C0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9C4++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU1,Filter3_15P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x9C8++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU1,Filter3_15P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x9CC++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9D0++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9D4++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU1,FilterByteCountPru1"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU1            ,RX current filter Byte Count"
group.long 0x9D8++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU1,rx_class0_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x9DC++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU1,rx_class0_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x9E0++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU1,rx_class1_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x9E4++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU1,rx_class1_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x9E8++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU1,rx_class2_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x9EC++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU1,rx_class2_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x9F0++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU1,rx_class3_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x9F4++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU1,rx_class3_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x9F8++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU1,rx_class4_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x9FC++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU1,rx_class4_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0xA00++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU1,rx_class5_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0xA04++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU1,rx_class5_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0xA08++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU1,rx_class6_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0xA0C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU1,rx_class6_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0xA10++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU1,rx_class7_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0xA14++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU1,rx_class7_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0xA18++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU1,rx_class8_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0xA1C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU1,rx_class8_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0xA20++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU1,rx_class9_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0xA24++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU1,rx_class9_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0xA28++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU1,rx_class10_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0xA2C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU1,rx_class10_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0xA30++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU1,rx_class11_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0xA34++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU1,rx_class11_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0xA38++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU1,rx_class12_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0xA3C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU1,rx_class12_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0xA40++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU1,rx_class13_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0xA44++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU1,rx_class13_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0xA48++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU1,rx_class14_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0xA4C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU1,rx_class14_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0xA50++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU1,rx_class15_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0xA54++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU1,rx_class15_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0xA58++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU1,rx_class_cfg1Pru1"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0xA5C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU1,rx_class_cfg2Pru1"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0xA60++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA64++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA68++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA6C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA70++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA74++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA78++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA7C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA80++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA84++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA88++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA8C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA90++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA94++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA98++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA9C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xAA0++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU1,RX_greenPru1"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA4++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU1,SAHashPru1"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0xAA8++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU1,ConnectionHashPru1"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0xAAC++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU1,ConnectionHashStartPru1"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0xAB0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU1,RX_RateConfiguration0Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU1,RX_RateConfiguration1Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU1,RX_RateConfiguration2Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xABC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU1,RX_RateConfiguration3Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU1,RX_RateConfiguration4Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU1,RX_RateConfiguration5Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU1,RX_RateConfiguration6Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xACC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU1,RX_RateConfiguration7Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAD0++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU1,RX_RateSourceSelect0Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD4++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU1,RX_RateSourceSelect1Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU1,TX_RateConfiguration1_0Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xADC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU1,TX_RateConfiguration2_0Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0xAE0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU1,TX_RateConfiguration1_1Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAE4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU1,TX_RateConfiguration2_1Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0xAE8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU1,TX_RateConfiguration1_2Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAEC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU1,TX_RateConfiguration2_2Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0xAF0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU1,TX_RateConfiguration1_3Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAF4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU1,TX_RateConfiguration2_3Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0xAF8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU1,TX_RateConfiguration1_4Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAFC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU1,TX_RateConfiguration2_4Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0xB00++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU1,TX_RateConfiguration1_5Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB04++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU1,TX_RateConfiguration2_5Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0xB08++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU1,TX_RateConfiguration1_6Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB0C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU1,TX_RateConfiguration2_6Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0xB10++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU1,TX_RateConfiguration1_7Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB14++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU1,TX_RateConfiguration2_7Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0xB18++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU1,RXGoodFrameCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0xB1C++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU1,RXBCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0xB20++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU1,RXMCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0xB24++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU1,RXCRCErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0xB28++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU1,RXMIIErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0xB2C++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU1,RXOddNibbleFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0xB30++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU1,RXMaxSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0xB34++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU1,RXMaxSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0xB38++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU1,RXMinSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0xB3C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU1,RXMinSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0xB40++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU1,RXoverrunFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0xB44++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU1       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0xB48++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU1       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0xB4C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU1       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0xB50++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU1       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0xB54++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU1       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0xB58++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU1       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0xB5C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU1       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0xB60++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU1       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0xB64++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU1       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0xB68++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU1       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0xB6C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU1      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0xB70++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU1      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0xB74++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU1      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0xB78++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU1      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0xB7C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU1      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0xB80++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU1      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0xB84++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU1,RXSMDFragErrCountPru1"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU1      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU1    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU1     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU1    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0xB88++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU1,RXBucket1SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0xB8C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU1,RXBucket2SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0xB90++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU1,RXBucket3SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0xB94++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU1,RXBucket4SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0xB98++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU1,RX64BSizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0xB9C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU1,RXBucket1SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0xBA0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU1,RXBucket2SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBA4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU1,RXBucket3SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBA8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU1,RXBucket4SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xBAC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU1,RXBucket5SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0xBB0++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU1,RXTotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0xBB4++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU1,RX_TX_TotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0xBB8++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT1,TXGoodFrameCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0xBBC++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT1,TXBCFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0xBC0++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT1,TXMFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0xBC4++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT1,TXOddNibbleFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0xBC8++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT1,TXUnderFlowErrCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0xBCC++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT1,TXMaxSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0xBD0++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT1,TXMaxSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0xBD4++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT1,TXMinSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0xBD8++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT1,TXMinSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0xBDC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT1,TXBucket1SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0xBE0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT1,TXBucket2SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0xBE4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT1,TXBucket3SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0xBE8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT1,TXBucket4SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0xBEC++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT1,TX64BSizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0xBF0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT1,TXBucket1SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0xBF4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT1,TXBucket2SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBF8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT1,TXBucket3SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBFC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT1,TXBucket4SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xC00++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT1,TXBucket5SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0xC04++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT1,TXTotalByteCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0xC08++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT1,TXHSRTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0xC0C++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT1,TXHSRSeqPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0xC10++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT1,TXVLANTYPETAGPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0xC14++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT1,TXVLANINSTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"
base eaxi:0xB032000
width 22.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RXCFG0,RX Configuration 0 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS0      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW0          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW0           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE0     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN0            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL0           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE0     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS0 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE0           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RXCFG1,RX Configuration 1 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS1      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW1          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW1           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE1     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN1            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL1           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE1     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS1 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE1           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TXCFG0,TX Control Register 0"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY0         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY0      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN0        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR0 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE0 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL0          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE0          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE0     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE0           ,0h = TX PORT is disabled/stopped immediately" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TXCFG1,TX Control Register 1"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY1         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY1      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN1        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR1 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE1 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL1          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE1          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE1     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE1           ,0h = TX PORT is disabled/stopped immediately" "0,1"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_TX_CRC0,Transmit CRC32 Register 0"
hexmask.long 0x00 0.--31. 1. " TX_CRC0               ,FCS (CRC32) data can be read by PRU for diagnostics"
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_TX_CRC1,Transmit CRC32 Register 1"
hexmask.long 0x00 0.--31. 1. " TX_CRC1               ,FCS (CRC32) data can be read by PRU for diagnostics"
group.long 0x30++0x3
line.long 0x00 "ICSSG_TX_IPG0,TX IPG Register 0"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG0               ,Define the minimum Inter Packet Gap"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_IPG1,TX IPG Register 1"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG1               ,Define the minimum Inter Packet Gap"
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_PRS0,PORT_RAW_STATUS Register 0"
bitfld.long 0x00 1. " SYNC_MII0_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII0_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_PRS1,PORT_RAW_STATUS Register 1"
bitfld.long 0x00 1. " SYNC_MII1_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII1_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_RX_FRMS0,RX Frame Size Register 0"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM0           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM0          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x44++0x3
line.long 0x00 "ICSSG_RX_FRMS1,RX Frame Size Register 1"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM1           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM1          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x48++0x3
line.long 0x00 "ICSSG_RX_PCNT0,RX Preamble Cnt Register 0"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT0          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT0         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_RX_PCNT1,RX Preamble Cnt Register 1"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT1          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT1         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x3
line.long 0x00 "ICSSG_RX_ERR0,RX Error Register 0"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR0       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR0      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR0      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR0     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
group.long 0x54++0x3
line.long 0x00 "ICSSG_RX_ERR1,RX Error Register 1"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR1       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR1      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR1      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR1     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL0,RX FIFO Level 0 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL0        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL1,RX FIFO Level 1 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL1        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL0,TX FIFO Register 0"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL0        ,Define the number of valid nibbles in the TX FIFO"
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL1,TX FIFO Register 1"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL1        ,Define the number of valid nibbles in the TX FIFO"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PROTECT"
tree "PRU_ICSSG0_PR1_PROT_SLV"
base eaxi:0xB024C00
width 18.
group.long 0x0++0x3
line.long 0x00 "ICSSG_UNLOCK_KEY,LOCK KEY"
hexmask.long 0x00 0.--31. 1. " UNLOCK_KEY         ,UnLock Key Pattern 0x83E7_0B13. To UnLock 0x0000_0000. To Lock Must unlock to update MMRs."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CFG,Config"
bitfld.long 0x00 6. " PRU1_DMEM1_LOCK_EN ,Write Protect DMEM10h = Disable 1h = Enable. When enabled only PRU1 can write to DMEM1" "0,1"
bitfld.long 0x00 5. "         PRU0_DMEM0_LOCK_EN ,Write Protect DMEM00h = Disable 1h = Enable. When enabled only PRU0 can write to DMEM0" "0,1"
textline "                           "
bitfld.long 0x00 4. " ICSS_CFG_WP_EN     ,Write Protect ICSS_CFG0h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 3. "         RTU1_PRU_WP_EN     ,Write Protect RTU_PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 2. " RTU0_PRU_WP_EN     ,Write Protect RTU_PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 1. "         PRU1_WP_EN         ,Write Protect PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 0. " PRU0_WP_EN         ,Write Protect PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM"
tree "PRU_ICSSG0_PR1_PDSP0_IRAM"
base eaxi:0xB02200
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_PDSP1_IRAM"
base eaxi:0xB02400
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM"
base eaxi:0xB023000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM"
base eaxi:0xB023800
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
tree "PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG"
base eaxi:0xB022400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"
base eaxi:0xB023400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"
base eaxi:0xB023C00
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG"
base eaxi:0xB024400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAM"
tree "PRU_ICSSG0_RAM_SLV_RAM"
base eaxi:0xB010000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAT_SLICE0"
tree "PRU_ICSSG0_RAT_SLICE0_CFG_CFG"
base eaxi:0xB008000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree "PRU_ICSSG0_RAT_SLICE1_CFG"
base eaxi:0xB009000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_TASKS_MGR_PRU0"
tree "PRU_ICSSG0_TASKS_MGR_PRU0"
base eaxi:0xB02A000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG0_TASKS_MGR_RTU0"
base eaxi:0xB02A100
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG0_TASKS_MGR_PRU1"
base eaxi:0xB02A200
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG0_TASKS_MGR_RTU1"
base eaxi:0xB02A300
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_UART0"
tree "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV"
base eaxi:0xB028000
width 16.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RBR_TBR,Registers"
hexmask.long.word 0x00 8.--17. 1. " TBR_DATA    ,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "      RBR_DATA     ,Receive Buffer Register"
group.long 0x4++0x3
line.long 0x00 "ICSSG_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x00 3. " EDSSI       ,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x00 2. "         ELSI         ,Enable for Receiver Line Status Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " ETBEI       ,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x00 0. "         ERBI         ,Enable for Receiver Data Available Interrupt" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x00 14.--15. " FCR_RXFIFTL ,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x00 11. "         FCR_DMAMODE1 ,DMA Mode Select" "0,1"
textline "                         "
bitfld.long 0x00 10. " FCR_TXCLR   ,Transmitter FIFO Reset" "0,1"
bitfld.long 0x00 9. "         FCR_RXCLR    ,Receiver FIFO Reset" "0,1"
textline "                         "
bitfld.long 0x00 8. " FCR_FIFOEN  ,FIFO Enable Register" "0,1"
bitfld.long 0x00 6.--7. "         IIR_FIFOEN   ,FIFOs enabled" "0,1,2,3"
textline "                         "
bitfld.long 0x00 1.--3. " IIR_INTID   ,Interrupt Type" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         IIR_IPEND    ,Receiver Data Available Interrupt Pending" "0,1"
group.long 0xC++0x3
line.long 0x00 "ICSSG_LCTR,Line Control Register"
bitfld.long 0x00 7. " DLAB        ,Divisor Latch Access Bit" "0,1"
bitfld.long 0x00 6. "         BC           ,Break Control" "0,1"
textline "                         "
bitfld.long 0x00 5. " SP          ,Stick Parity" "0,1"
bitfld.long 0x00 4. "         EPS          ,Even Parity Select" "0,1"
textline "                         "
bitfld.long 0x00 3. " PEN         ,Parity Enable" "0,1"
bitfld.long 0x00 2. "         STB          ,Number of Stop Bits" "0,1"
textline "                         "
bitfld.long 0x00 1. " WLS1        ,Word Length Select Bit 1" "0,1"
bitfld.long 0x00 0. "         WLS0         ,Word Length Select Bit 0" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MCTR,Modem Control Register"
bitfld.long 0x00 5. " AFE         ,Autoflow Control Enable" "0,1"
bitfld.long 0x00 4. "         LOOP         ,LOOP Bit" "0,1"
textline "                         "
bitfld.long 0x00 3. " OUT2        ,Out2 Bit" "0,1"
bitfld.long 0x00 2. "         OUT1         ,Out1 Bit" "0,1"
textline "                         "
bitfld.long 0x00 1. " RTS         ,Ready to Send" "0,1"
bitfld.long 0x00 0. "         DTR          ,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "ICSSG_LSR1,Line Status Register1"
bitfld.long 0x00 7. " RXFIFOE     ,Receiver FIFO Error" "0,1"
bitfld.long 0x00 6. "         TEMT         ,Transmitter Empty" "0,1"
textline "                         "
bitfld.long 0x00 5. " THRE        ,Transmitter Holding Register" "0,1"
bitfld.long 0x00 4. "         BI           ,Break Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " FE          ,Framing Error" "0,1"
bitfld.long 0x00 2. "         PE           ,Parity Error" "0,1"
textline "                         "
bitfld.long 0x00 1. " OE          ,Overrun Error" "0,1"
bitfld.long 0x00 0. "         DR           ,Data Ready" "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "ICSSG_MSR,Modem Status Register"
bitfld.long 0x00 7. " CD          ,Carrier Detect" "0,1"
bitfld.long 0x00 6. "         RI           ,Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 5. " DSR         ,Data Set Ready" "0,1"
bitfld.long 0x00 4. "         CTS          ,Clear To Send" "0,1"
textline "                         "
bitfld.long 0x00 3. " DCD         ,Delta Carrier Detect" "0,1"
bitfld.long 0x00 2. "         TERI         ,Trailing Edge Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 1. " DDSR        ,Delta Set Ready" "0,1"
bitfld.long 0x00 0. "         DCTS         ,Delta Clear To Send" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA        ,Scratch Register Bits"
group.long 0x20++0x3
line.long 0x00 "ICSSG_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLL         ,Divisor Latch [LSB]"
group.long 0x24++0x3
line.long 0x00 "ICSSG_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLH         ,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_PID,Peripheral ID Register"
hexmask.long 0x00 0.--31. 1. " PID         ,"
group.long 0x30++0x3
line.long 0x00 "ICSSG_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. " URST        ,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "         UTRST        ,UART Transmitter Reset Bit" "0,1"
textline "                         "
bitfld.long 0x00 13. " URRST       ,UART Receiver Reset Bit" "0,1"
bitfld.long 0x00 1. "         RES          ,Free Bit" "0,1"
textline "                         "
bitfld.long 0x00 0. " FREE        ,Free Bit" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_MODE,UART Mode Definition Register"
bitfld.long 0x00 0. " OSM_SEL     ,Oversampling Mode Select" "0,1"
width 0x0B
tree.end
tree.end
tree.end
tree "ICSS_1"
tree "PRU_ICSSG_CFG"
tree "PRU_ICSSG1_PR1_CFG_SLV"
base eaxi:0xB126000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID_REG,Register"
hexmask.long 0x00 0.--31. 1. " ICSS_IDVER                 ,Module ID field"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_HWDIS_REG,HW Disable Register"
hexmask.long.byte 0x00 0.--7. 1. " HWDIS                      ,Read the state of the efuse bits which drive pr1_hw_disable[7:0]"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_GPCFG0_REG,GP Configuration 0 Register"
in
textline "                                         "
hgroup.long 0xC++0x3
hide.long 0x00 "ICSSG_GPCFG1_REG,GP Configuration 1 Register"
in
textline "                                         "
group.long 0x10++0x3
line.long 0x00 "ICSSG_CGR_REG,Clock Gating Register"
bitfld.long 0x00 31. " ICSS_STOP_ACK              ,ICSS" "0,1"
bitfld.long 0x00 30. "         ICSS_STOP_REQ              ,ICSS" "0,1"
textline "                                         "
bitfld.long 0x00 29. " ICSS_PWR_IDLE              ,ICSS" "0,1"
bitfld.long 0x00 17. "         IEP_CLK_EN                 ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 16. " IEP_CLK_STOP_ACK           ,IEP" "0,1"
bitfld.long 0x00 15. "         IEP_CLK_STOP_REQ           ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 14. " ECAP_CLK_EN                ,ECAP" "0,1"
bitfld.long 0x00 13. "         ECAP_CLK_STOP_ACK          ,ECAP" "0,1"
textline "                                         "
bitfld.long 0x00 12. " ECAP_CLK_STOP_REQ          ,ECAP" "0,1"
bitfld.long 0x00 11. "         UART_CLK_EN                ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 10. " UART_CLK_STOP_ACK          ,UART" "0,1"
bitfld.long 0x00 9. "         UART_CLK_STOP_REQ          ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 8. " INTC_CLK_EN                ,INTC" "0,1"
bitfld.long 0x00 7. "         INTC_CLK_STOP_ACK          ,INTC" "0,1"
textline "                                         "
bitfld.long 0x00 6. " INTC_CLK_STOP_REQ          ,INTC" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_GPECFG0_REG,GP Enc Configuration 0 Register"
bitfld.long 0x00 17. " PRU0_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU0_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU0_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU0_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU0_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU0_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU0_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU0_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x18++0x3
line.long 0x00 "ICSSG_GPECFG1_REG,GP Enc Configuration 1 Register"
bitfld.long 0x00 17. " PRU1_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU1_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU1_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU1_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU1_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU1_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU1_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU1_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_MII_RT_REG,MII_RT Event Enable Register"
bitfld.long 0x00 0. " MII_RT_EVENT_EN            ,Note: This bit field is non-functional on this device." "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_IEPCLK_REG,IEP Configuration Register"
bitfld.long 0x00 1. " IEP1_SLV_EN                ,IEP1 Master Counter Slave enable" "0,1"
bitfld.long 0x00 0. "         IEP_OCP_CLK_EN             ,Defines the source of the IEP CLK" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_SPP_REG,Scratchpad Priority and Shift Register"
bitfld.long 0x00 3. " RTU_XFR_SHIFT_EN           ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 2. "         XFR_BYTE_SHIFT_EN          ,Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations." "0,1"
textline "                                         "
bitfld.long 0x00 1. " XFR_SHIFT_EN               ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 0. "         PRU1_PAD_HP_EN             ,Reserved" "0,1"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CORE_SYNC_REG,CoreSync Configuration Register"
bitfld.long 0x00 0. " CORE_VBUSP_SYNC_EN         ," "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SA_MX_REG,SA Mux Selection Register"
bitfld.long 0x00 10.--11. " PWM3_REMAP_EN              ,pwm3_remap_en controls icss_wrap glue" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_REMAP_EN              ,pwm0_remap_en controls icss_wrap glue" "0,1,2,3"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " SA_MUX_SEL                 ,Reserved"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU0_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU0_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG0,PRU0 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG0,PRU0 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU0_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x50++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG1,PRU0 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0x54++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG1,PRU0 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU0_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0x58++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG2,PRU0 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0x5C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG2,PRU0 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU0_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0x60++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG3,PRU0 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG3,PRU0 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU0_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0x68++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG4,PRU0 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG4,PRU0 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU0_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0x70++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG5,PRU0 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0x74++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG5,PRU0 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU0_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0x78++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG6,PRU0 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG6,PRU0 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU0_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0x80++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG7,PRU0 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0x84++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG7,PRU0 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU0_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0x88++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG8,PRU0 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG8,PRU0 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU0_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0x90++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU1_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU1_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x94++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG0,PRU1 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x98++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG0,PRU1 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU1_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG1,PRU1 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG1,PRU1 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU1_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG2,PRU1 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG2,PRU1 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU1_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG3,PRU1 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG3,PRU1 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU1_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG4,PRU1 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG4,PRU1 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU1_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG5,PRU1 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG5,PRU1 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU1_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG6,PRU1 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG6,PRU1 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU1_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG7,PRU1 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG7,PRU1 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU1_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG8,PRU1 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG8,PRU1 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU1_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_PRU0_ED_RX_CFG_REG,PRU0 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU0_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU0_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_PRU0_ED_TX_CFG_REG,PRU0 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU0_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU0_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU0_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU0_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU0_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU0_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG0_REG,PRU0 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG1_REG,PRU0 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF0++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG0_REG,PRU0 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG1_REG,PRU0 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG0_REG,PRU0 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG1_REG,PRU0 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x100++0x3
line.long 0x00 "ICSSG_PRU1_ED_RX_CFG_REG,PRU1 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU1_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU1_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "ICSSG_PRU1_ED_TX_CFG_REG,PRU1 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU1_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU1_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU1_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU1_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU1_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU1_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0x108++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG0_REG,PRU1 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x10C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG1_REG,PRU1 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x110++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG0_REG,PRU1 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x114++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG1_REG,PRU1 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x118++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG0_REG,PRU1 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG1_REG,PRU1 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x124++0x3
line.long 0x00 "ICSSG_RTU0_POKE_EN0_REG,RTU0 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU0_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU0_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU0_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU0_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU0_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU0_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU0_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU0_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x12C++0x3
line.long 0x00 "ICSSG_RTU1_POKE_EN0_REG,RTU1 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU1_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU1_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU1_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU1_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU1_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU1_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU1_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU1_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x3
line.long 0x00 "ICSSG_PWM0,PWM0 Trip Configuration Register"
bitfld.long 0x00 30. " PWM0_TRIP_S                ,Trip Status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM0_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM0_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM0_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM0_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM0_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM0_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM0_DEBOUNCE_VALUE        ,Debounce counter , defines the number of core_clk required for the pulse not to get rejected"
group.long 0x134++0x3
line.long 0x00 "ICSSG_PWM1,PWM1 Trip Configuration Register"
bitfld.long 0x00 30. " PWM1_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM1_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM1_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM1_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM1_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM1_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM1_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM1_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x138++0x3
line.long 0x00 "ICSSG_PWM2,PWM2 Trip Configuration Register"
bitfld.long 0x00 30. " PWM2_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM2_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM2_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM2_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM2_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM2_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM2_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM2_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_PWM3,PWM3 Trip Configuration Register"
bitfld.long 0x00 30. " PWM3_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM3_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM3_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM3_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM3_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM3_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM3_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM3_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x140++0x3
line.long 0x00 "ICSSG_PWM0_0,PWM0 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM0_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x144++0x3
line.long 0x00 "ICSSG_PWM0_1,PWM0 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM0_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x148++0x3
line.long 0x00 "ICSSG_PWM0_2,PWM0 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM0_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x14C++0x3
line.long 0x00 "ICSSG_PWM1_0,PWM1 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM1_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x150++0x3
line.long 0x00 "ICSSG_PWM1_1,PWM1 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM1_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x154++0x3
line.long 0x00 "ICSSG_PWM1_2,PWM1 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM1_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x158++0x3
line.long 0x00 "ICSSG_PWM2_0,PWM2 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM2_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_PWM2_1,PWM2 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM2_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_PWM2_2,PWM2 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM2_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x164++0x3
line.long 0x00 "ICSSG_PWM3_0,PWM3 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM3_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x168++0x3
line.long 0x00 "ICSSG_PWM3_1,PWM3 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM3_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x16C++0x3
line.long 0x00 "ICSSG_PWM3_2,PWM3 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM3_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x170++0x3
line.long 0x00 "ICSSG_SPIN_LOCK0,Spin Lock 0 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_0       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_0          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_0       ,Spin Lock Status" "0,1"
group.long 0x174++0x3
line.long 0x00 "ICSSG_SPIN_LOCK1,Spin Lock 1 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_1       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_1          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_1       ,Spin Lock Status" "0,1"
group.long 0x178++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG0,PA STATS PDSP0 Vector 0 Register"
bitfld.long 0x00 31. " PA_PDSP0_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP0_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP0_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x17C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT0,PA STATS PDSP0 Status 0 Register"
bitfld.long 0x00 1.--3. " PA_PDSP0_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP0_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG1,PA STATS PDSP0 Vector 1 Register"
bitfld.long 0x00 31. " PA_PDSP1_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP1_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP1_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT1,PA STATS PDSP0 Status 1 Register"
bitfld.long 0x00 1.--3. " PA_PDSP1_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP1_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x188++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG2,PA STATS PDSP0 Vector 2 Register"
bitfld.long 0x00 31. " PA_PDSP2_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP2_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP2_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT2,PA STATS PDSP0 Status 2 Register"
bitfld.long 0x00 1.--3. " PA_PDSP2_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP2_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG3,PA STATS PDSP0 Vector 3 Register"
bitfld.long 0x00 31. " PA_PDSP3_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP3_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP3_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x194++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT3,PA STATS PDSP0 Status 3 Register"
bitfld.long 0x00 1.--3. " PA_PDSP3_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP3_READY             ,pa_pdsp{i}_ready" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_DRAM0"
tree "PRU_ICSSG1_DRAM0_SLV_RAM"
base eaxi:0xB100000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree "PRU_ICSSG1_DRAM1_SLV_RAM"
base eaxi:0xB102000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECAP0"
tree "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV"
base eaxi:0xB130000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_TSCNT,Time Stamp Counter Register"
hexmask.long 0x00 0.--31. 1. " TSCNT      ,Active 32-bit counter register which is used as the capture time-base ."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CNTPHS,Counter Phase Control Register"
hexmask.long 0x00 0.--31. 1. " CNTPHS     ,Counter phase value register that can be programmed for phase lag/lead. This register shadows"
group.long 0x8++0x3
line.long 0x00 "ICSSG_CAP1,Capture-1 Register"
hexmask.long 0x00 0.--31. 1. " CAP1       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.(b) Software may be useful for test purposes/initialisation.(c) APRD shadow register (that is,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_CAP2,Capture-2 Register"
hexmask.long 0x00 0.--31. 1. " CAP2       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.b) Software may be useful for test purposes.c) ACMP shadow register (that is,"
group.long 0x10++0x3
line.long 0x00 "ICSSG_CAP3,Capture-3 Register"
hexmask.long 0x00 0.--31. 1. " CAP3       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APER) register. User updates the PWM period value via this register. In this mode"
group.long 0x14++0x3
line.long 0x00 "ICSSG_CAP4,Capture-4 Register"
hexmask.long 0x00 0.--31. 1. " CAP4       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. User updates the PWM compare value via this register. In this mode"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ECCTL2_ECCTL1,ECAP Control Register 1"
bitfld.long 0x00 27.--31. " FILTER     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        APWMPOL     ,APWM output polarity select:0 = output is active high (that is, compare value defines high time)1 = output is active low (that is, compare value defines low time)Note: This is applicable only in APWM operating mode." "0,1"
textline "                              "
bitfld.long 0x00 25. " CAP_APWM   ,CAP/APWM operating mode select:0 = ECAP module operates in capture mode. This mode forces the following configuration:a) Inhibitsb) Inhibits shadow loads onc) Permits user to enable ICSSG_CAP1 to ICSSG_CAP4 register load.d) ECAP input/APWM output pin operates as a capture input.1 = ECAP module operates in APWM mode. This mode forces the following configuration:a) Resets TSCNT on CTR = PRD event (period boundary).b) Permits shadow loading on ICSSG_CAP1 and ICSSG_CAP2 registers.c) Disables loading of time-stamps into ICSSG_CAP1 to ICSSG_CAP4 registers.d) ECAP input/APWM ouput pin operates as a APWM output." "0,1"
bitfld.long 0x00 24. "         SWSYNC      ,Software forced counter (0 = writing a zero has no effect will always return a zero1 = writing a one will force aNote: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode, the synchronizing can also be done via the CTR = PRD event." "0,1"
textline "                              "
bitfld.long 0x00 22.--23. " SYNCO_SEL  ,Sync-out select:0b00 = select sync-in event to be the sync-out signal (pass through)0b01 = select CTR = PRD event to be the sync-out signal0b10 = disable sync out signal0b11 = disable sync out signalNote: Selection CTR = PRD is meaningful only in APWM mode, however can still be chosen in CAP mode, if user believes it to be useful." "0,1,2,3"
bitfld.long 0x00 21. "         SYNCI_EN    ,Counter (0 = disable sync-in option1 = enable counter (" "0,1"
textline "                              "
bitfld.long 0x00 20. " TSCNTSTP   ,Counter stop (freeze) control:0 = counter stopped1 = counter free running" "0,1"
bitfld.long 0x00 19. "         REARM_RESET ,One-shot re-arming, that is, wait for stop trigger:0 = writing a zero has no effect (reading always returns a 0)1 = writing a one arms the one-shot sequence as follows:1) resets the mod4 counter to zero2) un-freezes the mod4 counter3) enables capture register loadsNote: The re-arm function is valid in onesht or continous mode." "0,1"
textline "                              "
bitfld.long 0x00 17.--18. " STOPVALUE  ,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.0b00 = stop after capture event 10b01 = stop after capture event 20b10 = stop after capture event 30b11 = stop after capture event 4Note: STOPVALUE is compared to mod4 counter, and when equal, the following two actions occur: (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited.Note: In one shot mode, further interrupt events are blocked until re-armed, once the number of events captured has been reached ." "0,1,2,3"
bitfld.long 0x00 16. "         CONT_ONESHT ,Continuous or one-shot mode control (applicable only in capture mode):0 = operate in continuous mode1 = operate in one-shot mode" "0,1"
textline "                              "
bitfld.long 0x00 15. " FREE       ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
bitfld.long 0x00 14. "         SOFT        ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
textline "                              "
bitfld.long 0x00 9.--13. " EVTFLTPS   ,Event filter prescale select:0b00000 divide by 1 (that is, no prescale, by-pass the prescaler)0b00001 divide by 20b00010 divide by 40b00011 divide by 60b00100 divide by 80b00101 divide by 100b11110 divide by 600b11111 divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "        CAPLDEN     ,Enable loading of CAP(1-4) registers on a capture event:0 = disable CAP 1-4 register loads at capture event time1 = enable CAP(1-4) register loads at capture event time" "0,1"
textline "                              "
bitfld.long 0x00 7. " CTRRST4    ,Counter reset on capture event 4:0 = do not reset counter on capture event 4 (absolute time stamp)1 = reset counter after event 4 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 6. "         CAP4POL     ,Capture event 4 polarity select:0 = capture event 4 triggered on a rising edge (RE)1 = capture event 4 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 5. " CTRRST3    ,Counter reset on capture event 3:0 = do not reset counter on capture event 3 (absolute time stamp)1 = reset counter after event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 4. "         CAP3POL     ,Capture event 3 polarity select:0 = capture event 3 triggered on a rising edge (RE)1 = capture event 3 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 3. " CTRRST2    ,Counter reset on capture event 2:0 = do not reset counter on capture event 2 (absolute time stamp)1 = reset counter after event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 2. "         CAP2POL     ,Capture event 2 polarity select:0 = capture event 2 triggered on a rising edge (RE)1 = capture event 2 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 1. " CTRRST1    ,Counter reset on capture event 1:0 = do not reset counter on capture event 1 (absolute time stamp)1 = reset counter after event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 0. "         CAP1POL     ,Capture event 1 polarity select:0 = capture event 1 triggered on a rising edge (RE)1 = capture event 1 triggered on a falling edge (FE)" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ECFLG_ECEINT,ECAP Interrupt Enable Register"
hexmask.long.byte 0x00 24.--31. 1. " FLAG_RESV0 ,"
bitfld.long 0x00 23. "        FLAG_CMPEQ  ,Compare equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 22. " FLAG_PRDEQ ,Period equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
bitfld.long 0x00 21. "         FLAG_CNTOVF ,Counter overflow status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is active in CAP and APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 20. " FLAG_CEVT4 ,Capture event 4 status flag:0 = indicates no event occurred1 = indicates the fourth event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 19. "         FLAG_CEVT3  ,Capture event 3 status flag:0 = indicates no event occurred1 = indicates the third event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 18. " FLAG_CEVT2 ,Capture event 2 status flag:0 = indicates no event occurred1 = indicates the second event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 17. "         FLAG_CEVT1  ,Capture event 1 status flag:0 = indicates no event occurred1 = indicates the first event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 16. " FLAG_INT   ,Global interrupt status flag:0 = indicates no interrupt generated1 = indicates that an interrupt was generated from one of the following events" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         EN_RESV1    ,"
textline "                              "
bitfld.long 0x00 7. " EN_CMPEQ   ,Compare equal interrupt enable:0 = disable compare equal as an interrupt source1 = enable compare equal as an interrupt source" "0,1"
bitfld.long 0x00 6. "         EN_PRDEQ    ,Period equal interrupt enable:0 = disable period equal as an interrupt source1 = enable period equal as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 5. " EN_CNTOVF  ,Counter overflow interrupt enable:0 = disable counter overflow as an interrupt source1 = enable counter overflow as an interrupt source" "0,1"
bitfld.long 0x00 4. "         EN_CEVT4    ,Capture event 4 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 3. " EN_CEVT3   ,Capture event 3 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 2. "         EN_CEVT2    ,Capture event 2 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 1. " EN_CEVT1   ,Capture event 1 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 0. "         EN_RESV0    ," "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_ECCLR,ECAP Interrupt Clear Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV0      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Compare equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Period equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Counter overflow status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Capture event 4 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Capture event 3 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Capture event 2 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Capture event 1 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 0. " INT        ,Global interrupt clear flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the clear flag and enable further interrupts to be generated if any of the clear flags are set to 1" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_ECFRC,ECAP Interrupt Forcing Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV1      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Force compare equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CMPEQ flag bit" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Force period equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the PRDEQ flag bit" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Force counter overflow:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CNTOVF flag bit" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Force capture event 4:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT4 flag bit" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Force capture event 3:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT3 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Force capture event 2:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT2 flag bit" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Force capture event 1:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT1 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 0. " RESV0      ," "0,1"
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_PID,ECAP Peripheral Id Register"
hexmask.long 0x00 0.--31. 1. " REVID      ,TI internal data."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECC_AGGR"
tree "PRU_ICSSG0_ECC_AGGR"
base eahb:0xBF01000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                       ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                           ,bu" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                    ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                       ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " REVMAJ                       ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                       ,Custom version" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " REVMIN                       ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_VECTOR,ECC Vector Register"
in
textline "                                    "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                     ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "ICSSG_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "ICSSG_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x13C++0x3
line.long 0x00 "ICSSG_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "ICSSG_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "ICSSG_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x200++0x3
line.long 0x00 "ICSSG_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                      ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                       ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "ICSSG_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                    "
group.long 0x208++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_IEP"
tree "PRU_ICSSG0_IEP0"
tree "PRU_ICSSG1_IEP0"
base eaxi:0xB12E000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG0_IEP1"
tree "PRU_ICSSG1_IEP1"
base eaxi:0xB12F000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree.end
tree.end
tree "PRU_ICSSG_INTC"
tree "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"
base eaxi:0xB120000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REVISION_REG,Revision Register"
bitfld.long 0x00 30.--31. " REV_SCHEME            ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     REV_MODULE     ,Module ID"
textline "                                          "
bitfld.long 0x00 11.--15. " REV_RTL               ,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    REV_MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 6.--7. " REV_CUSTOM            ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "     REV_MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x00 4. " PRIORITY_HOLD_MODE    ,Priority Holding Mode" "0,1"
bitfld.long 0x00 2.--3. "     NEST_MODE      ,Nesting Mode" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 1. " WAKEUP_MODE           ,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_GLOBAL_ENABLE_HINT_REG,Global Host Int Enable Register"
bitfld.long 0x00 0. " ENABLE_HINT_ANY       ,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_GLB_NEST_LEVEL_REG,Global Nesting Level Register"
bitfld.long 0x00 31. " GLB_NEST_AUTO_OVR     ,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     GLB_NEST_LEVEL ,Global Nesting Level"
wgroup.long 0x20++0x3
line.long 0x00 "ICSSG_STATUS_SET_INDEX_REG,Status Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_SET_INDEX      ,Status Set Index Register (write index to set status of)"
wgroup.long 0x24++0x3
line.long 0x00 "ICSSG_STATUS_CLR_INDEX_REG,Status Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_CLR_INDEX      ,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ENABLE_SET_INDEX_REG,Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_SET_INDEX      ,Enable Set Index Register (write index to set enable of)"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_INDEX_REG,Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_CLR_INDEX      ,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_SET_INDEX_REG,Host Int Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Enable set for Host Interrupts"
group.long 0x38++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_CLR_INDEX_REG,Host Int Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x00 "ICSSG_GLB_PRI_INTR_REG,Global Prioritized Interrupt Register"
bitfld.long 0x00 31. " GLB_NONE              ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     GLB_PRI_INTR   ,Prioritized Interrupt"
group.long 0x200++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG0,Raw Status Register 0"
bitfld.long 0x00 31. " RAW_STATUS_31         ,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_30  ,Raw Status (write 1 to set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_29         ,Raw Status (write 1 to set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_28  ,Raw Status (write 1 to set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_27         ,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_26  ,Raw Status (write 1 to set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_25         ,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_24  ,Raw Status (write 1 to set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_23         ,Raw Status (write 1 to set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_22  ,Raw Status (write 1 to set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_21         ,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_20  ,Raw Status (write 1 to set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_19         ,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_18  ,Raw Status (write 1 to set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_17         ,Raw Status (write 1 to set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_16  ,Raw Status (write 1 to set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_15         ,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_14  ,Raw Status (write 1 to set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_13         ,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_12  ,Raw Status (write 1 to set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_11         ,Raw Status (write 1 to set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_10  ,Raw Status (write 1 to set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_9          ,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_8   ,Raw Status (write 1 to set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_7          ,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_6   ,Raw Status (write 1 to set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_5          ,Raw Status (write 1 to set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_4   ,Raw Status (write 1 to set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_3          ,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_2   ,Raw Status (write 1 to set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_1          ,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_0   ,Raw Status (write 1 to set) for intr_in[0]" "0,1"
group.long 0x204++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG1,Raw Status Register 1"
bitfld.long 0x00 31. " RAW_STATUS_63         ,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_62  ,Raw Status (write 1 to set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_61         ,Raw Status (write 1 to set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_60  ,Raw Status (write 1 to set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_59         ,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_58  ,Raw Status (write 1 to set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_57         ,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_56  ,Raw Status (write 1 to set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_55         ,Raw Status (write 1 to set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_54  ,Raw Status (write 1 to set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_53         ,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_52  ,Raw Status (write 1 to set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_51         ,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_50  ,Raw Status (write 1 to set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_49         ,Raw Status (write 1 to set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_48  ,Raw Status (write 1 to set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_47         ,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_46  ,Raw Status (write 1 to set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_45         ,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_44  ,Raw Status (write 1 to set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_43         ,Raw Status (write 1 to set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_42  ,Raw Status (write 1 to set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_41         ,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_40  ,Raw Status (write 1 to set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_39         ,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_38  ,Raw Status (write 1 to set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_37         ,Raw Status (write 1 to set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_36  ,Raw Status (write 1 to set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_35         ,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_34  ,Raw Status (write 1 to set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_33         ,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_32  ,Raw Status (write 1 to set) for intr_in[32]" "0,1"
group.long 0x208++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG2,Raw Status Register 2"
bitfld.long 0x00 31. " RAW_STATUS_95         ,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_94  ,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_93         ,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_92  ,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_91         ,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_90  ,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_89         ,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_88  ,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_87         ,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_86  ,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_85         ,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_84  ,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_83         ,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_82  ,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_81         ,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_80  ,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_79         ,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_78  ,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_77         ,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_76  ,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_75         ,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_74  ,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_73         ,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_72  ,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_71         ,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_70  ,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_69         ,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_68  ,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_67         ,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_66  ,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_65         ,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_64  ,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG3,Raw Status Register 3"
bitfld.long 0x00 31. " RAW_STATUS_127        ,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_126 ,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_125        ,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_124 ,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_123        ,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_122 ,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_121        ,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_120 ,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_119        ,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_118 ,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_117        ,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_116 ,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_115        ,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_114 ,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_113        ,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_112 ,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_111        ,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_110 ,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_109        ,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_108 ,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_107        ,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_106 ,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_105        ,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_104 ,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_103        ,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_102 ,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_101        ,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_100 ,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_99         ,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_98  ,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_97         ,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_96  ,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG4,Raw Status Register 4"
bitfld.long 0x00 31. " RAW_STATUS_159        ,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_158 ,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_157        ,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_156 ,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_155        ,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_154 ,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_153        ,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_152 ,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_151        ,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_150 ,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_149        ,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_148 ,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_147        ,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_146 ,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_145        ,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_144 ,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_143        ,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_142 ,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_141        ,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_140 ,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_139        ,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_138 ,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_137        ,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_136 ,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_135        ,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_134 ,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_133        ,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_132 ,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_131        ,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_130 ,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_129        ,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_128 ,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG0,Enabled Status Register 0"
bitfld.long 0x00 31. " ENA_STATUS_31         ,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_30  ,Enabled Status for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_29         ,Enabled Status for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_28  ,Enabled Status for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_27         ,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_26  ,Enabled Status for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_25         ,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_24  ,Enabled Status for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_23         ,Enabled Status for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_22  ,Enabled Status for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_21         ,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_20  ,Enabled Status for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_19         ,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_18  ,Enabled Status for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_17         ,Enabled Status for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_16  ,Enabled Status for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_15         ,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_14  ,Enabled Status for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_13         ,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_12  ,Enabled Status for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_11         ,Enabled Status for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_10  ,Enabled Status for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_9          ,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_8   ,Enabled Status for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_7          ,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_6   ,Enabled Status for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_5          ,Enabled Status for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_4   ,Enabled Status for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_3          ,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_2   ,Enabled Status for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_1          ,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_0   ,Enabled Status for intr_in[0]" "0,1"
group.long 0x284++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG1,Enabled Status Register 1"
bitfld.long 0x00 31. " ENA_STATUS_63         ,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_62  ,Enabled Status for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_61         ,Enabled Status for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_60  ,Enabled Status for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_59         ,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_58  ,Enabled Status for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_57         ,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_56  ,Enabled Status for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_55         ,Enabled Status for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_54  ,Enabled Status for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_53         ,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_52  ,Enabled Status for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_51         ,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_50  ,Enabled Status for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_49         ,Enabled Status for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_48  ,Enabled Status for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_47         ,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_46  ,Enabled Status for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_45         ,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_44  ,Enabled Status for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_43         ,Enabled Status for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_42  ,Enabled Status for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_41         ,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_40  ,Enabled Status for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_39         ,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_38  ,Enabled Status for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_37         ,Enabled Status for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_36  ,Enabled Status for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_35         ,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_34  ,Enabled Status for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_33         ,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_32  ,Enabled Status for intr_in[32]" "0,1"
group.long 0x288++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG2,Enabled Status Register 2"
bitfld.long 0x00 31. " ENA_STATUS_95         ,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_94  ,Enabled Status for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_93         ,Enabled Status for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_92  ,Enabled Status for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_91         ,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_90  ,Enabled Status for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_89         ,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_88  ,Enabled Status for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_87         ,Enabled Status for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_86  ,Enabled Status for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_85         ,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_84  ,Enabled Status for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_83         ,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_82  ,Enabled Status for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_81         ,Enabled Status for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_80  ,Enabled Status for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_79         ,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_78  ,Enabled Status for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_77         ,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_76  ,Enabled Status for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_75         ,Enabled Status for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_74  ,Enabled Status for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_73         ,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_72  ,Enabled Status for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_71         ,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_70  ,Enabled Status for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_69         ,Enabled Status for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_68  ,Enabled Status for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_67         ,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_66  ,Enabled Status for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_65         ,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_64  ,Enabled Status for slv_events_in[0]" "0,1"
group.long 0x28C++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG3,Enabled Status Register 3"
bitfld.long 0x00 31. " ENA_STATUS_127        ,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_126 ,Enabled Status for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_125        ,Enabled Status for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_124 ,Enabled Status for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_123        ,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_122 ,Enabled Status for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_121        ,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_120 ,Enabled Status for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_119        ,Enabled Status for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_118 ,Enabled Status for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_117        ,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_116 ,Enabled Status for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_115        ,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_114 ,Enabled Status for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_113        ,Enabled Status for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_112 ,Enabled Status for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_111        ,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_110 ,Enabled Status for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_109        ,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_108 ,Enabled Status for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_107        ,Enabled Status for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_106 ,Enabled Status for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_105        ,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_104 ,Enabled Status for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_103        ,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_102 ,Enabled Status for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_101        ,Enabled Status for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_100 ,Enabled Status for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_99         ,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_98  ,Enabled Status for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_97         ,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_96  ,Enabled Status for slv_events_in[32]" "0,1"
group.long 0x290++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG4,Enabled Status Register 4"
bitfld.long 0x00 31. " ENA_STATUS_159        ,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_158 ,Enabled Status for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_157        ,Enabled Status for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_156 ,Enabled Status for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_155        ,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_154 ,Enabled Status for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_153        ,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_152 ,Enabled Status for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_151        ,Enabled Status for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_150 ,Enabled Status for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_149        ,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_148 ,Enabled Status for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_147        ,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_146 ,Enabled Status for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_145        ,Enabled Status for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_144 ,Enabled Status for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_143        ,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_142 ,Enabled Status for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_141        ,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_140 ,Enabled Status for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_139        ,Enabled Status for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_138 ,Enabled Status for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_137        ,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_136 ,Enabled Status for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_135        ,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_134 ,Enabled Status for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_133        ,Enabled Status for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_132 ,Enabled Status for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_131        ,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_130 ,Enabled Status for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_129        ,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_128 ,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_ENABLE_REG0,Enable Register 0"
bitfld.long 0x00 31. " ENABLE_31             ,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30      ,Enable (set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29             ,Enable (set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28      ,Enable (set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27             ,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26      ,Enable (set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25             ,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24      ,Enable (set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23             ,Enable (set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22      ,Enable (set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21             ,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20      ,Enable (set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19             ,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18      ,Enable (set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17             ,Enable (set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16      ,Enable (set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15             ,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14      ,Enable (set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13             ,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12      ,Enable (set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11             ,Enable (set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10      ,Enable (set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9              ,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8       ,Enable (set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7              ,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6       ,Enable (set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5              ,Enable (set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4       ,Enable (set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3              ,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2       ,Enable (set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1              ,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0       ,Enable (set) for intr_in[0]" "0,1"
group.long 0x304++0x3
line.long 0x00 "ICSSG_ENABLE_REG1,Enable Register 1"
bitfld.long 0x00 31. " ENABLE_63             ,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62      ,Enable (set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61             ,Enable (set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60      ,Enable (set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59             ,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58      ,Enable (set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57             ,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56      ,Enable (set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55             ,Enable (set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54      ,Enable (set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53             ,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52      ,Enable (set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51             ,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50      ,Enable (set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49             ,Enable (set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48      ,Enable (set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47             ,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46      ,Enable (set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45             ,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44      ,Enable (set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43             ,Enable (set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42      ,Enable (set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41             ,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40      ,Enable (set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39             ,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38      ,Enable (set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37             ,Enable (set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36      ,Enable (set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35             ,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34      ,Enable (set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33             ,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32      ,Enable (set) for intr_in[32]" "0,1"
group.long 0x308++0x3
line.long 0x00 "ICSSG_ENABLE_REG2,Enable Register 2"
bitfld.long 0x00 31. " ENABLE_95             ,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94      ,Enable (set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93             ,Enable (set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92      ,Enable (set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91             ,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90      ,Enable (set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89             ,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88      ,Enable (set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87             ,Enable (set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86      ,Enable (set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85             ,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84      ,Enable (set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83             ,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82      ,Enable (set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81             ,Enable (set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80      ,Enable (set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79             ,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78      ,Enable (set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77             ,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76      ,Enable (set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75             ,Enable (set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74      ,Enable (set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73             ,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72      ,Enable (set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71             ,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70      ,Enable (set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69             ,Enable (set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68      ,Enable (set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67             ,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66      ,Enable (set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65             ,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64      ,Enable (set) for slv_events_in[0]" "0,1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_ENABLE_REG3,Enable Register 3"
bitfld.long 0x00 31. " ENABLE_127            ,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126     ,Enable (set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125            ,Enable (set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124     ,Enable (set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123            ,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122     ,Enable (set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121            ,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120     ,Enable (set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119            ,Enable (set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118     ,Enable (set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117            ,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116     ,Enable (set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115            ,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114     ,Enable (set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113            ,Enable (set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112     ,Enable (set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111            ,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110     ,Enable (set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109            ,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108     ,Enable (set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107            ,Enable (set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106     ,Enable (set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105            ,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104     ,Enable (set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103            ,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102     ,Enable (set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101            ,Enable (set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100     ,Enable (set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99             ,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98      ,Enable (set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97             ,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96      ,Enable (set) for slv_events_in[32]" "0,1"
group.long 0x310++0x3
line.long 0x00 "ICSSG_ENABLE_REG4,Enable Register 4"
bitfld.long 0x00 31. " ENABLE_159            ,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158     ,Enable (set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157            ,Enable (set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156     ,Enable (set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155            ,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154     ,Enable (set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153            ,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152     ,Enable (set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151            ,Enable (set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150     ,Enable (set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149            ,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148     ,Enable (set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147            ,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146     ,Enable (set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145            ,Enable (set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144     ,Enable (set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143            ,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142     ,Enable (set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141            ,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140     ,Enable (set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139            ,Enable (set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138     ,Enable (set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137            ,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136     ,Enable (set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135            ,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134     ,Enable (set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133            ,Enable (set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132     ,Enable (set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131            ,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130     ,Enable (set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129            ,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128     ,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG0,Enable Clear Register 0"
bitfld.long 0x00 31. " ENABLE_31_CLR         ,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30_CLR  ,Enable clear for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29_CLR         ,Enable clear for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28_CLR  ,Enable clear for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27_CLR         ,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26_CLR  ,Enable clear for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25_CLR         ,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24_CLR  ,Enable clear for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23_CLR         ,Enable clear for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22_CLR  ,Enable clear for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21_CLR         ,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20_CLR  ,Enable clear for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19_CLR         ,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18_CLR  ,Enable clear for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17_CLR         ,Enable clear for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16_CLR  ,Enable clear for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15_CLR         ,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14_CLR  ,Enable clear for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13_CLR         ,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12_CLR  ,Enable clear for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11_CLR         ,Enable clear for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10_CLR  ,Enable clear for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9_CLR          ,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8_CLR   ,Enable clear for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7_CLR          ,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6_CLR   ,Enable clear for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5_CLR          ,Enable clear for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4_CLR   ,Enable clear for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3_CLR          ,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2_CLR   ,Enable clear for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1_CLR          ,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0_CLR   ,Enable clear for intr_in[0]" "0,1"
group.long 0x384++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG1,Enable Clear Register 1"
bitfld.long 0x00 31. " ENABLE_63_CLR         ,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62_CLR  ,Enable clear for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61_CLR         ,Enable clear for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60_CLR  ,Enable clear for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59_CLR         ,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58_CLR  ,Enable clear for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57_CLR         ,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56_CLR  ,Enable clear for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55_CLR         ,Enable clear for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54_CLR  ,Enable clear for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53_CLR         ,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52_CLR  ,Enable clear for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51_CLR         ,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50_CLR  ,Enable clear for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49_CLR         ,Enable clear for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48_CLR  ,Enable clear for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47_CLR         ,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46_CLR  ,Enable clear for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45_CLR         ,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44_CLR  ,Enable clear for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43_CLR         ,Enable clear for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42_CLR  ,Enable clear for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41_CLR         ,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40_CLR  ,Enable clear for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39_CLR         ,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38_CLR  ,Enable clear for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37_CLR         ,Enable clear for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36_CLR  ,Enable clear for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35_CLR         ,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34_CLR  ,Enable clear for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33_CLR         ,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32_CLR  ,Enable clear for intr_in[32]" "0,1"
group.long 0x388++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG2,Enable Clear Register 2"
bitfld.long 0x00 31. " ENABLE_95_CLR         ,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94_CLR  ,Enable clear for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93_CLR         ,Enable clear for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92_CLR  ,Enable clear for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91_CLR         ,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90_CLR  ,Enable clear for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89_CLR         ,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88_CLR  ,Enable clear for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87_CLR         ,Enable clear for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86_CLR  ,Enable clear for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85_CLR         ,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84_CLR  ,Enable clear for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83_CLR         ,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82_CLR  ,Enable clear for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81_CLR         ,Enable clear for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80_CLR  ,Enable clear for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79_CLR         ,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78_CLR  ,Enable clear for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77_CLR         ,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76_CLR  ,Enable clear for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75_CLR         ,Enable clear for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74_CLR  ,Enable clear for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73_CLR         ,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72_CLR  ,Enable clear for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71_CLR         ,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70_CLR  ,Enable clear for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69_CLR         ,Enable clear for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68_CLR  ,Enable clear for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67_CLR         ,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66_CLR  ,Enable clear for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65_CLR         ,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64_CLR  ,Enable clear for slv_events_in[0]" "0,1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG3,Enable Clear Register 3"
bitfld.long 0x00 31. " ENABLE_127_CLR        ,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126_CLR ,Enable clear for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125_CLR        ,Enable clear for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124_CLR ,Enable clear for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123_CLR        ,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122_CLR ,Enable clear for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121_CLR        ,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120_CLR ,Enable clear for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119_CLR        ,Enable clear for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118_CLR ,Enable clear for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117_CLR        ,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116_CLR ,Enable clear for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115_CLR        ,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114_CLR ,Enable clear for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113_CLR        ,Enable clear for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112_CLR ,Enable clear for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111_CLR        ,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110_CLR ,Enable clear for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109_CLR        ,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108_CLR ,Enable clear for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107_CLR        ,Enable clear for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106_CLR ,Enable clear for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105_CLR        ,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104_CLR ,Enable clear for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103_CLR        ,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102_CLR ,Enable clear for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101_CLR        ,Enable clear for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100_CLR ,Enable clear for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99_CLR         ,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98_CLR  ,Enable clear for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97_CLR         ,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96_CLR  ,Enable clear for slv_events_in[32]" "0,1"
group.long 0x390++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG4,Enable Clear Register 4"
bitfld.long 0x00 31. " ENABLE_159_CLR        ,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158_CLR ,Enable clear for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157_CLR        ,Enable clear for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156_CLR ,Enable clear for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155_CLR        ,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154_CLR ,Enable clear for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153_CLR        ,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152_CLR ,Enable clear for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151_CLR        ,Enable clear for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150_CLR ,Enable clear for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149_CLR        ,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148_CLR ,Enable clear for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147_CLR        ,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146_CLR ,Enable clear for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145_CLR        ,Enable clear for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144_CLR ,Enable clear for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143_CLR        ,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142_CLR ,Enable clear for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141_CLR        ,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140_CLR ,Enable clear for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139_CLR        ,Enable clear for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138_CLR ,Enable clear for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137_CLR        ,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136_CLR ,Enable clear for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135_CLR        ,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134_CLR ,Enable clear for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133_CLR        ,Enable clear for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132_CLR ,Enable clear for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131_CLR        ,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130_CLR ,Enable clear for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129_CLR        ,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128_CLR ,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x3
line.long 0x00 "ICSSG_CH_MAP_REG0,Interrupt Channel Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " CH_MAP_3              ,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_2       ,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_1              ,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_0       ,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x404++0x3
line.long 0x00 "ICSSG_CH_MAP_REG1,Interrupt Channel Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " CH_MAP_7              ,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_6       ,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_5              ,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_4       ,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x408++0x3
line.long 0x00 "ICSSG_CH_MAP_REG2,Interrupt Channel Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " CH_MAP_11             ,Interrupt Channel Map for intr_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_10      ,Interrupt Channel Map for intr_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_9              ,Interrupt Channel Map for intr_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_8       ,Interrupt Channel Map for intr_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG3,Interrupt Channel Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " CH_MAP_15             ,Interrupt Channel Map for intr_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_14      ,Interrupt Channel Map for intr_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_13             ,Interrupt Channel Map for intr_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_12      ,Interrupt Channel Map for intr_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x410++0x3
line.long 0x00 "ICSSG_CH_MAP_REG4,Interrupt Channel Map Register for 16 to 16+3"
bitfld.long 0x00 24.--28. " CH_MAP_19             ,Interrupt Channel Map for intr_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_18      ,Interrupt Channel Map for intr_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_17             ,Interrupt Channel Map for intr_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_16      ,Interrupt Channel Map for intr_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x414++0x3
line.long 0x00 "ICSSG_CH_MAP_REG5,Interrupt Channel Map Register for 20 to 20+3"
bitfld.long 0x00 24.--28. " CH_MAP_23             ,Interrupt Channel Map for intr_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_22      ,Interrupt Channel Map for intr_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_21             ,Interrupt Channel Map for intr_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_20      ,Interrupt Channel Map for intr_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x418++0x3
line.long 0x00 "ICSSG_CH_MAP_REG6,Interrupt Channel Map Register for 24 to 24+3"
bitfld.long 0x00 24.--28. " CH_MAP_27             ,Interrupt Channel Map for intr_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_26      ,Interrupt Channel Map for intr_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_25             ,Interrupt Channel Map for intr_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_24      ,Interrupt Channel Map for intr_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG7,Interrupt Channel Map Register for 28 to 28+3"
bitfld.long 0x00 24.--28. " CH_MAP_31             ,Interrupt Channel Map for intr_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_30      ,Interrupt Channel Map for intr_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_29             ,Interrupt Channel Map for intr_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_28      ,Interrupt Channel Map for intr_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x420++0x3
line.long 0x00 "ICSSG_CH_MAP_REG8,Interrupt Channel Map Register for 32 to 32+3"
bitfld.long 0x00 24.--28. " CH_MAP_35             ,Interrupt Channel Map for intr_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_34      ,Interrupt Channel Map for intr_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_33             ,Interrupt Channel Map for intr_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_32      ,Interrupt Channel Map for intr_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x424++0x3
line.long 0x00 "ICSSG_CH_MAP_REG9,Interrupt Channel Map Register for 36 to 36+3"
bitfld.long 0x00 24.--28. " CH_MAP_39             ,Interrupt Channel Map for intr_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_38      ,Interrupt Channel Map for intr_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_37             ,Interrupt Channel Map for intr_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_36      ,Interrupt Channel Map for intr_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x428++0x3
line.long 0x00 "ICSSG_CH_MAP_REG10,Interrupt Channel Map Register for 40 to 40+3"
bitfld.long 0x00 24.--28. " CH_MAP_43             ,Interrupt Channel Map for intr_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_42      ,Interrupt Channel Map for intr_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_41             ,Interrupt Channel Map for intr_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_40      ,Interrupt Channel Map for intr_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG11,Interrupt Channel Map Register for 44 to 44+3"
bitfld.long 0x00 24.--28. " CH_MAP_47             ,Interrupt Channel Map for intr_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_46      ,Interrupt Channel Map for intr_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_45             ,Interrupt Channel Map for intr_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_44      ,Interrupt Channel Map for intr_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x430++0x3
line.long 0x00 "ICSSG_CH_MAP_REG12,Interrupt Channel Map Register for 48 to 48+3"
bitfld.long 0x00 24.--28. " CH_MAP_51             ,Interrupt Channel Map for intr_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_50      ,Interrupt Channel Map for intr_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_49             ,Interrupt Channel Map for intr_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_48      ,Interrupt Channel Map for intr_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x434++0x3
line.long 0x00 "ICSSG_CH_MAP_REG13,Interrupt Channel Map Register for 52 to 52+3"
bitfld.long 0x00 24.--28. " CH_MAP_55             ,Interrupt Channel Map for intr_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_54      ,Interrupt Channel Map for intr_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_53             ,Interrupt Channel Map for intr_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_52      ,Interrupt Channel Map for intr_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x438++0x3
line.long 0x00 "ICSSG_CH_MAP_REG14,Interrupt Channel Map Register for 56 to 56+3"
bitfld.long 0x00 24.--28. " CH_MAP_59             ,Interrupt Channel Map for intr_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_58      ,Interrupt Channel Map for intr_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_57             ,Interrupt Channel Map for intr_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_56      ,Interrupt Channel Map for intr_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG15,Interrupt Channel Map Register for 60 to 60+3"
bitfld.long 0x00 24.--28. " CH_MAP_63             ,Interrupt Channel Map for intr_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_62      ,Interrupt Channel Map for intr_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_61             ,Interrupt Channel Map for intr_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_60      ,Interrupt Channel Map for intr_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x440++0x3
line.long 0x00 "ICSSG_CH_MAP_REG16,Interrupt Channel Map Register for 64 to 64+3"
bitfld.long 0x00 24.--28. " CH_MAP_67             ,Interrupt Channel Map for slv_events_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_66      ,Interrupt Channel Map for slv_events_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_65             ,Interrupt Channel Map for slv_events_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_64      ,Interrupt Channel Map for slv_events_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x444++0x3
line.long 0x00 "ICSSG_CH_MAP_REG17,Interrupt Channel Map Register for 68 to 68+3"
bitfld.long 0x00 24.--28. " CH_MAP_71             ,Interrupt Channel Map for slv_events_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_70      ,Interrupt Channel Map for slv_events_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_69             ,Interrupt Channel Map for slv_events_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_68      ,Interrupt Channel Map for slv_events_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x448++0x3
line.long 0x00 "ICSSG_CH_MAP_REG18,Interrupt Channel Map Register for 72 to 72+3"
bitfld.long 0x00 24.--28. " CH_MAP_75             ,Interrupt Channel Map for slv_events_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_74      ,Interrupt Channel Map for slv_events_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_73             ,Interrupt Channel Map for slv_events_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_72      ,Interrupt Channel Map for slv_events_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG19,Interrupt Channel Map Register for 76 to 76+3"
bitfld.long 0x00 24.--28. " CH_MAP_79             ,Interrupt Channel Map for slv_events_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_78      ,Interrupt Channel Map for slv_events_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_77             ,Interrupt Channel Map for slv_events_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_76      ,Interrupt Channel Map for slv_events_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x450++0x3
line.long 0x00 "ICSSG_CH_MAP_REG20,Interrupt Channel Map Register for 80 to 80+3"
bitfld.long 0x00 24.--28. " CH_MAP_83             ,Interrupt Channel Map for slv_events_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_82      ,Interrupt Channel Map for slv_events_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_81             ,Interrupt Channel Map for slv_events_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_80      ,Interrupt Channel Map for slv_events_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x454++0x3
line.long 0x00 "ICSSG_CH_MAP_REG21,Interrupt Channel Map Register for 84 to 84+3"
bitfld.long 0x00 24.--28. " CH_MAP_87             ,Interrupt Channel Map for slv_events_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_86      ,Interrupt Channel Map for slv_events_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_85             ,Interrupt Channel Map for slv_events_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_84      ,Interrupt Channel Map for slv_events_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x458++0x3
line.long 0x00 "ICSSG_CH_MAP_REG22,Interrupt Channel Map Register for 88 to 88+3"
bitfld.long 0x00 24.--28. " CH_MAP_91             ,Interrupt Channel Map for slv_events_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_90      ,Interrupt Channel Map for slv_events_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_89             ,Interrupt Channel Map for slv_events_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_88      ,Interrupt Channel Map for slv_events_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG23,Interrupt Channel Map Register for 92 to 92+3"
bitfld.long 0x00 24.--28. " CH_MAP_95             ,Interrupt Channel Map for slv_events_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_94      ,Interrupt Channel Map for slv_events_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_93             ,Interrupt Channel Map for slv_events_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_92      ,Interrupt Channel Map for slv_events_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x460++0x3
line.long 0x00 "ICSSG_CH_MAP_REG24,Interrupt Channel Map Register for 96 to 96+3"
bitfld.long 0x00 24.--28. " CH_MAP_99             ,Interrupt Channel Map for slv_events_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_98      ,Interrupt Channel Map for slv_events_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_97             ,Interrupt Channel Map for slv_events_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_96      ,Interrupt Channel Map for slv_events_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x464++0x3
line.long 0x00 "ICSSG_CH_MAP_REG25,Interrupt Channel Map Register for 100 to 100+3"
bitfld.long 0x00 24.--28. " CH_MAP_103            ,Interrupt Channel Map for slv_events_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_102     ,Interrupt Channel Map for slv_events_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_101            ,Interrupt Channel Map for slv_events_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_100     ,Interrupt Channel Map for slv_events_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x468++0x3
line.long 0x00 "ICSSG_CH_MAP_REG26,Interrupt Channel Map Register for 104 to 104+3"
bitfld.long 0x00 24.--28. " CH_MAP_107            ,Interrupt Channel Map for slv_events_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_106     ,Interrupt Channel Map for slv_events_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_105            ,Interrupt Channel Map for slv_events_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_104     ,Interrupt Channel Map for slv_events_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG27,Interrupt Channel Map Register for 108 to 108+3"
bitfld.long 0x00 24.--28. " CH_MAP_111            ,Interrupt Channel Map for slv_events_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_110     ,Interrupt Channel Map for slv_events_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_109            ,Interrupt Channel Map for slv_events_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_108     ,Interrupt Channel Map for slv_events_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x470++0x3
line.long 0x00 "ICSSG_CH_MAP_REG28,Interrupt Channel Map Register for 112 to 112+3"
bitfld.long 0x00 24.--28. " CH_MAP_115            ,Interrupt Channel Map for slv_events_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_114     ,Interrupt Channel Map for slv_events_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_113            ,Interrupt Channel Map for slv_events_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_112     ,Interrupt Channel Map for slv_events_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x474++0x3
line.long 0x00 "ICSSG_CH_MAP_REG29,Interrupt Channel Map Register for 116 to 116+3"
bitfld.long 0x00 24.--28. " CH_MAP_119            ,Interrupt Channel Map for slv_events_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_118     ,Interrupt Channel Map for slv_events_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_117            ,Interrupt Channel Map for slv_events_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_116     ,Interrupt Channel Map for slv_events_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x478++0x3
line.long 0x00 "ICSSG_CH_MAP_REG30,Interrupt Channel Map Register for 120 to 120+3"
bitfld.long 0x00 24.--28. " CH_MAP_123            ,Interrupt Channel Map for slv_events_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_122     ,Interrupt Channel Map for slv_events_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_121            ,Interrupt Channel Map for slv_events_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_120     ,Interrupt Channel Map for slv_events_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG31,Interrupt Channel Map Register for 124 to 124+3"
bitfld.long 0x00 24.--28. " CH_MAP_127            ,Interrupt Channel Map for slv_events_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_126     ,Interrupt Channel Map for slv_events_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_125            ,Interrupt Channel Map for slv_events_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_124     ,Interrupt Channel Map for slv_events_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x480++0x3
line.long 0x00 "ICSSG_CH_MAP_REG32,Interrupt Channel Map Register for 128 to 128+3"
bitfld.long 0x00 24.--28. " CH_MAP_131            ,Interrupt Channel Map for slv_events_in[67]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_130     ,Interrupt Channel Map for slv_events_in[66]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_129            ,Interrupt Channel Map for slv_events_in[65]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_128     ,Interrupt Channel Map for slv_events_in[64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x484++0x3
line.long 0x00 "ICSSG_CH_MAP_REG33,Interrupt Channel Map Register for 132 to 132+3"
bitfld.long 0x00 24.--28. " CH_MAP_135            ,Interrupt Channel Map for slv_events_in[71]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_134     ,Interrupt Channel Map for slv_events_in[70]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_133            ,Interrupt Channel Map for slv_events_in[69]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_132     ,Interrupt Channel Map for slv_events_in[68]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x488++0x3
line.long 0x00 "ICSSG_CH_MAP_REG34,Interrupt Channel Map Register for 136 to 136+3"
bitfld.long 0x00 24.--28. " CH_MAP_139            ,Interrupt Channel Map for slv_events_in[75]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_138     ,Interrupt Channel Map for slv_events_in[74]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_137            ,Interrupt Channel Map for slv_events_in[73]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_136     ,Interrupt Channel Map for slv_events_in[72]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG35,Interrupt Channel Map Register for 140 to 140+3"
bitfld.long 0x00 24.--28. " CH_MAP_143            ,Interrupt Channel Map for slv_events_in[79]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_142     ,Interrupt Channel Map for slv_events_in[78]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_141            ,Interrupt Channel Map for slv_events_in[77]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_140     ,Interrupt Channel Map for slv_events_in[76]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x490++0x3
line.long 0x00 "ICSSG_CH_MAP_REG36,Interrupt Channel Map Register for 144 to 144+3"
bitfld.long 0x00 24.--28. " CH_MAP_147            ,Interrupt Channel Map for slv_events_in[83]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_146     ,Interrupt Channel Map for slv_events_in[82]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_145            ,Interrupt Channel Map for slv_events_in[81]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_144     ,Interrupt Channel Map for slv_events_in[80]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x494++0x3
line.long 0x00 "ICSSG_CH_MAP_REG37,Interrupt Channel Map Register for 148 to 148+3"
bitfld.long 0x00 24.--28. " CH_MAP_151            ,Interrupt Channel Map for slv_events_in[87]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_150     ,Interrupt Channel Map for slv_events_in[86]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_149            ,Interrupt Channel Map for slv_events_in[85]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_148     ,Interrupt Channel Map for slv_events_in[84]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x498++0x3
line.long 0x00 "ICSSG_CH_MAP_REG38,Interrupt Channel Map Register for 152 to 152+3"
bitfld.long 0x00 24.--28. " CH_MAP_155            ,Interrupt Channel Map for slv_events_in[91]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_154     ,Interrupt Channel Map for slv_events_in[90]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_153            ,Interrupt Channel Map for slv_events_in[89]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_152     ,Interrupt Channel Map for slv_events_in[88]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG39,Interrupt Channel Map Register for 156 to 156+3"
bitfld.long 0x00 24.--28. " CH_MAP_159            ,Interrupt Channel Map for slv_events_in[95]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_158     ,Interrupt Channel Map for slv_events_in[94]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_157            ,Interrupt Channel Map for slv_events_in[93]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_156     ,Interrupt Channel Map for slv_events_in[92]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x800++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG0,Host Interrupt Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " HINT_MAP_3            ,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_2     ,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_1            ,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_0     ,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x804++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG1,Host Interrupt Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " HINT_MAP_7            ,Host Interrupt Map for Channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_6     ,Host Interrupt Map for Channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_5            ,Host Interrupt Map for Channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_4     ,Host Interrupt Map for Channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x808++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG2,Host Interrupt Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " HINT_MAP_11           ,Host Interrupt Map for Channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_10    ,Host Interrupt Map for Channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_9            ,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_8     ,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG3,Host Interrupt Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " HINT_MAP_15           ,Host Interrupt Map for Channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_14    ,Host Interrupt Map for Channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_13           ,Host Interrupt Map for Channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_12    ,Host Interrupt Map for Channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x810++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG4,Host Interrupt Map Register for 16 to 16+4"
bitfld.long 0x00 24.--28. " HINT_MAP_19           ,Host Interrupt Map for Channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_18    ,Host Interrupt Map for Channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_17           ,Host Interrupt Map for Channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_16    ,Host Interrupt Map for Channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x900++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG0,Host Int 0 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_0           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_0     ,Host Int 0 Prioritized Interrupt"
rgroup.long 0x904++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG1,Host Int 1 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_1           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_1     ,Host Int 1 Prioritized Interrupt"
rgroup.long 0x908++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG2,Host Int 2 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_2           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_2     ,Host Int 2 Prioritized Interrupt"
rgroup.long 0x90C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG3,Host Int 3 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_3           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_3     ,Host Int 3 Prioritized Interrupt"
rgroup.long 0x910++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG4,Host Int 4 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_4           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_4     ,Host Int 4 Prioritized Interrupt"
rgroup.long 0x914++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG5,Host Int 5 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_5           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_5     ,Host Int 5 Prioritized Interrupt"
rgroup.long 0x918++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG6,Host Int 6 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_6           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_6     ,Host Int 6 Prioritized Interrupt"
rgroup.long 0x91C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG7,Host Int 7 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_7           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_7     ,Host Int 7 Prioritized Interrupt"
rgroup.long 0x920++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG8,Host Int 8 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_8           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_8     ,Host Int 8 Prioritized Interrupt"
rgroup.long 0x924++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG9,Host Int 9 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_9           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_9     ,Host Int 9 Prioritized Interrupt"
rgroup.long 0x928++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG10,Host Int 10 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_10          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_10    ,Host Int 10 Prioritized Interrupt"
rgroup.long 0x92C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG11,Host Int 11 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_11          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_11    ,Host Int 11 Prioritized Interrupt"
rgroup.long 0x930++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG12,Host Int 12 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_12          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_12    ,Host Int 12 Prioritized Interrupt"
rgroup.long 0x934++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG13,Host Int 13 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_13          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_13    ,Host Int 13 Prioritized Interrupt"
rgroup.long 0x938++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG14,Host Int 14 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_14          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_14    ,Host Int 14 Prioritized Interrupt"
rgroup.long 0x93C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG15,Host Int 15 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_15          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_15    ,Host Int 15 Prioritized Interrupt"
rgroup.long 0x940++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG16,Host Int 16 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_16          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_16    ,Host Int 16 Prioritized Interrupt"
rgroup.long 0x944++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG17,Host Int 17 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_17          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_17    ,Host Int 17 Prioritized Interrupt"
rgroup.long 0x948++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG18,Host Int 18 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_18          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_18    ,Host Int 18 Prioritized Interrupt"
rgroup.long 0x94C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG19,Host Int 19 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_19          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_19    ,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x3
line.long 0x00 "ICSSG_POLARITY_REG0,Polarity Register 0"
bitfld.long 0x00 31. " POLARITY_31           ,Polarity for intr_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_30    ,Polarity for intr_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_29           ,Polarity for intr_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_28    ,Polarity for intr_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_27           ,Polarity for intr_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_26    ,Polarity for intr_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_25           ,Polarity for intr_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_24    ,Polarity for intr_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_23           ,Polarity for intr_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_22    ,Polarity for intr_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_21           ,Polarity for intr_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_20    ,Polarity for intr_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_19           ,Polarity for intr_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_18    ,Polarity for intr_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_17           ,Polarity for intr_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_16    ,Polarity for intr_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_15           ,Polarity for intr_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_14    ,Polarity for intr_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_13           ,Polarity for intr_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_12    ,Polarity for intr_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_11           ,Polarity for intr_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_10    ,Polarity for intr_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_9            ,Polarity for intr_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_8     ,Polarity for intr_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_7            ,Polarity for intr_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_6     ,Polarity for intr_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_5            ,Polarity for intr_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_4     ,Polarity for intr_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_3            ,Polarity for intr_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_2     ,Polarity for intr_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_1            ,Polarity for intr_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_0     ,Polarity for intr_in[0]0=low" "0,1"
group.long 0xD04++0x3
line.long 0x00 "ICSSG_POLARITY_REG1,Polarity Register 1"
bitfld.long 0x00 31. " POLARITY_63           ,Polarity for intr_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_62    ,Polarity for intr_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_61           ,Polarity for intr_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_60    ,Polarity for intr_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_59           ,Polarity for intr_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_58    ,Polarity for intr_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_57           ,Polarity for intr_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_56    ,Polarity for intr_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_55           ,Polarity for intr_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_54    ,Polarity for intr_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_53           ,Polarity for intr_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_52    ,Polarity for intr_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_51           ,Polarity for intr_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_50    ,Polarity for intr_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_49           ,Polarity for intr_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_48    ,Polarity for intr_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_47           ,Polarity for intr_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_46    ,Polarity for intr_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_45           ,Polarity for intr_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_44    ,Polarity for intr_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_43           ,Polarity for intr_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_42    ,Polarity for intr_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_41           ,Polarity for intr_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_40    ,Polarity for intr_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_39           ,Polarity for intr_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_38    ,Polarity for intr_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_37           ,Polarity for intr_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_36    ,Polarity for intr_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_35           ,Polarity for intr_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_34    ,Polarity for intr_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_33           ,Polarity for intr_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_32    ,Polarity for intr_in[32]0=low" "0,1"
group.long 0xD08++0x3
line.long 0x00 "ICSSG_POLARITY_REG2,Polarity Register 2"
bitfld.long 0x00 31. " POLARITY_95           ,Polarity for slv_events_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_94    ,Polarity for slv_events_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_93           ,Polarity for slv_events_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_92    ,Polarity for slv_events_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_91           ,Polarity for slv_events_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_90    ,Polarity for slv_events_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_89           ,Polarity for slv_events_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_88    ,Polarity for slv_events_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_87           ,Polarity for slv_events_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_86    ,Polarity for slv_events_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_85           ,Polarity for slv_events_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_84    ,Polarity for slv_events_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_83           ,Polarity for slv_events_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_82    ,Polarity for slv_events_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_81           ,Polarity for slv_events_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_80    ,Polarity for slv_events_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_79           ,Polarity for slv_events_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_78    ,Polarity for slv_events_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_77           ,Polarity for slv_events_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_76    ,Polarity for slv_events_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_75           ,Polarity for slv_events_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_74    ,Polarity for slv_events_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_73           ,Polarity for slv_events_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_72    ,Polarity for slv_events_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_71           ,Polarity for slv_events_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_70    ,Polarity for slv_events_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_69           ,Polarity for slv_events_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_68    ,Polarity for slv_events_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_67           ,Polarity for slv_events_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_66    ,Polarity for slv_events_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_65           ,Polarity for slv_events_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_64    ,Polarity for slv_events_in[0]0=low" "0,1"
group.long 0xD0C++0x3
line.long 0x00 "ICSSG_POLARITY_REG3,Polarity Register 3"
bitfld.long 0x00 31. " POLARITY_127          ,Polarity for slv_events_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_126   ,Polarity for slv_events_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_125          ,Polarity for slv_events_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_124   ,Polarity for slv_events_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_123          ,Polarity for slv_events_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_122   ,Polarity for slv_events_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_121          ,Polarity for slv_events_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_120   ,Polarity for slv_events_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_119          ,Polarity for slv_events_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_118   ,Polarity for slv_events_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_117          ,Polarity for slv_events_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_116   ,Polarity for slv_events_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_115          ,Polarity for slv_events_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_114   ,Polarity for slv_events_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_113          ,Polarity for slv_events_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_112   ,Polarity for slv_events_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_111          ,Polarity for slv_events_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_110   ,Polarity for slv_events_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_109          ,Polarity for slv_events_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_108   ,Polarity for slv_events_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_107          ,Polarity for slv_events_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_106   ,Polarity for slv_events_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_105          ,Polarity for slv_events_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_104   ,Polarity for slv_events_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_103          ,Polarity for slv_events_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_102   ,Polarity for slv_events_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_101          ,Polarity for slv_events_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_100   ,Polarity for slv_events_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_99           ,Polarity for slv_events_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_98    ,Polarity for slv_events_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_97           ,Polarity for slv_events_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_96    ,Polarity for slv_events_in[32]0=low" "0,1"
group.long 0xD10++0x3
line.long 0x00 "ICSSG_POLARITY_REG4,Polarity Register 4"
bitfld.long 0x00 31. " POLARITY_159          ,Polarity for slv_events_in[95]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_158   ,Polarity for slv_events_in[94]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_157          ,Polarity for slv_events_in[93]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_156   ,Polarity for slv_events_in[92]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_155          ,Polarity for slv_events_in[91]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_154   ,Polarity for slv_events_in[90]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_153          ,Polarity for slv_events_in[89]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_152   ,Polarity for slv_events_in[88]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_151          ,Polarity for slv_events_in[87]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_150   ,Polarity for slv_events_in[86]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_149          ,Polarity for slv_events_in[85]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_148   ,Polarity for slv_events_in[84]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_147          ,Polarity for slv_events_in[83]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_146   ,Polarity for slv_events_in[82]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_145          ,Polarity for slv_events_in[81]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_144   ,Polarity for slv_events_in[80]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_143          ,Polarity for slv_events_in[79]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_142   ,Polarity for slv_events_in[78]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_141          ,Polarity for slv_events_in[77]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_140   ,Polarity for slv_events_in[76]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_139          ,Polarity for slv_events_in[75]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_138   ,Polarity for slv_events_in[74]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_137          ,Polarity for slv_events_in[73]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_136   ,Polarity for slv_events_in[72]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_135          ,Polarity for slv_events_in[71]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_134   ,Polarity for slv_events_in[70]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_133          ,Polarity for slv_events_in[69]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_132   ,Polarity for slv_events_in[68]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_131          ,Polarity for slv_events_in[67]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_130   ,Polarity for slv_events_in[66]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_129          ,Polarity for slv_events_in[65]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_128   ,Polarity for slv_events_in[64]0=low" "0,1"
group.long 0xD80++0x3
line.long 0x00 "ICSSG_TYPE_REG0,Type Register 0"
bitfld.long 0x00 31. " TYPE_31               ,Type for intr_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_30        ,Type for intr_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_29               ,Type for intr_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_28        ,Type for intr_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_27               ,Type for intr_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_26        ,Type for intr_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_25               ,Type for intr_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_24        ,Type for intr_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_23               ,Type for intr_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_22        ,Type for intr_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_21               ,Type for intr_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_20        ,Type for intr_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_19               ,Type for intr_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_18        ,Type for intr_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_17               ,Type for intr_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_16        ,Type for intr_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_15               ,Type for intr_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_14        ,Type for intr_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_13               ,Type for intr_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_12        ,Type for intr_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_11               ,Type for intr_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_10        ,Type for intr_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_9                ,Type for intr_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_8         ,Type for intr_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_7                ,Type for intr_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_6         ,Type for intr_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_5                ,Type for intr_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_4         ,Type for intr_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_3                ,Type for intr_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_2         ,Type for intr_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_1                ,Type for intr_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_0         ,Type for intr_in[0]0=level" "0,1"
group.long 0xD84++0x3
line.long 0x00 "ICSSG_TYPE_REG1,Type Register 1"
bitfld.long 0x00 31. " TYPE_63               ,Type for intr_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_62        ,Type for intr_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_61               ,Type for intr_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_60        ,Type for intr_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_59               ,Type for intr_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_58        ,Type for intr_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_57               ,Type for intr_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_56        ,Type for intr_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_55               ,Type for intr_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_54        ,Type for intr_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_53               ,Type for intr_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_52        ,Type for intr_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_51               ,Type for intr_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_50        ,Type for intr_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_49               ,Type for intr_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_48        ,Type for intr_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_47               ,Type for intr_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_46        ,Type for intr_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_45               ,Type for intr_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_44        ,Type for intr_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_43               ,Type for intr_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_42        ,Type for intr_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_41               ,Type for intr_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_40        ,Type for intr_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_39               ,Type for intr_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_38        ,Type for intr_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_37               ,Type for intr_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_36        ,Type for intr_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_35               ,Type for intr_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_34        ,Type for intr_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_33               ,Type for intr_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_32        ,Type for intr_in[32]0=level" "0,1"
group.long 0xD88++0x3
line.long 0x00 "ICSSG_TYPE_REG2,Type Register 2"
bitfld.long 0x00 31. " TYPE_95               ,Type for slv_events_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_94        ,Type for slv_events_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_93               ,Type for slv_events_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_92        ,Type for slv_events_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_91               ,Type for slv_events_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_90        ,Type for slv_events_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_89               ,Type for slv_events_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_88        ,Type for slv_events_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_87               ,Type for slv_events_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_86        ,Type for slv_events_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_85               ,Type for slv_events_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_84        ,Type for slv_events_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_83               ,Type for slv_events_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_82        ,Type for slv_events_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_81               ,Type for slv_events_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_80        ,Type for slv_events_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_79               ,Type for slv_events_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_78        ,Type for slv_events_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_77               ,Type for slv_events_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_76        ,Type for slv_events_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_75               ,Type for slv_events_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_74        ,Type for slv_events_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_73               ,Type for slv_events_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_72        ,Type for slv_events_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_71               ,Type for slv_events_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_70        ,Type for slv_events_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_69               ,Type for slv_events_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_68        ,Type for slv_events_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_67               ,Type for slv_events_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_66        ,Type for slv_events_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_65               ,Type for slv_events_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_64        ,Type for slv_events_in[0]0=level" "0,1"
group.long 0xD8C++0x3
line.long 0x00 "ICSSG_TYPE_REG3,Type Register 3"
bitfld.long 0x00 31. " TYPE_127              ,Type for slv_events_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_126       ,Type for slv_events_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_125              ,Type for slv_events_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_124       ,Type for slv_events_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_123              ,Type for slv_events_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_122       ,Type for slv_events_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_121              ,Type for slv_events_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_120       ,Type for slv_events_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_119              ,Type for slv_events_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_118       ,Type for slv_events_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_117              ,Type for slv_events_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_116       ,Type for slv_events_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_115              ,Type for slv_events_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_114       ,Type for slv_events_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_113              ,Type for slv_events_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_112       ,Type for slv_events_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_111              ,Type for slv_events_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_110       ,Type for slv_events_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_109              ,Type for slv_events_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_108       ,Type for slv_events_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_107              ,Type for slv_events_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_106       ,Type for slv_events_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_105              ,Type for slv_events_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_104       ,Type for slv_events_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_103              ,Type for slv_events_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_102       ,Type for slv_events_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_101              ,Type for slv_events_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_100       ,Type for slv_events_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_99               ,Type for slv_events_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_98        ,Type for slv_events_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_97               ,Type for slv_events_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_96        ,Type for slv_events_in[32]0=level" "0,1"
group.long 0xD90++0x3
line.long 0x00 "ICSSG_TYPE_REG4,Type Register 4"
bitfld.long 0x00 31. " TYPE_159              ,Type for slv_events_in[95]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_158       ,Type for slv_events_in[94]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_157              ,Type for slv_events_in[93]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_156       ,Type for slv_events_in[92]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_155              ,Type for slv_events_in[91]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_154       ,Type for slv_events_in[90]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_153              ,Type for slv_events_in[89]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_152       ,Type for slv_events_in[88]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_151              ,Type for slv_events_in[87]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_150       ,Type for slv_events_in[86]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_149              ,Type for slv_events_in[85]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_148       ,Type for slv_events_in[84]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_147              ,Type for slv_events_in[83]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_146       ,Type for slv_events_in[82]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_145              ,Type for slv_events_in[81]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_144       ,Type for slv_events_in[80]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_143              ,Type for slv_events_in[79]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_142       ,Type for slv_events_in[78]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_141              ,Type for slv_events_in[77]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_140       ,Type for slv_events_in[76]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_139              ,Type for slv_events_in[75]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_138       ,Type for slv_events_in[74]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_137              ,Type for slv_events_in[73]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_136       ,Type for slv_events_in[72]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_135              ,Type for slv_events_in[71]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_134       ,Type for slv_events_in[70]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_133              ,Type for slv_events_in[69]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_132       ,Type for slv_events_in[68]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_131              ,Type for slv_events_in[67]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_130       ,Type for slv_events_in[66]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_129              ,Type for slv_events_in[65]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_128       ,Type for slv_events_in[64]0=level" "0,1"
group.long 0x1100++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG0,Host Int 0 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_0    ,Host Int 0 Nesting Level"
group.long 0x1104++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG1,Host Int 1 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_1    ,Host Int 1 Nesting Level"
group.long 0x1108++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG2,Host Int 2 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_2    ,Host Int 2 Nesting Level"
group.long 0x110C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG3,Host Int 3 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_3    ,Host Int 3 Nesting Level"
group.long 0x1110++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG4,Host Int 4 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_4    ,Host Int 4 Nesting Level"
group.long 0x1114++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG5,Host Int 5 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_5    ,Host Int 5 Nesting Level"
group.long 0x1118++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG6,Host Int 6 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_6    ,Host Int 6 Nesting Level"
group.long 0x111C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG7,Host Int 7 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_7    ,Host Int 7 Nesting Level"
group.long 0x1120++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG8,Host Int 8 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_8    ,Host Int 8 Nesting Level"
group.long 0x1124++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG9,Host Int 9 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_9    ,Host Int 9 Nesting Level"
group.long 0x1128++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG10,Host Int 10 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_10   ,Host Int 10 Nesting Level"
group.long 0x112C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG11,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_11   ,Host Int 11 Nesting Level"
group.long 0x1130++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG12,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_12   ,Host Int 12 Nesting Level"
group.long 0x1134++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG13,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_13   ,Host Int 13 Nesting Level"
group.long 0x1138++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG14,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_14   ,Host Int 14 Nesting Level"
group.long 0x113C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG15,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_15   ,Host Int 15 Nesting Level"
group.long 0x1140++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG16,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_16   ,Host Int 16 Nesting Level"
group.long 0x1144++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG17,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_17   ,Host Int 17 Nesting Level"
group.long 0x1148++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG18,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_18   ,Host Int 18 Nesting Level"
group.long 0x114C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG19,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_19   ,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x00 "ICSSG_ENABLE_HINT_REG0,Host Int Enable Register 0"
bitfld.long 0x00 19. " ENABLE_HINT_19        ,Enable for Host Int 19" "0,1"
bitfld.long 0x00 18. "     ENABLE_HINT_18 ,Enable for Host Int 18" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_HINT_17        ,Enable for Host Int 17" "0,1"
bitfld.long 0x00 16. "     ENABLE_HINT_16 ,Enable for Host Int 16" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_HINT_15        ,Enable for Host Int 15" "0,1"
bitfld.long 0x00 14. "     ENABLE_HINT_14 ,Enable for Host Int 14" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_HINT_13        ,Enable for Host Int 13" "0,1"
bitfld.long 0x00 12. "     ENABLE_HINT_12 ,Enable for Host Int 12" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_HINT_11        ,Enable for Host Int 11" "0,1"
bitfld.long 0x00 10. "     ENABLE_HINT_10 ,Enable for Host Int 10" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_HINT_9         ,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "     ENABLE_HINT_8  ,Enable for Host Int 8" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_HINT_7         ,Enable for Host Int 7" "0,1"
bitfld.long 0x00 6. "     ENABLE_HINT_6  ,Enable for Host Int 6" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_HINT_5         ,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "     ENABLE_HINT_4  ,Enable for Host Int 4" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_HINT_3         ,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "     ENABLE_HINT_2  ,Enable for Host Int 2" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_HINT_1         ,Enable for Host Int 1" "0,1"
bitfld.long 0x00 0. "     ENABLE_HINT_0  ,Enable for Host Int 0" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MDIO"
tree "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"
base eaxi:0xB132400
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_MDIO_VERSION_REG,MDIO Version Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                ,Module Identification value"
hexmask.long.byte 0x00 8.--15. 1. "      REVMAJ              ,Major revision value"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " REVMINOR             ,Minor revision value"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_CONTROL_REG,MDIO Control Register"
in
textline "                                        "
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_ALIVE_REG,MDIO Alive Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_LINK_REG,MDIO Link Register"
hexmask.long 0x00 0.--31. 1. " LINK                 ,MDIO Link state."
hgroup.long 0x10++0x3
hide.long 0x00 "ICSSG_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x14++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
in
textline "                                        "
group.long 0x18++0x3
line.long 0x00 "ICSSG_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x00 0. " LINKINTMASKSET       ,MDIO link interrupt mask set." "0,1"
hgroup.long 0x1C++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
in
textline "                                        "
hgroup.long 0x20++0x3
hide.long 0x00 "ICSSG_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x24++0x3
hide.long 0x00 "ICSSG_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
in
textline "                                        "
group.long 0x28++0x3
line.long 0x00 "ICSSG_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x00 0.--1. " USERINTMASKSET       ,MDIO user interrupt mask set for userintmasked[1:0], respectively." "0,1,2,3"
hgroup.long 0x2C++0x3
hide.long 0x00 "ICSSG_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
in
textline "                                        "
group.long 0x30++0x3
line.long 0x00 "ICSSG_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x00 2. " MDIO_MDCLK_O         ,MDIO Clock Output." "0,1"
bitfld.long 0x00 1. "         MDIO_OE             ,MDIO Output Enable." "0,1"
textline "                                        "
bitfld.long 0x00 0. " MDIO_PIN             ,MDIO_Pin Value." "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_POLL_REG,MDIO Poll Inter Register"
bitfld.long 0x00 31. " MANUALMODE           ,Manual Mode." "0,1"
bitfld.long 0x00 30. "         STATECHANGEMODE     ,State Change Mode." "0,1"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " IPG                  ,Polling Inter Packet Gap Value."
group.long 0x38++0x3
line.long 0x00 "ICSSG_POLL_EN_REG,MDIO Poll Enable Register"
hexmask.long 0x00 0.--31. 1. " POLL_EN              ,Poll Enable."
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CLAUS45_REG,Clause 45 Register"
hexmask.long 0x00 0.--31. 1. " CLAUSE45             ,MDIO clause 45 mode."
group.long 0x40++0x3
line.long 0x00 "ICSSG_USER_ADDR0_REG,MDIO User Address 0 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR0           ,User Address 0."
group.long 0x44++0x3
line.long 0x00 "ICSSG_USER_ADDR1_REG,MDIO User Address 1 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR1           ,User Address 1."
group.long 0x80++0x3
line.long 0x00 "ICSSG_USER_ACCESS_REG_j,MDIO User Access j Register Offset = 80h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 31. " GO                   ,Go." "0,1"
bitfld.long 0x00 30. "         WRITE               ,Write enable." "0,1"
textline "                                        "
bitfld.long 0x00 29. " ACK                  ,Acknowledge." "0,1"
bitfld.long 0x00 21.--25. "         REGADR              ,Register address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 16.--20. " PHYADR               ,PHY address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "        DATA                ,User data."
group.long 0x84++0x3
line.long 0x00 "ICSSG_USER_PHY_SEL_REG_j,MDIO User PHY Select j Register Offset = 84h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 7. " LINKSEL              ,Link status determination select." "0,1"
bitfld.long 0x00 6. "         LINKINT_ENABLE      ,Link change interrupt enable." "0,1"
textline "                                        "
bitfld.long 0x00 0.--4. " PHYADR_MON           ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_G_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base eaxi:0xB133000
width 35.
group.long 0x0++0x3
line.long 0x00 "ICSSG_ICSS_G_CFG,ICSSG Config"
bitfld.long 0x00 16. " SGMII_MODE                ,SGMII mode0: Fiber mode 1: SGMII mode" "0,1"
bitfld.long 0x00 10. "         RX_SFD_TX_SOF_EN         ,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RTU_PRU_PSI_SHARE_EN      ,Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO" "0,1"
bitfld.long 0x00 8. "         IEP1_TX_EN               ,Enable IEP1 for TX Enable0: Use IEP0 CMP3_4 1: Use IEP1 CMP3_4" "0,1"
textline "                                            "
bitfld.long 0x00 5.--6. " MII1_MODE                 ,MII1 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
bitfld.long 0x00 3.--4. "         MII0_MODE                ,MII0 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2. " RX_L2_G_EN                ,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 1. "         TX_L2_EN                 ,Enable the TX L2 Fifo0: Disabled 1: Enabled" "0,1"
textline "                                            "
bitfld.long 0x00 0. " TX_L1_EN                  ,Enable the TX L1 Fifo0: Disabled 1: Enabled" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RGMII_CFG,RGMII"
bitfld.long 0x00 22. " RGMII1_FULLDUPLEX_IN      ,RGMII Fullduplex overide0: half 1: full" "0,1"
bitfld.long 0x00 21. "         RGMII1_GIG_IN            ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
textline "                                            "
bitfld.long 0x00 20. " RGMII1_INBAND             ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
bitfld.long 0x00 18. "         RGMII0_FULLDUPLEX_IN     ,RGMII Fullduplex overide0: half 1: full" "0,1"
textline "                                            "
bitfld.long 0x00 17. " RGMII0_GIG_IN             ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
bitfld.long 0x00 16. "         RGMII0_INBAND            ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RGMII_EEE_PHY_ONLY        ,RGMII Phy Only Low Power0: disable 1: enable" "0,1"
bitfld.long 0x00 8. "         RGMII_EEE_EN             ,RGMII Energy Efficient Enable0: disable 1: enable" "0,1"
textline "                                            "
bitfld.long 0x00 7. " RGMII1_FULLDUPLEX         ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
bitfld.long 0x00 5.--6. "         RGMII1_SPEED             ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 4. " RGMII1_LINK               ,RGMII Link Status0: link is down 1: link is up" "0,1"
bitfld.long 0x00 3. "         RGMII0_FULLDUPLEX        ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
textline "                                            "
bitfld.long 0x00 1.--2. " RGMII0_SPEED              ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
bitfld.long 0x00 0. "         RGMII0_LINK              ,RGMII Link Status0: link is down 1: link is up" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_MAC_PRU0_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU0_0                ,MAC pru0 DA3:DA0 Used for SAV and DA match"
group.long 0xC++0x3
line.long 0x00 "ICSSG_MAC_PRU0_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU0_1                ,MAC pru0 DA5:DA4 Used for SAV and DA match"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MAC_PRU1_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU1_0                ,MAC pru1 DA3:DA0 Used for SAV and DA match"
group.long 0x14++0x3
line.long 0x00 "ICSSG_MAC_PRU1_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU1_1                ,MAC pru1 DA5:DA4 Used for SAV and DA match"
group.long 0x18++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_0,MAC_Interface_0"
hexmask.long 0x00 0.--31. 1. " MAC_INF_0                 ,MAC Host interface DA3:DA0 Used for SAV and DA match"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_1,MAC_Interface_1"
hexmask.long.word 0x00 0.--15. 1. " MAC_INF_1                 ,MAC Host interface DA5:DA4 Used for SAV and DA match"
group.long 0x20++0x3
line.long 0x00 "ICSSG_PREEMPT_CFG,Preemption_Cfg"
hexmask.long.byte 0x00 24.--31. 1. " SMD_R                     ,Response frame TAG"
hexmask.long.byte 0x00 16.--23. 1. "        SMD_V                    ,Verification frame TAG"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " EXP_SMD                   ,None preemptable frame start, or express frame"
group.long 0x24++0x3
line.long 0x00 "ICSSG_SMDT1S_CFG,SMDType1SPreemptableFrameStartCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1S_3                  ,SMDT1S3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1S_2                 ,SMDT1S2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1S_1                  ,SMDT1S1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1S_0                 ,SMDT1S0 pattern"
group.long 0x28++0x3
line.long 0x00 "ICSSG_SMDT1C_CFG,SMDType1CNoneInitialFragCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1C_3                  ,SMDT1C3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1C_2                 ,SMDT1C2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1C_1                  ,SMDT1C1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1C_0                 ,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x00 "ICSSG_FRAG_CNT_CFG,FragCntCfg"
hexmask.long.byte 0x00 24.--31. 1. " FRAG_CNT_3                ,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        FRAG_CNT_2               ,FRAG Cnt2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " FRAG_CNT_1                ,FRAG Cnt1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        FRAG_CNT_0               ,FRAG Cnt0 pattern"
group.long 0x40++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH0,PaStatPush0"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_0           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_0          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_0           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_0          ,pa"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH1,PaStatPush1"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_1           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_1          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_1           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_1          ,pa"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH2,PaStatPush2"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_2           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_2          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_2           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_2          ,pa"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH3,PaStatPush3"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_3           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_3          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_3           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_3          ,pa"
group.long 0x60++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG1,FDBCfg1"
hexmask.long.tbyte 0x00 8.--25. 1. " SMEM_VLAN_OFFSET          ,SMEM VLAN FID table base address"
bitfld.long 0x00 3.--6. "    FDB_HASH_SIZE            ,FDB hash size0:64 1:128 2:256 3:512 4:1024 5:2048" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.long 0x00 0.--1. " FDB_BUCKET_SIZE           ,FDB buket size0:1 1:2 2:4 3:8" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG2,FDBCfg2"
bitfld.long 0x00 9.--12. " FDB_GEN_MODE_BYTE_EN      ,FDB General Mode Byte compare size0 = 1 Byte, 15 = 16 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "        FDB_GEN_MODE_EN_BK1      ,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
textline "                                            "
bitfld.long 0x00 7. " FDB_GEN_MODE_EN_BK0       ,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x00 6. "         FDB_VLAN_EN              ,FDB Global VLAN Enable" "0,1"
textline "                                            "
bitfld.long 0x00 5. " FDB_HSR_EN                ,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x00 2. "         FDB_HOST_EN              ,FDB HOST Enable" "0,1"
textline "                                            "
bitfld.long 0x00 1. " FDB_PRU1_EN               ,FDB PRU1 Enable" "0,1"
bitfld.long 0x00 0. "         FDB_PRU0_EN              ,FDB PRU0 Enable" "0,1"
group.long 0x68++0x3
line.long 0x00 "ICSSG_FDB_GEN_STATUS,FDBStatus"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_FDB_DF_VLAN,FDBDefaultPRUVLAN"
hexmask.long.word 0x00 16.--27. 1. " FDB_PRU1_DF_VLAN          ,FDB Default VLAN for PRU1"
hexmask.long.word 0x00 0.--11. 1. "      FDB_PRU0_DF_VLAN         ,FDB Default VLAN for PRU0"
group.long 0x70++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA0,FDB_HOST_DA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_DA0              ,FDB HOST DA3:0"
group.long 0x74++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA1,FDB_HOST_DA5:4_Cfg"
hexmask.long.word 0x00 0.--15. 1. " FDB_HOST_DA1              ,FDB HOST DA5:4"
group.long 0x78++0x3
line.long 0x00 "ICSSG_FDB_HOST_SA0,FDB_HOST_SA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_SA0              ,FDB HOST SA3:0"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_FDB_HOST_VLAN_SA1,FDB_HOST_VLAN_SA5:4_Cfg"
hexmask.long.word 0x00 16.--31. 1. " FDB_HOST_VLAN_HSR         ,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x00 0.--15. 1. "      FDB_HOST_SA1             ,FDB HOST SA5:4"
group.long 0x80++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU0,Filter1StartandLengthPru0"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x84++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU0,Filter1ConfigPru0"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU0,Filter1_0_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU0,Filter1_0_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x90++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU0,Filter1_0_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x94++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU0,Filter1_0_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x98++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU0,Filter1_1_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU0,Filter1_1_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU0,Filter1_1_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU0,Filter1_1_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU0,Filter1_2_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU0,Filter1_2_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU0,Filter1_2_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU0,Filter1_2_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU0,Filter1_3_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU0,Filter1_3_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU0,Filter1_3_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU0,Filter1_3_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU0,Filter1_4_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU0,Filter1_4_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU0,Filter1_4_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU0,Filter1_4_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU0,Filter1_5_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU0,Filter1_5_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU0,Filter1_5_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU0,Filter1_5_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU0,Filter1_6_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU0,Filter1_6_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU0,Filter1_6_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU0,Filter1_6_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU0,Filter1_7_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU0,Filter1_7_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x100++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU0,Filter1_7_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x104++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU0,Filter1_7_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x108++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU0,Filter3_0_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU0,Filter3_0_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x110++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU0,Filter3_0_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x114++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU0,Filter3_0_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x118++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU0,Filter3_0_LenPru0"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU0,Filter3_0_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x120++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU0,Filter3_0_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x124++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU0,Filter3_0_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x128++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU0,Filter3_1_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU0,Filter3_1_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x130++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU0,Filter3_1_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x134++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU0,Filter3_1_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x138++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU0,Filter3_1_LenPru0"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU0,Filter3_1_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x140++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU0,Filter3_1_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x144++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU0,Filter3_1_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x148++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU0,Filter3_2_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU0,Filter3_2_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x150++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU0,Filter3_2_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x154++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU0,Filter3_2_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x158++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU0,Filter3_2_LenPru0"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU0,Filter3_2_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU0,Filter3_2_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x164++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU0,Filter3_2_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x168++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU0,Filter3_3_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU0,Filter3_3_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x170++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU0,Filter3_3_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x174++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU0,Filter3_3_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x178++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU0,Filter3_3_LenPru0"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x17C++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU0,Filter3_3_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x180++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU0,Filter3_3_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x184++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU0,Filter3_3_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x188++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU0,Filter3_4_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU0,Filter3_4_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x190++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU0,Filter3_4_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x194++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU0,Filter3_4_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x198++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU0,Filter3_4_LenPru0"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x19C++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU0,Filter3_4_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1A0++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU0,Filter3_4_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1A4++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU0,Filter3_4_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1A8++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU0,Filter3_5_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU0,Filter3_5_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1B0++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU0,Filter3_5_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1B4++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU0,Filter3_5_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1B8++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU0,Filter3_5_LenPru0"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1BC++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU0,Filter3_5_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1C0++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU0,Filter3_5_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1C4++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU0,Filter3_5_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1C8++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU0,Filter3_6_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU0,Filter3_6_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1D0++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU0,Filter3_6_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1D4++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU0,Filter3_6_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1D8++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU0,Filter3_6_LenPru0"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1DC++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU0,Filter3_6_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1E0++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU0,Filter3_6_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1E4++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU0,Filter3_6_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1E8++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU0,Filter3_7_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU0,Filter3_7_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1F0++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU0,Filter3_7_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1F4++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU0,Filter3_7_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1F8++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU0,Filter3_7_LenPru0"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1FC++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU0,Filter3_7_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x200++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU0,Filter3_7_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x204++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU0,Filter3_7_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x208++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU0,Filter3_8_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU0,Filter3_8_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x210++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU0,Filter3_8_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x214++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU0,Filter3_8_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x218++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU0,Filter3_8_LenPru0"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x21C++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU0,Filter3_8_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x220++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU0,Filter3_8_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x224++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU0,Filter3_8_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x228++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU0,Filter3_9_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU0,Filter3_9_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x230++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU0,Filter3_9_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x234++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU0,Filter3_9_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x238++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU0,Filter3_9_LenPru0"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x23C++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU0,Filter3_9_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x240++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU0,Filter3_9_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x244++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU0,Filter3_9_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x248++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU0,Filter3_10_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU0,Filter3_10_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x250++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU0,Filter3_10_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x254++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU0,Filter3_10_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x258++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU0,Filter3_10_LenPru0"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x25C++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU0,Filter3_10_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x260++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU0,Filter3_10_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x264++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU0,Filter3_10_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x268++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU0,Filter3_11_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU0,Filter3_11_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x270++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU0,Filter3_11_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x274++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU0,Filter3_11_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x278++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU0,Filter3_11_LenPru0"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x27C++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU0,Filter3_11_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x280++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU0,Filter3_11_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x284++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU0,Filter3_11_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x288++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU0,Filter3_12_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU0,Filter3_12_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x290++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU0,Filter3_12_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x294++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU0,Filter3_12_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x298++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU0,Filter3_12_LenPru0"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x29C++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU0,Filter3_12_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2A0++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU0,Filter3_12_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2A4++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU0,Filter3_12_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2A8++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU0,Filter3_13_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU0,Filter3_13_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2B0++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU0,Filter3_13_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2B4++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU0,Filter3_13_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2B8++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU0,Filter3_13_LenPru0"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2BC++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU0,Filter3_13_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2C0++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU0,Filter3_13_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2C4++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU0,Filter3_13_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2C8++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU0,Filter3_14_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU0,Filter3_14_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2D0++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU0,Filter3_14_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2D4++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU0,Filter3_14_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2D8++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU0,Filter3_14_LenPru0"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2DC++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU0,Filter3_14_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2E0++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU0,Filter3_14_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2E4++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU0,Filter3_14_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2E8++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU0,Filter3_15_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU0,Filter3_15_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2F0++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU0,Filter3_15_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2F4++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU0,Filter3_15_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2F8++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU0,Filter3_15_LenPru0"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2FC++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU0,Filter3_15_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x300++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU0,Filter3_15_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x304++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU0,Filter3_15_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x308++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU0,Filter3_0P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU0,Filter3_0P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x310++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x314++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x318++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU0,Filter3_1P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x31C++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU0,Filter3_1P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x320++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x324++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x328++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU0,Filter3_2P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x32C++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU0,Filter3_2P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x330++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x334++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x338++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU0,Filter3_3P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x33C++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU0,Filter3_3P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x340++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x344++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x348++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU0,Filter3_4P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x34C++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU0,Filter3_4P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x350++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x354++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x358++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU0,Filter3_5P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x35C++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU0,Filter3_5P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x360++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x364++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x368++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU0,Filter3_6P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x36C++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU0,Filter3_6P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x370++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x374++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x378++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU0,Filter3_7P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x37C++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU0,Filter3_7P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x380++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x384++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x388++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU0,Filter3_8P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU0,Filter3_8P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x390++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x394++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x398++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU0,Filter3_9P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x39C++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU0,Filter3_9P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x3A0++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3A4++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3A8++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU0,Filter3_10P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x3AC++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU0,Filter3_10P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x3B0++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3B4++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3B8++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU0,Filter3_11P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x3BC++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU0,Filter3_11P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x3C0++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3C4++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3C8++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU0,Filter3_12P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x3CC++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU0,Filter3_12P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x3D0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3D4++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3D8++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU0,Filter3_13P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x3DC++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU0,Filter3_13P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x3E0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3E4++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3E8++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU0,Filter3_14P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x3EC++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU0,Filter3_14P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x3F0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3F4++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3F8++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU0,Filter3_15P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x3FC++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU0,Filter3_15P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x400++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x404++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x408++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU0,FilterByteCountPru0"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU0            ,RX current filter Byte Count"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU0,rx_class0_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x410++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU0,rx_class0_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x414++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU0,rx_class1_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x418++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU0,rx_class1_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU0,rx_class2_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x420++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU0,rx_class2_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x424++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU0,rx_class3_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x428++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU0,rx_class3_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU0,rx_class4_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x430++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU0,rx_class4_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0x434++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU0,rx_class5_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0x438++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU0,rx_class5_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU0,rx_class6_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0x440++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU0,rx_class6_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0x444++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU0,rx_class7_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0x448++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU0,rx_class7_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU0,rx_class8_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0x450++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU0,rx_class8_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0x454++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU0,rx_class9_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0x458++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU0,rx_class9_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU0,rx_class10_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0x460++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU0,rx_class10_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0x464++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU0,rx_class11_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0x468++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU0,rx_class11_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU0,rx_class12_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0x470++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU0,rx_class12_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0x474++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU0,rx_class13_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0x478++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU0,rx_class13_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU0,rx_class14_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0x480++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU0,rx_class14_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0x484++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU0,rx_class15_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0x488++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU0,rx_class15_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU0,rx_class_cfg1Pru0"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0x490++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU0,rx_class_cfg2Pru0"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0x494++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x498++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4AC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4BC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4CC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D4++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU0,RX_greenPru0"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4D8++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU0,SAHashPru0"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0x4DC++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU0,ConnectionHashPru0"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0x4E0++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU0,ConnectionHashStartPru0"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0x4E4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU0,RX_RateConfiguration0Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4E8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU0,RX_RateConfiguration1Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4EC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU0,RX_RateConfiguration2Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU0,RX_RateConfiguration3Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU0,RX_RateConfiguration4Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU0,RX_RateConfiguration5Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4FC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU0,RX_RateConfiguration6Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x500++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU0,RX_RateConfiguration7Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x504++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU0,RX_RateSourceSelect0Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x508++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU0,RX_RateSourceSelect1Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU0,TX_RateConfiguration1_0Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x510++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU0,TX_RateConfiguration2_0Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0x514++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU0,TX_RateConfiguration1_1Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x518++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU0,TX_RateConfiguration2_1Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0x51C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU0,TX_RateConfiguration1_2Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x520++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU0,TX_RateConfiguration2_2Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0x524++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU0,TX_RateConfiguration1_3Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x528++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU0,TX_RateConfiguration2_3Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0x52C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU0,TX_RateConfiguration1_4Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x530++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU0,TX_RateConfiguration2_4Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0x534++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU0,TX_RateConfiguration1_5Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x538++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU0,TX_RateConfiguration2_5Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0x53C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU0,TX_RateConfiguration1_6Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x540++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU0,TX_RateConfiguration2_6Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0x544++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU0,TX_RateConfiguration1_7Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x548++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU0,TX_RateConfiguration2_7Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0x54C++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU0,RXGoodFrameCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0x550++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU0,RXBCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0x554++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU0,RXMCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0x558++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU0,RXCRCErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0x55C++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU0,RXMIIErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0x560++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU0,RXOddNibbleFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0x564++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU0,RXMaxSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0x568++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU0,RXMaxSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0x56C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU0,RXMinSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0x570++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU0,RXMinSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0x574++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU0,RXoverrunFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0x578++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU0       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0x57C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU0       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0x580++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU0       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0x584++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU0       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0x588++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU0       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0x58C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU0       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0x590++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU0       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0x594++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU0       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0x598++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU0       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0x59C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU0       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0x5A0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU0      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0x5A4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU0      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0x5A8++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU0      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0x5AC++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU0      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0x5B0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU0      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0x5B4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU0      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0x5B8++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU0,RXSMDFragErrCountPru0"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU0      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU0    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU0     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU0    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0x5BC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU0,RXBucket1SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0x5C0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU0,RXBucket2SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0x5C4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU0,RXBucket3SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0x5C8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU0,RXBucket4SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0x5CC++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU0,RX64BSizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0x5D0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU0,RXBucket1SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0x5D4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU0,RXBucket2SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x5D8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU0,RXBucket3SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x5DC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU0,RXBucket4SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x5E0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU0,RXBucket5SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0x5E4++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU0,RXTotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0x5E8++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU0,RX_TX_TotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0x5EC++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT0,TXGoodFrameCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0x5F0++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT0,TXBCFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0x5F4++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT0,TXMFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0x5F8++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT0,TXOddNibbleFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0x5FC++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT0,TXUnderFlowErrCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0x600++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT0,TXMaxSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0x604++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT0,TXMaxSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0x608++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT0,TXMinSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0x60C++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT0,TXMinSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0x610++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT0,TXBucket1SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0x614++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT0,TXBucket2SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0x618++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT0,TXBucket3SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0x61C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT0,TXBucket4SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0x620++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT0,TX64BSizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0x624++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT0,TXBucket1SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0x628++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT0,TXBucket2SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x62C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT0,TXBucket3SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x630++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT0,TXBucket4SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x634++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT0,TXBucket5SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0x638++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT0,TXTotalByteCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0x63C++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT0,TXHSRTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0x640++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT0,TXHSRSeqPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0x644++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT0,TXVLANTYPETAGPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0x648++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT0,TXVLANINSTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
group.long 0x64C++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU1,Filter1StartandLengthPru1"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x650++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU1,Filter1ConfigPru1"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x654++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU1,Filter1_0_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x658++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU1,Filter1_0_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x65C++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU1,Filter1_0_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x660++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU1,Filter1_0_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x664++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU1,Filter1_1_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x668++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU1,Filter1_1_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0x66C++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU1,Filter1_1_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x670++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU1,Filter1_1_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x674++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU1,Filter1_2_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0x678++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU1,Filter1_2_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0x67C++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU1,Filter1_2_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x680++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU1,Filter1_2_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x684++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU1,Filter1_3_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0x688++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU1,Filter1_3_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0x68C++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU1,Filter1_3_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x690++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU1,Filter1_3_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x694++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU1,Filter1_4_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0x698++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU1,Filter1_4_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0x69C++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU1,Filter1_4_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6A0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU1,Filter1_4_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6A4++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU1,Filter1_5_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0x6A8++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU1,Filter1_5_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0x6AC++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU1,Filter1_5_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6B0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU1,Filter1_5_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6B4++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU1,Filter1_6_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0x6B8++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU1,Filter1_6_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0x6BC++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU1,Filter1_6_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6C0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU1,Filter1_6_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6C4++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU1,Filter1_7_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0x6C8++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU1,Filter1_7_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x6CC++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU1,Filter1_7_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6D0++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU1,Filter1_7_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6D4++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU1,Filter3_0_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU1,Filter3_0_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6DC++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU1,Filter3_0_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x6E0++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU1,Filter3_0_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x6E4++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU1,Filter3_0_LenPru1"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x6E8++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU1,Filter3_0_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x6EC++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU1,Filter3_0_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x6F0++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU1,Filter3_0_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x6F4++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU1,Filter3_1_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU1,Filter3_1_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6FC++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU1,Filter3_1_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x700++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU1,Filter3_1_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x704++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU1,Filter3_1_LenPru1"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x708++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU1,Filter3_1_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x70C++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU1,Filter3_1_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x710++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU1,Filter3_1_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x714++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU1,Filter3_2_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU1,Filter3_2_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x71C++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU1,Filter3_2_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x720++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU1,Filter3_2_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x724++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU1,Filter3_2_LenPru1"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x728++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU1,Filter3_2_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x72C++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU1,Filter3_2_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x730++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU1,Filter3_2_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x734++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU1,Filter3_3_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU1,Filter3_3_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x73C++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU1,Filter3_3_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x740++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU1,Filter3_3_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x744++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU1,Filter3_3_LenPru1"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x748++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU1,Filter3_3_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x74C++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU1,Filter3_3_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x750++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU1,Filter3_3_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x754++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU1,Filter3_4_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU1,Filter3_4_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x75C++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU1,Filter3_4_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x760++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU1,Filter3_4_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x764++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU1,Filter3_4_LenPru1"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x768++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU1,Filter3_4_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x76C++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU1,Filter3_4_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x770++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU1,Filter3_4_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x774++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU1,Filter3_5_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU1,Filter3_5_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x77C++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU1,Filter3_5_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x780++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU1,Filter3_5_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x784++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU1,Filter3_5_LenPru1"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x788++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU1,Filter3_5_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x78C++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU1,Filter3_5_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x790++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU1,Filter3_5_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x794++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU1,Filter3_6_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU1,Filter3_6_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x79C++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU1,Filter3_6_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7A0++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU1,Filter3_6_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7A4++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU1,Filter3_6_LenPru1"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7A8++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU1,Filter3_6_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7AC++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU1,Filter3_6_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7B0++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU1,Filter3_6_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7B4++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU1,Filter3_7_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU1,Filter3_7_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7BC++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU1,Filter3_7_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7C0++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU1,Filter3_7_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7C4++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU1,Filter3_7_LenPru1"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7C8++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU1,Filter3_7_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7CC++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU1,Filter3_7_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7D0++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU1,Filter3_7_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7D4++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU1,Filter3_8_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU1,Filter3_8_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7DC++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU1,Filter3_8_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7E0++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU1,Filter3_8_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7E4++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU1,Filter3_8_LenPru1"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7E8++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU1,Filter3_8_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7EC++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU1,Filter3_8_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7F0++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU1,Filter3_8_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7F4++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU1,Filter3_9_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU1,Filter3_9_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7FC++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU1,Filter3_9_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x800++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU1,Filter3_9_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x804++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU1,Filter3_9_LenPru1"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x808++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU1,Filter3_9_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU1,Filter3_9_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x810++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU1,Filter3_9_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x814++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU1,Filter3_10_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU1,Filter3_10_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x81C++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU1,Filter3_10_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x820++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU1,Filter3_10_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x824++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU1,Filter3_10_LenPru1"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x828++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU1,Filter3_10_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x82C++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU1,Filter3_10_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x830++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU1,Filter3_10_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x834++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU1,Filter3_11_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU1,Filter3_11_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x83C++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU1,Filter3_11_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x840++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU1,Filter3_11_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x844++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU1,Filter3_11_LenPru1"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x848++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU1,Filter3_11_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x84C++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU1,Filter3_11_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x850++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU1,Filter3_11_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x854++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU1,Filter3_12_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU1,Filter3_12_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x85C++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU1,Filter3_12_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x860++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU1,Filter3_12_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x864++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU1,Filter3_12_LenPru1"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x868++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU1,Filter3_12_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x86C++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU1,Filter3_12_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x870++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU1,Filter3_12_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x874++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU1,Filter3_13_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU1,Filter3_13_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x87C++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU1,Filter3_13_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x880++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU1,Filter3_13_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x884++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU1,Filter3_13_LenPru1"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x888++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU1,Filter3_13_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88C++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU1,Filter3_13_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x890++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU1,Filter3_13_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x894++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU1,Filter3_14_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU1,Filter3_14_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x89C++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU1,Filter3_14_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8A0++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU1,Filter3_14_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8A4++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU1,Filter3_14_LenPru1"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8A8++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU1,Filter3_14_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8AC++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU1,Filter3_14_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8B0++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU1,Filter3_14_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8B4++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU1,Filter3_15_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU1,Filter3_15_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x8BC++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU1,Filter3_15_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8C0++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU1,Filter3_15_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8C4++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU1,Filter3_15_LenPru1"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8C8++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU1,Filter3_15_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8CC++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU1,Filter3_15_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8D0++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU1,Filter3_15_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8D4++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU1,Filter3_0P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x8D8++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU1,Filter3_0P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x8DC++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8E0++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8E4++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU1,Filter3_1P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x8E8++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU1,Filter3_1P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x8EC++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8F0++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8F4++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU1,Filter3_2P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x8F8++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU1,Filter3_2P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x8FC++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x900++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x904++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU1,Filter3_3P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x908++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU1,Filter3_3P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x90C++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x910++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x914++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU1,Filter3_4P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x918++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU1,Filter3_4P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x91C++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x920++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x924++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU1,Filter3_5P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x928++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU1,Filter3_5P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x92C++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x930++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x934++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU1,Filter3_6P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x938++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU1,Filter3_6P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x93C++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x940++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x944++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU1,Filter3_7P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x948++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU1,Filter3_7P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x94C++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x950++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x954++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU1,Filter3_8P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x958++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU1,Filter3_8P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x95C++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x960++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x964++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU1,Filter3_9P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x968++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU1,Filter3_9P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x96C++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x970++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x974++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU1,Filter3_10P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x978++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU1,Filter3_10P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x97C++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x980++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x984++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU1,Filter3_11P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x988++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU1,Filter3_11P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x98C++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x990++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x994++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU1,Filter3_12P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x998++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU1,Filter3_12P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x99C++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9A0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9A4++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU1,Filter3_13P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x9A8++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU1,Filter3_13P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x9AC++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9B0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9B4++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU1,Filter3_14P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x9B8++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU1,Filter3_14P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x9BC++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9C0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9C4++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU1,Filter3_15P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x9C8++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU1,Filter3_15P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x9CC++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9D0++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9D4++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU1,FilterByteCountPru1"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU1            ,RX current filter Byte Count"
group.long 0x9D8++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU1,rx_class0_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x9DC++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU1,rx_class0_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x9E0++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU1,rx_class1_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x9E4++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU1,rx_class1_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x9E8++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU1,rx_class2_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x9EC++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU1,rx_class2_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x9F0++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU1,rx_class3_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x9F4++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU1,rx_class3_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x9F8++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU1,rx_class4_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x9FC++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU1,rx_class4_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0xA00++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU1,rx_class5_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0xA04++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU1,rx_class5_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0xA08++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU1,rx_class6_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0xA0C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU1,rx_class6_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0xA10++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU1,rx_class7_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0xA14++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU1,rx_class7_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0xA18++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU1,rx_class8_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0xA1C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU1,rx_class8_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0xA20++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU1,rx_class9_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0xA24++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU1,rx_class9_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0xA28++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU1,rx_class10_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0xA2C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU1,rx_class10_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0xA30++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU1,rx_class11_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0xA34++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU1,rx_class11_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0xA38++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU1,rx_class12_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0xA3C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU1,rx_class12_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0xA40++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU1,rx_class13_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0xA44++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU1,rx_class13_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0xA48++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU1,rx_class14_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0xA4C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU1,rx_class14_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0xA50++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU1,rx_class15_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0xA54++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU1,rx_class15_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0xA58++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU1,rx_class_cfg1Pru1"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0xA5C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU1,rx_class_cfg2Pru1"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0xA60++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA64++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA68++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA6C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA70++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA74++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA78++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA7C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA80++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA84++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA88++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA8C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA90++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA94++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA98++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA9C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xAA0++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU1,RX_greenPru1"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA4++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU1,SAHashPru1"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0xAA8++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU1,ConnectionHashPru1"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0xAAC++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU1,ConnectionHashStartPru1"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0xAB0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU1,RX_RateConfiguration0Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU1,RX_RateConfiguration1Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU1,RX_RateConfiguration2Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xABC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU1,RX_RateConfiguration3Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU1,RX_RateConfiguration4Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU1,RX_RateConfiguration5Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU1,RX_RateConfiguration6Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xACC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU1,RX_RateConfiguration7Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAD0++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU1,RX_RateSourceSelect0Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD4++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU1,RX_RateSourceSelect1Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU1,TX_RateConfiguration1_0Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xADC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU1,TX_RateConfiguration2_0Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0xAE0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU1,TX_RateConfiguration1_1Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAE4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU1,TX_RateConfiguration2_1Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0xAE8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU1,TX_RateConfiguration1_2Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAEC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU1,TX_RateConfiguration2_2Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0xAF0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU1,TX_RateConfiguration1_3Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAF4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU1,TX_RateConfiguration2_3Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0xAF8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU1,TX_RateConfiguration1_4Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAFC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU1,TX_RateConfiguration2_4Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0xB00++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU1,TX_RateConfiguration1_5Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB04++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU1,TX_RateConfiguration2_5Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0xB08++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU1,TX_RateConfiguration1_6Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB0C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU1,TX_RateConfiguration2_6Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0xB10++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU1,TX_RateConfiguration1_7Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB14++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU1,TX_RateConfiguration2_7Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0xB18++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU1,RXGoodFrameCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0xB1C++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU1,RXBCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0xB20++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU1,RXMCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0xB24++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU1,RXCRCErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0xB28++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU1,RXMIIErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0xB2C++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU1,RXOddNibbleFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0xB30++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU1,RXMaxSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0xB34++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU1,RXMaxSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0xB38++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU1,RXMinSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0xB3C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU1,RXMinSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0xB40++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU1,RXoverrunFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0xB44++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU1       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0xB48++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU1       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0xB4C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU1       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0xB50++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU1       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0xB54++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU1       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0xB58++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU1       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0xB5C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU1       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0xB60++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU1       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0xB64++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU1       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0xB68++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU1       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0xB6C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU1      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0xB70++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU1      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0xB74++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU1      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0xB78++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU1      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0xB7C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU1      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0xB80++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU1      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0xB84++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU1,RXSMDFragErrCountPru1"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU1      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU1    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU1     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU1    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0xB88++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU1,RXBucket1SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0xB8C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU1,RXBucket2SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0xB90++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU1,RXBucket3SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0xB94++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU1,RXBucket4SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0xB98++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU1,RX64BSizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0xB9C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU1,RXBucket1SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0xBA0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU1,RXBucket2SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBA4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU1,RXBucket3SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBA8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU1,RXBucket4SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xBAC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU1,RXBucket5SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0xBB0++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU1,RXTotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0xBB4++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU1,RX_TX_TotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0xBB8++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT1,TXGoodFrameCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0xBBC++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT1,TXBCFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0xBC0++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT1,TXMFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0xBC4++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT1,TXOddNibbleFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0xBC8++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT1,TXUnderFlowErrCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0xBCC++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT1,TXMaxSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0xBD0++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT1,TXMaxSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0xBD4++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT1,TXMinSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0xBD8++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT1,TXMinSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0xBDC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT1,TXBucket1SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0xBE0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT1,TXBucket2SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0xBE4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT1,TXBucket3SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0xBE8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT1,TXBucket4SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0xBEC++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT1,TX64BSizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0xBF0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT1,TXBucket1SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0xBF4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT1,TXBucket2SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBF8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT1,TXBucket3SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBFC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT1,TXBucket4SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xC00++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT1,TXBucket5SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0xC04++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT1,TXTotalByteCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0xC08++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT1,TXHSRTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0xC0C++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT1,TXHSRSeqPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0xC10++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT1,TXVLANTYPETAGPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0xC14++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT1,TXVLANINSTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"
base eaxi:0xB132000
width 22.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RXCFG0,RX Configuration 0 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS0      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW0          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW0           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE0     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN0            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL0           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE0     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS0 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE0           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RXCFG1,RX Configuration 1 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS1      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW1          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW1           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE1     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN1            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL1           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE1     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS1 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE1           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TXCFG0,TX Control Register 0"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY0         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY0      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN0        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR0 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE0 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL0          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE0          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE0     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE0           ,0h = TX PORT is disabled/stopped immediately" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TXCFG1,TX Control Register 1"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY1         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY1      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN1        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR1 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE1 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL1          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE1          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE1     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE1           ,0h = TX PORT is disabled/stopped immediately" "0,1"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_TX_CRC0,Transmit CRC32 Register 0"
hexmask.long 0x00 0.--31. 1. " TX_CRC0               ,FCS (CRC32) data can be read by PRU for diagnostics"
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_TX_CRC1,Transmit CRC32 Register 1"
hexmask.long 0x00 0.--31. 1. " TX_CRC1               ,FCS (CRC32) data can be read by PRU for diagnostics"
group.long 0x30++0x3
line.long 0x00 "ICSSG_TX_IPG0,TX IPG Register 0"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG0               ,Define the minimum Inter Packet Gap"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_IPG1,TX IPG Register 1"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG1               ,Define the minimum Inter Packet Gap"
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_PRS0,PORT_RAW_STATUS Register 0"
bitfld.long 0x00 1. " SYNC_MII0_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII0_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_PRS1,PORT_RAW_STATUS Register 1"
bitfld.long 0x00 1. " SYNC_MII1_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII1_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_RX_FRMS0,RX Frame Size Register 0"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM0           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM0          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x44++0x3
line.long 0x00 "ICSSG_RX_FRMS1,RX Frame Size Register 1"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM1           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM1          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x48++0x3
line.long 0x00 "ICSSG_RX_PCNT0,RX Preamble Cnt Register 0"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT0          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT0         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_RX_PCNT1,RX Preamble Cnt Register 1"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT1          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT1         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x3
line.long 0x00 "ICSSG_RX_ERR0,RX Error Register 0"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR0       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR0      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR0      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR0     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
group.long 0x54++0x3
line.long 0x00 "ICSSG_RX_ERR1,RX Error Register 1"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR1       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR1      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR1      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR1     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL0,RX FIFO Level 0 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL0        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL1,RX FIFO Level 1 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL1        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL0,TX FIFO Register 0"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL0        ,Define the number of valid nibbles in the TX FIFO"
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL1,TX FIFO Register 1"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL1        ,Define the number of valid nibbles in the TX FIFO"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PROTECT"
tree "PRU_ICSSG0_PR1_PROT_SLV"
base eaxi:0xB124C00
width 18.
group.long 0x0++0x3
line.long 0x00 "ICSSG_UNLOCK_KEY,LOCK KEY"
hexmask.long 0x00 0.--31. 1. " UNLOCK_KEY         ,UnLock Key Pattern 0x83E7_0B13. To UnLock 0x0000_0000. To Lock Must unlock to update MMRs."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CFG,Config"
bitfld.long 0x00 6. " PRU1_DMEM1_LOCK_EN ,Write Protect DMEM10h = Disable 1h = Enable. When enabled only PRU1 can write to DMEM1" "0,1"
bitfld.long 0x00 5. "         PRU0_DMEM0_LOCK_EN ,Write Protect DMEM00h = Disable 1h = Enable. When enabled only PRU0 can write to DMEM0" "0,1"
textline "                           "
bitfld.long 0x00 4. " ICSS_CFG_WP_EN     ,Write Protect ICSS_CFG0h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 3. "         RTU1_PRU_WP_EN     ,Write Protect RTU_PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 2. " RTU0_PRU_WP_EN     ,Write Protect RTU_PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 1. "         PRU1_WP_EN         ,Write Protect PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 0. " PRU0_WP_EN         ,Write Protect PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM"
tree "PRU_ICSSG1_PR1_PDSP0_IRAM"
base eaxi:0xB122000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM"
base eaxi:0xB123000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM"
base eaxi:0xB123800
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_PDSP1_IRAM"
base eaxi:0xB124000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
tree "PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG"
base eaxi:0xB122400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"
base eaxi:0xB123400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"
base eaxi:0xB123C00
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG"
base eaxi:0xB124400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAM"
tree "PRU_ICSSG1_RAM_SLV_RAM"
base eaxi:0xB110000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAT_SLICE0"
tree "PRU_ICSSG1_RAT_SLICE0_CFG_CFG"
base eaxi:0xB108000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree "PRU_ICSSG1_RAT_SLICE1_CFG"
base eaxi:0xB109000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_TASKS_MGR_PRU0"
tree "PRU_ICSSG1_TASKS_MGR_PRU0"
base eaxi:0xB12A000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG1_TASKS_MGR_RTU0"
base eaxi:0xB12A100
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG1_TASKS_MGR_PRU1"
base eaxi:0xB12A200
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG1_TASKS_MGR_RTU1"
base eaxi:0xB12A300
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_UART0"
tree "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV"
base eaxi:0xB128000
width 16.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RBR_TBR,Registers"
hexmask.long.word 0x00 8.--17. 1. " TBR_DATA    ,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "      RBR_DATA     ,Receive Buffer Register"
group.long 0x4++0x3
line.long 0x00 "ICSSG_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x00 3. " EDSSI       ,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x00 2. "         ELSI         ,Enable for Receiver Line Status Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " ETBEI       ,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x00 0. "         ERBI         ,Enable for Receiver Data Available Interrupt" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x00 14.--15. " FCR_RXFIFTL ,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x00 11. "         FCR_DMAMODE1 ,DMA Mode Select" "0,1"
textline "                         "
bitfld.long 0x00 10. " FCR_TXCLR   ,Transmitter FIFO Reset" "0,1"
bitfld.long 0x00 9. "         FCR_RXCLR    ,Receiver FIFO Reset" "0,1"
textline "                         "
bitfld.long 0x00 8. " FCR_FIFOEN  ,FIFO Enable Register" "0,1"
bitfld.long 0x00 6.--7. "         IIR_FIFOEN   ,FIFOs enabled" "0,1,2,3"
textline "                         "
bitfld.long 0x00 1.--3. " IIR_INTID   ,Interrupt Type" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         IIR_IPEND    ,Receiver Data Available Interrupt Pending" "0,1"
group.long 0xC++0x3
line.long 0x00 "ICSSG_LCTR,Line Control Register"
bitfld.long 0x00 7. " DLAB        ,Divisor Latch Access Bit" "0,1"
bitfld.long 0x00 6. "         BC           ,Break Control" "0,1"
textline "                         "
bitfld.long 0x00 5. " SP          ,Stick Parity" "0,1"
bitfld.long 0x00 4. "         EPS          ,Even Parity Select" "0,1"
textline "                         "
bitfld.long 0x00 3. " PEN         ,Parity Enable" "0,1"
bitfld.long 0x00 2. "         STB          ,Number of Stop Bits" "0,1"
textline "                         "
bitfld.long 0x00 1. " WLS1        ,Word Length Select Bit 1" "0,1"
bitfld.long 0x00 0. "         WLS0         ,Word Length Select Bit 0" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MCTR,Modem Control Register"
bitfld.long 0x00 5. " AFE         ,Autoflow Control Enable" "0,1"
bitfld.long 0x00 4. "         LOOP         ,LOOP Bit" "0,1"
textline "                         "
bitfld.long 0x00 3. " OUT2        ,Out2 Bit" "0,1"
bitfld.long 0x00 2. "         OUT1         ,Out1 Bit" "0,1"
textline "                         "
bitfld.long 0x00 1. " RTS         ,Ready to Send" "0,1"
bitfld.long 0x00 0. "         DTR          ,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "ICSSG_LSR1,Line Status Register1"
bitfld.long 0x00 7. " RXFIFOE     ,Receiver FIFO Error" "0,1"
bitfld.long 0x00 6. "         TEMT         ,Transmitter Empty" "0,1"
textline "                         "
bitfld.long 0x00 5. " THRE        ,Transmitter Holding Register" "0,1"
bitfld.long 0x00 4. "         BI           ,Break Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " FE          ,Framing Error" "0,1"
bitfld.long 0x00 2. "         PE           ,Parity Error" "0,1"
textline "                         "
bitfld.long 0x00 1. " OE          ,Overrun Error" "0,1"
bitfld.long 0x00 0. "         DR           ,Data Ready" "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "ICSSG_MSR,Modem Status Register"
bitfld.long 0x00 7. " CD          ,Carrier Detect" "0,1"
bitfld.long 0x00 6. "         RI           ,Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 5. " DSR         ,Data Set Ready" "0,1"
bitfld.long 0x00 4. "         CTS          ,Clear To Send" "0,1"
textline "                         "
bitfld.long 0x00 3. " DCD         ,Delta Carrier Detect" "0,1"
bitfld.long 0x00 2. "         TERI         ,Trailing Edge Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 1. " DDSR        ,Delta Set Ready" "0,1"
bitfld.long 0x00 0. "         DCTS         ,Delta Clear To Send" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA        ,Scratch Register Bits"
group.long 0x20++0x3
line.long 0x00 "ICSSG_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLL         ,Divisor Latch [LSB]"
group.long 0x24++0x3
line.long 0x00 "ICSSG_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLH         ,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_PID,Peripheral ID Register"
hexmask.long 0x00 0.--31. 1. " PID         ,"
group.long 0x30++0x3
line.long 0x00 "ICSSG_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. " URST        ,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "         UTRST        ,UART Transmitter Reset Bit" "0,1"
textline "                         "
bitfld.long 0x00 13. " URRST       ,UART Receiver Reset Bit" "0,1"
bitfld.long 0x00 1. "         RES          ,Free Bit" "0,1"
textline "                         "
bitfld.long 0x00 0. " FREE        ,Free Bit" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_MODE,UART Mode Definition Register"
bitfld.long 0x00 0. " OSM_SEL     ,Oversampling Mode Select" "0,1"
width 0x0B
tree.end
tree.end
tree.end
tree "ICSS_2"
tree "PRU_ICSSG_CFG"
tree "PRU_ICSSG2_PR1_CFG_SLV"
base eaxi:0xB226000
width 32.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID_REG,Register"
hexmask.long 0x00 0.--31. 1. " ICSS_IDVER                 ,Module ID field"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_HWDIS_REG,HW Disable Register"
hexmask.long.byte 0x00 0.--7. 1. " HWDIS                      ,Read the state of the efuse bits which drive pr1_hw_disable[7:0]"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_GPCFG0_REG,GP Configuration 0 Register"
in
textline "                                         "
hgroup.long 0xC++0x3
hide.long 0x00 "ICSSG_GPCFG1_REG,GP Configuration 1 Register"
in
textline "                                         "
group.long 0x10++0x3
line.long 0x00 "ICSSG_CGR_REG,Clock Gating Register"
bitfld.long 0x00 31. " ICSS_STOP_ACK              ,ICSS" "0,1"
bitfld.long 0x00 30. "         ICSS_STOP_REQ              ,ICSS" "0,1"
textline "                                         "
bitfld.long 0x00 29. " ICSS_PWR_IDLE              ,ICSS" "0,1"
bitfld.long 0x00 17. "         IEP_CLK_EN                 ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 16. " IEP_CLK_STOP_ACK           ,IEP" "0,1"
bitfld.long 0x00 15. "         IEP_CLK_STOP_REQ           ,IEP" "0,1"
textline "                                         "
bitfld.long 0x00 14. " ECAP_CLK_EN                ,ECAP" "0,1"
bitfld.long 0x00 13. "         ECAP_CLK_STOP_ACK          ,ECAP" "0,1"
textline "                                         "
bitfld.long 0x00 12. " ECAP_CLK_STOP_REQ          ,ECAP" "0,1"
bitfld.long 0x00 11. "         UART_CLK_EN                ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 10. " UART_CLK_STOP_ACK          ,UART" "0,1"
bitfld.long 0x00 9. "         UART_CLK_STOP_REQ          ,UART" "0,1"
textline "                                         "
bitfld.long 0x00 8. " INTC_CLK_EN                ,INTC" "0,1"
bitfld.long 0x00 7. "         INTC_CLK_STOP_ACK          ,INTC" "0,1"
textline "                                         "
bitfld.long 0x00 6. " INTC_CLK_STOP_REQ          ,INTC" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_GPECFG0_REG,GP Enc Configuration 0 Register"
bitfld.long 0x00 17. " PRU0_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU0_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU0_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU0_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU0_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU0_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU0_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU0_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x18++0x3
line.long 0x00 "ICSSG_GPECFG1_REG,GP Enc Configuration 1 Register"
bitfld.long 0x00 17. " PRU1_GPO_SHIFT_CLK_DONE    ,Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x00 16. "         PRU1_GPO_SHIFT_CLK_HIGH    ,Shift Clock Stop High" "0,1"
textline "                                         "
hexmask.long.byte 0x00 8.--15. 1. " PRU1_GPO_SHIFT_CNT         ,Shift Bit Count"
bitfld.long 0x00 6. "        PRU1_GPO_SHIFT_GP_EN       ,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
textline "                                         "
bitfld.long 0x00 5. " PRU1_GPO_SHIFT_CLK_FREE    ,Free Running Clock Mode" "0,1"
bitfld.long 0x00 4. "         PRU1_GPO_SHIFT_SWAP        ,0x0 = No Swap" "0,1"
textline "                                         "
bitfld.long 0x00 1. " PRU1_GPI_SHIFT_EN          ,GPI Shift In Enable" "0,1"
bitfld.long 0x00 0. "         PRU1_GPI_SB_P              ,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_MII_RT_REG,MII_RT Event Enable Register"
bitfld.long 0x00 0. " MII_RT_EVENT_EN            ,Note: This bit field is non-functional on this device." "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_IEPCLK_REG,IEP Configuration Register"
bitfld.long 0x00 1. " IEP1_SLV_EN                ,IEP1 Master Counter Slave enable" "0,1"
bitfld.long 0x00 0. "         IEP_OCP_CLK_EN             ,Defines the source of the IEP CLK" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_SPP_REG,Scratchpad Priority and Shift Register"
bitfld.long 0x00 3. " RTU_XFR_SHIFT_EN           ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 2. "         XFR_BYTE_SHIFT_EN          ,Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations." "0,1"
textline "                                         "
bitfld.long 0x00 1. " XFR_SHIFT_EN               ,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations." "0,1"
bitfld.long 0x00 0. "         PRU1_PAD_HP_EN             ,Reserved" "0,1"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CORE_SYNC_REG,CoreSync Configuration Register"
bitfld.long 0x00 0. " CORE_VBUSP_SYNC_EN         ," "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SA_MX_REG,SA Mux Selection Register"
bitfld.long 0x00 10.--11. " PWM3_REMAP_EN              ,pwm3_remap_en controls icss_wrap glue" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_REMAP_EN              ,pwm0_remap_en controls icss_wrap glue" "0,1,2,3"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " SA_MUX_SEL                 ,Reserved"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU0_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU0_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG0,PRU0 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG0,PRU0 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU0_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x50++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG1,PRU0 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0x54++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG1,PRU0 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU0_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0x58++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG2,PRU0 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0x5C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG2,PRU0 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU0_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0x60++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG3,PRU0 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG3,PRU0 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU0_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0x68++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG4,PRU0 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG4,PRU0 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU0_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0x70++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG5,PRU0 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0x74++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG5,PRU0 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU0_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0x78++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG6,PRU0 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG6,PRU0 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU0_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0x80++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG7,PRU0 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0x84++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG7,PRU0 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU0_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0x88++0x3
line.long 0x00 "ICSSG_PRU0_SD_CLK_SEL_REG8,PRU0 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU0_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU0_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU0_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU0_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU0_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU0_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU0_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG8,PRU0 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU0_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU0_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU0_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU0_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU0_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU0_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU0_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0x90++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x00 4. " PRU1_SD_DIVFACTOR_FRAC     ," "0,1"
bitfld.long 0x00 0.--3. "         PRU1_SD_DIVFACTOR          ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x94++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG0,PRU1 FD, ACC and Clock Selection Register 0"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_0         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_0   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_0         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_0   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL0           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV0           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL0           ,Selects the clock source" "0,1,2,3"
group.long 0x98++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG0,PRU1 FD and Over Sample Size Register 0"
bitfld.long 0x00 23. " PRU1_FD_EN_0               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_0          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_0    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_0          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_0    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_0      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE0       ,Over Sample Rate"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG1,PRU1 FD, ACC and Clock Selection Register 1"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_1         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_1   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_1         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_1   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL1           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV1           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL1           ,Selects the clock source" "0,1,2,3"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG1,PRU1 FD and Over Sample Size Register 1"
bitfld.long 0x00 23. " PRU1_FD_EN_1               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_1          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_1    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_1          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_1    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_1      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE1       ,Over Sample Rate"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG2,PRU1 FD, ACC and Clock Selection Register 2"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_2         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_2   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_2         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_2   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL2           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV2           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL2           ,Selects the clock source" "0,1,2,3"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG2,PRU1 FD and Over Sample Size Register 2"
bitfld.long 0x00 23. " PRU1_FD_EN_2               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_2          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_2    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_2          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_2    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_2      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE2       ,Over Sample Rate"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG3,PRU1 FD, ACC and Clock Selection Register 3"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_3         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_3   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_3         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_3   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL3           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV3           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL3           ,Selects the clock source" "0,1,2,3"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG3,PRU1 FD and Over Sample Size Register 3"
bitfld.long 0x00 23. " PRU1_FD_EN_3               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_3          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_3    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_3          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_3    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_3      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE3       ,Over Sample Rate"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG4,PRU1 FD, ACC and Clock Selection Register 4"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_4         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_4   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_4         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_4   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL4           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV4           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL4           ,Selects the clock source" "0,1,2,3"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG4,PRU1 FD and Over Sample Size Register 4"
bitfld.long 0x00 23. " PRU1_FD_EN_4               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_4          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_4    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_4          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_4    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_4      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE4       ,Over Sample Rate"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG5,PRU1 FD, ACC and Clock Selection Register 5"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_5         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_5   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_5         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_5   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL5           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV5           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL5           ,Selects the clock source" "0,1,2,3"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG5,PRU1 FD and Over Sample Size Register 5"
bitfld.long 0x00 23. " PRU1_FD_EN_5               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_5          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_5    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_5          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_5    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_5      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE5       ,Over Sample Rate"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG6,PRU1 FD, ACC and Clock Selection Register 6"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_6         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_6   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_6         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_6   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL6           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV6           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL6           ,Selects the clock source" "0,1,2,3"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG6,PRU1 FD and Over Sample Size Register 6"
bitfld.long 0x00 23. " PRU1_FD_EN_6               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_6          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_6    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_6          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_6    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_6      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE6       ,Over Sample Rate"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG7,PRU1 FD, ACC and Clock Selection Register 7"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_7         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_7   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_7         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_7   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL7           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV7           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL7           ,Selects the clock source" "0,1,2,3"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG7,PRU1 FD and Over Sample Size Register 7"
bitfld.long 0x00 23. " PRU1_FD_EN_7               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_7          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_7    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_7          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_7    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_7      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE7       ,Over Sample Rate"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_PRU1_SD_CLK_SEL_REG8,PRU1 FD, ACC and Clock Selection Register 8"
bitfld.long 0x00 22. " PRU1_FD_ZERO_MAX_8         ,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x00 17.--21. "         PRU1_FD_ZERO_MAX_LIMIT_8   ,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 16. " PRU1_FD_ZERO_MIN_8         ,Fast Detect Zero Count Min Threshold Hit" "0,1"
bitfld.long 0x00 11.--15. "         PRU1_FD_ZERO_MIN_LIMIT_8   ,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.long 0x00 4.--5. " PRU1_SD_ACC_SEL8           ,00: acc3 is selected" "0,1,2,3"
bitfld.long 0x00 2. "         PRU1_SD_CLK_INV8           ,Optional clock inversion post clock selection mux" "0,1"
textline "                                         "
bitfld.long 0x00 0.--1. " PRU1_SD_CLK_SEL8           ,Selects the clock source" "0,1,2,3"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG8,PRU1 FD and Over Sample Size Register 8"
bitfld.long 0x00 23. " PRU1_FD_EN_8               ,Fast Detect One Enable" "0,1"
bitfld.long 0x00 22. "         PRU1_FD_ONE_MAX_8          ,Fast Detect One Count Max Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 17.--21. " PRU1_FD_ONE_MAX_LIMIT_8    ,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "        PRU1_FD_ONE_MIN_8          ,Fast Detect One Count Min Threshold Hit" "0,1"
textline "                                         "
bitfld.long 0x00 11.--15. " PRU1_FD_ONE_MIN_LIMIT_8    ,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "        PRU1_FD_WINDOW_SIZE_8      ,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
textline "                                         "
hexmask.long.byte 0x00 0.--7. 1. " PRU1_SD_SAMPLE_SIZE8       ,Over Sample Rate"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_PRU0_ED_RX_CFG_REG,PRU0 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU0_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU0_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_PRU0_ED_TX_CFG_REG,PRU0 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU0_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU0_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU0_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU0_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU0_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU0_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU0_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU0_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG0_REG,PRU0 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH0_CFG1_REG,PRU0 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF0++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG0_REG,PRU0 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH1_CFG1_REG,PRU0 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0xF8++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG0_REG,PRU0 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU0_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU0_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU0_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU0_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU0_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU0_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU0_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_PRU0_ED_CH2_CFG1_REG,PRU0 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU0_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU0_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x100++0x3
line.long 0x00 "ICSSG_PRU1_ED_RX_CFG_REG,PRU1 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_RX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_RX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
bitfld.long 0x00 3. "         PRU1_ED_RX_SB_POL          ,Defines the polarity of the RX Start Bit" "0,1"
textline "                                         "
bitfld.long 0x00 0.--2. " PRU1_ED_RX_SAMPLE_SIZE     ,Over Sample size" "0,1,2,3,4,5,6,7"
group.long 0x104++0x3
line.long 0x00 "ICSSG_PRU1_ED_TX_CFG_REG,PRU1 ED Transmit Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_TX_DIV_FACTOR      ,div factor for divh16"
bitfld.long 0x00 15. "      PRU1_ED_TX_DIV_FACTOR_FRAC ,Enable Fractional division before the divh16" "0,1"
textline "                                         "
bitfld.long 0x00 10. " PRU1_ENDAT2_CLK_SYNC       ,Observation of pru<n>_endat2_clk pin state" "0,1"
bitfld.long 0x00 9. "         PRU1_ENDAT1_CLK_SYNC       ,Observation of pru<n>_endat1_clk pin state" "0,1"
textline "                                         "
bitfld.long 0x00 8. " PRU1_ENDAT0_CLK_SYNC       ,Observation of pru<n>_endat0_clk pin state" "0,1"
bitfld.long 0x00 7. "         PRU1_ED_BUSY_2             ,Determines when you can assert tx go for channel 2" "0,1"
textline "                                         "
bitfld.long 0x00 6. " PRU1_ED_BUSY_1             ,Determines when you can assert tx go for channel 1" "0,1"
bitfld.long 0x00 5. "         PRU1_ED_BUSY_0             ,Determines when you can assert tx go for channel 0" "0,1"
textline "                                         "
bitfld.long 0x00 4. " PRU1_ED_TX_CLK_SEL         ,Selects the clock source for the divh16fr" "0,1"
group.long 0x108++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG0_REG,PRU1 ED Channel 0 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS0 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT0        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN0    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP0          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE0     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE0     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY0           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x10C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH0_CFG1_REG,PRU1 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER0     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER0 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x110++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG0_REG,PRU1 ED Channel 1 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS1 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT1        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN1    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP1          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE1     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE1     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY1           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x114++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH1_CFG1_REG,PRU1 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER1     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER1 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x118++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG0_REG,PRU1 ED Channel 2 Configuration 0 Register"
bitfld.long 0x00 31. " PRU1_ED_TX_FIFO_SWAP_BITS2 ,This enables the swapping of the bits when they are loaded into the TX FIFO." "0,1"
bitfld.long 0x00 30. "         PRU1_ED_SW_CLK_OUT2        ,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
textline "                                         "
bitfld.long 0x00 29. " PRU1_ED_CLK_OUT_OVR_EN2    ,When set, this gives the SW the ablity to have direct control of pru<n>_ endat<m>_clk. CAREFUL consideration to not override clock during free running mode of this will cause clock duty cycle violation." "0,1"
bitfld.long 0x00 28. "         PRU1_ED_RX_SNOOP2          ,Direct Read of pru<n>_ endat<m>_in state" "0,1"
textline "                                         "
hexmask.long.word 0x00 16.--27. 1. " PRU1_ED_RX_FRAME_SIZE2     ,RX frame size, after SB is detected"
bitfld.long 0x00 11.--15. "      PRU1_ED_TX_FRAME_SIZE2     ,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.long.word 0x00 0.--10. 1. " PRU1_ED_TX_WDLY2           ,EnDAT TX wire delay using 200Mhz steps (CORE clock). Software should program a number divisible by 5. (Hw"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_PRU1_ED_CH2_CFG1_REG,PRU1 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x00 16.--31. 1. " PRU1_ED_RX_EN_COUNTER2     ,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)."
hexmask.long.word 0x00 0.--15. 1. "      PRU1_ED_TST_DELAY_COUNTER2 ,This counter will start after the tx_wire_delay has been met. After this counter expires the 1st transmit clock will be driven high. Counts in CORE cycles. Software programs value divisible by 5, and hardware will count by 5."
group.long 0x124++0x3
line.long 0x00 "ICSSG_RTU0_POKE_EN0_REG,RTU0 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU0_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU0_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU0_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU0_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU0_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU0_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU0_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU0_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x12C++0x3
line.long 0x00 "ICSSG_RTU1_POKE_EN0_REG,RTU1 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. " RTU1_POKE_R27_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "        RTU1_POKE_R26_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 20.--23. " RTU1_POKE_R25_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "        RTU1_POKE_R24_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " RTU1_POKE_R23_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "        RTU1_POKE_R22_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 4.--7. " RTU1_POKE_R21_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        RTU1_POKE_R20_EN           ,This enables the external values to get poked into PRU?s internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x3
line.long 0x00 "ICSSG_PWM0,PWM0 Trip Configuration Register"
bitfld.long 0x00 30. " PWM0_TRIP_S                ,Trip Status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM0_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM0_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM0_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM0_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM0_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM0_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM0_DEBOUNCE_VALUE        ,Debounce counter , defines the number of core_clk required for the pulse not to get rejected"
group.long 0x134++0x3
line.long 0x00 "ICSSG_PWM1,PWM1 Trip Configuration Register"
bitfld.long 0x00 30. " PWM1_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM1_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM1_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM1_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM1_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM1_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM1_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM1_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x138++0x3
line.long 0x00 "ICSSG_PWM2,PWM2 Trip Configuration Register"
bitfld.long 0x00 30. " PWM2_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM2_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM2_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM2_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM2_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM2_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM2_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM2_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_PWM3,PWM3 Trip Configuration Register"
bitfld.long 0x00 30. " PWM3_TRIP_S                ,Trip status" "0,1"
hexmask.long.word 0x00 21.--29. 1. "         PWM3_TRIP_VEC              ,Trip trigger cause vector"
textline "                                         "
bitfld.long 0x00 20. " PWM3_POS_ERR_TRIP          ,Software position feedback error trip" "0,1"
bitfld.long 0x00 19. "         PWM3_OVER_ERR_TRIP         ,Software overcurrent error trip" "0,1"
textline "                                         "
bitfld.long 0x00 18. " PWM3_TRIP_RESET            ,Software trip reset" "0,1"
bitfld.long 0x00 17. "         PWM3_TRIP_CMP0_EN          ,CMP0 reset trip clear enable" "0,1"
textline "                                         "
hexmask.long.word 0x00 8.--16. 1. " PWM3_TRIP_MASK             ,Software mask for trip, one hot"
hexmask.long.byte 0x00 0.--7. 1. "      PWM3_DEBOUNCE_VALUE        ,Debounce counter, defines the number of core_clk required for the pulse not to get rejected"
group.long 0x140++0x3
line.long 0x00 "ICSSG_PWM0_0,PWM0 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM0_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x144++0x3
line.long 0x00 "ICSSG_PWM0_1,PWM0 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM0_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x148++0x3
line.long 0x00 "ICSSG_PWM0_2,PWM0 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM0_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM0_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM0_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM0_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM0_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM0_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x14C++0x3
line.long 0x00 "ICSSG_PWM1_0,PWM1 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM1_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x150++0x3
line.long 0x00 "ICSSG_PWM1_1,PWM1 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM1_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x154++0x3
line.long 0x00 "ICSSG_PWM1_2,PWM1 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM1_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM1_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM1_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM1_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM1_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM1_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x158++0x3
line.long 0x00 "ICSSG_PWM2_0,PWM2 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM2_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_PWM2_1,PWM2 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM2_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_PWM2_2,PWM2 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM2_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM2_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM2_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM2_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM2_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM2_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x164++0x3
line.long 0x00 "ICSSG_PWM3_0,PWM3 State Configuration 0 Register"
bitfld.long 0x00 10.--11. " PWM3_0_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_0_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_0_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_0_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_0_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_0_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x168++0x3
line.long 0x00 "ICSSG_PWM3_1,PWM3 State Configuration 1 Register"
bitfld.long 0x00 10.--11. " PWM3_1_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_1_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_1_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_1_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_1_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_1_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x16C++0x3
line.long 0x00 "ICSSG_PWM3_2,PWM3 State Configuration 2 Register"
bitfld.long 0x00 10.--11. " PWM3_2_NEG_ACT             ,Active neg state 00 toggle 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 8.--9. "         PWM3_2_POS_ACT             ,Active pos state 00 toggle 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 6.--7. " PWM3_2_NEG_TRIP            ,Trip neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 4.--5. "         PWM3_2_POS_TRIP            ,Trip pos state 00 z 01 L 10 H" "0,1,2,3"
textline "                                         "
bitfld.long 0x00 2.--3. " PWM3_2_NEG_INIT            ,Initial neg state 00 z 01 L 10 H" "0,1,2,3"
bitfld.long 0x00 0.--1. "         PWM3_2_POS_INIT            ,Initial pos state 00 z 01 L 10 H" "0,1,2,3"
group.long 0x170++0x3
line.long 0x00 "ICSSG_SPIN_LOCK0,Spin Lock 0 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_0       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_0          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_0       ,Spin Lock Status" "0,1"
group.long 0x174++0x3
line.long 0x00 "ICSSG_SPIN_LOCK1,Spin Lock 1 Register"
bitfld.long 0x00 8.--13. " MMR_OWN_REQ_VECTOR_1       ,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "        MMR_OWN_REQ_CLR_1          ,Spin Lock Status Clear" "0,1"
textline "                                         "
bitfld.long 0x00 0. " MMR_OWN_REQ_STATUS_1       ,Spin Lock Status" "0,1"
group.long 0x178++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG0,PA STATS PDSP0 Vector 0 Register"
bitfld.long 0x00 31. " PA_PDSP0_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP0_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP0_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x17C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT0,PA STATS PDSP0 Status 0 Register"
bitfld.long 0x00 1.--3. " PA_PDSP0_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP0_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG1,PA STATS PDSP0 Vector 1 Register"
bitfld.long 0x00 31. " PA_PDSP1_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP1_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP1_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT1,PA STATS PDSP0 Status 1 Register"
bitfld.long 0x00 1.--3. " PA_PDSP1_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP1_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x188++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG2,PA STATS PDSP0 Vector 2 Register"
bitfld.long 0x00 31. " PA_PDSP2_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP2_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP2_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT2,PA STATS PDSP0 Status 2 Register"
bitfld.long 0x00 1.--3. " PA_PDSP2_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP2_READY             ,pa_pdsp{i}_ready" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_CFG3,PA STATS PDSP0 Vector 3 Register"
bitfld.long 0x00 31. " PA_PDSP3_INC_TYPE          ,pa_pdsp{i}_inc_type" "0,1"
hexmask.long.tbyte 0x00 14.--30. 1. "         PA_PDSP3_INC_VAL           ,pa_pdsp{i}_inc_val"
textline "                                         "
hexmask.long.word 0x00 0.--13. 1. " PA_PDSP3_INDEX             ,pa_pdsp{i}_index"
rgroup.long 0x194++0x3
line.long 0x00 "ICSSG_PA_STAT_PDSP_STAT3,PA STATS PDSP0 Status 3 Register"
bitfld.long 0x00 1.--3. " PA_PDSP3_STATUS            ,pa_pdsp{i}_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         PA_PDSP3_READY             ,pa_pdsp{i}_ready" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_DRAM0"
tree "PRU_ICSSG2_DRAM0_SLV_RAM"
base eaxi:0xB200000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree "PRU_ICSSG2_DRAM1_SLV_RAM"
base eaxi:0xB202000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECAP0"
tree "PRU_ICSSG2_PR1_ICSS_ECAP0_ECAP_SLV"
base eaxi:0xB230000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_TSCNT,Time Stamp Counter Register"
hexmask.long 0x00 0.--31. 1. " TSCNT      ,Active 32-bit counter register which is used as the capture time-base ."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CNTPHS,Counter Phase Control Register"
hexmask.long 0x00 0.--31. 1. " CNTPHS     ,Counter phase value register that can be programmed for phase lag/lead. This register shadows"
group.long 0x8++0x3
line.long 0x00 "ICSSG_CAP1,Capture-1 Register"
hexmask.long 0x00 0.--31. 1. " CAP1       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.(b) Software may be useful for test purposes/initialisation.(c) APRD shadow register (that is,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_CAP2,Capture-2 Register"
hexmask.long 0x00 0.--31. 1. " CAP2       ,This register can be loaded (written) by the following:a) Time-stamp (that is, counter value) during a capture event.b) Software may be useful for test purposes.c) ACMP shadow register (that is,"
group.long 0x10++0x3
line.long 0x00 "ICSSG_CAP3,Capture-3 Register"
hexmask.long 0x00 0.--31. 1. " CAP3       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APER) register. User updates the PWM period value via this register. In this mode"
group.long 0x14++0x3
line.long 0x00 "ICSSG_CAP4,Capture-4 Register"
hexmask.long 0x00 0.--31. 1. " CAP4       ,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. User updates the PWM compare value via this register. In this mode"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ECCTL2_ECCTL1,ECAP Control Register 1"
bitfld.long 0x00 27.--31. " FILTER     ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "        APWMPOL     ,APWM output polarity select:0 = output is active high (that is, compare value defines high time)1 = output is active low (that is, compare value defines low time)Note: This is applicable only in APWM operating mode." "0,1"
textline "                              "
bitfld.long 0x00 25. " CAP_APWM   ,CAP/APWM operating mode select:0 = ECAP module operates in capture mode. This mode forces the following configuration:a) Inhibitsb) Inhibits shadow loads onc) Permits user to enable ICSSG_CAP1 to ICSSG_CAP4 register load.d) ECAP input/APWM output pin operates as a capture input.1 = ECAP module operates in APWM mode. This mode forces the following configuration:a) Resets TSCNT on CTR = PRD event (period boundary).b) Permits shadow loading on ICSSG_CAP1 and ICSSG_CAP2 registers.c) Disables loading of time-stamps into ICSSG_CAP1 to ICSSG_CAP4 registers.d) ECAP input/APWM ouput pin operates as a APWM output." "0,1"
bitfld.long 0x00 24. "         SWSYNC      ,Software forced counter (0 = writing a zero has no effect will always return a zero1 = writing a one will force aNote: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode, the synchronizing can also be done via the CTR = PRD event." "0,1"
textline "                              "
bitfld.long 0x00 22.--23. " SYNCO_SEL  ,Sync-out select:0b00 = select sync-in event to be the sync-out signal (pass through)0b01 = select CTR = PRD event to be the sync-out signal0b10 = disable sync out signal0b11 = disable sync out signalNote: Selection CTR = PRD is meaningful only in APWM mode, however can still be chosen in CAP mode, if user believes it to be useful." "0,1,2,3"
bitfld.long 0x00 21. "         SYNCI_EN    ,Counter (0 = disable sync-in option1 = enable counter (" "0,1"
textline "                              "
bitfld.long 0x00 20. " TSCNTSTP   ,Counter stop (freeze) control:0 = counter stopped1 = counter free running" "0,1"
bitfld.long 0x00 19. "         REARM_RESET ,One-shot re-arming, that is, wait for stop trigger:0 = writing a zero has no effect (reading always returns a 0)1 = writing a one arms the one-shot sequence as follows:1) resets the mod4 counter to zero2) un-freezes the mod4 counter3) enables capture register loadsNote: The re-arm function is valid in onesht or continous mode." "0,1"
textline "                              "
bitfld.long 0x00 17.--18. " STOPVALUE  ,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen, that is, capture sequence is stopped.0b00 = stop after capture event 10b01 = stop after capture event 20b10 = stop after capture event 30b11 = stop after capture event 4Note: STOPVALUE is compared to mod4 counter, and when equal, the following two actions occur: (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited.Note: In one shot mode, further interrupt events are blocked until re-armed, once the number of events captured has been reached ." "0,1,2,3"
bitfld.long 0x00 16. "         CONT_ONESHT ,Continuous or one-shot mode control (applicable only in capture mode):0 = operate in continuous mode1 = operate in one-shot mode" "0,1"
textline "                              "
bitfld.long 0x00 15. " FREE       ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
bitfld.long 0x00 14. "         SOFT        ,Emulation control.0b00 =0b01 =0b1x =" "0,1"
textline "                              "
bitfld.long 0x00 9.--13. " EVTFLTPS   ,Event filter prescale select:0b00000 divide by 1 (that is, no prescale, by-pass the prescaler)0b00001 divide by 20b00010 divide by 40b00011 divide by 60b00100 divide by 80b00101 divide by 100b11110 divide by 600b11111 divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "        CAPLDEN     ,Enable loading of CAP(1-4) registers on a capture event:0 = disable CAP 1-4 register loads at capture event time1 = enable CAP(1-4) register loads at capture event time" "0,1"
textline "                              "
bitfld.long 0x00 7. " CTRRST4    ,Counter reset on capture event 4:0 = do not reset counter on capture event 4 (absolute time stamp)1 = reset counter after event 4 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 6. "         CAP4POL     ,Capture event 4 polarity select:0 = capture event 4 triggered on a rising edge (RE)1 = capture event 4 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 5. " CTRRST3    ,Counter reset on capture event 3:0 = do not reset counter on capture event 3 (absolute time stamp)1 = reset counter after event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 4. "         CAP3POL     ,Capture event 3 polarity select:0 = capture event 3 triggered on a rising edge (RE)1 = capture event 3 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 3. " CTRRST2    ,Counter reset on capture event 2:0 = do not reset counter on capture event 2 (absolute time stamp)1 = reset counter after event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 2. "         CAP2POL     ,Capture event 2 polarity select:0 = capture event 2 triggered on a rising edge (RE)1 = capture event 2 triggered on a falling edge (FE)" "0,1"
textline "                              "
bitfld.long 0x00 1. " CTRRST1    ,Counter reset on capture event 1:0 = do not reset counter on capture event 1 (absolute time stamp)1 = reset counter after event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x00 0. "         CAP1POL     ,Capture event 1 polarity select:0 = capture event 1 triggered on a rising edge (RE)1 = capture event 1 triggered on a falling edge (FE)" "0,1"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ECFLG_ECEINT,ECAP Interrupt Enable Register"
hexmask.long.byte 0x00 24.--31. 1. " FLAG_RESV0 ,"
bitfld.long 0x00 23. "        FLAG_CMPEQ  ,Compare equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 22. " FLAG_PRDEQ ,Period equal status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is only active in APWM mode." "0,1"
bitfld.long 0x00 21. "         FLAG_CNTOVF ,Counter overflow status flag:0 = indicates no event occurred1 = indicates the counter (Note: This flag is active in CAP and APWM mode." "0,1"
textline "                              "
bitfld.long 0x00 20. " FLAG_CEVT4 ,Capture event 4 status flag:0 = indicates no event occurred1 = indicates the fourth event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 19. "         FLAG_CEVT3  ,Capture event 3 status flag:0 = indicates no event occurred1 = indicates the third event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 18. " FLAG_CEVT2 ,Capture event 2 status flag:0 = indicates no event occurred1 = indicates the second event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
bitfld.long 0x00 17. "         FLAG_CEVT1  ,Capture event 1 status flag:0 = indicates no event occurred1 = indicates the first event occurred at ECAPx pinNote: This flag is only active in CAP mode." "0,1"
textline "                              "
bitfld.long 0x00 16. " FLAG_INT   ,Global interrupt status flag:0 = indicates no interrupt generated1 = indicates that an interrupt was generated from one of the following events" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "         EN_RESV1    ,"
textline "                              "
bitfld.long 0x00 7. " EN_CMPEQ   ,Compare equal interrupt enable:0 = disable compare equal as an interrupt source1 = enable compare equal as an interrupt source" "0,1"
bitfld.long 0x00 6. "         EN_PRDEQ    ,Period equal interrupt enable:0 = disable period equal as an interrupt source1 = enable period equal as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 5. " EN_CNTOVF  ,Counter overflow interrupt enable:0 = disable counter overflow as an interrupt source1 = enable counter overflow as an interrupt source" "0,1"
bitfld.long 0x00 4. "         EN_CEVT4    ,Capture event 4 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 3. " EN_CEVT3   ,Capture event 3 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 2. "         EN_CEVT2    ,Capture event 2 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
textline "                              "
bitfld.long 0x00 1. " EN_CEVT1   ,Capture event 1 interrupt enable:0 = disable capture event 1 as an interrupt source1 = enable capture event 1 as an interrupt source" "0,1"
bitfld.long 0x00 0. "         EN_RESV0    ," "0,1"
group.long 0x30++0x3
line.long 0x00 "ICSSG_ECCLR,ECAP Interrupt Clear Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV0      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Compare equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Period equal status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Counter overflow status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Capture event 4 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Capture event 3 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Capture event 2 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Capture event 1 status flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the status flag condition" "0,1"
textline "                              "
bitfld.long 0x00 0. " INT        ,Global interrupt clear flag:0 = Writing a 0 has no effect. Always reads back a 0.1 = Writing a 1 clears the clear flag and enable further interrupts to be generated if any of the clear flags are set to 1" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_ECFRC,ECAP Interrupt Forcing Register"
hexmask.long.byte 0x00 8.--15. 1. " RESV1      ,"
bitfld.long 0x00 7. "        CMPEQ       ,Force compare equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CMPEQ flag bit" "0,1"
textline "                              "
bitfld.long 0x00 6. " PRDEQ      ,Force period equal:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the PRDEQ flag bit" "0,1"
bitfld.long 0x00 5. "         CNTOVF      ,Force counter overflow:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CNTOVF flag bit" "0,1"
textline "                              "
bitfld.long 0x00 4. " CEVT4      ,Force capture event 4:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT4 flag bit" "0,1"
bitfld.long 0x00 3. "         CEVT3       ,Force capture event 3:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT3 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 2. " CEVT2      ,Force capture event 2:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT2 flag bit" "0,1"
bitfld.long 0x00 1. "         CEVT1       ,Force capture event 1:0 = Writing of 0 is ignored. Always reads back a 0.1 = Writing a 1 sets the the CEVT1 flag bit" "0,1"
textline "                              "
bitfld.long 0x00 0. " RESV0      ," "0,1"
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_PID,ECAP Peripheral Id Register"
hexmask.long 0x00 0.--31. 1. " REVID      ,TI internal data."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_ECC_AGGR"
tree "PRU_ICSSG2_ECC_AGGR"
base eahb:0xBF02000
width 27.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REV,Revision parameters"
bitfld.long 0x00 30.--31. " SCHEME                       ,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "     BU                           ,bu" "0,1,2,3"
textline "                                    "
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID                    ,Module ID"
bitfld.long 0x00 11.--15. "  REVRTL                       ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                    "
bitfld.long 0x00 8.--10. " REVMAJ                       ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "     CUSTOM                       ,Custom version" "0,1,2,3"
textline "                                    "
bitfld.long 0x00 0.--5. " REVMIN                       ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_VECTOR,ECC Vector Register"
in
textline "                                    "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_STAT,Misc Status"
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS                     ,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x3
line.long 0x00 "ICSSG_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0xC0++0x3
hide.long 0x00 "ICSSG_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x13C++0x3
line.long 0x00 "ICSSG_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. " EOI_WR                       ,EOI Register" "0,1"
group.long 0x140++0x3
line.long 0x00 "ICSSG_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_PEND       ,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_PEND                 ,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_PEND          ,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_PEND               ,Interrupt Pending Status for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_PEND               ,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x3
line.long 0x00 "ICSSG_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. " PR1_RTU1_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
bitfld.long 0x00 5. "     PR1_RTU0_IRAM_ECC_ENABLE_SET ,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
textline "                                    "
bitfld.long 0x00 4. " PR1_RAM_ENABLE_SET           ,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "     PR1_PDSP1_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
textline "                                    "
bitfld.long 0x00 2. " PR1_PDSP0_IRAM_ENABLE_SET    ,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "     PR1_DRAM1_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
textline "                                    "
bitfld.long 0x00 0. " PR1_DRAM0_ENABLE_SET         ,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
hgroup.long 0x1C0++0x3
hide.long 0x00 "ICSSG_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
in
textline "                                    "
group.long 0x200++0x3
line.long 0x00 "ICSSG_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. " TIMEOUT                      ,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "     PARITY                       ,interrupt enable set for parity errors" "0,1"
hgroup.long 0x204++0x3
hide.long 0x00 "ICSSG_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
in
textline "                                    "
group.long 0x208++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status set for parity errors" "0,1,2,3"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x00 2.--3. " TIMEOUT                      ,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x00 0.--1. "     PARITY                       ,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_IEP0"
tree "PRU_ICSSG2_IEP0"
base eaxi:0xB22E000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree "PRU_ICSSG2_IEP1"
base eaxi:0xB22F000
width 29.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. " CMP_INC         ,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "      DEFAULT_INC     ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 0. " CNT_ENABLE      ,Counter enable." "0,1"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_GLOBAL_STATUS_REG,Status Register"
in
textline "                                      "
group.long 0x8++0x3
line.long 0x00 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT      ,"
group.long 0xC++0x3
line.long 0x00 "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
hexmask.long 0x00 0.--31. 1. " SLOW_COMPEN_CNT ,Slow compensation counter."
group.long 0x10++0x3
line.long 0x00 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
hexmask.long 0x00 0.--31. 1. " COUNT_LO        ,64-bit count value (lower 32-bits)."
group.long 0x14++0x3
line.long 0x00 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
hexmask.long 0x00 0.--31. 1. " COUNT_HI        ,64-bit count value (upper 32-bits)."
group.long 0x18++0x3
line.long 0x00 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x00 18.--23. " EXT_CAP_EN      ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 10.--17. 1. "        CAP_ASYNC_EN    ,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable."
textline "                                      "
hexmask.long.word 0x00 0.--9. 1. " CAP_EN          ,"
rgroup.long 0x1C++0x3
line.long 0x00 "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x00 16.--23. 1. " CAP_RAW         ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]."
hexmask.long.word 0x00 0.--10. 1. "        CAP_VALID       ,"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x2C++0x3
line.long 0x00 "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x30++0x3
line.long 0x00 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x34++0x3
line.long 0x00 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x40++0x3
line.long 0x00 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x44++0x3
line.long 0x00 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,Value captured for CAPR<i> (fall) event, where i = 0 to 5. Lower 32-bits."
rgroup.long 0x4C++0x3
line.long 0x00 "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,Value captured for CAPR<i> (rise) event, where i = 0 to 5. Upper 32-bits."
rgroup.long 0x50++0x3
line.long 0x00 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,Value captured for CAPR6 event. Lower 32-bits."
rgroup.long 0x54++0x3
line.long 0x00 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,Value captured for CAPR6 event. Upper 32-bits."
rgroup.long 0x58++0x3
line.long 0x00 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x5C++0x3
line.long 0x00 "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,Value captured for CAPF6 (fall) event. Lower 32-bits."
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,Value captured for CAPR7 (rise) event. Lower 32-bits."
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,Value captured for CAPR7 (rise) event. Upper 32-bits."
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,Value captured for CAPF7 (fall) event. Lower 32-bits."
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,Value captured for CAPF7 (fall) event. Upper 32-bits."
group.long 0x70++0x3
line.long 0x00 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x00 17. " SHADOW_EN       ," "0,1"
hexmask.long.word 0x00 1.--16. 1. "         CMP_EN          ,Enable bits for each of the compare registers"
textline "                                      "
bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter" "0,1"
hgroup.long 0x74++0x3
hide.long 0x00 "ICSSG_CMP_STATUS_REG,Compare Status Register"
in
textline "                                      "
group.long 0x78++0x3
line.long 0x00 "ICSSG_CMP0_REG0,Compare 0 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP0_0          ,Compare 0 low value"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_CMP0_REG1,Compare 0 High Register"
hexmask.long 0x00 0.--31. 1. " CMP0_1          ,Compare 0 high value"
group.long 0x80++0x3
line.long 0x00 "ICSSG_CMP1_REG0,Compare 1 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP1_0          ,Compare 1 low value"
group.long 0x84++0x3
line.long 0x00 "ICSSG_CMP1_REG1,Compare 1 High Register"
hexmask.long 0x00 0.--31. 1. " CMP1_1          ,Compare 1 high value"
group.long 0x88++0x3
line.long 0x00 "ICSSG_CMP2_REG0,Compare 2 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP2_0          ,Compare 2 low value"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_CMP2_REG1,Compare 2 High Register"
hexmask.long 0x00 0.--31. 1. " CMP2_1          ,Compare 2 high value"
group.long 0x90++0x3
line.long 0x00 "ICSSG_CMP3_REG0,Compare 3 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP3_0          ,Compare 3 low value"
group.long 0x94++0x3
line.long 0x00 "ICSSG_CMP3_REG1,Compare 3 High Register"
hexmask.long 0x00 0.--31. 1. " CMP3_1          ,Compare 3 high value"
group.long 0x98++0x3
line.long 0x00 "ICSSG_CMP4_REG0,Compare 4 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP4_0          ,Compare 4 low value"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_CMP4_REG1,Compare 4 High Register"
hexmask.long 0x00 0.--31. 1. " CMP4_1          ,Compare 4 high value"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_CMP5_REG0,Compare 5 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP5_0          ,Compare 5 low value"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_CMP5_REG1,Compare 5 High Register"
hexmask.long 0x00 0.--31. 1. " CMP5_1          ,Compare 5 high value"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_CMP6_REG0,Compare 6 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP6_0          ,Compare 6 low value"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_CMP6_REG1,Compare 6 High Register"
hexmask.long 0x00 0.--31. 1. " CMP6_1          ,Compare 6 high value"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_CMP7_REG0,Compare 7 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP7_0          ,Compare 7 low value"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_CMP7_REG1,Compare 7 High Register"
hexmask.long 0x00 0.--31. 1. " CMP7_1          ,Compare 7 high value"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG0     ,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG0         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xBC++0x3
line.long 0x00 "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1"
hexmask.long.word 0x00 16.--31. 1. " RX_MIN_IPG1     ,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low."
hexmask.long.word 0x00 0.--15. 1. "      RX_IPG1         ,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low."
group.long 0xC0++0x3
line.long 0x00 "ICSSG_CMP8_REG0,Compare 8 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP8_0          ,Compare 8 low value"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_CMP8_REG1,Compare 8 High Register"
hexmask.long 0x00 0.--31. 1. " CMP8_1          ,Reset value (upper 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_CMP9_REG0,Compare 9 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP9_0          ,Compare 9 low value"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_CMP9_REG1,Compare 9 High Register"
hexmask.long 0x00 0.--31. 1. " CMP9_1          ,Compare 9 high value"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_CMP10_REG0,Compare 10 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP10_0         ,Compare 10 low value"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_CMP10_REG1,Compare 10 High Register"
hexmask.long 0x00 0.--31. 1. " CMP10_1         ,Compare 10 high value"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_CMP11_REG0,Compare 11 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP11_0         ,Compare 11 low value"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_CMP11_REG1,Compare 11 High Register"
hexmask.long 0x00 0.--31. 1. " CMP11_1         ,Compare 11 high value"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_CMP12_REG0,Compare 12 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP12_0         ,Compare 12 low value"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_CMP12_REG1,Compare 12 High Register"
hexmask.long 0x00 0.--31. 1. " CMP12_1         ,Compare 12 high value"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_CMP13_REG0,Compare 13 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP13_0         ,Compare 13 low value"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_CMP13_REG1,Compare 13 High Register"
hexmask.long 0x00 0.--31. 1. " CMP13_1         ,Compare 13 high value"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_CMP14_REG0,Compare 14 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP14_0         ,Compare 14 low value"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_CMP14_REG1,Compare 14 High Register"
hexmask.long 0x00 0.--31. 1. " CMP14_1         ,Compare 14 high value"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_CMP15_REG0,Compare 15 Low Register"
hexmask.long 0x00 0.--31. 1. " CMP15_0         ,Compare 15 low value"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_CMP15_REG1,Compare 15 High Register"
hexmask.long 0x00 0.--31. 1. " CMP15_1         ,Compare 15 high value"
group.long 0x100++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_0     ,Reset value (lower 32-bits). This register enables SW to define the reset state of the Master Counter, which can be reset by the following events (if enabled):"
group.long 0x104++0x3
line.long 0x00 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits)"
hexmask.long 0x00 0.--31. 1. " RESET_VAL_1     ,This enables SW to define the reset state of the Master counter when it gets reset do to the following 3 possible events if enabled: CMP0 event; eHRPWM0_SYNCO event; eHRPWM3_SYNCO event. It should be in increments of the DEFAULT_INC, default state is 5 For example, 0000_000Ah"
hgroup.long 0x108++0x3
hide.long 0x00 "ICSSG_PWM_REG,PWM Sync Out Register"
in
textline "                                      "
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00"
hexmask.long 0x00 0.--31. 1. " CAPR0_0         ,"
rgroup.long 0x110++0x3
line.long 0x00 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10"
hexmask.long 0x00 0.--31. 1. " CAPR0_1         ,"
rgroup.long 0x114++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01"
hexmask.long 0x00 0.--31. 1. " CAPR1_0         ,"
rgroup.long 0x118++0x3
line.long 0x00 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11"
hexmask.long 0x00 0.--31. 1. " CAPR1_1         ,"
rgroup.long 0x11C++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02"
hexmask.long 0x00 0.--31. 1. " CAPR2_0         ,"
rgroup.long 0x120++0x3
line.long 0x00 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12"
hexmask.long 0x00 0.--31. 1. " CAPR2_1         ,"
rgroup.long 0x124++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03"
hexmask.long 0x00 0.--31. 1. " CAPR3_0         ,"
rgroup.long 0x128++0x3
line.long 0x00 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13"
hexmask.long 0x00 0.--31. 1. " CAPR3_1         ,"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04"
hexmask.long 0x00 0.--31. 1. " CAPR4_0         ,"
rgroup.long 0x130++0x3
line.long 0x00 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14"
hexmask.long 0x00 0.--31. 1. " CAPR4_1         ,"
rgroup.long 0x134++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05"
hexmask.long 0x00 0.--31. 1. " CAPR5_0         ,"
rgroup.long 0x138++0x3
line.long 0x00 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15"
hexmask.long 0x00 0.--31. 1. " CAPR5_1         ,"
rgroup.long 0x13C++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06"
hexmask.long 0x00 0.--31. 1. " CAPR6_0         ,"
rgroup.long 0x140++0x3
line.long 0x00 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16"
hexmask.long 0x00 0.--31. 1. " CAPR6_1         ,"
rgroup.long 0x144++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06"
hexmask.long 0x00 0.--31. 1. " CAPF6_0         ,"
rgroup.long 0x148++0x3
line.long 0x00 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16"
hexmask.long 0x00 0.--31. 1. " CAPF6_1         ,"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07"
hexmask.long 0x00 0.--31. 1. " CAPR7_0         ,"
rgroup.long 0x150++0x3
line.long 0x00 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17"
hexmask.long 0x00 0.--31. 1. " CAPR7_1         ,"
rgroup.long 0x154++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07"
hexmask.long 0x00 0.--31. 1. " CAPF7_0         ,"
rgroup.long 0x158++0x3
line.long 0x00 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17"
hexmask.long 0x00 0.--31. 1. " CAPF7_1         ,"
group.long 0x180++0x3
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. " SYNC1_IND_EN    ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0." "0,1"
bitfld.long 0x00 7. "         SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 6. " SYNC1_ACK_EN    ,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "         SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
textline "                                      "
bitfld.long 0x00 4. " SYNC0_ACK_EN    ,SYNC0 acknowledgement mode enable" "0,1"
bitfld.long 0x00 2. "         SYNC1_EN        ,SYNC1 generation enable" "0,1"
textline "                                      "
bitfld.long 0x00 1. " SYNC0_EN        ,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "         SYNC_EN         ,SYNC generation enable" "0,1"
rgroup.long 0x184++0x3
line.long 0x00 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x00 1. " FIRST_SYNC1     ,SYNC1 First Event status" "0,1"
bitfld.long 0x00 0. "         FIRST_SYNC0     ,SYNC0 First Event status" "0,1"
rgroup.long 0x188++0x3
line.long 0x00 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x00 0. " SYNC0_PEND      ,SYNC0 pending state" "0,1"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x00 0. " SYNC1_PEND      ,SYNC1 pending state" "0,1"
group.long 0x190++0x3
line.long 0x00 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_HPW        ,Defines the number of clock cycles SYNC0/1 will be high."
group.long 0x194++0x3
line.long 0x00 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC0_PERIOD    ,Defines the period between the rising edges of SYNC0."
group.long 0x198++0x3
line.long 0x00 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
hexmask.long 0x00 0.--31. 1. " SYNC1_DELAY     ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1."
group.long 0x19C++0x3
line.long 0x00 "ICSSG_SYNC_START_REG,Sync Start Configure Register"
hexmask.long 0x00 0.--31. 1. " SYNC_START      ,Defines the start time after the activation event."
group.long 0x200++0x3
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. " PRE_DIV         ,Defines the number of ICSS_IEP_CLK cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if ICSS_IEP_CLK is 200 MHz."
group.long 0x204++0x3
line.long 0x00 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PDI_WD_TIME     ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRUSS_IEP_WD_PREDIV[15-0] PRE_DIV is set to 100us, then the value 0x03e8 (or 1000) provides a rate of 100ms."
group.long 0x208++0x3
line.long 0x00 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x00 0.--15. 1. " PD_WD_TIME      ,Defines the number of WD ticks (or increments) for PD WD, that is, the number of WD increments."
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x00 16. " PDI_WD_STAT     ,WD PDI status." "0,1"
bitfld.long 0x00 0. "         PD_WD_STAT      ,WD PD status (triggered by Sync Mangers status)." "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x00 8.--15. 1. " PD_EXP_CNT      ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh."
hexmask.long.byte 0x00 0.--7. 1. "        PDI_EXP_CNT     ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh."
group.long 0x214++0x3
line.long 0x00 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x00 16. " PDI_WD_EN       ,Watchdog PDI" "0,1"
bitfld.long 0x00 0. "         PD_WD_EN        ,Watchdog PD" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. " OUT_MODE        ,Defines events that triggers data out to be updated." "0,1,2,3"
bitfld.long 0x00 4.--5. "         IN_MODE         ,Defines event that triggers data in to be sampled" "0,1,2,3"
textline "                                      "
bitfld.long 0x00 3. " WD_MODE         ,Defines Watchdog behavior" "0,1"
bitfld.long 0x00 2. "         BIDI_MODE       ,Defines the digital input/output direction. NOTE THAT DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1"
textline "                                      "
bitfld.long 0x00 1. " OUTVALID_MODE   ,Defines the outvalid mode behavior." "0,1"
bitfld.long 0x00 0. "         OUTVALID_POL    ,Defines OUTVALID polarity" "0,1"
rgroup.long 0x304++0x3
line.long 0x00 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
hexmask.long 0x00 0.--31. 1. " DIGIO_STAT      ,Reserved"
rgroup.long 0x308++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN         ,Data input. Digital inputs can be configured to be sampled in four ways."
rgroup.long 0x30C++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
hexmask.long 0x00 0.--31. 1. " DATA_IN_RAW     ,Data input which direct sample of PR<k>_EDIO_DATA[0:31]. Only PR<k>_EDIO_DATA[0:3] are exported to device pins in this device."
group.long 0x310++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
hexmask.long 0x00 0.--31. 1. " DATA_OUT        ,Data output. Digital outputs can be configured to be updated in four ways."
group.long 0x314++0x3
line.long 0x00 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0]"
hexmask.long 0x00 0.--31. 1. " DATA_OUT_EN     ,Data input which controls tri-state of PR<k>_EDIO_DATA[0:3]"
group.long 0x318++0x3
line.long 0x00 "ICSSG_DIGIO_EXP_REG,DIGIO, Defines which RX_EOF is used"
bitfld.long 0x00 13. " EOF_SEL         ,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x00 12. "         SOF_SEL         ,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
textline "                                      "
bitfld.long 0x00 8.--11. " SOF_DLY         ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "        OUTVALID_DLY    ,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                      "
bitfld.long 0x00 2. " SW_OUTVALID     ,PR<k>_EDIO_OUTVALID = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1"
bitfld.long 0x00 1. "         OUTVALID_OVR_EN ,Software override enable" "0,1"
textline "                                      "
bitfld.long 0x00 0. " SW_DATA_OUT_UP  ,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1." "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_INTC"
tree "PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV"
base eaxi:0xB220000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_REVISION_REG,Revision Register"
bitfld.long 0x00 30.--31. " REV_SCHEME            ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "     REV_MODULE     ,Module ID"
textline "                                          "
bitfld.long 0x00 11.--15. " REV_RTL               ,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "    REV_MAJOR      ,Major revision" "0,1,2,3,4,5,6,7"
textline "                                          "
bitfld.long 0x00 6.--7. " REV_CUSTOM            ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "     REV_MINOR      ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4++0x3
line.long 0x00 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x00 4. " PRIORITY_HOLD_MODE    ,Priority Holding Mode" "0,1"
bitfld.long 0x00 2.--3. "     NEST_MODE      ,Nesting Mode" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 1. " WAKEUP_MODE           ,Wakeup mode enable" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_GLOBAL_ENABLE_HINT_REG,Global Host Int Enable Register"
bitfld.long 0x00 0. " ENABLE_HINT_ANY       ,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_GLB_NEST_LEVEL_REG,Global Nesting Level Register"
bitfld.long 0x00 31. " GLB_NEST_AUTO_OVR     ,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     GLB_NEST_LEVEL ,Global Nesting Level"
wgroup.long 0x20++0x3
line.long 0x00 "ICSSG_STATUS_SET_INDEX_REG,Status Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_SET_INDEX      ,Status Set Index Register (write index to set status of)"
wgroup.long 0x24++0x3
line.long 0x00 "ICSSG_STATUS_CLR_INDEX_REG,Status Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " STATUS_CLR_INDEX      ,Status Clear Index Register (write index to clear status of)"
group.long 0x28++0x3
line.long 0x00 "ICSSG_ENABLE_SET_INDEX_REG,Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_SET_INDEX      ,Enable Set Index Register (write index to set enable of)"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_INDEX_REG,Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " ENABLE_CLR_INDEX      ,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_SET_INDEX_REG,Host Int Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Enable set for Host Interrupts"
group.long 0x38++0x3
line.long 0x00 "ICSSG_HINT_ENABLE_CLR_INDEX_REG,Host Int Enable Clear Index Register"
hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Enable clear for Host Interrupts"
rgroup.long 0x80++0x3
line.long 0x00 "ICSSG_GLB_PRI_INTR_REG,Global Prioritized Interrupt Register"
bitfld.long 0x00 31. " GLB_NONE              ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     GLB_PRI_INTR   ,Prioritized Interrupt"
group.long 0x200++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG0,Raw Status Register 0"
bitfld.long 0x00 31. " RAW_STATUS_31         ,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_30  ,Raw Status (write 1 to set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_29         ,Raw Status (write 1 to set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_28  ,Raw Status (write 1 to set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_27         ,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_26  ,Raw Status (write 1 to set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_25         ,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_24  ,Raw Status (write 1 to set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_23         ,Raw Status (write 1 to set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_22  ,Raw Status (write 1 to set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_21         ,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_20  ,Raw Status (write 1 to set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_19         ,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_18  ,Raw Status (write 1 to set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_17         ,Raw Status (write 1 to set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_16  ,Raw Status (write 1 to set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_15         ,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_14  ,Raw Status (write 1 to set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_13         ,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_12  ,Raw Status (write 1 to set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_11         ,Raw Status (write 1 to set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_10  ,Raw Status (write 1 to set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_9          ,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_8   ,Raw Status (write 1 to set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_7          ,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_6   ,Raw Status (write 1 to set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_5          ,Raw Status (write 1 to set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_4   ,Raw Status (write 1 to set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_3          ,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_2   ,Raw Status (write 1 to set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_1          ,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_0   ,Raw Status (write 1 to set) for intr_in[0]" "0,1"
group.long 0x204++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG1,Raw Status Register 1"
bitfld.long 0x00 31. " RAW_STATUS_63         ,Raw Status (write 1 to set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_62  ,Raw Status (write 1 to set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_61         ,Raw Status (write 1 to set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_60  ,Raw Status (write 1 to set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_59         ,Raw Status (write 1 to set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_58  ,Raw Status (write 1 to set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_57         ,Raw Status (write 1 to set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_56  ,Raw Status (write 1 to set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_55         ,Raw Status (write 1 to set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_54  ,Raw Status (write 1 to set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_53         ,Raw Status (write 1 to set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_52  ,Raw Status (write 1 to set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_51         ,Raw Status (write 1 to set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_50  ,Raw Status (write 1 to set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_49         ,Raw Status (write 1 to set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_48  ,Raw Status (write 1 to set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_47         ,Raw Status (write 1 to set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_46  ,Raw Status (write 1 to set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_45         ,Raw Status (write 1 to set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_44  ,Raw Status (write 1 to set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_43         ,Raw Status (write 1 to set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_42  ,Raw Status (write 1 to set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_41         ,Raw Status (write 1 to set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_40  ,Raw Status (write 1 to set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_39         ,Raw Status (write 1 to set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_38  ,Raw Status (write 1 to set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_37         ,Raw Status (write 1 to set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_36  ,Raw Status (write 1 to set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_35         ,Raw Status (write 1 to set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_34  ,Raw Status (write 1 to set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_33         ,Raw Status (write 1 to set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_32  ,Raw Status (write 1 to set) for intr_in[32]" "0,1"
group.long 0x208++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG2,Raw Status Register 2"
bitfld.long 0x00 31. " RAW_STATUS_95         ,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_94  ,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_93         ,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_92  ,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_91         ,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_90  ,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_89         ,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_88  ,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_87         ,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_86  ,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_85         ,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_84  ,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_83         ,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_82  ,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_81         ,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_80  ,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_79         ,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_78  ,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_77         ,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_76  ,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_75         ,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_74  ,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_73         ,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_72  ,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_71         ,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_70  ,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_69         ,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_68  ,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_67         ,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_66  ,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_65         ,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_64  ,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
group.long 0x20C++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG3,Raw Status Register 3"
bitfld.long 0x00 31. " RAW_STATUS_127        ,Raw Status (write 1 to set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_126 ,Raw Status (write 1 to set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_125        ,Raw Status (write 1 to set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_124 ,Raw Status (write 1 to set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_123        ,Raw Status (write 1 to set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_122 ,Raw Status (write 1 to set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_121        ,Raw Status (write 1 to set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_120 ,Raw Status (write 1 to set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_119        ,Raw Status (write 1 to set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_118 ,Raw Status (write 1 to set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_117        ,Raw Status (write 1 to set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_116 ,Raw Status (write 1 to set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_115        ,Raw Status (write 1 to set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_114 ,Raw Status (write 1 to set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_113        ,Raw Status (write 1 to set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_112 ,Raw Status (write 1 to set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_111        ,Raw Status (write 1 to set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_110 ,Raw Status (write 1 to set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_109        ,Raw Status (write 1 to set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_108 ,Raw Status (write 1 to set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_107        ,Raw Status (write 1 to set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_106 ,Raw Status (write 1 to set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_105        ,Raw Status (write 1 to set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_104 ,Raw Status (write 1 to set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_103        ,Raw Status (write 1 to set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_102 ,Raw Status (write 1 to set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_101        ,Raw Status (write 1 to set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_100 ,Raw Status (write 1 to set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_99         ,Raw Status (write 1 to set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_98  ,Raw Status (write 1 to set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_97         ,Raw Status (write 1 to set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_96  ,Raw Status (write 1 to set) for slv_events_in[32]" "0,1"
group.long 0x210++0x3
line.long 0x00 "ICSSG_RAW_STATUS_REG4,Raw Status Register 4"
bitfld.long 0x00 31. " RAW_STATUS_159        ,Raw Status (write 1 to set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     RAW_STATUS_158 ,Raw Status (write 1 to set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " RAW_STATUS_157        ,Raw Status (write 1 to set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     RAW_STATUS_156 ,Raw Status (write 1 to set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " RAW_STATUS_155        ,Raw Status (write 1 to set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     RAW_STATUS_154 ,Raw Status (write 1 to set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " RAW_STATUS_153        ,Raw Status (write 1 to set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     RAW_STATUS_152 ,Raw Status (write 1 to set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " RAW_STATUS_151        ,Raw Status (write 1 to set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     RAW_STATUS_150 ,Raw Status (write 1 to set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " RAW_STATUS_149        ,Raw Status (write 1 to set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     RAW_STATUS_148 ,Raw Status (write 1 to set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " RAW_STATUS_147        ,Raw Status (write 1 to set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     RAW_STATUS_146 ,Raw Status (write 1 to set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " RAW_STATUS_145        ,Raw Status (write 1 to set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     RAW_STATUS_144 ,Raw Status (write 1 to set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " RAW_STATUS_143        ,Raw Status (write 1 to set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     RAW_STATUS_142 ,Raw Status (write 1 to set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " RAW_STATUS_141        ,Raw Status (write 1 to set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     RAW_STATUS_140 ,Raw Status (write 1 to set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " RAW_STATUS_139        ,Raw Status (write 1 to set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     RAW_STATUS_138 ,Raw Status (write 1 to set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " RAW_STATUS_137        ,Raw Status (write 1 to set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     RAW_STATUS_136 ,Raw Status (write 1 to set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " RAW_STATUS_135        ,Raw Status (write 1 to set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     RAW_STATUS_134 ,Raw Status (write 1 to set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " RAW_STATUS_133        ,Raw Status (write 1 to set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     RAW_STATUS_132 ,Raw Status (write 1 to set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " RAW_STATUS_131        ,Raw Status (write 1 to set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     RAW_STATUS_130 ,Raw Status (write 1 to set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " RAW_STATUS_129        ,Raw Status (write 1 to set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     RAW_STATUS_128 ,Raw Status (write 1 to set) for slv_events_in[64]" "0,1"
group.long 0x280++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG0,Enabled Status Register 0"
bitfld.long 0x00 31. " ENA_STATUS_31         ,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_30  ,Enabled Status for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_29         ,Enabled Status for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_28  ,Enabled Status for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_27         ,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_26  ,Enabled Status for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_25         ,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_24  ,Enabled Status for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_23         ,Enabled Status for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_22  ,Enabled Status for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_21         ,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_20  ,Enabled Status for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_19         ,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_18  ,Enabled Status for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_17         ,Enabled Status for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_16  ,Enabled Status for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_15         ,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_14  ,Enabled Status for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_13         ,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_12  ,Enabled Status for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_11         ,Enabled Status for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_10  ,Enabled Status for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_9          ,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_8   ,Enabled Status for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_7          ,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_6   ,Enabled Status for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_5          ,Enabled Status for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_4   ,Enabled Status for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_3          ,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_2   ,Enabled Status for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_1          ,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_0   ,Enabled Status for intr_in[0]" "0,1"
group.long 0x284++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG1,Enabled Status Register 1"
bitfld.long 0x00 31. " ENA_STATUS_63         ,Enabled Status for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_62  ,Enabled Status for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_61         ,Enabled Status for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_60  ,Enabled Status for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_59         ,Enabled Status for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_58  ,Enabled Status for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_57         ,Enabled Status for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_56  ,Enabled Status for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_55         ,Enabled Status for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_54  ,Enabled Status for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_53         ,Enabled Status for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_52  ,Enabled Status for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_51         ,Enabled Status for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_50  ,Enabled Status for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_49         ,Enabled Status for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_48  ,Enabled Status for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_47         ,Enabled Status for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_46  ,Enabled Status for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_45         ,Enabled Status for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_44  ,Enabled Status for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_43         ,Enabled Status for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_42  ,Enabled Status for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_41         ,Enabled Status for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_40  ,Enabled Status for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_39         ,Enabled Status for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_38  ,Enabled Status for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_37         ,Enabled Status for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_36  ,Enabled Status for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_35         ,Enabled Status for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_34  ,Enabled Status for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_33         ,Enabled Status for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_32  ,Enabled Status for intr_in[32]" "0,1"
group.long 0x288++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG2,Enabled Status Register 2"
bitfld.long 0x00 31. " ENA_STATUS_95         ,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_94  ,Enabled Status for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_93         ,Enabled Status for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_92  ,Enabled Status for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_91         ,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_90  ,Enabled Status for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_89         ,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_88  ,Enabled Status for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_87         ,Enabled Status for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_86  ,Enabled Status for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_85         ,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_84  ,Enabled Status for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_83         ,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_82  ,Enabled Status for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_81         ,Enabled Status for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_80  ,Enabled Status for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_79         ,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_78  ,Enabled Status for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_77         ,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_76  ,Enabled Status for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_75         ,Enabled Status for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_74  ,Enabled Status for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_73         ,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_72  ,Enabled Status for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_71         ,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_70  ,Enabled Status for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_69         ,Enabled Status for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_68  ,Enabled Status for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_67         ,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_66  ,Enabled Status for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_65         ,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_64  ,Enabled Status for slv_events_in[0]" "0,1"
group.long 0x28C++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG3,Enabled Status Register 3"
bitfld.long 0x00 31. " ENA_STATUS_127        ,Enabled Status for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_126 ,Enabled Status for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_125        ,Enabled Status for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_124 ,Enabled Status for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_123        ,Enabled Status for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_122 ,Enabled Status for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_121        ,Enabled Status for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_120 ,Enabled Status for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_119        ,Enabled Status for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_118 ,Enabled Status for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_117        ,Enabled Status for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_116 ,Enabled Status for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_115        ,Enabled Status for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_114 ,Enabled Status for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_113        ,Enabled Status for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_112 ,Enabled Status for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_111        ,Enabled Status for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_110 ,Enabled Status for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_109        ,Enabled Status for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_108 ,Enabled Status for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_107        ,Enabled Status for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_106 ,Enabled Status for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_105        ,Enabled Status for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_104 ,Enabled Status for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_103        ,Enabled Status for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_102 ,Enabled Status for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_101        ,Enabled Status for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_100 ,Enabled Status for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_99         ,Enabled Status for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_98  ,Enabled Status for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_97         ,Enabled Status for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_96  ,Enabled Status for slv_events_in[32]" "0,1"
group.long 0x290++0x3
line.long 0x00 "ICSSG_ENA_STATUS_REG4,Enabled Status Register 4"
bitfld.long 0x00 31. " ENA_STATUS_159        ,Enabled Status for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENA_STATUS_158 ,Enabled Status for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENA_STATUS_157        ,Enabled Status for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENA_STATUS_156 ,Enabled Status for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENA_STATUS_155        ,Enabled Status for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENA_STATUS_154 ,Enabled Status for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENA_STATUS_153        ,Enabled Status for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENA_STATUS_152 ,Enabled Status for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENA_STATUS_151        ,Enabled Status for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENA_STATUS_150 ,Enabled Status for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENA_STATUS_149        ,Enabled Status for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENA_STATUS_148 ,Enabled Status for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENA_STATUS_147        ,Enabled Status for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENA_STATUS_146 ,Enabled Status for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENA_STATUS_145        ,Enabled Status for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENA_STATUS_144 ,Enabled Status for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENA_STATUS_143        ,Enabled Status for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENA_STATUS_142 ,Enabled Status for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENA_STATUS_141        ,Enabled Status for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENA_STATUS_140 ,Enabled Status for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENA_STATUS_139        ,Enabled Status for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENA_STATUS_138 ,Enabled Status for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENA_STATUS_137        ,Enabled Status for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENA_STATUS_136 ,Enabled Status for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENA_STATUS_135        ,Enabled Status for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENA_STATUS_134 ,Enabled Status for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENA_STATUS_133        ,Enabled Status for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENA_STATUS_132 ,Enabled Status for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENA_STATUS_131        ,Enabled Status for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENA_STATUS_130 ,Enabled Status for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENA_STATUS_129        ,Enabled Status for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENA_STATUS_128 ,Enabled Status for slv_events_in[64]" "0,1"
group.long 0x300++0x3
line.long 0x00 "ICSSG_ENABLE_REG0,Enable Register 0"
bitfld.long 0x00 31. " ENABLE_31             ,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30      ,Enable (set) for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29             ,Enable (set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28      ,Enable (set) for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27             ,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26      ,Enable (set) for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25             ,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24      ,Enable (set) for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23             ,Enable (set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22      ,Enable (set) for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21             ,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20      ,Enable (set) for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19             ,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18      ,Enable (set) for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17             ,Enable (set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16      ,Enable (set) for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15             ,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14      ,Enable (set) for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13             ,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12      ,Enable (set) for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11             ,Enable (set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10      ,Enable (set) for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9              ,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8       ,Enable (set) for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7              ,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6       ,Enable (set) for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5              ,Enable (set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4       ,Enable (set) for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3              ,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2       ,Enable (set) for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1              ,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0       ,Enable (set) for intr_in[0]" "0,1"
group.long 0x304++0x3
line.long 0x00 "ICSSG_ENABLE_REG1,Enable Register 1"
bitfld.long 0x00 31. " ENABLE_63             ,Enable (set) for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62      ,Enable (set) for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61             ,Enable (set) for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60      ,Enable (set) for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59             ,Enable (set) for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58      ,Enable (set) for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57             ,Enable (set) for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56      ,Enable (set) for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55             ,Enable (set) for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54      ,Enable (set) for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53             ,Enable (set) for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52      ,Enable (set) for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51             ,Enable (set) for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50      ,Enable (set) for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49             ,Enable (set) for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48      ,Enable (set) for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47             ,Enable (set) for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46      ,Enable (set) for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45             ,Enable (set) for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44      ,Enable (set) for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43             ,Enable (set) for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42      ,Enable (set) for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41             ,Enable (set) for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40      ,Enable (set) for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39             ,Enable (set) for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38      ,Enable (set) for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37             ,Enable (set) for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36      ,Enable (set) for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35             ,Enable (set) for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34      ,Enable (set) for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33             ,Enable (set) for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32      ,Enable (set) for intr_in[32]" "0,1"
group.long 0x308++0x3
line.long 0x00 "ICSSG_ENABLE_REG2,Enable Register 2"
bitfld.long 0x00 31. " ENABLE_95             ,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94      ,Enable (set) for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93             ,Enable (set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92      ,Enable (set) for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91             ,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90      ,Enable (set) for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89             ,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88      ,Enable (set) for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87             ,Enable (set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86      ,Enable (set) for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85             ,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84      ,Enable (set) for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83             ,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82      ,Enable (set) for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81             ,Enable (set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80      ,Enable (set) for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79             ,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78      ,Enable (set) for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77             ,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76      ,Enable (set) for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75             ,Enable (set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74      ,Enable (set) for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73             ,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72      ,Enable (set) for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71             ,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70      ,Enable (set) for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69             ,Enable (set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68      ,Enable (set) for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67             ,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66      ,Enable (set) for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65             ,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64      ,Enable (set) for slv_events_in[0]" "0,1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_ENABLE_REG3,Enable Register 3"
bitfld.long 0x00 31. " ENABLE_127            ,Enable (set) for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126     ,Enable (set) for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125            ,Enable (set) for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124     ,Enable (set) for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123            ,Enable (set) for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122     ,Enable (set) for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121            ,Enable (set) for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120     ,Enable (set) for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119            ,Enable (set) for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118     ,Enable (set) for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117            ,Enable (set) for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116     ,Enable (set) for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115            ,Enable (set) for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114     ,Enable (set) for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113            ,Enable (set) for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112     ,Enable (set) for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111            ,Enable (set) for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110     ,Enable (set) for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109            ,Enable (set) for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108     ,Enable (set) for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107            ,Enable (set) for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106     ,Enable (set) for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105            ,Enable (set) for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104     ,Enable (set) for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103            ,Enable (set) for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102     ,Enable (set) for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101            ,Enable (set) for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100     ,Enable (set) for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99             ,Enable (set) for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98      ,Enable (set) for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97             ,Enable (set) for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96      ,Enable (set) for slv_events_in[32]" "0,1"
group.long 0x310++0x3
line.long 0x00 "ICSSG_ENABLE_REG4,Enable Register 4"
bitfld.long 0x00 31. " ENABLE_159            ,Enable (set) for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158     ,Enable (set) for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157            ,Enable (set) for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156     ,Enable (set) for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155            ,Enable (set) for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154     ,Enable (set) for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153            ,Enable (set) for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152     ,Enable (set) for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151            ,Enable (set) for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150     ,Enable (set) for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149            ,Enable (set) for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148     ,Enable (set) for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147            ,Enable (set) for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146     ,Enable (set) for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145            ,Enable (set) for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144     ,Enable (set) for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143            ,Enable (set) for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142     ,Enable (set) for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141            ,Enable (set) for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140     ,Enable (set) for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139            ,Enable (set) for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138     ,Enable (set) for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137            ,Enable (set) for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136     ,Enable (set) for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135            ,Enable (set) for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134     ,Enable (set) for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133            ,Enable (set) for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132     ,Enable (set) for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131            ,Enable (set) for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130     ,Enable (set) for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129            ,Enable (set) for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128     ,Enable (set) for slv_events_in[64]" "0,1"
group.long 0x380++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG0,Enable Clear Register 0"
bitfld.long 0x00 31. " ENABLE_31_CLR         ,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_30_CLR  ,Enable clear for intr_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_29_CLR         ,Enable clear for intr_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_28_CLR  ,Enable clear for intr_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_27_CLR         ,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_26_CLR  ,Enable clear for intr_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_25_CLR         ,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_24_CLR  ,Enable clear for intr_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_23_CLR         ,Enable clear for intr_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_22_CLR  ,Enable clear for intr_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_21_CLR         ,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_20_CLR  ,Enable clear for intr_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_19_CLR         ,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_18_CLR  ,Enable clear for intr_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_17_CLR         ,Enable clear for intr_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_16_CLR  ,Enable clear for intr_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_15_CLR         ,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_14_CLR  ,Enable clear for intr_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_13_CLR         ,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_12_CLR  ,Enable clear for intr_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_11_CLR         ,Enable clear for intr_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_10_CLR  ,Enable clear for intr_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_9_CLR          ,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_8_CLR   ,Enable clear for intr_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_7_CLR          ,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_6_CLR   ,Enable clear for intr_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_5_CLR          ,Enable clear for intr_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_4_CLR   ,Enable clear for intr_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_3_CLR          ,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_2_CLR   ,Enable clear for intr_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_1_CLR          ,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_0_CLR   ,Enable clear for intr_in[0]" "0,1"
group.long 0x384++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG1,Enable Clear Register 1"
bitfld.long 0x00 31. " ENABLE_63_CLR         ,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_62_CLR  ,Enable clear for intr_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_61_CLR         ,Enable clear for intr_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_60_CLR  ,Enable clear for intr_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_59_CLR         ,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_58_CLR  ,Enable clear for intr_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_57_CLR         ,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_56_CLR  ,Enable clear for intr_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_55_CLR         ,Enable clear for intr_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_54_CLR  ,Enable clear for intr_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_53_CLR         ,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_52_CLR  ,Enable clear for intr_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_51_CLR         ,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_50_CLR  ,Enable clear for intr_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_49_CLR         ,Enable clear for intr_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_48_CLR  ,Enable clear for intr_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_47_CLR         ,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_46_CLR  ,Enable clear for intr_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_45_CLR         ,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_44_CLR  ,Enable clear for intr_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_43_CLR         ,Enable clear for intr_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_42_CLR  ,Enable clear for intr_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_41_CLR         ,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_40_CLR  ,Enable clear for intr_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_39_CLR         ,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_38_CLR  ,Enable clear for intr_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_37_CLR         ,Enable clear for intr_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_36_CLR  ,Enable clear for intr_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_35_CLR         ,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_34_CLR  ,Enable clear for intr_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_33_CLR         ,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_32_CLR  ,Enable clear for intr_in[32]" "0,1"
group.long 0x388++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG2,Enable Clear Register 2"
bitfld.long 0x00 31. " ENABLE_95_CLR         ,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "     ENABLE_94_CLR  ,Enable clear for slv_events_in[30]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_93_CLR         ,Enable clear for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "     ENABLE_92_CLR  ,Enable clear for slv_events_in[28]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_91_CLR         ,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "     ENABLE_90_CLR  ,Enable clear for slv_events_in[26]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_89_CLR         ,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "     ENABLE_88_CLR  ,Enable clear for slv_events_in[24]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_87_CLR         ,Enable clear for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "     ENABLE_86_CLR  ,Enable clear for slv_events_in[22]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_85_CLR         ,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "     ENABLE_84_CLR  ,Enable clear for slv_events_in[20]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_83_CLR         ,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "     ENABLE_82_CLR  ,Enable clear for slv_events_in[18]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_81_CLR         ,Enable clear for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "     ENABLE_80_CLR  ,Enable clear for slv_events_in[16]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_79_CLR         ,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "     ENABLE_78_CLR  ,Enable clear for slv_events_in[14]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_77_CLR         ,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "     ENABLE_76_CLR  ,Enable clear for slv_events_in[12]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_75_CLR         ,Enable clear for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "     ENABLE_74_CLR  ,Enable clear for slv_events_in[10]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_73_CLR         ,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "     ENABLE_72_CLR  ,Enable clear for slv_events_in[8]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_71_CLR         ,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "     ENABLE_70_CLR  ,Enable clear for slv_events_in[6]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_69_CLR         ,Enable clear for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "     ENABLE_68_CLR  ,Enable clear for slv_events_in[4]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_67_CLR         ,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "     ENABLE_66_CLR  ,Enable clear for slv_events_in[2]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_65_CLR         ,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "     ENABLE_64_CLR  ,Enable clear for slv_events_in[0]" "0,1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG3,Enable Clear Register 3"
bitfld.long 0x00 31. " ENABLE_127_CLR        ,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0x00 30. "     ENABLE_126_CLR ,Enable clear for slv_events_in[62]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_125_CLR        ,Enable clear for slv_events_in[61]" "0,1"
bitfld.long 0x00 28. "     ENABLE_124_CLR ,Enable clear for slv_events_in[60]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_123_CLR        ,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0x00 26. "     ENABLE_122_CLR ,Enable clear for slv_events_in[58]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_121_CLR        ,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0x00 24. "     ENABLE_120_CLR ,Enable clear for slv_events_in[56]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_119_CLR        ,Enable clear for slv_events_in[55]" "0,1"
bitfld.long 0x00 22. "     ENABLE_118_CLR ,Enable clear for slv_events_in[54]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_117_CLR        ,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0x00 20. "     ENABLE_116_CLR ,Enable clear for slv_events_in[52]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_115_CLR        ,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0x00 18. "     ENABLE_114_CLR ,Enable clear for slv_events_in[50]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_113_CLR        ,Enable clear for slv_events_in[49]" "0,1"
bitfld.long 0x00 16. "     ENABLE_112_CLR ,Enable clear for slv_events_in[48]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_111_CLR        ,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0x00 14. "     ENABLE_110_CLR ,Enable clear for slv_events_in[46]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_109_CLR        ,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0x00 12. "     ENABLE_108_CLR ,Enable clear for slv_events_in[44]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_107_CLR        ,Enable clear for slv_events_in[43]" "0,1"
bitfld.long 0x00 10. "     ENABLE_106_CLR ,Enable clear for slv_events_in[42]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_105_CLR        ,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0x00 8. "     ENABLE_104_CLR ,Enable clear for slv_events_in[40]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_103_CLR        ,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0x00 6. "     ENABLE_102_CLR ,Enable clear for slv_events_in[38]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_101_CLR        ,Enable clear for slv_events_in[37]" "0,1"
bitfld.long 0x00 4. "     ENABLE_100_CLR ,Enable clear for slv_events_in[36]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_99_CLR         ,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0x00 2. "     ENABLE_98_CLR  ,Enable clear for slv_events_in[34]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_97_CLR         ,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0x00 0. "     ENABLE_96_CLR  ,Enable clear for slv_events_in[32]" "0,1"
group.long 0x390++0x3
line.long 0x00 "ICSSG_ENABLE_CLR_REG4,Enable Clear Register 4"
bitfld.long 0x00 31. " ENABLE_159_CLR        ,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x00 30. "     ENABLE_158_CLR ,Enable clear for slv_events_in[94]" "0,1"
textline "                                          "
bitfld.long 0x00 29. " ENABLE_157_CLR        ,Enable clear for slv_events_in[93]" "0,1"
bitfld.long 0x00 28. "     ENABLE_156_CLR ,Enable clear for slv_events_in[92]" "0,1"
textline "                                          "
bitfld.long 0x00 27. " ENABLE_155_CLR        ,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x00 26. "     ENABLE_154_CLR ,Enable clear for slv_events_in[90]" "0,1"
textline "                                          "
bitfld.long 0x00 25. " ENABLE_153_CLR        ,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x00 24. "     ENABLE_152_CLR ,Enable clear for slv_events_in[88]" "0,1"
textline "                                          "
bitfld.long 0x00 23. " ENABLE_151_CLR        ,Enable clear for slv_events_in[87]" "0,1"
bitfld.long 0x00 22. "     ENABLE_150_CLR ,Enable clear for slv_events_in[86]" "0,1"
textline "                                          "
bitfld.long 0x00 21. " ENABLE_149_CLR        ,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x00 20. "     ENABLE_148_CLR ,Enable clear for slv_events_in[84]" "0,1"
textline "                                          "
bitfld.long 0x00 19. " ENABLE_147_CLR        ,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x00 18. "     ENABLE_146_CLR ,Enable clear for slv_events_in[82]" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_145_CLR        ,Enable clear for slv_events_in[81]" "0,1"
bitfld.long 0x00 16. "     ENABLE_144_CLR ,Enable clear for slv_events_in[80]" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_143_CLR        ,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x00 14. "     ENABLE_142_CLR ,Enable clear for slv_events_in[78]" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_141_CLR        ,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x00 12. "     ENABLE_140_CLR ,Enable clear for slv_events_in[76]" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_139_CLR        ,Enable clear for slv_events_in[75]" "0,1"
bitfld.long 0x00 10. "     ENABLE_138_CLR ,Enable clear for slv_events_in[74]" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_137_CLR        ,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x00 8. "     ENABLE_136_CLR ,Enable clear for slv_events_in[72]" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_135_CLR        ,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x00 6. "     ENABLE_134_CLR ,Enable clear for slv_events_in[70]" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_133_CLR        ,Enable clear for slv_events_in[69]" "0,1"
bitfld.long 0x00 4. "     ENABLE_132_CLR ,Enable clear for slv_events_in[68]" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_131_CLR        ,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x00 2. "     ENABLE_130_CLR ,Enable clear for slv_events_in[66]" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_129_CLR        ,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x00 0. "     ENABLE_128_CLR ,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x3
line.long 0x00 "ICSSG_CH_MAP_REG0,Interrupt Channel Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " CH_MAP_3              ,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_2       ,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_1              ,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_0       ,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x404++0x3
line.long 0x00 "ICSSG_CH_MAP_REG1,Interrupt Channel Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " CH_MAP_7              ,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_6       ,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_5              ,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_4       ,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x408++0x3
line.long 0x00 "ICSSG_CH_MAP_REG2,Interrupt Channel Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " CH_MAP_11             ,Interrupt Channel Map for intr_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_10      ,Interrupt Channel Map for intr_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_9              ,Interrupt Channel Map for intr_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_8       ,Interrupt Channel Map for intr_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG3,Interrupt Channel Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " CH_MAP_15             ,Interrupt Channel Map for intr_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_14      ,Interrupt Channel Map for intr_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_13             ,Interrupt Channel Map for intr_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_12      ,Interrupt Channel Map for intr_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x410++0x3
line.long 0x00 "ICSSG_CH_MAP_REG4,Interrupt Channel Map Register for 16 to 16+3"
bitfld.long 0x00 24.--28. " CH_MAP_19             ,Interrupt Channel Map for intr_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_18      ,Interrupt Channel Map for intr_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_17             ,Interrupt Channel Map for intr_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_16      ,Interrupt Channel Map for intr_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x414++0x3
line.long 0x00 "ICSSG_CH_MAP_REG5,Interrupt Channel Map Register for 20 to 20+3"
bitfld.long 0x00 24.--28. " CH_MAP_23             ,Interrupt Channel Map for intr_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_22      ,Interrupt Channel Map for intr_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_21             ,Interrupt Channel Map for intr_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_20      ,Interrupt Channel Map for intr_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x418++0x3
line.long 0x00 "ICSSG_CH_MAP_REG6,Interrupt Channel Map Register for 24 to 24+3"
bitfld.long 0x00 24.--28. " CH_MAP_27             ,Interrupt Channel Map for intr_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_26      ,Interrupt Channel Map for intr_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_25             ,Interrupt Channel Map for intr_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_24      ,Interrupt Channel Map for intr_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG7,Interrupt Channel Map Register for 28 to 28+3"
bitfld.long 0x00 24.--28. " CH_MAP_31             ,Interrupt Channel Map for intr_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_30      ,Interrupt Channel Map for intr_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_29             ,Interrupt Channel Map for intr_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_28      ,Interrupt Channel Map for intr_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x420++0x3
line.long 0x00 "ICSSG_CH_MAP_REG8,Interrupt Channel Map Register for 32 to 32+3"
bitfld.long 0x00 24.--28. " CH_MAP_35             ,Interrupt Channel Map for intr_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_34      ,Interrupt Channel Map for intr_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_33             ,Interrupt Channel Map for intr_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_32      ,Interrupt Channel Map for intr_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x424++0x3
line.long 0x00 "ICSSG_CH_MAP_REG9,Interrupt Channel Map Register for 36 to 36+3"
bitfld.long 0x00 24.--28. " CH_MAP_39             ,Interrupt Channel Map for intr_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_38      ,Interrupt Channel Map for intr_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_37             ,Interrupt Channel Map for intr_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_36      ,Interrupt Channel Map for intr_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x428++0x3
line.long 0x00 "ICSSG_CH_MAP_REG10,Interrupt Channel Map Register for 40 to 40+3"
bitfld.long 0x00 24.--28. " CH_MAP_43             ,Interrupt Channel Map for intr_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_42      ,Interrupt Channel Map for intr_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_41             ,Interrupt Channel Map for intr_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_40      ,Interrupt Channel Map for intr_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG11,Interrupt Channel Map Register for 44 to 44+3"
bitfld.long 0x00 24.--28. " CH_MAP_47             ,Interrupt Channel Map for intr_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_46      ,Interrupt Channel Map for intr_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_45             ,Interrupt Channel Map for intr_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_44      ,Interrupt Channel Map for intr_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x430++0x3
line.long 0x00 "ICSSG_CH_MAP_REG12,Interrupt Channel Map Register for 48 to 48+3"
bitfld.long 0x00 24.--28. " CH_MAP_51             ,Interrupt Channel Map for intr_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_50      ,Interrupt Channel Map for intr_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_49             ,Interrupt Channel Map for intr_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_48      ,Interrupt Channel Map for intr_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x434++0x3
line.long 0x00 "ICSSG_CH_MAP_REG13,Interrupt Channel Map Register for 52 to 52+3"
bitfld.long 0x00 24.--28. " CH_MAP_55             ,Interrupt Channel Map for intr_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_54      ,Interrupt Channel Map for intr_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_53             ,Interrupt Channel Map for intr_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_52      ,Interrupt Channel Map for intr_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x438++0x3
line.long 0x00 "ICSSG_CH_MAP_REG14,Interrupt Channel Map Register for 56 to 56+3"
bitfld.long 0x00 24.--28. " CH_MAP_59             ,Interrupt Channel Map for intr_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_58      ,Interrupt Channel Map for intr_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_57             ,Interrupt Channel Map for intr_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_56      ,Interrupt Channel Map for intr_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG15,Interrupt Channel Map Register for 60 to 60+3"
bitfld.long 0x00 24.--28. " CH_MAP_63             ,Interrupt Channel Map for intr_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_62      ,Interrupt Channel Map for intr_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_61             ,Interrupt Channel Map for intr_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_60      ,Interrupt Channel Map for intr_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x440++0x3
line.long 0x00 "ICSSG_CH_MAP_REG16,Interrupt Channel Map Register for 64 to 64+3"
bitfld.long 0x00 24.--28. " CH_MAP_67             ,Interrupt Channel Map for slv_events_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_66      ,Interrupt Channel Map for slv_events_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_65             ,Interrupt Channel Map for slv_events_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_64      ,Interrupt Channel Map for slv_events_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x444++0x3
line.long 0x00 "ICSSG_CH_MAP_REG17,Interrupt Channel Map Register for 68 to 68+3"
bitfld.long 0x00 24.--28. " CH_MAP_71             ,Interrupt Channel Map for slv_events_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_70      ,Interrupt Channel Map for slv_events_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_69             ,Interrupt Channel Map for slv_events_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_68      ,Interrupt Channel Map for slv_events_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x448++0x3
line.long 0x00 "ICSSG_CH_MAP_REG18,Interrupt Channel Map Register for 72 to 72+3"
bitfld.long 0x00 24.--28. " CH_MAP_75             ,Interrupt Channel Map for slv_events_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_74      ,Interrupt Channel Map for slv_events_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_73             ,Interrupt Channel Map for slv_events_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_72      ,Interrupt Channel Map for slv_events_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG19,Interrupt Channel Map Register for 76 to 76+3"
bitfld.long 0x00 24.--28. " CH_MAP_79             ,Interrupt Channel Map for slv_events_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_78      ,Interrupt Channel Map for slv_events_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_77             ,Interrupt Channel Map for slv_events_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_76      ,Interrupt Channel Map for slv_events_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x450++0x3
line.long 0x00 "ICSSG_CH_MAP_REG20,Interrupt Channel Map Register for 80 to 80+3"
bitfld.long 0x00 24.--28. " CH_MAP_83             ,Interrupt Channel Map for slv_events_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_82      ,Interrupt Channel Map for slv_events_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_81             ,Interrupt Channel Map for slv_events_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_80      ,Interrupt Channel Map for slv_events_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x454++0x3
line.long 0x00 "ICSSG_CH_MAP_REG21,Interrupt Channel Map Register for 84 to 84+3"
bitfld.long 0x00 24.--28. " CH_MAP_87             ,Interrupt Channel Map for slv_events_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_86      ,Interrupt Channel Map for slv_events_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_85             ,Interrupt Channel Map for slv_events_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_84      ,Interrupt Channel Map for slv_events_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x458++0x3
line.long 0x00 "ICSSG_CH_MAP_REG22,Interrupt Channel Map Register for 88 to 88+3"
bitfld.long 0x00 24.--28. " CH_MAP_91             ,Interrupt Channel Map for slv_events_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_90      ,Interrupt Channel Map for slv_events_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_89             ,Interrupt Channel Map for slv_events_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_88      ,Interrupt Channel Map for slv_events_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG23,Interrupt Channel Map Register for 92 to 92+3"
bitfld.long 0x00 24.--28. " CH_MAP_95             ,Interrupt Channel Map for slv_events_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_94      ,Interrupt Channel Map for slv_events_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_93             ,Interrupt Channel Map for slv_events_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_92      ,Interrupt Channel Map for slv_events_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x460++0x3
line.long 0x00 "ICSSG_CH_MAP_REG24,Interrupt Channel Map Register for 96 to 96+3"
bitfld.long 0x00 24.--28. " CH_MAP_99             ,Interrupt Channel Map for slv_events_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_98      ,Interrupt Channel Map for slv_events_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_97             ,Interrupt Channel Map for slv_events_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_96      ,Interrupt Channel Map for slv_events_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x464++0x3
line.long 0x00 "ICSSG_CH_MAP_REG25,Interrupt Channel Map Register for 100 to 100+3"
bitfld.long 0x00 24.--28. " CH_MAP_103            ,Interrupt Channel Map for slv_events_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_102     ,Interrupt Channel Map for slv_events_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_101            ,Interrupt Channel Map for slv_events_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_100     ,Interrupt Channel Map for slv_events_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x468++0x3
line.long 0x00 "ICSSG_CH_MAP_REG26,Interrupt Channel Map Register for 104 to 104+3"
bitfld.long 0x00 24.--28. " CH_MAP_107            ,Interrupt Channel Map for slv_events_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_106     ,Interrupt Channel Map for slv_events_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_105            ,Interrupt Channel Map for slv_events_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_104     ,Interrupt Channel Map for slv_events_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG27,Interrupt Channel Map Register for 108 to 108+3"
bitfld.long 0x00 24.--28. " CH_MAP_111            ,Interrupt Channel Map for slv_events_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_110     ,Interrupt Channel Map for slv_events_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_109            ,Interrupt Channel Map for slv_events_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_108     ,Interrupt Channel Map for slv_events_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x470++0x3
line.long 0x00 "ICSSG_CH_MAP_REG28,Interrupt Channel Map Register for 112 to 112+3"
bitfld.long 0x00 24.--28. " CH_MAP_115            ,Interrupt Channel Map for slv_events_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_114     ,Interrupt Channel Map for slv_events_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_113            ,Interrupt Channel Map for slv_events_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_112     ,Interrupt Channel Map for slv_events_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x474++0x3
line.long 0x00 "ICSSG_CH_MAP_REG29,Interrupt Channel Map Register for 116 to 116+3"
bitfld.long 0x00 24.--28. " CH_MAP_119            ,Interrupt Channel Map for slv_events_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_118     ,Interrupt Channel Map for slv_events_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_117            ,Interrupt Channel Map for slv_events_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_116     ,Interrupt Channel Map for slv_events_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x478++0x3
line.long 0x00 "ICSSG_CH_MAP_REG30,Interrupt Channel Map Register for 120 to 120+3"
bitfld.long 0x00 24.--28. " CH_MAP_123            ,Interrupt Channel Map for slv_events_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_122     ,Interrupt Channel Map for slv_events_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_121            ,Interrupt Channel Map for slv_events_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_120     ,Interrupt Channel Map for slv_events_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG31,Interrupt Channel Map Register for 124 to 124+3"
bitfld.long 0x00 24.--28. " CH_MAP_127            ,Interrupt Channel Map for slv_events_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_126     ,Interrupt Channel Map for slv_events_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_125            ,Interrupt Channel Map for slv_events_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_124     ,Interrupt Channel Map for slv_events_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x480++0x3
line.long 0x00 "ICSSG_CH_MAP_REG32,Interrupt Channel Map Register for 128 to 128+3"
bitfld.long 0x00 24.--28. " CH_MAP_131            ,Interrupt Channel Map for slv_events_in[67]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_130     ,Interrupt Channel Map for slv_events_in[66]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_129            ,Interrupt Channel Map for slv_events_in[65]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_128     ,Interrupt Channel Map for slv_events_in[64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x484++0x3
line.long 0x00 "ICSSG_CH_MAP_REG33,Interrupt Channel Map Register for 132 to 132+3"
bitfld.long 0x00 24.--28. " CH_MAP_135            ,Interrupt Channel Map for slv_events_in[71]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_134     ,Interrupt Channel Map for slv_events_in[70]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_133            ,Interrupt Channel Map for slv_events_in[69]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_132     ,Interrupt Channel Map for slv_events_in[68]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x488++0x3
line.long 0x00 "ICSSG_CH_MAP_REG34,Interrupt Channel Map Register for 136 to 136+3"
bitfld.long 0x00 24.--28. " CH_MAP_139            ,Interrupt Channel Map for slv_events_in[75]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_138     ,Interrupt Channel Map for slv_events_in[74]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_137            ,Interrupt Channel Map for slv_events_in[73]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_136     ,Interrupt Channel Map for slv_events_in[72]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG35,Interrupt Channel Map Register for 140 to 140+3"
bitfld.long 0x00 24.--28. " CH_MAP_143            ,Interrupt Channel Map for slv_events_in[79]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_142     ,Interrupt Channel Map for slv_events_in[78]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_141            ,Interrupt Channel Map for slv_events_in[77]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_140     ,Interrupt Channel Map for slv_events_in[76]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x490++0x3
line.long 0x00 "ICSSG_CH_MAP_REG36,Interrupt Channel Map Register for 144 to 144+3"
bitfld.long 0x00 24.--28. " CH_MAP_147            ,Interrupt Channel Map for slv_events_in[83]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_146     ,Interrupt Channel Map for slv_events_in[82]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_145            ,Interrupt Channel Map for slv_events_in[81]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_144     ,Interrupt Channel Map for slv_events_in[80]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x494++0x3
line.long 0x00 "ICSSG_CH_MAP_REG37,Interrupt Channel Map Register for 148 to 148+3"
bitfld.long 0x00 24.--28. " CH_MAP_151            ,Interrupt Channel Map for slv_events_in[87]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_150     ,Interrupt Channel Map for slv_events_in[86]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_149            ,Interrupt Channel Map for slv_events_in[85]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_148     ,Interrupt Channel Map for slv_events_in[84]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x498++0x3
line.long 0x00 "ICSSG_CH_MAP_REG38,Interrupt Channel Map Register for 152 to 152+3"
bitfld.long 0x00 24.--28. " CH_MAP_155            ,Interrupt Channel Map for slv_events_in[91]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_154     ,Interrupt Channel Map for slv_events_in[90]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_153            ,Interrupt Channel Map for slv_events_in[89]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_152     ,Interrupt Channel Map for slv_events_in[88]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_CH_MAP_REG39,Interrupt Channel Map Register for 156 to 156+3"
bitfld.long 0x00 24.--28. " CH_MAP_159            ,Interrupt Channel Map for slv_events_in[95]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    CH_MAP_158     ,Interrupt Channel Map for slv_events_in[94]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " CH_MAP_157            ,Interrupt Channel Map for slv_events_in[93]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    CH_MAP_156     ,Interrupt Channel Map for slv_events_in[92]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x800++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG0,Host Interrupt Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. " HINT_MAP_3            ,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_2     ,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_1            ,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_0     ,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x804++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG1,Host Interrupt Map Register for 4 to 4+3"
bitfld.long 0x00 24.--28. " HINT_MAP_7            ,Host Interrupt Map for Channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_6     ,Host Interrupt Map for Channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_5            ,Host Interrupt Map for Channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_4     ,Host Interrupt Map for Channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x808++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG2,Host Interrupt Map Register for 8 to 8+3"
bitfld.long 0x00 24.--28. " HINT_MAP_11           ,Host Interrupt Map for Channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_10    ,Host Interrupt Map for Channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_9            ,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_8     ,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG3,Host Interrupt Map Register for 12 to 12+3"
bitfld.long 0x00 24.--28. " HINT_MAP_15           ,Host Interrupt Map for Channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_14    ,Host Interrupt Map for Channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_13           ,Host Interrupt Map for Channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_12    ,Host Interrupt Map for Channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x810++0x3
line.long 0x00 "ICSSG_HINT_MAP_REG4,Host Interrupt Map Register for 16 to 16+4"
bitfld.long 0x00 24.--28. " HINT_MAP_19           ,Host Interrupt Map for Channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "    HINT_MAP_18    ,Host Interrupt Map for Channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--12. " HINT_MAP_17           ,Host Interrupt Map for Channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "    HINT_MAP_16    ,Host Interrupt Map for Channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x900++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG0,Host Int 0 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_0           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_0     ,Host Int 0 Prioritized Interrupt"
rgroup.long 0x904++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG1,Host Int 1 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_1           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_1     ,Host Int 1 Prioritized Interrupt"
rgroup.long 0x908++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG2,Host Int 2 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_2           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_2     ,Host Int 2 Prioritized Interrupt"
rgroup.long 0x90C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG3,Host Int 3 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_3           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_3     ,Host Int 3 Prioritized Interrupt"
rgroup.long 0x910++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG4,Host Int 4 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_4           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_4     ,Host Int 4 Prioritized Interrupt"
rgroup.long 0x914++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG5,Host Int 5 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_5           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_5     ,Host Int 5 Prioritized Interrupt"
rgroup.long 0x918++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG6,Host Int 6 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_6           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_6     ,Host Int 6 Prioritized Interrupt"
rgroup.long 0x91C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG7,Host Int 7 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_7           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_7     ,Host Int 7 Prioritized Interrupt"
rgroup.long 0x920++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG8,Host Int 8 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_8           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_8     ,Host Int 8 Prioritized Interrupt"
rgroup.long 0x924++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG9,Host Int 9 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_9           ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_9     ,Host Int 9 Prioritized Interrupt"
rgroup.long 0x928++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG10,Host Int 10 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_10          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_10    ,Host Int 10 Prioritized Interrupt"
rgroup.long 0x92C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG11,Host Int 11 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_11          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_11    ,Host Int 11 Prioritized Interrupt"
rgroup.long 0x930++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG12,Host Int 12 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_12          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_12    ,Host Int 12 Prioritized Interrupt"
rgroup.long 0x934++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG13,Host Int 13 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_13          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_13    ,Host Int 13 Prioritized Interrupt"
rgroup.long 0x938++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG14,Host Int 14 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_14          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_14    ,Host Int 14 Prioritized Interrupt"
rgroup.long 0x93C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG15,Host Int 15 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_15          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_15    ,Host Int 15 Prioritized Interrupt"
rgroup.long 0x940++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG16,Host Int 16 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_16          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_16    ,Host Int 16 Prioritized Interrupt"
rgroup.long 0x944++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG17,Host Int 17 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_17          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_17    ,Host Int 17 Prioritized Interrupt"
rgroup.long 0x948++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG18,Host Int 18 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_18          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_18    ,Host Int 18 Prioritized Interrupt"
rgroup.long 0x94C++0x3
line.long 0x00 "ICSSG_PRI_HINT_REG19,Host Int 19 Prioritized Interrupt Register"
bitfld.long 0x00 31. " NONE_HINT_19          ,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "     PRI_HINT_19    ,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x3
line.long 0x00 "ICSSG_POLARITY_REG0,Polarity Register 0"
bitfld.long 0x00 31. " POLARITY_31           ,Polarity for intr_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_30    ,Polarity for intr_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_29           ,Polarity for intr_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_28    ,Polarity for intr_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_27           ,Polarity for intr_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_26    ,Polarity for intr_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_25           ,Polarity for intr_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_24    ,Polarity for intr_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_23           ,Polarity for intr_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_22    ,Polarity for intr_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_21           ,Polarity for intr_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_20    ,Polarity for intr_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_19           ,Polarity for intr_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_18    ,Polarity for intr_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_17           ,Polarity for intr_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_16    ,Polarity for intr_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_15           ,Polarity for intr_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_14    ,Polarity for intr_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_13           ,Polarity for intr_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_12    ,Polarity for intr_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_11           ,Polarity for intr_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_10    ,Polarity for intr_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_9            ,Polarity for intr_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_8     ,Polarity for intr_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_7            ,Polarity for intr_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_6     ,Polarity for intr_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_5            ,Polarity for intr_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_4     ,Polarity for intr_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_3            ,Polarity for intr_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_2     ,Polarity for intr_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_1            ,Polarity for intr_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_0     ,Polarity for intr_in[0]0=low" "0,1"
group.long 0xD04++0x3
line.long 0x00 "ICSSG_POLARITY_REG1,Polarity Register 1"
bitfld.long 0x00 31. " POLARITY_63           ,Polarity for intr_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_62    ,Polarity for intr_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_61           ,Polarity for intr_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_60    ,Polarity for intr_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_59           ,Polarity for intr_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_58    ,Polarity for intr_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_57           ,Polarity for intr_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_56    ,Polarity for intr_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_55           ,Polarity for intr_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_54    ,Polarity for intr_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_53           ,Polarity for intr_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_52    ,Polarity for intr_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_51           ,Polarity for intr_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_50    ,Polarity for intr_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_49           ,Polarity for intr_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_48    ,Polarity for intr_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_47           ,Polarity for intr_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_46    ,Polarity for intr_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_45           ,Polarity for intr_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_44    ,Polarity for intr_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_43           ,Polarity for intr_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_42    ,Polarity for intr_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_41           ,Polarity for intr_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_40    ,Polarity for intr_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_39           ,Polarity for intr_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_38    ,Polarity for intr_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_37           ,Polarity for intr_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_36    ,Polarity for intr_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_35           ,Polarity for intr_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_34    ,Polarity for intr_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_33           ,Polarity for intr_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_32    ,Polarity for intr_in[32]0=low" "0,1"
group.long 0xD08++0x3
line.long 0x00 "ICSSG_POLARITY_REG2,Polarity Register 2"
bitfld.long 0x00 31. " POLARITY_95           ,Polarity for slv_events_in[31]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_94    ,Polarity for slv_events_in[30]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_93           ,Polarity for slv_events_in[29]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_92    ,Polarity for slv_events_in[28]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_91           ,Polarity for slv_events_in[27]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_90    ,Polarity for slv_events_in[26]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_89           ,Polarity for slv_events_in[25]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_88    ,Polarity for slv_events_in[24]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_87           ,Polarity for slv_events_in[23]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_86    ,Polarity for slv_events_in[22]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_85           ,Polarity for slv_events_in[21]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_84    ,Polarity for slv_events_in[20]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_83           ,Polarity for slv_events_in[19]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_82    ,Polarity for slv_events_in[18]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_81           ,Polarity for slv_events_in[17]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_80    ,Polarity for slv_events_in[16]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_79           ,Polarity for slv_events_in[15]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_78    ,Polarity for slv_events_in[14]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_77           ,Polarity for slv_events_in[13]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_76    ,Polarity for slv_events_in[12]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_75           ,Polarity for slv_events_in[11]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_74    ,Polarity for slv_events_in[10]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_73           ,Polarity for slv_events_in[9]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_72    ,Polarity for slv_events_in[8]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_71           ,Polarity for slv_events_in[7]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_70    ,Polarity for slv_events_in[6]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_69           ,Polarity for slv_events_in[5]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_68    ,Polarity for slv_events_in[4]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_67           ,Polarity for slv_events_in[3]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_66    ,Polarity for slv_events_in[2]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_65           ,Polarity for slv_events_in[1]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_64    ,Polarity for slv_events_in[0]0=low" "0,1"
group.long 0xD0C++0x3
line.long 0x00 "ICSSG_POLARITY_REG3,Polarity Register 3"
bitfld.long 0x00 31. " POLARITY_127          ,Polarity for slv_events_in[63]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_126   ,Polarity for slv_events_in[62]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_125          ,Polarity for slv_events_in[61]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_124   ,Polarity for slv_events_in[60]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_123          ,Polarity for slv_events_in[59]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_122   ,Polarity for slv_events_in[58]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_121          ,Polarity for slv_events_in[57]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_120   ,Polarity for slv_events_in[56]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_119          ,Polarity for slv_events_in[55]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_118   ,Polarity for slv_events_in[54]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_117          ,Polarity for slv_events_in[53]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_116   ,Polarity for slv_events_in[52]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_115          ,Polarity for slv_events_in[51]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_114   ,Polarity for slv_events_in[50]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_113          ,Polarity for slv_events_in[49]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_112   ,Polarity for slv_events_in[48]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_111          ,Polarity for slv_events_in[47]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_110   ,Polarity for slv_events_in[46]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_109          ,Polarity for slv_events_in[45]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_108   ,Polarity for slv_events_in[44]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_107          ,Polarity for slv_events_in[43]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_106   ,Polarity for slv_events_in[42]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_105          ,Polarity for slv_events_in[41]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_104   ,Polarity for slv_events_in[40]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_103          ,Polarity for slv_events_in[39]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_102   ,Polarity for slv_events_in[38]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_101          ,Polarity for slv_events_in[37]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_100   ,Polarity for slv_events_in[36]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_99           ,Polarity for slv_events_in[35]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_98    ,Polarity for slv_events_in[34]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_97           ,Polarity for slv_events_in[33]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_96    ,Polarity for slv_events_in[32]0=low" "0,1"
group.long 0xD10++0x3
line.long 0x00 "ICSSG_POLARITY_REG4,Polarity Register 4"
bitfld.long 0x00 31. " POLARITY_159          ,Polarity for slv_events_in[95]0=low" "0,1"
bitfld.long 0x00 30. "     POLARITY_158   ,Polarity for slv_events_in[94]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 29. " POLARITY_157          ,Polarity for slv_events_in[93]0=low" "0,1"
bitfld.long 0x00 28. "     POLARITY_156   ,Polarity for slv_events_in[92]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 27. " POLARITY_155          ,Polarity for slv_events_in[91]0=low" "0,1"
bitfld.long 0x00 26. "     POLARITY_154   ,Polarity for slv_events_in[90]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 25. " POLARITY_153          ,Polarity for slv_events_in[89]0=low" "0,1"
bitfld.long 0x00 24. "     POLARITY_152   ,Polarity for slv_events_in[88]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 23. " POLARITY_151          ,Polarity for slv_events_in[87]0=low" "0,1"
bitfld.long 0x00 22. "     POLARITY_150   ,Polarity for slv_events_in[86]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 21. " POLARITY_149          ,Polarity for slv_events_in[85]0=low" "0,1"
bitfld.long 0x00 20. "     POLARITY_148   ,Polarity for slv_events_in[84]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 19. " POLARITY_147          ,Polarity for slv_events_in[83]0=low" "0,1"
bitfld.long 0x00 18. "     POLARITY_146   ,Polarity for slv_events_in[82]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 17. " POLARITY_145          ,Polarity for slv_events_in[81]0=low" "0,1"
bitfld.long 0x00 16. "     POLARITY_144   ,Polarity for slv_events_in[80]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 15. " POLARITY_143          ,Polarity for slv_events_in[79]0=low" "0,1"
bitfld.long 0x00 14. "     POLARITY_142   ,Polarity for slv_events_in[78]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 13. " POLARITY_141          ,Polarity for slv_events_in[77]0=low" "0,1"
bitfld.long 0x00 12. "     POLARITY_140   ,Polarity for slv_events_in[76]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 11. " POLARITY_139          ,Polarity for slv_events_in[75]0=low" "0,1"
bitfld.long 0x00 10. "     POLARITY_138   ,Polarity for slv_events_in[74]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 9. " POLARITY_137          ,Polarity for slv_events_in[73]0=low" "0,1"
bitfld.long 0x00 8. "     POLARITY_136   ,Polarity for slv_events_in[72]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 7. " POLARITY_135          ,Polarity for slv_events_in[71]0=low" "0,1"
bitfld.long 0x00 6. "     POLARITY_134   ,Polarity for slv_events_in[70]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 5. " POLARITY_133          ,Polarity for slv_events_in[69]0=low" "0,1"
bitfld.long 0x00 4. "     POLARITY_132   ,Polarity for slv_events_in[68]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 3. " POLARITY_131          ,Polarity for slv_events_in[67]0=low" "0,1"
bitfld.long 0x00 2. "     POLARITY_130   ,Polarity for slv_events_in[66]0=low" "0,1"
textline "                                          "
bitfld.long 0x00 1. " POLARITY_129          ,Polarity for slv_events_in[65]0=low" "0,1"
bitfld.long 0x00 0. "     POLARITY_128   ,Polarity for slv_events_in[64]0=low" "0,1"
group.long 0xD80++0x3
line.long 0x00 "ICSSG_TYPE_REG0,Type Register 0"
bitfld.long 0x00 31. " TYPE_31               ,Type for intr_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_30        ,Type for intr_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_29               ,Type for intr_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_28        ,Type for intr_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_27               ,Type for intr_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_26        ,Type for intr_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_25               ,Type for intr_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_24        ,Type for intr_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_23               ,Type for intr_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_22        ,Type for intr_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_21               ,Type for intr_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_20        ,Type for intr_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_19               ,Type for intr_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_18        ,Type for intr_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_17               ,Type for intr_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_16        ,Type for intr_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_15               ,Type for intr_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_14        ,Type for intr_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_13               ,Type for intr_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_12        ,Type for intr_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_11               ,Type for intr_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_10        ,Type for intr_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_9                ,Type for intr_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_8         ,Type for intr_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_7                ,Type for intr_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_6         ,Type for intr_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_5                ,Type for intr_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_4         ,Type for intr_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_3                ,Type for intr_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_2         ,Type for intr_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_1                ,Type for intr_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_0         ,Type for intr_in[0]0=level" "0,1"
group.long 0xD84++0x3
line.long 0x00 "ICSSG_TYPE_REG1,Type Register 1"
bitfld.long 0x00 31. " TYPE_63               ,Type for intr_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_62        ,Type for intr_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_61               ,Type for intr_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_60        ,Type for intr_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_59               ,Type for intr_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_58        ,Type for intr_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_57               ,Type for intr_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_56        ,Type for intr_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_55               ,Type for intr_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_54        ,Type for intr_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_53               ,Type for intr_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_52        ,Type for intr_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_51               ,Type for intr_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_50        ,Type for intr_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_49               ,Type for intr_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_48        ,Type for intr_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_47               ,Type for intr_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_46        ,Type for intr_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_45               ,Type for intr_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_44        ,Type for intr_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_43               ,Type for intr_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_42        ,Type for intr_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_41               ,Type for intr_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_40        ,Type for intr_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_39               ,Type for intr_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_38        ,Type for intr_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_37               ,Type for intr_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_36        ,Type for intr_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_35               ,Type for intr_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_34        ,Type for intr_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_33               ,Type for intr_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_32        ,Type for intr_in[32]0=level" "0,1"
group.long 0xD88++0x3
line.long 0x00 "ICSSG_TYPE_REG2,Type Register 2"
bitfld.long 0x00 31. " TYPE_95               ,Type for slv_events_in[31]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_94        ,Type for slv_events_in[30]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_93               ,Type for slv_events_in[29]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_92        ,Type for slv_events_in[28]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_91               ,Type for slv_events_in[27]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_90        ,Type for slv_events_in[26]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_89               ,Type for slv_events_in[25]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_88        ,Type for slv_events_in[24]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_87               ,Type for slv_events_in[23]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_86        ,Type for slv_events_in[22]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_85               ,Type for slv_events_in[21]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_84        ,Type for slv_events_in[20]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_83               ,Type for slv_events_in[19]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_82        ,Type for slv_events_in[18]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_81               ,Type for slv_events_in[17]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_80        ,Type for slv_events_in[16]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_79               ,Type for slv_events_in[15]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_78        ,Type for slv_events_in[14]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_77               ,Type for slv_events_in[13]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_76        ,Type for slv_events_in[12]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_75               ,Type for slv_events_in[11]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_74        ,Type for slv_events_in[10]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_73               ,Type for slv_events_in[9]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_72        ,Type for slv_events_in[8]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_71               ,Type for slv_events_in[7]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_70        ,Type for slv_events_in[6]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_69               ,Type for slv_events_in[5]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_68        ,Type for slv_events_in[4]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_67               ,Type for slv_events_in[3]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_66        ,Type for slv_events_in[2]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_65               ,Type for slv_events_in[1]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_64        ,Type for slv_events_in[0]0=level" "0,1"
group.long 0xD8C++0x3
line.long 0x00 "ICSSG_TYPE_REG3,Type Register 3"
bitfld.long 0x00 31. " TYPE_127              ,Type for slv_events_in[63]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_126       ,Type for slv_events_in[62]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_125              ,Type for slv_events_in[61]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_124       ,Type for slv_events_in[60]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_123              ,Type for slv_events_in[59]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_122       ,Type for slv_events_in[58]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_121              ,Type for slv_events_in[57]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_120       ,Type for slv_events_in[56]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_119              ,Type for slv_events_in[55]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_118       ,Type for slv_events_in[54]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_117              ,Type for slv_events_in[53]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_116       ,Type for slv_events_in[52]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_115              ,Type for slv_events_in[51]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_114       ,Type for slv_events_in[50]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_113              ,Type for slv_events_in[49]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_112       ,Type for slv_events_in[48]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_111              ,Type for slv_events_in[47]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_110       ,Type for slv_events_in[46]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_109              ,Type for slv_events_in[45]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_108       ,Type for slv_events_in[44]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_107              ,Type for slv_events_in[43]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_106       ,Type for slv_events_in[42]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_105              ,Type for slv_events_in[41]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_104       ,Type for slv_events_in[40]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_103              ,Type for slv_events_in[39]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_102       ,Type for slv_events_in[38]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_101              ,Type for slv_events_in[37]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_100       ,Type for slv_events_in[36]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_99               ,Type for slv_events_in[35]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_98        ,Type for slv_events_in[34]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_97               ,Type for slv_events_in[33]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_96        ,Type for slv_events_in[32]0=level" "0,1"
group.long 0xD90++0x3
line.long 0x00 "ICSSG_TYPE_REG4,Type Register 4"
bitfld.long 0x00 31. " TYPE_159              ,Type for slv_events_in[95]0=level" "0,1"
bitfld.long 0x00 30. "     TYPE_158       ,Type for slv_events_in[94]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 29. " TYPE_157              ,Type for slv_events_in[93]0=level" "0,1"
bitfld.long 0x00 28. "     TYPE_156       ,Type for slv_events_in[92]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 27. " TYPE_155              ,Type for slv_events_in[91]0=level" "0,1"
bitfld.long 0x00 26. "     TYPE_154       ,Type for slv_events_in[90]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 25. " TYPE_153              ,Type for slv_events_in[89]0=level" "0,1"
bitfld.long 0x00 24. "     TYPE_152       ,Type for slv_events_in[88]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 23. " TYPE_151              ,Type for slv_events_in[87]0=level" "0,1"
bitfld.long 0x00 22. "     TYPE_150       ,Type for slv_events_in[86]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 21. " TYPE_149              ,Type for slv_events_in[85]0=level" "0,1"
bitfld.long 0x00 20. "     TYPE_148       ,Type for slv_events_in[84]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 19. " TYPE_147              ,Type for slv_events_in[83]0=level" "0,1"
bitfld.long 0x00 18. "     TYPE_146       ,Type for slv_events_in[82]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 17. " TYPE_145              ,Type for slv_events_in[81]0=level" "0,1"
bitfld.long 0x00 16. "     TYPE_144       ,Type for slv_events_in[80]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 15. " TYPE_143              ,Type for slv_events_in[79]0=level" "0,1"
bitfld.long 0x00 14. "     TYPE_142       ,Type for slv_events_in[78]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 13. " TYPE_141              ,Type for slv_events_in[77]0=level" "0,1"
bitfld.long 0x00 12. "     TYPE_140       ,Type for slv_events_in[76]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 11. " TYPE_139              ,Type for slv_events_in[75]0=level" "0,1"
bitfld.long 0x00 10. "     TYPE_138       ,Type for slv_events_in[74]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 9. " TYPE_137              ,Type for slv_events_in[73]0=level" "0,1"
bitfld.long 0x00 8. "     TYPE_136       ,Type for slv_events_in[72]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 7. " TYPE_135              ,Type for slv_events_in[71]0=level" "0,1"
bitfld.long 0x00 6. "     TYPE_134       ,Type for slv_events_in[70]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 5. " TYPE_133              ,Type for slv_events_in[69]0=level" "0,1"
bitfld.long 0x00 4. "     TYPE_132       ,Type for slv_events_in[68]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 3. " TYPE_131              ,Type for slv_events_in[67]0=level" "0,1"
bitfld.long 0x00 2. "     TYPE_130       ,Type for slv_events_in[66]0=level" "0,1"
textline "                                          "
bitfld.long 0x00 1. " TYPE_129              ,Type for slv_events_in[65]0=level" "0,1"
bitfld.long 0x00 0. "     TYPE_128       ,Type for slv_events_in[64]0=level" "0,1"
group.long 0x1100++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG0,Host Int 0 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_0    ,Host Int 0 Nesting Level"
group.long 0x1104++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG1,Host Int 1 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_1    ,Host Int 1 Nesting Level"
group.long 0x1108++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG2,Host Int 2 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_2    ,Host Int 2 Nesting Level"
group.long 0x110C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG3,Host Int 3 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_3    ,Host Int 3 Nesting Level"
group.long 0x1110++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG4,Host Int 4 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_4    ,Host Int 4 Nesting Level"
group.long 0x1114++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG5,Host Int 5 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_5    ,Host Int 5 Nesting Level"
group.long 0x1118++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG6,Host Int 6 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_6    ,Host Int 6 Nesting Level"
group.long 0x111C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG7,Host Int 7 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_7    ,Host Int 7 Nesting Level"
group.long 0x1120++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG8,Host Int 8 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_8    ,Host Int 8 Nesting Level"
group.long 0x1124++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG9,Host Int 9 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_9    ,Host Int 9 Nesting Level"
group.long 0x1128++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG10,Host Int 10 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_10   ,Host Int 10 Nesting Level"
group.long 0x112C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG11,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_11   ,Host Int 11 Nesting Level"
group.long 0x1130++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG12,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_12   ,Host Int 12 Nesting Level"
group.long 0x1134++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG13,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_13   ,Host Int 13 Nesting Level"
group.long 0x1138++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG14,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_14   ,Host Int 14 Nesting Level"
group.long 0x113C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG15,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_15   ,Host Int 15 Nesting Level"
group.long 0x1140++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG16,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_16   ,Host Int 16 Nesting Level"
group.long 0x1144++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG17,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_17   ,Host Int 17 Nesting Level"
group.long 0x1148++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG18,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_18   ,Host Int 18 Nesting Level"
group.long 0x114C++0x3
line.long 0x00 "ICSSG_NEST_LEVEL_REG19,Host Int 11 Nesting Level Register"
bitfld.long 0x00 31. " NEST_AUTO_OVR         ,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "     NEST_HINT_19   ,Host Int 19 Nesting Level"
group.long 0x1500++0x3
line.long 0x00 "ICSSG_ENABLE_HINT_REG0,Host Int Enable Register 0"
bitfld.long 0x00 19. " ENABLE_HINT_19        ,Enable for Host Int 19" "0,1"
bitfld.long 0x00 18. "     ENABLE_HINT_18 ,Enable for Host Int 18" "0,1"
textline "                                          "
bitfld.long 0x00 17. " ENABLE_HINT_17        ,Enable for Host Int 17" "0,1"
bitfld.long 0x00 16. "     ENABLE_HINT_16 ,Enable for Host Int 16" "0,1"
textline "                                          "
bitfld.long 0x00 15. " ENABLE_HINT_15        ,Enable for Host Int 15" "0,1"
bitfld.long 0x00 14. "     ENABLE_HINT_14 ,Enable for Host Int 14" "0,1"
textline "                                          "
bitfld.long 0x00 13. " ENABLE_HINT_13        ,Enable for Host Int 13" "0,1"
bitfld.long 0x00 12. "     ENABLE_HINT_12 ,Enable for Host Int 12" "0,1"
textline "                                          "
bitfld.long 0x00 11. " ENABLE_HINT_11        ,Enable for Host Int 11" "0,1"
bitfld.long 0x00 10. "     ENABLE_HINT_10 ,Enable for Host Int 10" "0,1"
textline "                                          "
bitfld.long 0x00 9. " ENABLE_HINT_9         ,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "     ENABLE_HINT_8  ,Enable for Host Int 8" "0,1"
textline "                                          "
bitfld.long 0x00 7. " ENABLE_HINT_7         ,Enable for Host Int 7" "0,1"
bitfld.long 0x00 6. "     ENABLE_HINT_6  ,Enable for Host Int 6" "0,1"
textline "                                          "
bitfld.long 0x00 5. " ENABLE_HINT_5         ,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "     ENABLE_HINT_4  ,Enable for Host Int 4" "0,1"
textline "                                          "
bitfld.long 0x00 3. " ENABLE_HINT_3         ,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "     ENABLE_HINT_2  ,Enable for Host Int 2" "0,1"
textline "                                          "
bitfld.long 0x00 1. " ENABLE_HINT_1         ,Enable for Host Int 1" "0,1"
bitfld.long 0x00 0. "     ENABLE_HINT_0  ,Enable for Host Int 0" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MDIO"
tree "PRU_ICSSG2_PR1_MDIO_V1P7_MDIO"
base eaxi:0xB232400
width 31.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_MDIO_VERSION_REG,MDIO Version Register"
hexmask.long.word 0x00 16.--31. 1. " MODID                ,Module Identification value"
hexmask.long.byte 0x00 8.--15. 1. "      REVMAJ              ,Major revision value"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " REVMINOR             ,Minor revision value"
hgroup.long 0x4++0x3
hide.long 0x00 "ICSSG_CONTROL_REG,MDIO Control Register"
in
textline "                                        "
hgroup.long 0x8++0x3
hide.long 0x00 "ICSSG_ALIVE_REG,MDIO Alive Register"
in
textline "                                        "
rgroup.long 0xC++0x3
line.long 0x00 "ICSSG_LINK_REG,MDIO Link Register"
hexmask.long 0x00 0.--31. 1. " LINK                 ,MDIO Link state."
hgroup.long 0x10++0x3
hide.long 0x00 "ICSSG_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x14++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
in
textline "                                        "
group.long 0x18++0x3
line.long 0x00 "ICSSG_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x00 0. " LINKINTMASKSET       ,MDIO link interrupt mask set." "0,1"
hgroup.long 0x1C++0x3
hide.long 0x00 "ICSSG_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
in
textline "                                        "
hgroup.long 0x20++0x3
hide.long 0x00 "ICSSG_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
in
textline "                                        "
hgroup.long 0x24++0x3
hide.long 0x00 "ICSSG_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
in
textline "                                        "
group.long 0x28++0x3
line.long 0x00 "ICSSG_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x00 0.--1. " USERINTMASKSET       ,MDIO user interrupt mask set for userintmasked[1:0], respectively." "0,1,2,3"
hgroup.long 0x2C++0x3
hide.long 0x00 "ICSSG_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
in
textline "                                        "
group.long 0x30++0x3
line.long 0x00 "ICSSG_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x00 2. " MDIO_MDCLK_O         ,MDIO Clock Output." "0,1"
bitfld.long 0x00 1. "         MDIO_OE             ,MDIO Output Enable." "0,1"
textline "                                        "
bitfld.long 0x00 0. " MDIO_PIN             ,MDIO_Pin Value." "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_POLL_REG,MDIO Poll Inter Register"
bitfld.long 0x00 31. " MANUALMODE           ,Manual Mode." "0,1"
bitfld.long 0x00 30. "         STATECHANGEMODE     ,State Change Mode." "0,1"
textline "                                        "
hexmask.long.byte 0x00 0.--7. 1. " IPG                  ,Polling Inter Packet Gap Value."
group.long 0x38++0x3
line.long 0x00 "ICSSG_POLL_EN_REG,MDIO Poll Enable Register"
hexmask.long 0x00 0.--31. 1. " POLL_EN              ,Poll Enable."
group.long 0x3C++0x3
line.long 0x00 "ICSSG_CLAUS45_REG,Clause 45 Register"
hexmask.long 0x00 0.--31. 1. " CLAUSE45             ,MDIO clause 45 mode."
group.long 0x40++0x3
line.long 0x00 "ICSSG_USER_ADDR0_REG,MDIO User Address 0 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR0           ,User Address 0."
group.long 0x44++0x3
line.long 0x00 "ICSSG_USER_ADDR1_REG,MDIO User Address 1 Register"
hexmask.long.word 0x00 0.--15. 1. " USER_ADDR1           ,User Address 1."
group.long 0x80++0x3
line.long 0x00 "ICSSG_USER_ACCESS_REG_j,MDIO User Access j Register Offset = 80h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 31. " GO                   ,Go." "0,1"
bitfld.long 0x00 30. "         WRITE               ,Write enable." "0,1"
textline "                                        "
bitfld.long 0x00 29. " ACK                  ,Acknowledge." "0,1"
bitfld.long 0x00 21.--25. "         REGADR              ,Register address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                        "
bitfld.long 0x00 16.--20. " PHYADR               ,PHY address." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "        DATA                ,User data."
group.long 0x84++0x3
line.long 0x00 "ICSSG_USER_PHY_SEL_REG_j,MDIO User PHY Select j Register Offset = 84h + (j * 8h); where j = 0h to 1h"
bitfld.long 0x00 7. " LINKSEL              ,Link status determination select." "0,1"
bitfld.long 0x00 6. "         LINKINT_ENABLE      ,Link change interrupt enable." "0,1"
textline "                                        "
bitfld.long 0x00 0.--4. " PHYADR_MON           ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_G_RT"
tree "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base eaxi:0xB233000
width 35.
group.long 0x0++0x3
line.long 0x00 "ICSSG_ICSS_G_CFG,ICSSG Config"
bitfld.long 0x00 16. " SGMII_MODE                ,SGMII mode0: Fiber mode 1: SGMII mode" "0,1"
bitfld.long 0x00 10. "         RX_SFD_TX_SOF_EN         ,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RTU_PRU_PSI_SHARE_EN      ,Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO" "0,1"
bitfld.long 0x00 8. "         IEP1_TX_EN               ,Enable IEP1 for TX Enable0: Use IEP0 CMP3_4 1: Use IEP1 CMP3_4" "0,1"
textline "                                            "
bitfld.long 0x00 5.--6. " MII1_MODE                 ,MII1 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
bitfld.long 0x00 3.--4. "         MII0_MODE                ,MII0 mode0: MII 1: RGMII 2: SGMII" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2. " RX_L2_G_EN                ,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 1. "         TX_L2_EN                 ,Enable the TX L2 Fifo0: Disabled 1: Enabled" "0,1"
textline "                                            "
bitfld.long 0x00 0. " TX_L1_EN                  ,Enable the TX L1 Fifo0: Disabled 1: Enabled" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RGMII_CFG,RGMII"
bitfld.long 0x00 22. " RGMII1_FULLDUPLEX_IN      ,RGMII Fullduplex overide0: half 1: full" "0,1"
bitfld.long 0x00 21. "         RGMII1_GIG_IN            ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
textline "                                            "
bitfld.long 0x00 20. " RGMII1_INBAND             ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
bitfld.long 0x00 18. "         RGMII0_FULLDUPLEX_IN     ,RGMII Fullduplex overide0: half 1: full" "0,1"
textline "                                            "
bitfld.long 0x00 17. " RGMII0_GIG_IN             ,RGMII GigBit Enable0: 100 Mbs 1: 1000 Mbs" "0,1"
bitfld.long 0x00 16. "         RGMII0_INBAND            ,RGMII In BandEnable or Force0: InBAND is Disabled 1: InBAND Enable" "0,1"
textline "                                            "
bitfld.long 0x00 9. " RGMII_EEE_PHY_ONLY        ,RGMII Phy Only Low Power0: disable 1: enable" "0,1"
bitfld.long 0x00 8. "         RGMII_EEE_EN             ,RGMII Energy Efficient Enable0: disable 1: enable" "0,1"
textline "                                            "
bitfld.long 0x00 7. " RGMII1_FULLDUPLEX         ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
bitfld.long 0x00 5.--6. "         RGMII1_SPEED             ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 4. " RGMII1_LINK               ,RGMII Link Status0: link is down 1: link is up" "0,1"
bitfld.long 0x00 3. "         RGMII0_FULLDUPLEX        ,RGMII Fullduplex0: half duplex 1: full duplex" "0,1"
textline "                                            "
bitfld.long 0x00 1.--2. " RGMII0_SPEED              ,RGMII Speed00: 10Mpbs 01: 100Mpbs 10: 1000 Mpbs" "0,1,2,3"
bitfld.long 0x00 0. "         RGMII0_LINK              ,RGMII Link Status0: link is down 1: link is up" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_MAC_PRU0_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU0_0                ,MAC pru0 DA3:DA0 Used for SAV and DA match"
group.long 0xC++0x3
line.long 0x00 "ICSSG_MAC_PRU0_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU0_1                ,MAC pru0 DA5:DA4 Used for SAV and DA match"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MAC_PRU1_0,"
hexmask.long 0x00 0.--31. 1. " MAC_PRU1_0                ,MAC pru1 DA3:DA0 Used for SAV and DA match"
group.long 0x14++0x3
line.long 0x00 "ICSSG_MAC_PRU1_1,"
hexmask.long.word 0x00 0.--15. 1. " MAC_PRU1_1                ,MAC pru1 DA5:DA4 Used for SAV and DA match"
group.long 0x18++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_0,MAC_Interface_0"
hexmask.long 0x00 0.--31. 1. " MAC_INF_0                 ,MAC Host interface DA3:DA0 Used for SAV and DA match"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_MAC_INTERFACE_1,MAC_Interface_1"
hexmask.long.word 0x00 0.--15. 1. " MAC_INF_1                 ,MAC Host interface DA5:DA4 Used for SAV and DA match"
group.long 0x20++0x3
line.long 0x00 "ICSSG_PREEMPT_CFG,Preemption_Cfg"
hexmask.long.byte 0x00 24.--31. 1. " SMD_R                     ,Response frame TAG"
hexmask.long.byte 0x00 16.--23. 1. "        SMD_V                    ,Verification frame TAG"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " EXP_SMD                   ,None preemptable frame start, or express frame"
group.long 0x24++0x3
line.long 0x00 "ICSSG_SMDT1S_CFG,SMDType1SPreemptableFrameStartCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1S_3                  ,SMDT1S3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1S_2                 ,SMDT1S2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1S_1                  ,SMDT1S1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1S_0                 ,SMDT1S0 pattern"
group.long 0x28++0x3
line.long 0x00 "ICSSG_SMDT1C_CFG,SMDType1CNoneInitialFragCfg"
hexmask.long.byte 0x00 24.--31. 1. " SMDT1C_3                  ,SMDT1C3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        SMDT1C_2                 ,SMDT1C2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " SMDT1C_1                  ,SMDT1C1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        SMDT1C_0                 ,SMDT1C0 pattern"
group.long 0x34++0x3
line.long 0x00 "ICSSG_FRAG_CNT_CFG,FragCntCfg"
hexmask.long.byte 0x00 24.--31. 1. " FRAG_CNT_3                ,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "        FRAG_CNT_2               ,FRAG Cnt2 pattern"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " FRAG_CNT_1                ,FRAG Cnt1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "        FRAG_CNT_0               ,FRAG Cnt0 pattern"
group.long 0x40++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH0,PaStatPush0"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_0           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_0          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_0           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_0          ,pa"
group.long 0x44++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH1,PaStatPush1"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_1           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_1          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_1           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_1          ,pa"
group.long 0x48++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH2,PaStatPush2"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_2           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_2          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_2           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_2          ,pa"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_PA_STAT_PUSH3,PaStatPush3"
hexmask.long.byte 0x00 24.--31. 1. " PA_STAT_PUSH3_3           ,pa"
hexmask.long.byte 0x00 16.--23. 1. "        PA_STAT_PUSH2_3          ,pa"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " PA_STAT_PUSH1_3           ,pa"
hexmask.long.byte 0x00 0.--7. 1. "        PA_STAT_PUSH0_3          ,pa"
group.long 0x60++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG1,FDBCfg1"
hexmask.long.tbyte 0x00 8.--25. 1. " SMEM_VLAN_OFFSET          ,SMEM VLAN FID table base address"
bitfld.long 0x00 3.--6. "    FDB_HASH_SIZE            ,FDB hash size0:64 1:128 2:256 3:512 4:1024 5:2048" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
bitfld.long 0x00 0.--1. " FDB_BUCKET_SIZE           ,FDB buket size0:1 1:2 2:4 3:8" "0,1,2,3"
group.long 0x64++0x3
line.long 0x00 "ICSSG_FDB_GEN_CFG2,FDBCfg2"
bitfld.long 0x00 9.--12. " FDB_GEN_MODE_BYTE_EN      ,FDB General Mode Byte compare size0 = 1 Byte, 15 = 16 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "        FDB_GEN_MODE_EN_BK1      ,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
textline "                                            "
bitfld.long 0x00 7. " FDB_GEN_MODE_EN_BK0       ,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x00 6. "         FDB_VLAN_EN              ,FDB Global VLAN Enable" "0,1"
textline "                                            "
bitfld.long 0x00 5. " FDB_HSR_EN                ,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x00 2. "         FDB_HOST_EN              ,FDB HOST Enable" "0,1"
textline "                                            "
bitfld.long 0x00 1. " FDB_PRU1_EN               ,FDB PRU1 Enable" "0,1"
bitfld.long 0x00 0. "         FDB_PRU0_EN              ,FDB PRU0 Enable" "0,1"
group.long 0x68++0x3
line.long 0x00 "ICSSG_FDB_GEN_STATUS,FDBStatus"
group.long 0x6C++0x3
line.long 0x00 "ICSSG_FDB_DF_VLAN,FDBDefaultPRUVLAN"
hexmask.long.word 0x00 16.--27. 1. " FDB_PRU1_DF_VLAN          ,FDB Default VLAN for PRU1"
hexmask.long.word 0x00 0.--11. 1. "      FDB_PRU0_DF_VLAN         ,FDB Default VLAN for PRU0"
group.long 0x70++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA0,FDB_HOST_DA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_DA0              ,FDB HOST DA3:0"
group.long 0x74++0x3
line.long 0x00 "ICSSG_FDB_HOST_DA1,FDB_HOST_DA5:4_Cfg"
hexmask.long.word 0x00 0.--15. 1. " FDB_HOST_DA1              ,FDB HOST DA5:4"
group.long 0x78++0x3
line.long 0x00 "ICSSG_FDB_HOST_SA0,FDB_HOST_SA3:0_Cfg"
hexmask.long 0x00 0.--31. 1. " FDB_HOST_SA0              ,FDB HOST SA3:0"
group.long 0x7C++0x3
line.long 0x00 "ICSSG_FDB_HOST_VLAN_SA1,FDB_HOST_VLAN_SA5:4_Cfg"
hexmask.long.word 0x00 16.--31. 1. " FDB_HOST_VLAN_HSR         ,FDB HOST VLAN[11:0] OR HSR[15:0]"
hexmask.long.word 0x00 0.--15. 1. "      FDB_HOST_SA1             ,FDB HOST SA5:4"
group.long 0x80++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU0,Filter1StartandLengthPru0"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x84++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU0,Filter1ConfigPru0"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU0,Filter1_0_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x8C++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU0,Filter1_0_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x90++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU0,Filter1_0_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x94++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU0,Filter1_0_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x98++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU0,Filter1_1_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x9C++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU0,Filter1_1_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0xA0++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU0,Filter1_1_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xA4++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU0,Filter1_1_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xA8++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU0,Filter1_2_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0xAC++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU0,Filter1_2_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0xB0++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU0,Filter1_2_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xB4++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU0,Filter1_2_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xB8++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU0,Filter1_3_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0xBC++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU0,Filter1_3_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0xC0++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU0,Filter1_3_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xC4++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU0,Filter1_3_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xC8++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU0,Filter1_4_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0xCC++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU0,Filter1_4_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0xD0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU0,Filter1_4_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xD4++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU0,Filter1_4_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xD8++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU0,Filter1_5_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0xDC++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU0,Filter1_5_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0xE0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU0,Filter1_5_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xE4++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU0,Filter1_5_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xE8++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU0,Filter1_6_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0xEC++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU0,Filter1_6_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0xF0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU0,Filter1_6_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0xF4++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU0,Filter1_6_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0xF8++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU0,Filter1_7_DA0_Pru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0xFC++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU0,Filter1_7_DA1_Pru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x100++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU0,Filter1_7_DA0MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x104++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU0,Filter1_7_DA1MaskPru0"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x108++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU0,Filter3_0_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x10C++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU0,Filter3_0_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x110++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU0,Filter3_0_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x114++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU0,Filter3_0_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x118++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU0,Filter3_0_LenPru0"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x11C++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU0,Filter3_0_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x120++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU0,Filter3_0_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x124++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU0,Filter3_0_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x128++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU0,Filter3_1_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x12C++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU0,Filter3_1_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x130++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU0,Filter3_1_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x134++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU0,Filter3_1_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x138++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU0,Filter3_1_LenPru0"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x13C++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU0,Filter3_1_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x140++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU0,Filter3_1_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x144++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU0,Filter3_1_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x148++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU0,Filter3_2_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x14C++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU0,Filter3_2_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x150++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU0,Filter3_2_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x154++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU0,Filter3_2_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x158++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU0,Filter3_2_LenPru0"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x15C++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU0,Filter3_2_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x160++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU0,Filter3_2_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x164++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU0,Filter3_2_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x168++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU0,Filter3_3_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x16C++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU0,Filter3_3_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x170++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU0,Filter3_3_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x174++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU0,Filter3_3_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x178++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU0,Filter3_3_LenPru0"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x17C++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU0,Filter3_3_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x180++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU0,Filter3_3_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x184++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU0,Filter3_3_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x188++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU0,Filter3_4_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x18C++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU0,Filter3_4_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x190++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU0,Filter3_4_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x194++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU0,Filter3_4_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x198++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU0,Filter3_4_LenPru0"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x19C++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU0,Filter3_4_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1A0++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU0,Filter3_4_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1A4++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU0,Filter3_4_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1A8++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU0,Filter3_5_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1AC++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU0,Filter3_5_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1B0++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU0,Filter3_5_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1B4++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU0,Filter3_5_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1B8++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU0,Filter3_5_LenPru0"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1BC++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU0,Filter3_5_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1C0++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU0,Filter3_5_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1C4++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU0,Filter3_5_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1C8++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU0,Filter3_6_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1CC++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU0,Filter3_6_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1D0++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU0,Filter3_6_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1D4++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU0,Filter3_6_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1D8++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU0,Filter3_6_LenPru0"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1DC++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU0,Filter3_6_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x1E0++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU0,Filter3_6_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x1E4++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU0,Filter3_6_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x1E8++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU0,Filter3_7_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x1EC++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU0,Filter3_7_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x1F0++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU0,Filter3_7_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x1F4++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU0,Filter3_7_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x1F8++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU0,Filter3_7_LenPru0"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x1FC++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU0,Filter3_7_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x200++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU0,Filter3_7_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x204++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU0,Filter3_7_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x208++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU0,Filter3_8_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x20C++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU0,Filter3_8_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x210++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU0,Filter3_8_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x214++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU0,Filter3_8_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x218++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU0,Filter3_8_LenPru0"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x21C++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU0,Filter3_8_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x220++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU0,Filter3_8_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x224++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU0,Filter3_8_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x228++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU0,Filter3_9_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x22C++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU0,Filter3_9_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x230++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU0,Filter3_9_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x234++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU0,Filter3_9_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU0    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU0   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x238++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU0,Filter3_9_LenPru0"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU0     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU0  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU0  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x23C++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU0,Filter3_9_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x240++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU0,Filter3_9_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x244++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU0,Filter3_9_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x248++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU0,Filter3_10_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x24C++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU0,Filter3_10_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x250++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU0,Filter3_10_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x254++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU0,Filter3_10_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x258++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU0,Filter3_10_LenPru0"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x25C++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU0,Filter3_10_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x260++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU0,Filter3_10_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x264++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU0,Filter3_10_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x268++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU0,Filter3_11_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x26C++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU0,Filter3_11_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x270++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU0,Filter3_11_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x274++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU0,Filter3_11_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x278++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU0,Filter3_11_LenPru0"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x27C++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU0,Filter3_11_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x280++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU0,Filter3_11_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x284++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU0,Filter3_11_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x288++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU0,Filter3_12_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x28C++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU0,Filter3_12_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x290++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU0,Filter3_12_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x294++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU0,Filter3_12_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x298++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU0,Filter3_12_LenPru0"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x29C++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU0,Filter3_12_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2A0++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU0,Filter3_12_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2A4++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU0,Filter3_12_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2A8++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU0,Filter3_13_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2AC++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU0,Filter3_13_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2B0++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU0,Filter3_13_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2B4++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU0,Filter3_13_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2B8++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU0,Filter3_13_LenPru0"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2BC++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU0,Filter3_13_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2C0++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU0,Filter3_13_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2C4++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU0,Filter3_13_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2C8++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU0,Filter3_14_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2CC++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU0,Filter3_14_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2D0++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU0,Filter3_14_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2D4++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU0,Filter3_14_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2D8++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU0,Filter3_14_LenPru0"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2DC++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU0,Filter3_14_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x2E0++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU0,Filter3_14_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x2E4++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU0,Filter3_14_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x2E8++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU0,Filter3_15_StartPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x2EC++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU0,Filter3_15_StartAutoPru0"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x2F0++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU0,Filter3_15_StartoffsetPru0"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x2F4++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU0,Filter3_15_JmpoffsetPru0"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU0   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU0  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x2F8++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU0,Filter3_15_LenPru0"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU0    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU0 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU0 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x2FC++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU0,Filter3_15_ConfigPru0"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x300++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU0,Filter3_15_TPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x304++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU0,Filter3_15_T_MaskPru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x308++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU0,Filter3_0P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x30C++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU0,Filter3_0P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x310++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x314++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x318++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU0,Filter3_1P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x31C++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU0,Filter3_1P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x320++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x324++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x328++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU0,Filter3_2P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x32C++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU0,Filter3_2P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x330++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x334++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x338++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU0,Filter3_3P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x33C++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU0,Filter3_3P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x340++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x344++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x348++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU0,Filter3_4P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x34C++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU0,Filter3_4P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x350++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x354++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x358++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU0,Filter3_5P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x35C++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU0,Filter3_5P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x360++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x364++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x368++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU0,Filter3_6P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x36C++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU0,Filter3_6P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x370++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x374++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x378++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU0,Filter3_7P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x37C++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU0,Filter3_7P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x380++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x384++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x388++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU0,Filter3_8P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x38C++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU0,Filter3_8P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x390++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x394++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x398++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU0,Filter3_9P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x39C++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU0,Filter3_9P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x3A0++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3A4++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3A8++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU0,Filter3_10P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x3AC++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU0,Filter3_10P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x3B0++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3B4++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3B8++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU0,Filter3_11P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x3BC++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU0,Filter3_11P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x3C0++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3C4++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3C8++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU0,Filter3_12P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x3CC++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU0,Filter3_12P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x3D0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3D4++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3D8++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU0,Filter3_13P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x3DC++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU0,Filter3_13P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x3E0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3E4++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3E8++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU0,Filter3_14P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x3EC++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU0,Filter3_14P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x3F0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x3F4++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x3F8++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU0,Filter3_15P0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x3FC++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU0,Filter3_15P1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x400++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU0,Filter3P_Mask0Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x404++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU0,Filter3P_Mask1Pru0"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x408++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU0,FilterByteCountPru0"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU0            ,RX current filter Byte Count"
group.long 0x40C++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU0,rx_class0_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x410++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU0,rx_class0_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x414++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU0,rx_class1_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x418++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU0,rx_class1_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x41C++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU0,rx_class2_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x420++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU0,rx_class2_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x424++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU0,rx_class3_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x428++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU0,rx_class3_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x42C++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU0,rx_class4_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x430++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU0,rx_class4_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0x434++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU0,rx_class5_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0x438++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU0,rx_class5_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0x43C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU0,rx_class6_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0x440++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU0,rx_class6_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0x444++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU0,rx_class7_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0x448++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU0,rx_class7_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0x44C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU0,rx_class8_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0x450++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU0,rx_class8_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0x454++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU0,rx_class9_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0x458++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU0,rx_class9_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0x45C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU0,rx_class10_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0x460++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU0,rx_class10_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0x464++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU0,rx_class11_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0x468++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU0,rx_class11_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0x46C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU0,rx_class12_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0x470++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU0,rx_class12_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0x474++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU0,rx_class13_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0x478++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU0,rx_class13_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0x47C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU0,rx_class14_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0x480++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU0,rx_class14_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0x484++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU0,rx_class15_and_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0x488++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU0,rx_class15_or_enablesPru0"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0x48C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU0,rx_class_cfg1Pru0"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0x490++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU0,rx_class_cfg2Pru0"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0x494++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x498++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x49C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4A8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4AC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4B8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4BC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C4++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4C8++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4CC++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D0++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU0,rx_class_gate_cfgPru0"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D4++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU0,RX_greenPru0"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4D8++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU0,SAHashPru0"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0x4DC++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU0,ConnectionHashPru0"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0x4E0++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU0,ConnectionHashStartPru0"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0x4E4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU0,RX_RateConfiguration0Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4E8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU0,RX_RateConfiguration1Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4EC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU0,RX_RateConfiguration2Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU0,RX_RateConfiguration3Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU0,RX_RateConfiguration4Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4F8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU0,RX_RateConfiguration5Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x4FC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU0,RX_RateConfiguration6Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x500++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU0,RX_RateConfiguration7Pru0"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x504++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU0,RX_RateSourceSelect0Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x508++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU0,RX_RateSourceSelect1Pru0"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU0,TX_RateConfiguration1_0Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x510++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU0,TX_RateConfiguration2_0Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0x514++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU0,TX_RateConfiguration1_1Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x518++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU0,TX_RateConfiguration2_1Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0x51C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU0,TX_RateConfiguration1_2Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x520++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU0,TX_RateConfiguration2_2Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0x524++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU0,TX_RateConfiguration1_3Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x528++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU0,TX_RateConfiguration2_3Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0x52C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU0,TX_RateConfiguration1_4Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x530++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU0,TX_RateConfiguration2_4Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0x534++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU0,TX_RateConfiguration1_5Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x538++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU0,TX_RateConfiguration2_5Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0x53C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU0,TX_RateConfiguration1_6Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x540++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU0,TX_RateConfiguration2_6Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0x544++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU0,TX_RateConfiguration1_7Pru0"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0x548++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU0,TX_RateConfiguration2_7Pru0"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0x54C++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU0,RXGoodFrameCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0x550++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU0,RXBCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0x554++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU0,RXMCFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0x558++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU0,RXCRCErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0x55C++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU0,RXMIIErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0x560++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU0,RXOddNibbleFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0x564++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU0,RXMaxSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0x568++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU0,RXMaxSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0x56C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU0,RXMinSizeFramePru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0x570++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU0,RXMinSizeErrFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0x574++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU0,RXoverrunFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0x578++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU0       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0x57C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU0       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0x580++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU0       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0x584++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU0       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0x588++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU0       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0x58C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU0       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0x590++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU0       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0x594++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU0       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0x598++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU0       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0x59C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU0       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0x5A0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU0      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0x5A4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU0      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0x5A8++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU0      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0x5AC++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU0      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0x5B0++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU0      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0x5B4++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU0,RXClass0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU0      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0x5B8++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU0,RXSMDFragErrCountPru0"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU0      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU0    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU0     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU0    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0x5BC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU0,RXBucket1SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0x5C0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU0,RXBucket2SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0x5C4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU0,RXBucket3SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0x5C8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU0,RXBucket4SizeConfigPru0"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0x5CC++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU0,RX64BSizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0x5D0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU0,RXBucket1SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0x5D4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU0,RXBucket2SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x5D8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU0,RXBucket3SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x5DC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU0,RXBucket4SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x5E0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU0,RXBucket5SizedFrameCountPru0"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0x5E4++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU0,RXTotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0x5E8++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU0,RX_TX_TotalByteCountPru0"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0x5EC++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT0,TXGoodFrameCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0x5F0++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT0,TXBCFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0x5F4++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT0,TXMFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0x5F8++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT0,TXOddNibbleFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0x5FC++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT0,TXUnderFlowErrCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0x600++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT0,TXMaxSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0x604++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT0,TXMaxSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0x608++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT0,TXMinSizeFramePort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0x60C++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT0,TXMinSizeErrFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0x610++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT0,TXBucket1SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0x614++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT0,TXBucket2SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0x618++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT0,TXBucket3SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0x61C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT0,TXBucket4SizeConfigPort0"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0x620++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT0,TX64BSizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0x624++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT0,TXBucket1SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0x628++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT0,TXBucket2SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0x62C++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT0,TXBucket3SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0x630++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT0,TXBucket4SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0x634++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT0,TXBucket5SizedFrameCountPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0x638++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT0,TXTotalByteCountPort0"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0x63C++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT0,TXHSRTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0x640++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT0,TXHSRSeqPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0x644++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT0,TXVLANTYPETAGPort0"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0x648++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT0,TXVLANINSTAGPort0"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
group.long 0x64C++0x3
line.long 0x00 "ICSSG_FT1_START_LEN_PRU1,Filter1StartandLengthPru1"
bitfld.long 0x00 16.--19. " FT1_LEN                   ,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--14. 1. "        FT1_START                ,Byte count start for Filter1.Any wrt will clear all Filter1 Status Bits"
group.long 0x650++0x3
line.long 0x00 "ICSSG_FT1_CFG_PRU1,Filter1ConfigPru1"
bitfld.long 0x00 14.--15. " FT1_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 12.--13. "         FT1_6CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " FT1_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 8.--9. "         FT1_4CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " FT1_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 4.--5. "         FT1_2CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " FT1_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
bitfld.long 0x00 0.--1. "         FT1_0CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x654++0x3
line.long 0x00 "ICSSG_FT1_0_DA0_PRU1,Filter1_0_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA0                 ,Filter1 DA4:DA1"
group.long 0x658++0x3
line.long 0x00 "ICSSG_FT1_0_DA1_PRU1,Filter1_0_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA1                 ,Filter1 DA6:DA5"
group.long 0x65C++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK0_PRU1,Filter1_0_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_0_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x660++0x3
line.long 0x00 "ICSSG_FT1_0_DA_MASK1_PRU1,Filter1_0_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_0_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x664++0x3
line.long 0x00 "ICSSG_FT1_1_DA0_PRU1,Filter1_1_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA0                 ,Filter1 DA4:DA1"
group.long 0x668++0x3
line.long 0x00 "ICSSG_FT1_1_DA1_PRU1,Filter1_1_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA1                 ,Filter1 DA6:DA5"
group.long 0x66C++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK0_PRU1,Filter1_1_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_1_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x670++0x3
line.long 0x00 "ICSSG_FT1_1_DA_MASK1_PRU1,Filter1_1_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_1_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x674++0x3
line.long 0x00 "ICSSG_FT1_2_DA0_PRU1,Filter1_2_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA0                 ,Filter1 DA4:DA1"
group.long 0x678++0x3
line.long 0x00 "ICSSG_FT1_2_DA1_PRU1,Filter1_2_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA1                 ,Filter1 DA6:DA5"
group.long 0x67C++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK0_PRU1,Filter1_2_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_2_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x680++0x3
line.long 0x00 "ICSSG_FT1_2_DA_MASK1_PRU1,Filter1_2_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_2_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x684++0x3
line.long 0x00 "ICSSG_FT1_3_DA0_PRU1,Filter1_3_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA0                 ,Filter1 DA4:DA1"
group.long 0x688++0x3
line.long 0x00 "ICSSG_FT1_3_DA1_PRU1,Filter1_3_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA1                 ,Filter1 DA6:DA5"
group.long 0x68C++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK0_PRU1,Filter1_3_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_3_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x690++0x3
line.long 0x00 "ICSSG_FT1_3_DA_MASK1_PRU1,Filter1_3_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_3_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x694++0x3
line.long 0x00 "ICSSG_FT1_4_DA0_PRU1,Filter1_4_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA0                 ,Filter1 DA4:DA1"
group.long 0x698++0x3
line.long 0x00 "ICSSG_FT1_4_DA1_PRU1,Filter1_4_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA1                 ,Filter1 DA6:DA5"
group.long 0x69C++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK0_PRU1,Filter1_4_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_4_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6A0++0x3
line.long 0x00 "ICSSG_FT1_4_DA_MASK1_PRU1,Filter1_4_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_4_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6A4++0x3
line.long 0x00 "ICSSG_FT1_5_DA0_PRU1,Filter1_5_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA0                 ,Filter1 DA4:DA1"
group.long 0x6A8++0x3
line.long 0x00 "ICSSG_FT1_5_DA1_PRU1,Filter1_5_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA1                 ,Filter1 DA6:DA5"
group.long 0x6AC++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK0_PRU1,Filter1_5_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_5_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6B0++0x3
line.long 0x00 "ICSSG_FT1_5_DA_MASK1_PRU1,Filter1_5_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_5_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6B4++0x3
line.long 0x00 "ICSSG_FT1_6_DA0_PRU1,Filter1_6_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA0                 ,Filter1 DA4:DA1"
group.long 0x6B8++0x3
line.long 0x00 "ICSSG_FT1_6_DA1_PRU1,Filter1_6_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA1                 ,Filter1 DA6:DA5"
group.long 0x6BC++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK0_PRU1,Filter1_6_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_6_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6C0++0x3
line.long 0x00 "ICSSG_FT1_6_DA_MASK1_PRU1,Filter1_6_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_6_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6C4++0x3
line.long 0x00 "ICSSG_FT1_7_DA0_PRU1,Filter1_7_DA0_Pru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA0                 ,Filter1 DA4:DA1"
group.long 0x6C8++0x3
line.long 0x00 "ICSSG_FT1_7_DA1_PRU1,Filter1_7_DA1_Pru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA1                 ,Filter1 DA6:DA5"
group.long 0x6CC++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK0_PRU1,Filter1_7_DA0MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT1_7_DA_MASK0            ,Filter1 MDA4:MDA1 set to 1 to mask that bit"
group.long 0x6D0++0x3
line.long 0x00 "ICSSG_FT1_7_DA_MASK1_PRU1,Filter1_7_DA1MaskPru1"
hexmask.long.word 0x00 0.--15. 1. " FT1_7_DA_MASK1            ,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6D4++0x3
line.long 0x00 "ICSSG_FT3_0_START_PRU1,Filter3_0_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6D8++0x3
line.long 0x00 "ICSSG_FT3_0_START_AUTO_PRU1,Filter3_0_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6DC++0x3
line.long 0x00 "ICSSG_FT3_0_START_LEN_PRU1,Filter3_0_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x6E0++0x3
line.long 0x00 "ICSSG_FT3_0_JMP_OFFSET_PRU1,Filter3_0_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_0_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_0_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x6E4++0x3
line.long 0x00 "ICSSG_FT3_0_LEN_PRU1,Filter3_0_LenPru1"
bitfld.long 0x00 24. " FT3_0_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_0_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_0_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x6E8++0x3
line.long 0x00 "ICSSG_FT3_0_CFG_PRU1,Filter3_0_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_0_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_0_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_0CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x6EC++0x3
line.long 0x00 "ICSSG_FT3_0_T_PRU1,Filter3_0_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x6F0++0x3
line.long 0x00 "ICSSG_FT3_0_T_MASK_PRU1,Filter3_0_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x6F4++0x3
line.long 0x00 "ICSSG_FT3_1_START_PRU1,Filter3_1_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x6F8++0x3
line.long 0x00 "ICSSG_FT3_1_START_AUTO_PRU1,Filter3_1_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x6FC++0x3
line.long 0x00 "ICSSG_FT3_1_START_LEN_PRU1,Filter3_1_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x700++0x3
line.long 0x00 "ICSSG_FT3_1_JMP_OFFSET_PRU1,Filter3_1_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_1_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_1_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x704++0x3
line.long 0x00 "ICSSG_FT3_1_LEN_PRU1,Filter3_1_LenPru1"
bitfld.long 0x00 24. " FT3_1_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_1_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_1_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x708++0x3
line.long 0x00 "ICSSG_FT3_1_CFG_PRU1,Filter3_1_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_1_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_1_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_1CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x70C++0x3
line.long 0x00 "ICSSG_FT3_1_T_PRU1,Filter3_1_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x710++0x3
line.long 0x00 "ICSSG_FT3_1_T_MASK_PRU1,Filter3_1_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x714++0x3
line.long 0x00 "ICSSG_FT3_2_START_PRU1,Filter3_2_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x718++0x3
line.long 0x00 "ICSSG_FT3_2_START_AUTO_PRU1,Filter3_2_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x71C++0x3
line.long 0x00 "ICSSG_FT3_2_START_LEN_PRU1,Filter3_2_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x720++0x3
line.long 0x00 "ICSSG_FT3_2_JMP_OFFSET_PRU1,Filter3_2_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_2_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_2_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x724++0x3
line.long 0x00 "ICSSG_FT3_2_LEN_PRU1,Filter3_2_LenPru1"
bitfld.long 0x00 24. " FT3_2_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_2_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_2_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x728++0x3
line.long 0x00 "ICSSG_FT3_2_CFG_PRU1,Filter3_2_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_2_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_2_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_2CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x72C++0x3
line.long 0x00 "ICSSG_FT3_2_T_PRU1,Filter3_2_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x730++0x3
line.long 0x00 "ICSSG_FT3_2_T_MASK_PRU1,Filter3_2_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x734++0x3
line.long 0x00 "ICSSG_FT3_3_START_PRU1,Filter3_3_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x738++0x3
line.long 0x00 "ICSSG_FT3_3_START_AUTO_PRU1,Filter3_3_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x73C++0x3
line.long 0x00 "ICSSG_FT3_3_START_LEN_PRU1,Filter3_3_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x740++0x3
line.long 0x00 "ICSSG_FT3_3_JMP_OFFSET_PRU1,Filter3_3_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_3_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_3_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x744++0x3
line.long 0x00 "ICSSG_FT3_3_LEN_PRU1,Filter3_3_LenPru1"
bitfld.long 0x00 24. " FT3_3_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_3_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_3_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x748++0x3
line.long 0x00 "ICSSG_FT3_3_CFG_PRU1,Filter3_3_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_3_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_3_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_3CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x74C++0x3
line.long 0x00 "ICSSG_FT3_3_T_PRU1,Filter3_3_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x750++0x3
line.long 0x00 "ICSSG_FT3_3_T_MASK_PRU1,Filter3_3_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x754++0x3
line.long 0x00 "ICSSG_FT3_4_START_PRU1,Filter3_4_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x758++0x3
line.long 0x00 "ICSSG_FT3_4_START_AUTO_PRU1,Filter3_4_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x75C++0x3
line.long 0x00 "ICSSG_FT3_4_START_LEN_PRU1,Filter3_4_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x760++0x3
line.long 0x00 "ICSSG_FT3_4_JMP_OFFSET_PRU1,Filter3_4_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_4_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_4_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x764++0x3
line.long 0x00 "ICSSG_FT3_4_LEN_PRU1,Filter3_4_LenPru1"
bitfld.long 0x00 24. " FT3_4_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_4_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_4_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x768++0x3
line.long 0x00 "ICSSG_FT3_4_CFG_PRU1,Filter3_4_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_4_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_4_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_4CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x76C++0x3
line.long 0x00 "ICSSG_FT3_4_T_PRU1,Filter3_4_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x770++0x3
line.long 0x00 "ICSSG_FT3_4_T_MASK_PRU1,Filter3_4_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x774++0x3
line.long 0x00 "ICSSG_FT3_5_START_PRU1,Filter3_5_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x778++0x3
line.long 0x00 "ICSSG_FT3_5_START_AUTO_PRU1,Filter3_5_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x77C++0x3
line.long 0x00 "ICSSG_FT3_5_START_LEN_PRU1,Filter3_5_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x780++0x3
line.long 0x00 "ICSSG_FT3_5_JMP_OFFSET_PRU1,Filter3_5_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_5_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_5_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x784++0x3
line.long 0x00 "ICSSG_FT3_5_LEN_PRU1,Filter3_5_LenPru1"
bitfld.long 0x00 24. " FT3_5_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_5_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_5_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x788++0x3
line.long 0x00 "ICSSG_FT3_5_CFG_PRU1,Filter3_5_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_5_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_5_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_5CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x78C++0x3
line.long 0x00 "ICSSG_FT3_5_T_PRU1,Filter3_5_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x790++0x3
line.long 0x00 "ICSSG_FT3_5_T_MASK_PRU1,Filter3_5_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x794++0x3
line.long 0x00 "ICSSG_FT3_6_START_PRU1,Filter3_6_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x798++0x3
line.long 0x00 "ICSSG_FT3_6_START_AUTO_PRU1,Filter3_6_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x79C++0x3
line.long 0x00 "ICSSG_FT3_6_START_LEN_PRU1,Filter3_6_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7A0++0x3
line.long 0x00 "ICSSG_FT3_6_JMP_OFFSET_PRU1,Filter3_6_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_6_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_6_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7A4++0x3
line.long 0x00 "ICSSG_FT3_6_LEN_PRU1,Filter3_6_LenPru1"
bitfld.long 0x00 24. " FT3_6_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_6_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_6_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7A8++0x3
line.long 0x00 "ICSSG_FT3_6_CFG_PRU1,Filter3_6_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_6_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_6_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_6CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7AC++0x3
line.long 0x00 "ICSSG_FT3_6_T_PRU1,Filter3_6_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7B0++0x3
line.long 0x00 "ICSSG_FT3_6_T_MASK_PRU1,Filter3_6_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7B4++0x3
line.long 0x00 "ICSSG_FT3_7_START_PRU1,Filter3_7_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7B8++0x3
line.long 0x00 "ICSSG_FT3_7_START_AUTO_PRU1,Filter3_7_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7BC++0x3
line.long 0x00 "ICSSG_FT3_7_START_LEN_PRU1,Filter3_7_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7C0++0x3
line.long 0x00 "ICSSG_FT3_7_JMP_OFFSET_PRU1,Filter3_7_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_7_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_7_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7C4++0x3
line.long 0x00 "ICSSG_FT3_7_LEN_PRU1,Filter3_7_LenPru1"
bitfld.long 0x00 24. " FT3_7_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_7_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_7_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7C8++0x3
line.long 0x00 "ICSSG_FT3_7_CFG_PRU1,Filter3_7_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_7_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_7_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_7CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7CC++0x3
line.long 0x00 "ICSSG_FT3_7_T_PRU1,Filter3_7_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7D0++0x3
line.long 0x00 "ICSSG_FT3_7_T_MASK_PRU1,Filter3_7_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7D4++0x3
line.long 0x00 "ICSSG_FT3_8_START_PRU1,Filter3_8_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7D8++0x3
line.long 0x00 "ICSSG_FT3_8_START_AUTO_PRU1,Filter3_8_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7DC++0x3
line.long 0x00 "ICSSG_FT3_8_START_LEN_PRU1,Filter3_8_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x7E0++0x3
line.long 0x00 "ICSSG_FT3_8_JMP_OFFSET_PRU1,Filter3_8_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_8_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_8_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x7E4++0x3
line.long 0x00 "ICSSG_FT3_8_LEN_PRU1,Filter3_8_LenPru1"
bitfld.long 0x00 24. " FT3_8_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_8_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_8_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x7E8++0x3
line.long 0x00 "ICSSG_FT3_8_CFG_PRU1,Filter3_8_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_8_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_8_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_8CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x7EC++0x3
line.long 0x00 "ICSSG_FT3_8_T_PRU1,Filter3_8_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x7F0++0x3
line.long 0x00 "ICSSG_FT3_8_T_MASK_PRU1,Filter3_8_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x7F4++0x3
line.long 0x00 "ICSSG_FT3_9_START_PRU1,Filter3_9_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x7F8++0x3
line.long 0x00 "ICSSG_FT3_9_START_AUTO_PRU1,Filter3_9_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x7FC++0x3
line.long 0x00 "ICSSG_FT3_9_START_LEN_PRU1,Filter3_9_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x800++0x3
line.long 0x00 "ICSSG_FT3_9_JMP_OFFSET_PRU1,Filter3_9_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_9_NJMP_OFFSET_PRU1    ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_9_IJMP_OFFSET_PRU1   ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x804++0x3
line.long 0x00 "ICSSG_FT3_9_LEN_PRU1,Filter3_9_LenPru1"
bitfld.long 0x00 24. " FT3_9_LEN_BIG_EN_PRU1     ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_9_LEN_SIZE_BIT_PRU1  ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_9_LEN_START_BIT_PRU1  ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x808++0x3
line.long 0x00 "ICSSG_FT3_9_CFG_PRU1,Filter3_9_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_9_TRIG_OR_EN          ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_9_VLAN_SKIP_EN       ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_9CFG                  ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x80C++0x3
line.long 0x00 "ICSSG_FT3_9_T_PRU1,Filter3_9_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T                   ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x810++0x3
line.long 0x00 "ICSSG_FT3_9_T_MASK_PRU1,Filter3_9_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_T_MASK              ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x814++0x3
line.long 0x00 "ICSSG_FT3_10_START_PRU1,Filter3_10_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x818++0x3
line.long 0x00 "ICSSG_FT3_10_START_AUTO_PRU1,Filter3_10_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x81C++0x3
line.long 0x00 "ICSSG_FT3_10_START_LEN_PRU1,Filter3_10_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x820++0x3
line.long 0x00 "ICSSG_FT3_10_JMP_OFFSET_PRU1,Filter3_10_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_10_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_10_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x824++0x3
line.long 0x00 "ICSSG_FT3_10_LEN_PRU1,Filter3_10_LenPru1"
bitfld.long 0x00 24. " FT3_10_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_10_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_10_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x828++0x3
line.long 0x00 "ICSSG_FT3_10_CFG_PRU1,Filter3_10_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_10_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_10_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_10CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x82C++0x3
line.long 0x00 "ICSSG_FT3_10_T_PRU1,Filter3_10_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x830++0x3
line.long 0x00 "ICSSG_FT3_10_T_MASK_PRU1,Filter3_10_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x834++0x3
line.long 0x00 "ICSSG_FT3_11_START_PRU1,Filter3_11_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_FT3_11_START_AUTO_PRU1,Filter3_11_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x83C++0x3
line.long 0x00 "ICSSG_FT3_11_START_LEN_PRU1,Filter3_11_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x840++0x3
line.long 0x00 "ICSSG_FT3_11_JMP_OFFSET_PRU1,Filter3_11_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_11_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_11_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x844++0x3
line.long 0x00 "ICSSG_FT3_11_LEN_PRU1,Filter3_11_LenPru1"
bitfld.long 0x00 24. " FT3_11_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_11_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_11_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x848++0x3
line.long 0x00 "ICSSG_FT3_11_CFG_PRU1,Filter3_11_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_11_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_11_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_11CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x84C++0x3
line.long 0x00 "ICSSG_FT3_11_T_PRU1,Filter3_11_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x850++0x3
line.long 0x00 "ICSSG_FT3_11_T_MASK_PRU1,Filter3_11_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x854++0x3
line.long 0x00 "ICSSG_FT3_12_START_PRU1,Filter3_12_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x858++0x3
line.long 0x00 "ICSSG_FT3_12_START_AUTO_PRU1,Filter3_12_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x85C++0x3
line.long 0x00 "ICSSG_FT3_12_START_LEN_PRU1,Filter3_12_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x860++0x3
line.long 0x00 "ICSSG_FT3_12_JMP_OFFSET_PRU1,Filter3_12_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_12_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_12_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x864++0x3
line.long 0x00 "ICSSG_FT3_12_LEN_PRU1,Filter3_12_LenPru1"
bitfld.long 0x00 24. " FT3_12_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_12_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_12_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x868++0x3
line.long 0x00 "ICSSG_FT3_12_CFG_PRU1,Filter3_12_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_12_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_12_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_12CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x86C++0x3
line.long 0x00 "ICSSG_FT3_12_T_PRU1,Filter3_12_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x870++0x3
line.long 0x00 "ICSSG_FT3_12_T_MASK_PRU1,Filter3_12_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x874++0x3
line.long 0x00 "ICSSG_FT3_13_START_PRU1,Filter3_13_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x878++0x3
line.long 0x00 "ICSSG_FT3_13_START_AUTO_PRU1,Filter3_13_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x87C++0x3
line.long 0x00 "ICSSG_FT3_13_START_LEN_PRU1,Filter3_13_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x880++0x3
line.long 0x00 "ICSSG_FT3_13_JMP_OFFSET_PRU1,Filter3_13_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_13_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_13_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x884++0x3
line.long 0x00 "ICSSG_FT3_13_LEN_PRU1,Filter3_13_LenPru1"
bitfld.long 0x00 24. " FT3_13_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_13_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_13_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x888++0x3
line.long 0x00 "ICSSG_FT3_13_CFG_PRU1,Filter3_13_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_13_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_13_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_13CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x88C++0x3
line.long 0x00 "ICSSG_FT3_13_T_PRU1,Filter3_13_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x890++0x3
line.long 0x00 "ICSSG_FT3_13_T_MASK_PRU1,Filter3_13_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x894++0x3
line.long 0x00 "ICSSG_FT3_14_START_PRU1,Filter3_14_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x898++0x3
line.long 0x00 "ICSSG_FT3_14_START_AUTO_PRU1,Filter3_14_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x89C++0x3
line.long 0x00 "ICSSG_FT3_14_START_LEN_PRU1,Filter3_14_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8A0++0x3
line.long 0x00 "ICSSG_FT3_14_JMP_OFFSET_PRU1,Filter3_14_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_14_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_14_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8A4++0x3
line.long 0x00 "ICSSG_FT3_14_LEN_PRU1,Filter3_14_LenPru1"
bitfld.long 0x00 24. " FT3_14_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_14_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_14_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8A8++0x3
line.long 0x00 "ICSSG_FT3_14_CFG_PRU1,Filter3_14_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_14_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_14_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_14CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8AC++0x3
line.long 0x00 "ICSSG_FT3_14_T_PRU1,Filter3_14_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8B0++0x3
line.long 0x00 "ICSSG_FT3_14_T_MASK_PRU1,Filter3_14_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8B4++0x3
line.long 0x00 "ICSSG_FT3_15_START_PRU1,Filter3_15_StartPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START                 ,Byte count start for Filter3.Any wrt will clear all Filter3 Status Bits SW can read to determine next start during Auto"
rgroup.long 0x8B8++0x3
line.long 0x00 "ICSSG_FT3_15_START_AUTO_PRU1,Filter3_15_StartAutoPru1"
hexmask.long.word 0x00 0.--14. 1. " FT3_START_AUTO            ,Byte count start for Auto skip mode"
group.long 0x8BC++0x3
line.long 0x00 "ICSSG_FT3_15_START_LEN_PRU1,Filter3_15_StartoffsetPru1"
bitfld.long 0x00 20.--22. " FT3_OFFSET_END            ,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "         FT3_OFFSET_START         ,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
textline "                                            "
hexmask.long.word 0x00 0.--14. 1. " FT3_OFFSET                ,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
group.long 0x8C0++0x3
line.long 0x00 "ICSSG_FT3_15_JMP_OFFSET_PRU1,Filter3_15_JmpoffsetPru1"
hexmask.long.word 0x00 16.--30. 1. " FT3_15_NJMP_OFFSET_PRU1   ,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x00 0.--14. 1. "      FT3_15_IJMP_OFFSET_PRU1  ,Defines the Intial Offset to compare when auto arm jump is enabled"
group.long 0x8C4++0x3
line.long 0x00 "ICSSG_FT3_15_LEN_PRU1,Filter3_15_LenPru1"
bitfld.long 0x00 24. " FT3_15_LEN_BIG_EN_PRU1    ,Enable Big Indian on Length" "0,1"
bitfld.long 0x00 16.--19. "         FT3_15_LEN_SIZE_BIT_PRU1 ,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                            "
hexmask.long.word 0x00 0.--8. 1. " FT3_15_LEN_START_BIT_PRU1 ,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
group.long 0x8C8++0x3
line.long 0x00 "ICSSG_FT3_15_CFG_PRU1,Filter3_15_ConfigPru1"
hexmask.long.word 0x00 16.--31. 1. " FT3_15_TRIG_OR_EN         ,Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x00 2. "      FT3_15_VLAN_SKIP_EN      ,0: Disabled 1: Enable" "0,1"
textline "                                            "
bitfld.long 0x00 0.--1. " FT3_15CFG                 ,0: Disabled 1: EQ 2: GT 3: LT" "0,1,2,3"
group.long 0x8CC++0x3
line.long 0x00 "ICSSG_FT3_15_T_PRU1,Filter3_15_TPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T                  ,Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled"
group.long 0x8D0++0x3
line.long 0x00 "ICSSG_FT3_15_T_MASK_PRU1,Filter3_15_T_MaskPru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_T_MASK             ,Filter3 MT4:MT1 Note if Auto Skip is enabled then Type filter is not enabled set to 1 to mask that bit"
group.long 0x8D4++0x3
line.long 0x00 "ICSSG_FT3_0_P0_PRU1,Filter3_0P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P0                  ,Filter3 P4:P1"
group.long 0x8D8++0x3
line.long 0x00 "ICSSG_FT3_0_P1_PRU1,Filter3_0P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P1                  ,Filter3 P8:P5"
group.long 0x8DC++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8E0++0x3
line.long 0x00 "ICSSG_FT3_0_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_0_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8E4++0x3
line.long 0x00 "ICSSG_FT3_1_P0_PRU1,Filter3_1P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P0                  ,Filter3 P4:P1"
group.long 0x8E8++0x3
line.long 0x00 "ICSSG_FT3_1_P1_PRU1,Filter3_1P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P1                  ,Filter3 P8:P5"
group.long 0x8EC++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x8F0++0x3
line.long 0x00 "ICSSG_FT3_1_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_1_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x8F4++0x3
line.long 0x00 "ICSSG_FT3_2_P0_PRU1,Filter3_2P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P0                  ,Filter3 P4:P1"
group.long 0x8F8++0x3
line.long 0x00 "ICSSG_FT3_2_P1_PRU1,Filter3_2P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P1                  ,Filter3 P8:P5"
group.long 0x8FC++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x900++0x3
line.long 0x00 "ICSSG_FT3_2_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_2_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x904++0x3
line.long 0x00 "ICSSG_FT3_3_P0_PRU1,Filter3_3P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P0                  ,Filter3 P4:P1"
group.long 0x908++0x3
line.long 0x00 "ICSSG_FT3_3_P1_PRU1,Filter3_3P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P1                  ,Filter3 P8:P5"
group.long 0x90C++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x910++0x3
line.long 0x00 "ICSSG_FT3_3_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_3_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x914++0x3
line.long 0x00 "ICSSG_FT3_4_P0_PRU1,Filter3_4P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P0                  ,Filter3 P4:P1"
group.long 0x918++0x3
line.long 0x00 "ICSSG_FT3_4_P1_PRU1,Filter3_4P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P1                  ,Filter3 P8:P5"
group.long 0x91C++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x920++0x3
line.long 0x00 "ICSSG_FT3_4_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_4_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x924++0x3
line.long 0x00 "ICSSG_FT3_5_P0_PRU1,Filter3_5P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P0                  ,Filter3 P4:P1"
group.long 0x928++0x3
line.long 0x00 "ICSSG_FT3_5_P1_PRU1,Filter3_5P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P1                  ,Filter3 P8:P5"
group.long 0x92C++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x930++0x3
line.long 0x00 "ICSSG_FT3_5_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_5_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x934++0x3
line.long 0x00 "ICSSG_FT3_6_P0_PRU1,Filter3_6P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P0                  ,Filter3 P4:P1"
group.long 0x938++0x3
line.long 0x00 "ICSSG_FT3_6_P1_PRU1,Filter3_6P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P1                  ,Filter3 P8:P5"
group.long 0x93C++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x940++0x3
line.long 0x00 "ICSSG_FT3_6_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_6_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x944++0x3
line.long 0x00 "ICSSG_FT3_7_P0_PRU1,Filter3_7P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P0                  ,Filter3 P4:P1"
group.long 0x948++0x3
line.long 0x00 "ICSSG_FT3_7_P1_PRU1,Filter3_7P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P1                  ,Filter3 P8:P5"
group.long 0x94C++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x950++0x3
line.long 0x00 "ICSSG_FT3_7_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_7_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x954++0x3
line.long 0x00 "ICSSG_FT3_8_P0_PRU1,Filter3_8P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P0                  ,Filter3 P4:P1"
group.long 0x958++0x3
line.long 0x00 "ICSSG_FT3_8_P1_PRU1,Filter3_8P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P1                  ,Filter3 P8:P5"
group.long 0x95C++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x960++0x3
line.long 0x00 "ICSSG_FT3_8_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_8_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x964++0x3
line.long 0x00 "ICSSG_FT3_9_P0_PRU1,Filter3_9P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P0                  ,Filter3 P4:P1"
group.long 0x968++0x3
line.long 0x00 "ICSSG_FT3_9_P1_PRU1,Filter3_9P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P1                  ,Filter3 P8:P5"
group.long 0x96C++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK0             ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x970++0x3
line.long 0x00 "ICSSG_FT3_9_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_9_P_MASK1             ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x974++0x3
line.long 0x00 "ICSSG_FT3_10_P0_PRU1,Filter3_10P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P0                 ,Filter3 P4:P1"
group.long 0x978++0x3
line.long 0x00 "ICSSG_FT3_10_P1_PRU1,Filter3_10P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P1                 ,Filter3 P8:P5"
group.long 0x97C++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x980++0x3
line.long 0x00 "ICSSG_FT3_10_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_10_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x984++0x3
line.long 0x00 "ICSSG_FT3_11_P0_PRU1,Filter3_11P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P0                 ,Filter3 P4:P1"
group.long 0x988++0x3
line.long 0x00 "ICSSG_FT3_11_P1_PRU1,Filter3_11P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P1                 ,Filter3 P8:P5"
group.long 0x98C++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x990++0x3
line.long 0x00 "ICSSG_FT3_11_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_11_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x994++0x3
line.long 0x00 "ICSSG_FT3_12_P0_PRU1,Filter3_12P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P0                 ,Filter3 P4:P1"
group.long 0x998++0x3
line.long 0x00 "ICSSG_FT3_12_P1_PRU1,Filter3_12P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P1                 ,Filter3 P8:P5"
group.long 0x99C++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9A0++0x3
line.long 0x00 "ICSSG_FT3_12_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_12_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9A4++0x3
line.long 0x00 "ICSSG_FT3_13_P0_PRU1,Filter3_13P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P0                 ,Filter3 P4:P1"
group.long 0x9A8++0x3
line.long 0x00 "ICSSG_FT3_13_P1_PRU1,Filter3_13P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P1                 ,Filter3 P8:P5"
group.long 0x9AC++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9B0++0x3
line.long 0x00 "ICSSG_FT3_13_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_13_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9B4++0x3
line.long 0x00 "ICSSG_FT3_14_P0_PRU1,Filter3_14P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P0                 ,Filter3 P4:P1"
group.long 0x9B8++0x3
line.long 0x00 "ICSSG_FT3_14_P1_PRU1,Filter3_14P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P1                 ,Filter3 P8:P5"
group.long 0x9BC++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9C0++0x3
line.long 0x00 "ICSSG_FT3_14_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_14_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9C4++0x3
line.long 0x00 "ICSSG_FT3_15_P0_PRU1,Filter3_15P0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P0                 ,Filter3 P4:P1"
group.long 0x9C8++0x3
line.long 0x00 "ICSSG_FT3_15_P1_PRU1,Filter3_15P1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P1                 ,Filter3 P8:P5"
group.long 0x9CC++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK0_PRU1,Filter3P_Mask0Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK0            ,Filter3 MP4:MP1 set to 1 to mask that bit"
group.long 0x9D0++0x3
line.long 0x00 "ICSSG_FT3_15_P_MASK1_PRU1,Filter3P_Mask1Pru1"
hexmask.long 0x00 0.--31. 1. " FT3_15_P_MASK1            ,Filter3 MP8:MP5 set to 1 to mask that bit"
group.long 0x9D4++0x3
line.long 0x00 "ICSSG_FT_RX_PTR_PRU1,FilterByteCountPru1"
hexmask.long 0x00 0.--31. 1. " FT_RX_PTR_PRU1            ,RX current filter Byte Count"
group.long 0x9D8++0x3
line.long 0x00 "ICSSG_RX_CLASS0_AND_EN_PRU1,rx_class0_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_AND_EN          ,rx class and enabels"
group.long 0x9DC++0x3
line.long 0x00 "ICSSG_RX_CLASS0_OR_EN_PRU1,rx_class0_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS0_OR_EN           ,rx class or enabels"
group.long 0x9E0++0x3
line.long 0x00 "ICSSG_RX_CLASS1_AND_EN_PRU1,rx_class1_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_AND_EN          ,rx class and enabels"
group.long 0x9E4++0x3
line.long 0x00 "ICSSG_RX_CLASS1_OR_EN_PRU1,rx_class1_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS1_OR_EN           ,rx class or enabels"
group.long 0x9E8++0x3
line.long 0x00 "ICSSG_RX_CLASS2_AND_EN_PRU1,rx_class2_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_AND_EN          ,rx class and enabels"
group.long 0x9EC++0x3
line.long 0x00 "ICSSG_RX_CLASS2_OR_EN_PRU1,rx_class2_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS2_OR_EN           ,rx class or enabels"
group.long 0x9F0++0x3
line.long 0x00 "ICSSG_RX_CLASS3_AND_EN_PRU1,rx_class3_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_AND_EN          ,rx class and enabels"
group.long 0x9F4++0x3
line.long 0x00 "ICSSG_RX_CLASS3_OR_EN_PRU1,rx_class3_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS3_OR_EN           ,rx class or enabels"
group.long 0x9F8++0x3
line.long 0x00 "ICSSG_RX_CLASS4_AND_EN_PRU1,rx_class4_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_AND_EN          ,rx class and enabels"
group.long 0x9FC++0x3
line.long 0x00 "ICSSG_RX_CLASS4_OR_EN_PRU1,rx_class4_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS4_OR_EN           ,rx class or enabels"
group.long 0xA00++0x3
line.long 0x00 "ICSSG_RX_CLASS5_AND_EN_PRU1,rx_class5_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_AND_EN          ,rx class and enabels"
group.long 0xA04++0x3
line.long 0x00 "ICSSG_RX_CLASS5_OR_EN_PRU1,rx_class5_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS5_OR_EN           ,rx class or enabels"
group.long 0xA08++0x3
line.long 0x00 "ICSSG_RX_CLASS6_AND_EN_PRU1,rx_class6_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_AND_EN          ,rx class and enabels"
group.long 0xA0C++0x3
line.long 0x00 "ICSSG_RX_CLASS6_OR_EN_PRU1,rx_class6_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS6_OR_EN           ,rx class or enabels"
group.long 0xA10++0x3
line.long 0x00 "ICSSG_RX_CLASS7_AND_EN_PRU1,rx_class7_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_AND_EN          ,rx class and enabels"
group.long 0xA14++0x3
line.long 0x00 "ICSSG_RX_CLASS7_OR_EN_PRU1,rx_class7_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS7_OR_EN           ,rx class or enabels"
group.long 0xA18++0x3
line.long 0x00 "ICSSG_RX_CLASS8_AND_EN_PRU1,rx_class8_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_AND_EN          ,rx class and enabels"
group.long 0xA1C++0x3
line.long 0x00 "ICSSG_RX_CLASS8_OR_EN_PRU1,rx_class8_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS8_OR_EN           ,rx class or enabels"
group.long 0xA20++0x3
line.long 0x00 "ICSSG_RX_CLASS9_AND_EN_PRU1,rx_class9_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_AND_EN          ,rx class and enabels"
group.long 0xA24++0x3
line.long 0x00 "ICSSG_RX_CLASS9_OR_EN_PRU1,rx_class9_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS9_OR_EN           ,rx class or enabels"
group.long 0xA28++0x3
line.long 0x00 "ICSSG_RX_CLASS10_AND_EN_PRU1,rx_class10_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_AND_EN         ,rx class and enabels"
group.long 0xA2C++0x3
line.long 0x00 "ICSSG_RX_CLASS10_OR_EN_PRU1,rx_class10_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS10_OR_EN          ,rx class or enabels"
group.long 0xA30++0x3
line.long 0x00 "ICSSG_RX_CLASS11_AND_EN_PRU1,rx_class11_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_AND_EN         ,rx class and enabels"
group.long 0xA34++0x3
line.long 0x00 "ICSSG_RX_CLASS11_OR_EN_PRU1,rx_class11_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS11_OR_EN          ,rx class or enabels"
group.long 0xA38++0x3
line.long 0x00 "ICSSG_RX_CLASS12_AND_EN_PRU1,rx_class12_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_AND_EN         ,rx class and enabels"
group.long 0xA3C++0x3
line.long 0x00 "ICSSG_RX_CLASS12_OR_EN_PRU1,rx_class12_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS12_OR_EN          ,rx class or enabels"
group.long 0xA40++0x3
line.long 0x00 "ICSSG_RX_CLASS13_AND_EN_PRU1,rx_class13_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_AND_EN         ,rx class and enabels"
group.long 0xA44++0x3
line.long 0x00 "ICSSG_RX_CLASS13_OR_EN_PRU1,rx_class13_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS13_OR_EN          ,rx class or enabels"
group.long 0xA48++0x3
line.long 0x00 "ICSSG_RX_CLASS14_AND_EN_PRU1,rx_class14_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_AND_EN         ,rx class and enabels"
group.long 0xA4C++0x3
line.long 0x00 "ICSSG_RX_CLASS14_OR_EN_PRU1,rx_class14_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS14_OR_EN          ,rx class or enabels"
group.long 0xA50++0x3
line.long 0x00 "ICSSG_RX_CLASS15_AND_EN_PRU1,rx_class15_and_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_AND_EN         ,rx class and enabels"
group.long 0xA54++0x3
line.long 0x00 "ICSSG_RX_CLASS15_OR_EN_PRU1,rx_class15_or_enablesPru1"
hexmask.long 0x00 0.--31. 1. " RX_CLASS15_OR_EN          ,rx class or enabels"
group.long 0xA58++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU1,rx_class_cfg1Pru1"
bitfld.long 0x00 30.--31. " RX_CLASS15_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 28.--29. "         RX_CLASS14_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 26.--27. " RX_CLASS13_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 24.--25. "         RX_CLASS12_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 22.--23. " RX_CLASS11_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 20.--21. "         RX_CLASS10_SEL           ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 18.--19. " RX_CLASS9_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 16.--17. "         RX_CLASS8_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 14.--15. " RX_CLASS7_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 12.--13. "         RX_CLASS6_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 10.--11. " RX_CLASS5_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 8.--9. "         RX_CLASS4_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 6.--7. " RX_CLASS3_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 4.--5. "         RX_CLASS2_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
textline "                                            "
bitfld.long 0x00 2.--3. " RX_CLASS1_SEL             ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
bitfld.long 0x00 0.--1. "         RX_CLASS0_SEL            ,rx class final term selection00: OR 01: AND 10: OR AND AND OR 11: OR OR AND" "0,1,2,3"
group.long 0xA5C++0x3
line.long 0x00 "ICSSG_RX_CLASS_CFG2_PRU1,rx_class_cfg2Pru1"
hexmask.long.word 0x00 16.--31. 1. " RX_CLASS_OR_NV            ,rx class or nv enable"
hexmask.long.word 0x00 0.--15. 1. "      RX_CLASS_AND_NV          ,rx class and nv enable"
group.long 0xA60++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES0_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN0          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK0           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK0        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK0           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL0         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA64++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES1_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN1          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK1           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK1        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK1           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL1         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA68++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES2_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN2          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK2           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK2        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK2           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL2         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA6C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES3_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN3          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK3           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK3        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK3           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL3         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA70++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES4_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN4          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK4           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK4        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK4           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL4         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA74++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES5_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN5          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK5           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK5        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK5           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL5         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA78++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES6_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN6          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK6           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK6        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK6           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL6         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA7C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES7_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN7          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK7           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK7        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK7           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL7         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA80++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES8_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN8          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK8           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK8        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK8           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL8         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA84++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES9_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN9          ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK9           ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK9        ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK9           ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL9         ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA88++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES10_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN10         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK10          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK10       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK10          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL10        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA8C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES11_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN11         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK11          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK11       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK11          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL11        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA90++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES12_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN12         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK12          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK12       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK12          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL12        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA94++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES13_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN13         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK13          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK13       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK13          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL13        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA98++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES14_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN14         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK14          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK14       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK14          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL14        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xA9C++0x3
line.long 0x00 "ICSSG_RX_CLASS_GATES15_PRU1,rx_class_gate_cfgPru1"
bitfld.long 0x00 8. " RX_RED_PHASE_EN15         ,red phase neable0: disable 1: enable" "0,1"
bitfld.long 0x00 6. "         RX_ALLOW_MASK15          ,allow mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 5. " RX_CLASS_RAW_MASK15       ,class raw mask0: unmask 1: mask" "0,1"
bitfld.long 0x00 4. "         RX_PHASE_MASK15          ,time phase mask0: unmask 1: mask" "0,1"
textline "                                            "
bitfld.long 0x00 0.--2. " RX_RATE_GATE_SEL15        ,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xAA0++0x3
line.long 0x00 "ICSSG_RX_GREEN_PRU1,RX_greenPru1"
bitfld.long 0x00 4. " RX_GREEN_VAL              ,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "         RX_GREEN_CMP_SEL         ,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAA4++0x3
line.long 0x00 "ICSSG_SA_HASH_PRU1,SAHashPru1"
hexmask.long.word 0x00 0.--9. 1. " SA_HASH_SEED              ,SA Hash Seed"
group.long 0xAA8++0x3
line.long 0x00 "ICSSG_CONN_HASH_PRU1,ConnectionHashPru1"
hexmask.long.word 0x00 0.--9. 1. " CONN_HASH_SEED            ,Connection Hash Seed"
group.long 0xAAC++0x3
line.long 0x00 "ICSSG_CONN_HASH_START_PRU1,ConnectionHashStartPru1"
hexmask.long.word 0x00 0.--14. 1. " CONN_HASH_START           ,Connection Hash Start which 4 Bytes to hash"
group.long 0xAB0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG0_PRU1,RX_RateConfiguration0Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE0         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG1_PRU1,RX_RateConfiguration1Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE1         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAB8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG2_PRU1,RX_RateConfiguration2Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE2         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xABC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG3_PRU1,RX_RateConfiguration3Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE3         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC0++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG4_PRU1,RX_RateConfiguration4Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE4         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC4++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG5_PRU1,RX_RateConfiguration5Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE5         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAC8++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG6_PRU1,RX_RateConfiguration6Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE6         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xACC++0x3
line.long 0x00 "ICSSG_RX_RATE_CFG7_PRU1,RX_RateConfiguration7Pru1"
hexmask.long 0x00 0.--31. 1. " RX_RATE_CIR_IDLE7         ,RX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAD0++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU1,RX_RateSourceSelect0Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL3          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL2         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL1          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL0         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD4++0x3
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL1_PRU1,RX_RateSourceSelect1Pru1"
bitfld.long 0x00 24.--29. " RX_RATE_SRC_SEL7          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "        RX_RATE_SRC_SEL6         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline "                                            "
bitfld.long 0x00 8.--13. " RX_RATE_SRC_SEL5          ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "        RX_RATE_SRC_SEL4         ,Map which filter/flag/class hit that rate logic uses, see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAD8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_0_PRU1,TX_RateConfiguration1_0Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE0         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xADC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_0_PRU1,TX_RateConfiguration2_0Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW0            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN0              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN0              ,TX Rate Pkt Length"
group.long 0xAE0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_1_PRU1,TX_RateConfiguration1_1Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE1         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAE4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_1_PRU1,TX_RateConfiguration2_1Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW1            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN1              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN1              ,TX Rate Pkt Length"
group.long 0xAE8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_2_PRU1,TX_RateConfiguration1_2Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE2         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAEC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_2_PRU1,TX_RateConfiguration2_2Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW2            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN2              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN2              ,TX Rate Pkt Length"
group.long 0xAF0++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_3_PRU1,TX_RateConfiguration1_3Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE3         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAF4++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_3_PRU1,TX_RateConfiguration2_3Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW3            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN3              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN3              ,TX Rate Pkt Length"
group.long 0xAF8++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_4_PRU1,TX_RateConfiguration1_4Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE4         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xAFC++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_4_PRU1,TX_RateConfiguration2_4Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW4            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN4              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN4              ,TX Rate Pkt Length"
group.long 0xB00++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_5_PRU1,TX_RateConfiguration1_5Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE5         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB04++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_5_PRU1,TX_RateConfiguration2_5Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW5            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN5              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN5              ,TX Rate Pkt Length"
group.long 0xB08++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_6_PRU1,TX_RateConfiguration1_6Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE6         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB0C++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_6_PRU1,TX_RateConfiguration2_6Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW6            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN6              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN6              ,TX Rate Pkt Length"
group.long 0xB10++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG1_7_PRU1,TX_RateConfiguration1_7Pru1"
hexmask.long 0x00 0.--31. 1. " TX_RATE_CIR_IDLE7         ,TX Rate Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle including EOF.The PIR counter is disabled with a zero value and packets will not be marked RED"
group.long 0xB14++0x3
line.long 0x00 "ICSSG_TX_RATE_CFG2_7_PRU1,TX_RateConfiguration2_7Pru1"
bitfld.long 0x00 17. " TX_RATE_ALLOW7            ,TX Rate Pkt Enable" "0,1"
bitfld.long 0x00 16. "         TX_RATE_EN7              ,TX Rate Pkt Enable" "0,1"
textline "                                            "
hexmask.long.word 0x00 0.--15. 1. " TX_RATE_LEN7              ,TX Rate Pkt Length"
group.long 0xB18++0x3
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU1,RXGoodFrameCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_GOOD_FRM_CNT           ,RX Good Frame Count Inc on none min err max err crc err odd err, Wrt subtracts"
group.long 0xB1C++0x3
line.long 0x00 "ICSSG_RX_STAT_BC_PRU1,RXBCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_BC_FRM_CNT             ,RX BC Frame Count Inc on BC type, Wrt subtracts"
group.long 0xB20++0x3
line.long 0x00 "ICSSG_RX_STAT_MC_PRU1,RXMCFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MC_FRM_CNT             ,RX MC Frame Count Inc on MC type, Wrt subtracts"
group.long 0xB24++0x3
line.long 0x00 "ICSSG_RX_STAT_CRC_ERR_PRU1,RXCRCErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_CRC_ERR_FRM_CNT        ,RX CRC Err Frame Count Inc on crc err, Wrt subtracts"
group.long 0xB28++0x3
line.long 0x00 "ICSSG_RX_STAT_MII_ERR_PRU1,RXMIIErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MII_ERR_FRM_CNT        ,RX MII Err Frame Count Inc on mii sgmii rgmii err, Wrt subtracts"
group.long 0xB2C++0x3
line.long 0x00 "ICSSG_RX_STAT_ODD_ERR_PRU1,RXOddNibbleFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_ODD_ERR_FRM_CNT        ,RX Odd Nibble Frame Count Inc on odd nibble mii, Wrt subtracts"
group.long 0xB30++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_SIZE_PRU1,RXMaxSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_SIZE_FRM           ,RX MAX Size Frame Count Limit"
group.long 0xB34++0x3
line.long 0x00 "ICSSG_RX_STAT_MAX_ERR_PRU1,RXMaxSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MAX_ERR_FRM_CNT        ,RX MAX Size Err Frame Count Inc if > than Limit, Wrt subtracts"
group.long 0xB38++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_SIZE_PRU1,RXMinSizeFramePru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_SIZE_FRM           ,RX MIN Size Frame Limit"
group.long 0xB3C++0x3
line.long 0x00 "ICSSG_RX_STAT_MIN_ERR_PRU1,RXMinSizeErrFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_MIN_ERR_FRM_CNT        ,RX MIN Size Frame Count Inc if < than limit, Wrt subtracts"
group.long 0xB40++0x3
line.long 0x00 "ICSSG_RX_STAT_OVERRUN_ERR_PRU1,RXoverrunFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_OVERRUN_ERR_FRM_CNT    ,RX L1 FIFO overflow Frame Count Inc on overflow event, Wrt subtracts"
group.long 0xB44++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS0_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS0_PRU1       ,RX Class0 Hit Count, Wrt subtracts"
group.long 0xB48++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS1_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS1_PRU1       ,RX Class1 Hit Count, Wrt subtracts"
group.long 0xB4C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS2_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS2_PRU1       ,RX Class2 Hit Count, Wrt subtracts"
group.long 0xB50++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS3_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS3_PRU1       ,RX Class3 Hit Count, Wrt subtracts"
group.long 0xB54++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS4_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS4_PRU1       ,RX Class4 Hit Count, Wrt subtracts"
group.long 0xB58++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS5_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS5_PRU1       ,RX Class5 Hit Count, Wrt subtracts"
group.long 0xB5C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS6_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS6_PRU1       ,RX Class6 Hit Count, Wrt subtracts"
group.long 0xB60++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS7_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS7_PRU1       ,RX Class7 Hit Count, Wrt subtracts"
group.long 0xB64++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS8_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS8_PRU1       ,RX Class8 Hit Count, Wrt subtracts"
group.long 0xB68++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS9_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS9_PRU1       ,RX Class9 Hit Count, Wrt subtracts"
group.long 0xB6C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS10_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS10_PRU1      ,RX Class10 Hit Count, Wrt subtracts"
group.long 0xB70++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS11_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS11_PRU1      ,RX Class11 Hit Count, Wrt subtracts"
group.long 0xB74++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS12_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS12_PRU1      ,RX Class12 Hit Count, Wrt subtracts"
group.long 0xB78++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS13_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS13_PRU1      ,RX Class13 Hit Count, Wrt subtracts"
group.long 0xB7C++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS14_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS14_PRU1      ,RX Class14 Hit Count, Wrt subtracts"
group.long 0xB80++0x3
line.long 0x00 "ICSSG_RX_STAT_CLASS15_HIT_PRU1,RXClass1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_CLASS15_PRU1      ,RX Class15 Hit Count, Wrt subtracts"
group.long 0xB84++0x3
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU1,RXSMDFragErrCountPru1"
hexmask.long.byte 0x00 24.--31. 1. " RX_STAT_SMD_ERR_PRU1      ,RX SMDS Error Count, Inc when first none 0x55 does not match any valid SMD, Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "        RX_STAT_FRAG_ERR_PRU1    ,RX Frag_Cnt Seq Error Count, Wrt subtracts"
textline "                                            "
hexmask.long.byte 0x00 8.--15. 1. " RX_STAT_SMDC_ERR_PRU1     ,RX SMDCx Seq Error Count, Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "        RX_STAT_SMDS_ERR_PRU1    ,RX SMDSx Seq Error Count, Wrt subtracts"
group.long 0xB88++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_SIZE_PRU1,RXBucket1SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT1_SIZE         ,RX Bucket1 Byte Size"
group.long 0xB8C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_SIZE_PRU1,RXBucket2SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT2_SIZE         ,RX Bucket2 Byte Size"
group.long 0xB90++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_SIZE_PRU1,RXBucket3SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT3_SIZE         ,RX Bucket3 Byte Size"
group.long 0xB94++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_SIZE_PRU1,RXBucket4SizeConfigPru1"
hexmask.long.word 0x00 0.--13. 1. " RX_STAT_BKT4_SIZE         ,RX Bucket4 Byte Size"
group.long 0xB98++0x3
line.long 0x00 "ICSSG_RX_STAT_64_PRU1,RX64BSizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_64_FRM_CNT             ,RX 64Byte Frame Count Inc if 64B size"
group.long 0xB9C++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT1_PRU1,RXBucket1SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT1              ,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
group.long 0xBA0++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT2_PRU1,RXBucket2SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT2              ,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBA4++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT3_PRU1,RXBucket3SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT3              ,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBA8++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT4_PRU1,RXBucket4SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT4              ,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xBAC++0x3
line.long 0x00 "ICSSG_RX_STAT_BKT5_PRU1,RXBucket5SizedFrameCountPru1"
hexmask.long.word 0x00 0.--15. 1. " RX_STAT_BKT5              ,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
group.long 0xBB0++0x3
line.long 0x00 "ICSSG_RX_STAT_TOTAL_BYTES_PRU1,RXTotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RX_STAT_TOTAL_BYTES_PRU   ,RX Total Byte Count"
group.long 0xBB4++0x3
line.long 0x00 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU1,RX_TX_TotalByteCountPru1"
hexmask.long 0x00 0.--31. 1. " RXTX_STAT_TOTAL_BYTES_PRU ,RX and TX Total Byte Count"
group.long 0xBB8++0x3
line.long 0x00 "ICSSG_TX_STAT_GOOD_PORT1,TXGoodFrameCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_GOOD_FRM_CNT           ,TX Good Frame Count Inc if no min size err max size err or mii odd nibble"
group.long 0xBBC++0x3
line.long 0x00 "ICSSG_TX_STAT_BC_PORT1,TXBCFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_BC_FRM_CNT             ,TX BC Frame Count Inc if BC"
group.long 0xBC0++0x3
line.long 0x00 "ICSSG_TX_STAT_MC_PORT1,TXMFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MC_FRM_CNT             ,TX MC Frame Count Inc if MC"
group.long 0xBC4++0x3
line.long 0x00 "ICSSG_TX_STAT_ODD_ERR_PORT1,TXOddNibbleFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_ODD_ERR_FRM_CNT        ,TX Odd Nibble Frame Count Inc if mii odd nibble"
group.long 0xBC8++0x3
line.long 0x00 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT1,TXUnderFlowErrCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_UNDERFLOW_CNT          ,TX MAX Underflow Error Cnt"
group.long 0xBCC++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_SIZE_PORT1,TXMaxSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_SIZE_FRM           ,TX MAX Size Frame Count Limit"
group.long 0xBD0++0x3
line.long 0x00 "ICSSG_TX_STAT_MAX_ERR_PORT1,TXMaxSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MAX_ERR_FRM_CNT        ,TX MAX Size Err Frame Count Inc if > max Limit"
group.long 0xBD4++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_SIZE_PORT1,TXMinSizeFramePort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_SIZE_FRM           ,TX MIN Size Frame Count Limit"
group.long 0xBD8++0x3
line.long 0x00 "ICSSG_TX_STAT_MIN_ERR_PORT1,TXMinSizeErrFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_MIN_ERR_FRM_CNT        ,TX MIN Size Err Frame Count Inc if < min Limit"
group.long 0xBDC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_SIZE_PORT1,TXBucket1SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT1_SIZE         ,TX Bucket1 Byte Size"
group.long 0xBE0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_SIZE_PORT1,TXBucket2SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT2_SIZE         ,TX Bucket2 Byte Size"
group.long 0xBE4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_SIZE_PORT1,TXBucket3SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT3_SIZE         ,TX Bucket3 Byte Size"
group.long 0xBE8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_SIZE_PORT1,TXBucket4SizeConfigPort1"
hexmask.long.word 0x00 0.--13. 1. " TX_STAT_BKT4_SIZE         ,TX Bucket4 Byte Size"
group.long 0xBEC++0x3
line.long 0x00 "ICSSG_TX_STAT_64_PORT1,TX64BSizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_64_FRM_CNT             ,TX 64Byte Frame Count Inc if 64B"
group.long 0xBF0++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT1_PORT1,TXBucket1SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT1              ,TX Bucket1 Inc if <= than Bucket1"
group.long 0xBF4++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT2_PORT1,TXBucket2SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT2              ,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
group.long 0xBF8++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT3_PORT1,TXBucket3SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT3              ,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
group.long 0xBFC++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT4_PORT1,TXBucket4SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT4              ,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
group.long 0xC00++0x3
line.long 0x00 "ICSSG_TX_STAT_BKT5_PORT1,TXBucket5SizedFrameCountPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_STAT_BKT5              ,TX Bucket5 Inc if > than Bucket4 Byte Size"
group.long 0xC04++0x3
line.long 0x00 "ICSSG_TX_STAT_TOTAL_BYTES_PORT1,TXTotalByteCountPort1"
hexmask.long 0x00 0.--31. 1. " TX_TOTAL_STAT_BYTES_PORT  ,TX Total Byte Count of all Frames"
group.long 0xC08++0x3
line.long 0x00 "ICSSG_TX_HSR_TAG_PORT1,TXHSRTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_HSR_TAG                ,HSR TAG"
group.long 0xC0C++0x3
line.long 0x00 "ICSSG_TX_HSR_SEQ_PORT1,TXHSRSeqPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_HSR_SEQ                ,HSR Seq count.It will incr for every HSR type"
group.long 0xC10++0x3
line.long 0x00 "ICSSG_TX_VLAN_TYPE_TAG_PORT1,TXVLANTYPETAGPort1"
hexmask.long.word 0x00 0.--15. 1. " TX_VLAN_TYPE_TAG          ,TX VLAN Type Tag, match to enable VLAN removal"
group.long 0xC14++0x3
line.long 0x00 "ICSSG_TX_VLAN_INS_TAG_PORT1,TXVLANINSTAGPort1"
hexmask.long 0x00 0.--31. 1. " TX_VLAN_INS_TAG           ,TX VLAN Insertion"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_MII_RT"
tree "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG"
base eaxi:0xB232000
width 22.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RXCFG0,RX Configuration 0 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS0      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW0          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW0           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE0     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN0            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL0           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE0     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS0 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE0           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x4++0x3
line.long 0x00 "ICSSG_RXCFG1,RX Configuration 1 Register"
bitfld.long 0x00 9. " RX_EOF_SCLR_DIS1      ,0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled" "0,1"
bitfld.long 0x00 8. "         RX_ERR_RAW1          ,0h = ERR Raw Mode Disabled" "0,1"
textline "                               "
bitfld.long 0x00 7. " RX_SFD_RAW1           ,0h = SFD Raw Mode Disabled" "0,1"
bitfld.long 0x00 6. "         RX_AUTO_FWD_PRE1     ,Auto Forward Preamble Mode" "0,1"
textline "                               "
bitfld.long 0x00 5. " RX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for RX R31 and RX L2." "0,1"
bitfld.long 0x00 4. "         RX_L2_EN1            ,0h = Disables RX L2 buffer." "0,1"
textline "                               "
bitfld.long 0x00 3. " RX_MUX_SEL1           ,0h = Select MII RX Data from Port 0" "0,1"
bitfld.long 0x00 2. "         RX_CUT_PREAMBLE1     ,0h = All data from Ethernet PHY are passed on to PRU register." "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_DATA_RDY_MODE_DIS1 ,0h = R31:16 is DATA_RDY mapeed" "0,1"
bitfld.long 0x00 0. "         RX_ENABLE1           ,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TXCFG0,TX Control Register 0"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY0         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY0      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN0        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR0 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE0 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL0          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP0         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE0          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE0     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE0           ,0h = TX PORT is disabled/stopped immediately" "0,1"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TXCFG1,TX Control Register 1"
bitfld.long 0x00 28.--30. " TX_CLK_DELAY1         ,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "         TX_START_DELAY1      ,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame."
textline "                               "
bitfld.long 0x00 11. " TX_32_MODE_EN1        ,0h = Disable 32-bit Data Push mode" "0,1"
bitfld.long 0x00 10. "         PRE_TX_AUTO_ESC_ERR1 ,This bit enables the HW actions required to implement the ESC Error handing table." "0,1"
textline "                               "
bitfld.long 0x00 9. " PRE_TX_AUTO_SEQUENCE1 ,When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter." "0,1"
bitfld.long 0x00 8. "         TX_MUX_SEL1          ,0h = TX data from PRU0 is selected" "0,1"
textline "                               "
bitfld.long 0x00 3. " TX_BYTE_SWAP1         ,Controls the order of the Byte0/1 placement for TX R30." "0,1"
bitfld.long 0x00 2. "         TX_EN_MODE1          ,0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1" "0,1"
textline "                               "
bitfld.long 0x00 1. " TX_AUTO_PREAMBLE1     ,0h = PRU will provide full pre-amble" "0,1"
bitfld.long 0x00 0. "         TX_ENABLE1           ,0h = TX PORT is disabled/stopped immediately" "0,1"
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_TX_CRC0,Transmit CRC32 Register 0"
hexmask.long 0x00 0.--31. 1. " TX_CRC0               ,FCS (CRC32) data can be read by PRU for diagnostics"
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_TX_CRC1,Transmit CRC32 Register 1"
hexmask.long 0x00 0.--31. 1. " TX_CRC1               ,FCS (CRC32) data can be read by PRU for diagnostics"
group.long 0x30++0x3
line.long 0x00 "ICSSG_TX_IPG0,TX IPG Register 0"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG0               ,Define the minimum Inter Packet Gap"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_IPG1,TX IPG Register 1"
hexmask.long.word 0x00 0.--9. 1. " TX_IPG1               ,Define the minimum Inter Packet Gap"
rgroup.long 0x38++0x3
line.long 0x00 "ICSSG_PRS0,PORT_RAW_STATUS Register 0"
bitfld.long 0x00 1. " SYNC_MII0_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII0_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
rgroup.long 0x3C++0x3
line.long 0x00 "ICSSG_PRS1,PORT_RAW_STATUS Register 1"
bitfld.long 0x00 1. " SYNC_MII1_CRS         ,Read the current state of pr1_mii<port>_crs" "0,1"
bitfld.long 0x00 0. "         SYNC_MII1_COL        ,Read the current state of pr1_mii<port>_col" "0,1"
group.long 0x40++0x3
line.long 0x00 "ICSSG_RX_FRMS0,RX Frame Size Register 0"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM0           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM0          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x44++0x3
line.long 0x00 "ICSSG_RX_FRMS1,RX Frame Size Register 1"
hexmask.long.word 0x00 16.--31. 1. " RX_MAX_FRM1           ,If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set."
hexmask.long.word 0x00 0.--15. 1. "      RX_MIN_FRM1          ,If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set."
group.long 0x48++0x3
line.long 0x00 "ICSSG_RX_PCNT0,RX Preamble Cnt Register 0"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT0          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT0         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x3
line.long 0x00 "ICSSG_RX_PCNT1,RX Preamble Cnt Register 1"
bitfld.long 0x00 4.--8. " RX_MAX_PCNT1          ,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "        RX_MIN_PCNT1         ,Define the min number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x3
line.long 0x00 "ICSSG_RX_ERR0,RX Error Register 0"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR0       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR0      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR0      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR0     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
group.long 0x54++0x3
line.long 0x00 "ICSSG_RX_ERR1,RX Error Register 1"
bitfld.long 0x00 3. " RX_MAX_FRM_ERR1       ,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "         RX_MIN_FRM_ERR1      ,Set when the FRAME total byte count is less than defined value" "0,1"
textline "                               "
bitfld.long 0x00 1. " RX_MAX_PCNT_ERR1      ,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "         RX_MIN_PCNT_ERR1     ,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
rgroup.long 0x60++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL0,RX FIFO Level 0 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL0        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x64++0x3
line.long 0x00 "ICSSG_RX_FIFO_LEVEL1,RX FIFO Level 1 Register"
hexmask.long.byte 0x00 0.--7. 1. " RX_FIFO_LEVEL1        ,Define the number of valid bytes in the RX FIFO"
rgroup.long 0x68++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL0,TX FIFO Register 0"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL0        ,Define the number of valid nibbles in the TX FIFO"
rgroup.long 0x6C++0x3
line.long 0x00 "ICSSG_TX_FIFO_LEVEL1,TX FIFO Register 1"
hexmask.long.byte 0x00 0.--7. 1. " TX_FIFO_LEVEL1        ,Define the number of valid nibbles in the TX FIFO"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PROTECT"
tree "PRU_ICSSG2_PR1_PROT_SLV"
base eaxi:0xB224C00
width 18.
group.long 0x0++0x3
line.long 0x00 "ICSSG_UNLOCK_KEY,LOCK KEY"
hexmask.long 0x00 0.--31. 1. " UNLOCK_KEY         ,UnLock Key Pattern 0x83E7_0B13. To UnLock 0x0000_0000. To Lock Must unlock to update MMRs."
group.long 0x4++0x3
line.long 0x00 "ICSSG_CFG,Config"
bitfld.long 0x00 6. " PRU1_DMEM1_LOCK_EN ,Write Protect DMEM10h = Disable 1h = Enable. When enabled only PRU1 can write to DMEM1" "0,1"
bitfld.long 0x00 5. "         PRU0_DMEM0_LOCK_EN ,Write Protect DMEM00h = Disable 1h = Enable. When enabled only PRU0 can write to DMEM0" "0,1"
textline "                           "
bitfld.long 0x00 4. " ICSS_CFG_WP_EN     ,Write Protect ICSS_CFG0h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 3. "         RTU1_PRU_WP_EN     ,Write Protect RTU_PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 2. " RTU0_PRU_WP_EN     ,Write Protect RTU_PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
bitfld.long 0x00 1. "         PRU1_WP_EN         ,Write Protect PRU1 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
textline "                           "
bitfld.long 0x00 0. " PRU0_WP_EN         ,Write Protect PRU0 access Debug register IMEM00h = Disable 1h = Enable" "0,1"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM"
tree "PRU_ICSSG2_PR1_PDSP0_IRAM"
base eaxi:0xB222000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM"
base eaxi:0xB223000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM"
base eaxi:0xB223800
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_PDSP1_IRAM"
base eaxi:0xB224000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register."
hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset."
bitfld.long 0x00 15. "      RUNSTATE      ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted." "0,1"
textline "                              "
bitfld.long 0x00 13. " TS_ENABLE        ,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface." "0,1"
bitfld.long 0x00 8. "         SINGLE_STEP   ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled." "0,1"
textline "                              "
bitfld.long 0x00 3. " COUNTER_ENABLE   ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1"
bitfld.long 0x00 2. "         SLEEPING      ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1"
textline "                              "
bitfld.long 0x00 1. " ENABLE           ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core.When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1"
bitfld.long 0x00 0. "         SOFT_RST_N    ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared." "0,1"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_PRU_STATUS,PRU Status Register."
hexmask.long.word 0x00 0.--15. 1. " PCOUNTER         ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter."
group.long 0x8++0x3
line.long 0x00 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register."
hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES  ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core.Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core."
group.long 0xC++0x3
line.long 0x00 "ICSSG_PRU_CYCLE,PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled."
hexmask.long 0x00 0.--31. 1. " CYCLECOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounter clears the [3]COUNTER_ENABLE bit in the"
rgroup.long 0x10++0x3
line.long 0x00 "ICSSG_PRU_STALL,PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count."
hexmask.long 0x00 0.--31. 1. " STALLCOUNT       ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in theCounting halts while the PRU is disabled or the counter is disabled, and resumes when re-eneabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register ("
group.long 0x20++0x3
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX    ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26."
hexmask.long.byte 0x00 0.--7. 1. "        C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25."
group.long 0x24++0x3
line.long 0x00 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching."
hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX    ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28."
hexmask.long.byte 0x00 0.--7. 1. "        C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27."
group.long 0x28++0x3
line.long 0x00 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory."
hexmask.long.word 0x00 16.--31. 1. " C29_POINTER      ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30."
hexmask.long.word 0x00 0.--15. 1. "      C28_POINTER   ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table."
hexmask.long.word 0x00 16.--31. 1. " C31_POINTER      ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32."
hexmask.long.word 0x00 0.--15. 1. "      C30_POINTER   ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
tree "PRU_ICSSG2_PR1_PDSP0_IRAM_DEBUG"
base eaxi:0xB222400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"
base eaxi:0xB223400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"
base eaxi:0xB223C00
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_PDSP1_IRAM_DEBUG"
base eaxi:0xB224400
width 20.
group.long 0x0++0x3
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written. Offset = 0h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " GP_REGy ,PRU Internal GP Register y: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal register file."
group.long 0x80++0x3
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31. This register allows an external agent to debug/or configure the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table. Offset = 80h + (y * 4); where y = 0 to 31"
hexmask.long 0x00 0.--31. 1. " CT_REGy ,PRU Internal Constants Table Entry y (where y = 0 to 31): Reading this field directly inspects the corresponding entry in the PRU internal constants table.Note: For each register y where y is less than the ctreg_cnt configuration parameter, the PRU internal Constants Table Entry Register will be writable and these registers are to be used to set the value for these constants. As for reads, the PRU must be disabled in order to access these registers."
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAM"
tree "PRU_ICSSG2_RAM_SLV_RAM"
base eaxi:0xB210000
width 17.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage. Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "  BYTE2 ,This is the UM byte"
textline "                          "
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "  BYTE0 ,This is the LS byte"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_RAT_SLICE"
tree "PRU_ICSSG2_RAT_SLICE0_CFG_CFG"
base eaxi:0xB208000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree "PRU_ICSSG2_RAT_SLICE1_CFG"
base eaxi:0xB209000
width 33.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module."
bitfld.long 0x00 30.--31. " SCHEME       ," "0,1,2,3"
bitfld.long 0x00 28.--29. "         BU        ,Business Unit:10 = Processors" "0,1,2,3"
textline "                                          "
hexmask.long.word 0x00 16.--27. 1. " FUNC         ,Module ID"
bitfld.long 0x00 11.--15. "      RTL       ,RTL revision.Will vary depending on release." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                          "
bitfld.long 0x00 8.--10. " MAJOR        ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "         CUSTOM    ,Custom" "0,1,2,3"
textline "                                          "
bitfld.long 0x00 0.--5. " MINOR        ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_CONFIG,The Config Register contains the configuration values for the module."
hexmask.long.byte 0x00 16.--23. 1. " ADDR_WIDTH   ,Number of address bits"
hexmask.long.byte 0x00 8.--15. 1. "        ADDRS     ,Number of addresses"
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " REGIONS      ,Number of regions"
group.long 0x20++0x3
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3h"
bitfld.long 0x00 31. " EN           ,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "         SIZE      ,Size of the Region in Address Bits.0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x3
line.long 0x00 "ICSSG_BASE_j,The Base Address for Region a. This is the source address for matching to a region. Offset = 24h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " BASE         ,Base Address for the Region.It must be aligned to the programmed size."
group.long 0x28++0x3
line.long 0x00 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3h"
hexmask.long 0x00 0.--31. 1. " LOWER        ,Translated Lower Address Bits for the Region.It must be aligned to the programmed size."
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. " UPPER        ,Translated Upper Address Bits for the Region"
group.long 0x804++0x3
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages."
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,The destination ID."
group.long 0x820++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging."
bitfld.long 0x00 1. " DISABLE_INTR ,Disables logging interrupt when set." "0,1"
bitfld.long 0x00 0. "         DISABLE_F ,Disables logging when set." "0,1"
rgroup.long 0x824++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header."
hexmask.long.byte 0x00 24.--31. 1. " TYPE_F       ,Type.4 = RAT."
hexmask.long.word 0x00 8.--23. 1. "        SRC_ID    ,Source ID."
textline "                                          "
hexmask.long.byte 0x00 0.--7. 1. " DEST_ID      ,Destination ID."
rgroup.long 0x828++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header."
hexmask.long.byte 0x00 24.--31. 1. " GROUP        ,Group."
hexmask.long.byte 0x00 16.--23. 1. "        CODE      ,Code.1 = Boundary crossing error."
rgroup.long 0x82C++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data."
hexmask.long 0x00 0.--31. 1. " ADDR_L       ,Address lower 32 bits."
rgroup.long 0x830++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data."
hexmask.long.word 0x00 0.--15. 1. " ADDR_H       ,Address upper 12 bits."
rgroup.long 0x834++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data."
hexmask.long.word 0x00 16.--27. 1. " ROUTEID      ,Route ID."
bitfld.long 0x00 13. "      WRITE     ,Write." "0,1"
textline "                                          "
bitfld.long 0x00 12. " READ         ,Read." "0,1"
bitfld.long 0x00 11. "         DEBUG     ,Debug." "0,1"
textline "                                          "
bitfld.long 0x00 10. " CACHEABLE    ,Cacheable." "0,1"
bitfld.long 0x00 9. "         PRIV      ,Priv." "0,1"
textline "                                          "
bitfld.long 0x00 8. " SECURE       ,Secure." "0,1"
hexmask.long.byte 0x00 0.--7. 1. "         PRIV_ID   ,Priv ID."
rgroup.long 0x838++0x3
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit."
hexmask.long.word 0x00 0.--9. 1. " BYTECNT      ,Byte count."
group.long 0x840++0x3
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal."
bitfld.long 0x00 0. " PEND_SET     ,Write a 1 to set the exception pend signal." "0,1"
hgroup.long 0x844++0x3
hide.long 0x00 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal."
in
textline "                                          "
group.long 0x848++0x3
line.long 0x00 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal."
bitfld.long 0x00 0. " ENABLE_SET   ,Write a 1 to set the exception interrupt enable signal." "0,1"
hgroup.long 0x84C++0x3
hide.long 0x00 "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal."
in
textline "                                          "
group.long 0x850++0x3
line.long 0x00 "ICSSG_EOI_REG,EOI Register"
hexmask.long.word 0x00 0.--15. 1. " EOI_WR       ,EOI Register"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_SGMII0"
tree "PRU_ICSSG2_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0"
base eaxi:0xB232100
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_SGMII_IDVER_REG,Identification and Version Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT          ,TX Identification Value"
bitfld.long 0x00 11.--15. "      RTL_VER        ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " MAJOR_VER         ,Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER      ,Minor Version Value"
group.long 0x4++0x3
line.long 0x00 "ICSSG_SOFT_RESET_REG,Software Reset Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 1. " RT_SOFT_RESET     ,NOT SUPPORTED" "0,1"
bitfld.long 0x00 0. "         SOFT_RESET     ,NOT SUPPORTED" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_CONTROL_REG,Control Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 6. " TEST_PATTERN_EN   ,Test Pattern Enable." "0,1"
bitfld.long 0x00 5. "         MASTER         ,Master Mode." "0,1"
textline "                                      "
bitfld.long 0x00 4. " LOOPBACK          ,Loopback mode." "0,1"
bitfld.long 0x00 3. "         MR_NP_LOADED   ,Next Page Loaded." "0,1"
textline "                                      "
bitfld.long 0x00 2. " FAST_LINK_TIMER   ,Fast Link Timer." "0,1"
bitfld.long 0x00 1. "         MR_AN_RESTART  ,Auto." "0,1"
textline "                                      "
bitfld.long 0x00 0. " MR_AN_ENABLE      ,Auto." "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "ICSSG_STATUS_REG,Status Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 5. " FIB_SIG_DETECT    ,Fiber Signal Detect." "0,1"
bitfld.long 0x00 4. "         LOCK           ,Lock." "0,1"
textline "                                      "
bitfld.long 0x00 3. " MR_PAGE_RX        ,Next Page Received." "0,1"
bitfld.long 0x00 2. "         MR_AN_COMPLETE ,Auto." "0,1"
textline "                                      "
bitfld.long 0x00 1. " AN_ERROR          ,Auto." "0,1"
bitfld.long 0x00 0. "         LINK           ,Link indicator." "0,1"
group.long 0x18++0x3
line.long 0x00 "ICSSG_MR_ADV_ABILITY_REG,Advertised Ability Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_ADV_ABILITY    ,Advertised Ability."
group.long 0x1C++0x3
line.long 0x00 "ICSSG_MR_NP_TX_REG,Next Page Transmit Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_NP_TX          ,Next Page Transmit."
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_MR_LP_ADV_ABILITY_REG,Link Partner Advertised Ability Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_ADV_ABILITY ,Link Partner Advertised Ability."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_MR_LP_NP_RX_REG,Link Partner Next Page Received Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_NP_RX       ,Link Partner Next Page Received."
group.long 0x30++0x3
line.long 0x00 "ICSSG_TX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " TX_CFG            ,Transmit configuration register output"
group.long 0x34++0x3
line.long 0x00 "ICSSG_RX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " RX_CFG            ,Receive configuration register output"
group.long 0x38++0x3
line.long 0x00 "ICSSG_AUX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " AUX_CFG           ,Auxiliary configuration register output"
group.long 0x40++0x3
line.long 0x00 "ICSSG_DIAG_CLEAR_REG,Diagnostics Clear Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 0. " DIAG_CLEAR        ,Diagnostics Clear." "0,1"
group.long 0x44++0x3
line.long 0x00 "ICSSG_DIAG_CONTROL_REG,Diagnostics Control Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 4.--6. " DIAG_SM_SEL       ,Diagnostic Select." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "         DIAG_EDGE_SEL  ,Diagnostis Hold Signals Edge Select" "0,1,2,3"
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_DIAG_STATUS_REG,Diagnostics Status Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " DIAG_STATUS       ,Diagnostics Status"
width 0x0B
tree.end
tree "PRU_ICSSG2_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1"
base eaxi:0xB232200
width 29.
rgroup.long 0x0++0x3
line.long 0x00 "ICSSG_SGMII_IDVER_REG,Identification and Version Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 16.--31. 1. " TX_IDENT          ,TX Identification Value"
bitfld.long 0x00 11.--15. "      RTL_VER        ,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                      "
bitfld.long 0x00 8.--10. " MAJOR_VER         ,Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "         MINOR_VER      ,Minor Version Value"
group.long 0x4++0x3
line.long 0x00 "ICSSG_SOFT_RESET_REG,Software Reset Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 1. " RT_SOFT_RESET     ,NOT SUPPORTED" "0,1"
bitfld.long 0x00 0. "         SOFT_RESET     ,NOT SUPPORTED" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_CONTROL_REG,Control Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 6. " TEST_PATTERN_EN   ,Test Pattern Enable." "0,1"
bitfld.long 0x00 5. "         MASTER         ,Master Mode." "0,1"
textline "                                      "
bitfld.long 0x00 4. " LOOPBACK          ,Loopback mode." "0,1"
bitfld.long 0x00 3. "         MR_NP_LOADED   ,Next Page Loaded." "0,1"
textline "                                      "
bitfld.long 0x00 2. " FAST_LINK_TIMER   ,Fast Link Timer." "0,1"
bitfld.long 0x00 1. "         MR_AN_RESTART  ,Auto." "0,1"
textline "                                      "
bitfld.long 0x00 0. " MR_AN_ENABLE      ,Auto." "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "ICSSG_STATUS_REG,Status Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 5. " FIB_SIG_DETECT    ,Fiber Signal Detect." "0,1"
bitfld.long 0x00 4. "         LOCK           ,Lock." "0,1"
textline "                                      "
bitfld.long 0x00 3. " MR_PAGE_RX        ,Next Page Received." "0,1"
bitfld.long 0x00 2. "         MR_AN_COMPLETE ,Auto." "0,1"
textline "                                      "
bitfld.long 0x00 1. " AN_ERROR          ,Auto." "0,1"
bitfld.long 0x00 0. "         LINK           ,Link indicator." "0,1"
group.long 0x18++0x3
line.long 0x00 "ICSSG_MR_ADV_ABILITY_REG,Advertised Ability Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_ADV_ABILITY    ,Advertised Ability."
group.long 0x1C++0x3
line.long 0x00 "ICSSG_MR_NP_TX_REG,Next Page Transmit Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_NP_TX          ,Next Page Transmit."
rgroup.long 0x20++0x3
line.long 0x00 "ICSSG_MR_LP_ADV_ABILITY_REG,Link Partner Advertised Ability Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_ADV_ABILITY ,Link Partner Advertised Ability."
rgroup.long 0x24++0x3
line.long 0x00 "ICSSG_MR_LP_NP_RX_REG,Link Partner Next Page Received Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " MR_LP_NP_RX       ,Link Partner Next Page Received."
group.long 0x30++0x3
line.long 0x00 "ICSSG_TX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " TX_CFG            ,Transmit configuration register output"
group.long 0x34++0x3
line.long 0x00 "ICSSG_RX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " RX_CFG            ,Receive configuration register output"
group.long 0x38++0x3
line.long 0x00 "ICSSG_AUX_CFG_REG,SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long 0x00 0.--31. 1. " AUX_CFG           ,Auxiliary configuration register output"
group.long 0x40++0x3
line.long 0x00 "ICSSG_DIAG_CLEAR_REG,Diagnostics Clear Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 0. " DIAG_CLEAR        ,Diagnostics Clear." "0,1"
group.long 0x44++0x3
line.long 0x00 "ICSSG_DIAG_CONTROL_REG,Diagnostics Control Register SGMII mode is supported only for PRU_ICSSG2 instance."
bitfld.long 0x00 4.--6. " DIAG_SM_SEL       ,Diagnostic Select." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "         DIAG_EDGE_SEL  ,Diagnostis Hold Signals Edge Select" "0,1,2,3"
rgroup.long 0x48++0x3
line.long 0x00 "ICSSG_DIAG_STATUS_REG,Diagnostics Status Register SGMII mode is supported only for PRU_ICSSG2 instance."
hexmask.long.word 0x00 0.--15. 1. " DIAG_STATUS       ,Diagnostics Status"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_TASKS_MGR_PRU"
tree "PRU_ICSSG2_TASKS_MGR_PRU0"
base eaxi:0xB22A000
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG2_TASKS_MGR_RTU0"
base eaxi:0xB22A100
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG2_TASKS_MGR_PRU1"
base eaxi:0xB22A200
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree "PRU_ICSSG2_TASKS_MGR_RTU1"
base eaxi:0xB22A300
width 21.
group.long 0x0++0x3
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. " TS2_EN_S4      ,TS2 Sub40: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 10. "     TS2_EN_S3      ,TS2 Sub30: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS2_EN_S2      ,TS2 Sub20: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 8. "     TS2_EN_S1      ,TS2 Sub10: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 7. " TS2_EN_S0      ,TS2 Sub00: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 6. "     TS1_EN_S4      ,TS1 Sub40: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 5. " TS1_EN_S3      ,TS1 Sub30: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 4. "     TS1_EN_S2      ,TS1 Sub20: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 3. " TS1_EN_S1      ,TS1 Sub10: Disabled 1: Enabled" "0,1"
bitfld.long 0x00 2. "     TS1_EN_S0      ,TS1 Sub00: Disabled 1: Enabled" "0,1"
textline "                              "
bitfld.long 0x00 0.--1. " TASKS_MGR_MODE ,TaskSwap Mode0: Disabled 1: RXTX 2: General_HW" "0,1,2,3"
rgroup.long 0x4++0x3
line.long 0x00 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x00 17. " TS2_SUB_PEND_4 ,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x00 16. "     TS2_SUB_PEND_3 ,Task2 Sub3 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 15. " TS2_SUB_PEND_2 ,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x00 14. "     TS2_SUB_PEND_1 ,Task2 Sub1 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 13. " TS2_SUB_PEND_0 ,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x00 12. "     TS1_SUB_PEND_4 ,Task1 Sub4 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 11. " TS1_SUB_PEND_3 ,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x00 10. "     TS1_SUB_PEND_2 ,Task1 Sub2 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 9. " TS1_SUB_PEND_1 ,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x00 8. "     TS1_SUB_PEND_0 ,Task1 Sub0 Pend State" "0,1"
textline "                              "
bitfld.long 0x00 4.--7. " TS2_STATE      ,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "    TS1_STATE      ,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8++0x3
line.long 0x00 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S0      ,TS1 Sub0 PC"
group.long 0xC++0x3
line.long 0x00 "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S1      ,TS1 Sub1 PC"
group.long 0x10++0x3
line.long 0x00 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S2      ,TS1 Sub2 PC"
group.long 0x14++0x3
line.long 0x00 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S3      ,TS1 Sub3 PC"
group.long 0x18++0x3
line.long 0x00 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS1_PC_S4      ,TS1 Sub4 PC"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S0      ,TS2 Sub0 PC"
group.long 0x20++0x3
line.long 0x00 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S1      ,TS2 Sub1 PC"
group.long 0x24++0x3
line.long 0x00 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S2      ,TS2 Sub2 PC"
group.long 0x28++0x3
line.long 0x00 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S3      ,TS2 Sub3 PC"
group.long 0x2C++0x3
line.long 0x00 "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x00 0.--13. 1. " TS2_PC_S4      ,TS2 Sub4 PC"
group.long 0x30++0x3
line.long 0x00 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x00 10.--14. " BKN_SIZE       ,RX BKN Size, After BK1 and BK@, then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "    BK2_SIZE       ,RX BK2 Size, The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                              "
bitfld.long 0x00 0.--4. " BK1_SIZE       ,RX BK1 Size , The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x3
line.long 0x00 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x00 0.--5. " TX_WM          ,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS1_GEN_S3_MX  ,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS1_GEN_S2_MX  ,TS1 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS1_GEN_S1_MX  ,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS1_GEN_S0_MX  ,TS1 Generic Sub0 MX Select"
group.long 0x3C++0x3
line.long 0x00 "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS1_GEN_S4_MX  ,TS1 Generic Sub4 MX Select"
group.long 0x40++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x00 24.--31. 1. " TS2_GEN_S3_MX  ,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x00 16.--23. 1. "    TS2_GEN_S2_MX  ,TS2 Generic Sub2 MX Select"
textline "                              "
hexmask.long.byte 0x00 8.--15. 1. " TS2_GEN_S1_MX  ,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x00 0.--7. 1. "    TS2_GEN_S0_MX  ,TS2 Generic Sub0 MX Select"
group.long 0x44++0x3
line.long 0x00 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x00 0.--7. 1. " TS2_GEN_S4_MX  ,TS2 Generic Sub4 MX Select"
group.long 0x48++0x3
line.long 0x00 "ICSSG_CAP_EN_CFG,Enable capture new event"
hexmask.long.word 0x00 0.--9. 1. " NEW_CAP_EN     ,Capture new event while in the same task Enable TS1_S0 = [0] .. TS2_S4 = [9]"
width 0x0B
tree.end
tree.end
tree "PRU_ICSSG_UART"
tree "PRU_ICSSG2_PR1_ICSS_UART_UART_SLV"
base eaxi:0xB228000
width 16.
group.long 0x0++0x3
line.long 0x00 "ICSSG_RBR_TBR,Registers"
hexmask.long.word 0x00 8.--17. 1. " TBR_DATA    ,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "      RBR_DATA     ,Receive Buffer Register"
group.long 0x4++0x3
line.long 0x00 "ICSSG_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x00 3. " EDSSI       ,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x00 2. "         ELSI         ,Enable for Receiver Line Status Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 1. " ETBEI       ,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x00 0. "         ERBI         ,Enable for Receiver Data Available Interrupt" "0,1"
group.long 0x8++0x3
line.long 0x00 "ICSSG_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x00 14.--15. " FCR_RXFIFTL ,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x00 11. "         FCR_DMAMODE1 ,DMA Mode Select" "0,1"
textline "                         "
bitfld.long 0x00 10. " FCR_TXCLR   ,Transmitter FIFO Reset" "0,1"
bitfld.long 0x00 9. "         FCR_RXCLR    ,Receiver FIFO Reset" "0,1"
textline "                         "
bitfld.long 0x00 8. " FCR_FIFOEN  ,FIFO Enable Register" "0,1"
bitfld.long 0x00 6.--7. "         IIR_FIFOEN   ,FIFOs enabled" "0,1,2,3"
textline "                         "
bitfld.long 0x00 1.--3. " IIR_INTID   ,Interrupt Type" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "         IIR_IPEND    ,Receiver Data Available Interrupt Pending" "0,1"
group.long 0xC++0x3
line.long 0x00 "ICSSG_LCTR,Line Control Register"
bitfld.long 0x00 7. " DLAB        ,Divisor Latch Access Bit" "0,1"
bitfld.long 0x00 6. "         BC           ,Break Control" "0,1"
textline "                         "
bitfld.long 0x00 5. " SP          ,Stick Parity" "0,1"
bitfld.long 0x00 4. "         EPS          ,Even Parity Select" "0,1"
textline "                         "
bitfld.long 0x00 3. " PEN         ,Parity Enable" "0,1"
bitfld.long 0x00 2. "         STB          ,Number of Stop Bits" "0,1"
textline "                         "
bitfld.long 0x00 1. " WLS1        ,Word Length Select Bit 1" "0,1"
bitfld.long 0x00 0. "         WLS0         ,Word Length Select Bit 0" "0,1"
group.long 0x10++0x3
line.long 0x00 "ICSSG_MCTR,Modem Control Register"
bitfld.long 0x00 5. " AFE         ,Autoflow Control Enable" "0,1"
bitfld.long 0x00 4. "         LOOP         ,LOOP Bit" "0,1"
textline "                         "
bitfld.long 0x00 3. " OUT2        ,Out2 Bit" "0,1"
bitfld.long 0x00 2. "         OUT1         ,Out1 Bit" "0,1"
textline "                         "
bitfld.long 0x00 1. " RTS         ,Ready to Send" "0,1"
bitfld.long 0x00 0. "         DTR          ,Data Terminal Ready" "0,1"
rgroup.long 0x14++0x3
line.long 0x00 "ICSSG_LSR1,Line Status Register1"
bitfld.long 0x00 7. " RXFIFOE     ,Receiver FIFO Error" "0,1"
bitfld.long 0x00 6. "         TEMT         ,Transmitter Empty" "0,1"
textline "                         "
bitfld.long 0x00 5. " THRE        ,Transmitter Holding Register" "0,1"
bitfld.long 0x00 4. "         BI           ,Break Interrupt" "0,1"
textline "                         "
bitfld.long 0x00 3. " FE          ,Framing Error" "0,1"
bitfld.long 0x00 2. "         PE           ,Parity Error" "0,1"
textline "                         "
bitfld.long 0x00 1. " OE          ,Overrun Error" "0,1"
bitfld.long 0x00 0. "         DR           ,Data Ready" "0,1"
rgroup.long 0x18++0x3
line.long 0x00 "ICSSG_MSR,Modem Status Register"
bitfld.long 0x00 7. " CD          ,Carrier Detect" "0,1"
bitfld.long 0x00 6. "         RI           ,Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 5. " DSR         ,Data Set Ready" "0,1"
bitfld.long 0x00 4. "         CTS          ,Clear To Send" "0,1"
textline "                         "
bitfld.long 0x00 3. " DCD         ,Delta Carrier Detect" "0,1"
bitfld.long 0x00 2. "         TERI         ,Trailing Edge Ring Indicator" "0,1"
textline "                         "
bitfld.long 0x00 1. " DDSR        ,Delta Set Ready" "0,1"
bitfld.long 0x00 0. "         DCTS         ,Delta Clear To Send" "0,1"
group.long 0x1C++0x3
line.long 0x00 "ICSSG_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x00 0.--7. 1. " DATA        ,Scratch Register Bits"
group.long 0x20++0x3
line.long 0x00 "ICSSG_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLL         ,Divisor Latch [LSB]"
group.long 0x24++0x3
line.long 0x00 "ICSSG_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x00 0.--7. 1. " DLH         ,Divisor Latch [MSB]"
rgroup.long 0x28++0x3
line.long 0x00 "ICSSG_PID,Peripheral ID Register"
hexmask.long 0x00 0.--31. 1. " PID         ,"
group.long 0x30++0x3
line.long 0x00 "ICSSG_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. " URST        ,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "         UTRST        ,UART Transmitter Reset Bit" "0,1"
textline "                         "
bitfld.long 0x00 13. " URRST       ,UART Receiver Reset Bit" "0,1"
bitfld.long 0x00 1. "         RES          ,Free Bit" "0,1"
textline "                         "
bitfld.long 0x00 0. " FREE        ,Free Bit" "0,1"
group.long 0x34++0x3
line.long 0x00 "ICSSG_MODE,UART Mode Definition Register"
bitfld.long 0x00 0. " OSM_SEL     ,Oversampling Mode Select" "0,1"
width 0x0B
tree.end
tree.end
tree.end
endif
; newline